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| 4358 | Serge | 1 | /* |
| 2 | * Copyright © 2009 Intel Corporation |
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| 3 | * |
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| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 5 | * copy of this software and associated documentation files (the "Software"), |
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| 6 | * to deal in the Software without restriction, including without limitation |
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| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 9 | * Software is furnished to do so, subject to the following conditions: |
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| 10 | * |
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| 11 | * The above copyright notice and this permission notice (including the next |
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| 12 | * paragraph) shall be included in all copies or substantial portions of the |
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| 13 | * Software. |
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| 14 | * |
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| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
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| 21 | * IN THE SOFTWARE. |
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| 22 | * |
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| 23 | * Authors: |
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| 24 | * Eric Anholt |
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| 25 | * |
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| 26 | */ |
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| 27 | |||
| 28 | #include "brw_context.h" |
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| 29 | #include "brw_state.h" |
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| 30 | #include "brw_defines.h" |
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| 31 | #include "intel_batchbuffer.h" |
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| 32 | #include "main/fbobject.h" |
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| 33 | |||
| 34 | static void |
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| 35 | gen6_upload_scissor_state(struct brw_context *brw) |
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| 36 | { |
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| 37 | struct gl_context *ctx = &brw->ctx; |
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| 38 | const bool render_to_fbo = _mesa_is_user_fbo(ctx->DrawBuffer); |
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| 39 | struct gen6_scissor_rect *scissor; |
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| 40 | uint32_t scissor_state_offset; |
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| 41 | |||
| 42 | scissor = brw_state_batch(brw, AUB_TRACE_SCISSOR_STATE, |
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| 43 | sizeof(*scissor), 32, &scissor_state_offset); |
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| 44 | |||
| 45 | /* _NEW_SCISSOR | _NEW_BUFFERS | _NEW_VIEWPORT */ |
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| 46 | |||
| 47 | /* The scissor only needs to handle the intersection of drawable and |
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| 48 | * scissor rect. Clipping to the boundaries of static shared buffers |
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| 49 | * for front/back/depth is covered by looping over cliprects in brw_draw.c. |
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| 50 | * |
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| 51 | * Note that the hardware's coordinates are inclusive, while Mesa's min is |
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| 52 | * inclusive but max is exclusive. |
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| 53 | */ |
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| 54 | if (ctx->DrawBuffer->_Xmin == ctx->DrawBuffer->_Xmax || |
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| 55 | ctx->DrawBuffer->_Ymin == ctx->DrawBuffer->_Ymax) { |
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| 56 | /* If the scissor was out of bounds and got clamped to 0 |
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| 57 | * width/height at the bounds, the subtraction of 1 from |
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| 58 | * maximums could produce a negative number and thus not clip |
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| 59 | * anything. Instead, just provide a min > max scissor inside |
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| 60 | * the bounds, which produces the expected no rendering. |
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| 61 | */ |
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| 62 | scissor->xmin = 1; |
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| 63 | scissor->xmax = 0; |
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| 64 | scissor->ymin = 1; |
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| 65 | scissor->ymax = 0; |
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| 66 | } else if (render_to_fbo) { |
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| 67 | /* texmemory: Y=0=bottom */ |
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| 68 | scissor->xmin = ctx->DrawBuffer->_Xmin; |
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| 69 | scissor->xmax = ctx->DrawBuffer->_Xmax - 1; |
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| 70 | scissor->ymin = ctx->DrawBuffer->_Ymin; |
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| 71 | scissor->ymax = ctx->DrawBuffer->_Ymax - 1; |
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| 72 | } |
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| 73 | else { |
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| 74 | /* memory: Y=0=top */ |
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| 75 | scissor->xmin = ctx->DrawBuffer->_Xmin; |
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| 76 | scissor->xmax = ctx->DrawBuffer->_Xmax - 1; |
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| 77 | scissor->ymin = ctx->DrawBuffer->Height - ctx->DrawBuffer->_Ymax; |
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| 78 | scissor->ymax = ctx->DrawBuffer->Height - ctx->DrawBuffer->_Ymin - 1; |
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| 79 | } |
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| 80 | |||
| 81 | BEGIN_BATCH(2); |
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| 82 | OUT_BATCH(_3DSTATE_SCISSOR_STATE_POINTERS << 16 | (2 - 2)); |
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| 83 | OUT_BATCH(scissor_state_offset); |
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| 84 | ADVANCE_BATCH(); |
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| 85 | } |
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| 86 | |||
| 87 | const struct brw_tracked_state gen6_scissor_state = { |
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| 88 | .dirty = { |
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| 89 | .mesa = _NEW_SCISSOR | _NEW_BUFFERS | _NEW_VIEWPORT, |
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| 90 | .brw = BRW_NEW_BATCH, |
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| 91 | .cache = 0, |
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| 92 | }, |
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| 93 | .emit = gen6_upload_scissor_state, |
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| 94 | }; |