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| 4358 | Serge | 1 | /********************************************************** |
| 2 | * Copyright 2008-2009 VMware, Inc. All rights reserved. |
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| 3 | * |
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| 4 | * Permission is hereby granted, free of charge, to any person |
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| 5 | * obtaining a copy of this software and associated documentation |
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| 6 | * files (the "Software"), to deal in the Software without |
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| 7 | * restriction, including without limitation the rights to use, copy, |
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| 8 | * modify, merge, publish, distribute, sublicense, and/or sell copies |
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| 9 | * of the Software, and to permit persons to whom the Software is |
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| 10 | * furnished to do so, subject to the following conditions: |
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| 11 | * |
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| 12 | * The above copyright notice and this permission notice shall be |
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| 13 | * included in all copies or substantial portions of the Software. |
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| 14 | * |
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| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
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| 16 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
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| 17 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
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| 18 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS |
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| 19 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN |
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| 20 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
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| 21 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
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| 22 | * SOFTWARE. |
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| 23 | * |
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| 24 | **********************************************************/ |
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| 25 | |||
| 26 | /** |
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| 27 | * @file |
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| 28 | * SVGA Shader Token Opcode Info |
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| 29 | * |
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| 30 | * @author Michal Krol |
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| 31 | */ |
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| 32 | |||
| 33 | #include "util/u_debug.h" |
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| 34 | #include "svga_shader_op.h" |
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| 35 | |||
| 36 | #include "../svga_hw_reg.h" |
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| 37 | #include "svga3d_shaderdefs.h" |
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| 38 | |||
| 39 | #define SVGA3DOP_INVALID SVGA3DOP_END |
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| 40 | #define TGSI_OPCODE_INVALID TGSI_OPCODE_LAST |
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| 41 | |||
| 42 | static struct sh_opcode_info opcode_info[] = |
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| 43 | { |
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| 44 | { "nop", 0, 0, 0, 0, SVGA3DOP_NOP }, |
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| 45 | { "mov", 1, 1, 0, 0, SVGA3DOP_MOV, }, |
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| 46 | { "add", 1, 2, 0, 0, SVGA3DOP_ADD, }, |
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| 47 | { "sub", 1, 2, 0, 0, SVGA3DOP_SUB, }, |
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| 48 | { "mad", 1, 3, 0, 0, SVGA3DOP_MAD, }, |
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| 49 | { "mul", 1, 2, 0, 0, SVGA3DOP_MUL, }, |
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| 50 | { "rcp", 1, 1, 0, 0, SVGA3DOP_RCP, }, |
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| 51 | { "rsq", 1, 1, 0, 0, SVGA3DOP_RSQ, }, |
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| 52 | { "dp3", 1, 2, 0, 0, SVGA3DOP_DP3, }, |
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| 53 | { "dp4", 1, 2, 0, 0, SVGA3DOP_DP4, }, |
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| 54 | { "min", 1, 2, 0, 0, SVGA3DOP_MIN, }, |
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| 55 | { "max", 1, 2, 0, 0, SVGA3DOP_MAX, }, |
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| 56 | { "slt", 1, 2, 0, 0, SVGA3DOP_SLT, }, |
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| 57 | { "sge", 1, 2, 0, 0, SVGA3DOP_SGE, }, |
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| 58 | { "exp", 1, 1, 0, 0, SVGA3DOP_EXP, }, |
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| 59 | { "log", 1, 1, 0, 0, SVGA3DOP_LOG, }, |
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| 60 | { "lit", 1, 1, 0, 0, SVGA3DOP_LIT, }, |
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| 61 | { "dst", 1, 2, 0, 0, SVGA3DOP_DST, }, |
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| 62 | { "lrp", 1, 3, 0, 0, SVGA3DOP_LRP, }, |
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| 63 | { "frc", 1, 1, 0, 0, SVGA3DOP_FRC, }, |
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| 64 | { "m4x4", 1, 2, 0, 0, SVGA3DOP_M4x4, }, |
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| 65 | { "m4x3", 1, 2, 0, 0, SVGA3DOP_M4x3, }, |
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| 66 | { "m3x4", 1, 2, 0, 0, SVGA3DOP_M3x4, }, |
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| 67 | { "m3x3", 1, 2, 0, 0, SVGA3DOP_M3x3, }, |
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| 68 | { "m3x2", 1, 2, 0, 0, SVGA3DOP_M3x2, }, |
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| 69 | { "call", 0, 1, 0, 0, SVGA3DOP_CALL, }, |
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| 70 | { "callnz", 0, 2, 0, 0, SVGA3DOP_CALLNZ, }, |
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| 71 | { "loop", 0, 2, 0, 1, SVGA3DOP_LOOP, }, |
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| 72 | { "ret", 0, 0, 0, 0, SVGA3DOP_RET, }, |
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| 73 | { "endloop", 0, 0, 1, 0, SVGA3DOP_ENDLOOP, }, |
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| 74 | { "label", 0, 1, 0, 0, SVGA3DOP_LABEL, }, |
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| 75 | { "dcl", 0, 0, 0, 0, SVGA3DOP_DCL, }, |
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| 76 | { "pow", 1, 2, 0, 0, SVGA3DOP_POW, }, |
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| 77 | { "crs", 1, 2, 0, 0, SVGA3DOP_CRS, }, |
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| 78 | { "sgn", 1, 3, 0, 0, SVGA3DOP_SGN, }, |
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| 79 | { "abs", 1, 1, 0, 0, SVGA3DOP_ABS, }, |
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| 80 | { "nrm", 1, 1, 0, 0, SVGA3DOP_NRM, }, /* 3-componenet normalization */ |
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| 81 | { "sincos", 1, 3, 0, 0, SVGA3DOP_SINCOS, }, |
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| 82 | { "rep", 0, 1, 0, 1, SVGA3DOP_REP, }, |
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| 83 | { "endrep", 0, 0, 1, 0, SVGA3DOP_ENDREP, }, |
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| 84 | { "if", 0, 1, 0, 1, SVGA3DOP_IF, }, |
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| 85 | { "ifc", 0, 2, 0, 1, SVGA3DOP_IFC, }, |
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| 86 | { "else", 0, 0, 1, 1, SVGA3DOP_ELSE, }, |
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| 87 | { "endif", 0, 0, 1, 0, SVGA3DOP_ENDIF, }, |
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| 88 | { "break", 0, 0, 0, 0, SVGA3DOP_BREAK, }, |
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| 89 | { "breakc", 0, 2, 0, 0, SVGA3DOP_BREAKC, }, |
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| 90 | { "mova", 1, 1, 0, 0, SVGA3DOP_MOVA, }, |
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| 91 | { "defb", 0, 0, 0, 0, SVGA3DOP_DEFB, }, |
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| 92 | { "defi", 0, 0, 0, 0, SVGA3DOP_DEFI, }, |
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| 93 | { "???", 0, 0, 0, 0, SVGA3DOP_INVALID, }, |
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| 94 | { "???", 0, 0, 0, 0, SVGA3DOP_INVALID, }, |
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| 95 | { "???", 0, 0, 0, 0, SVGA3DOP_INVALID, }, |
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| 96 | { "???", 0, 0, 0, 0, SVGA3DOP_INVALID, }, |
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| 97 | { "???", 0, 0, 0, 0, SVGA3DOP_INVALID, }, |
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| 98 | { "???", 0, 0, 0, 0, SVGA3DOP_INVALID, }, |
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| 99 | { "???", 0, 0, 0, 0, SVGA3DOP_INVALID, }, |
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| 100 | { "???", 0, 0, 0, 0, SVGA3DOP_INVALID, }, |
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| 101 | { "???", 0, 0, 0, 0, SVGA3DOP_INVALID, }, |
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| 102 | { "???", 0, 0, 0, 0, SVGA3DOP_INVALID, }, |
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| 103 | { "???", 0, 0, 0, 0, SVGA3DOP_INVALID, }, |
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| 104 | { "???", 0, 0, 0, 0, SVGA3DOP_INVALID, }, |
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| 105 | { "???", 0, 0, 0, 0, SVGA3DOP_INVALID, }, |
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| 106 | { "???", 0, 0, 0, 0, SVGA3DOP_INVALID, }, |
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| 107 | { "???", 0, 0, 0, 0, SVGA3DOP_INVALID, }, |
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| 108 | { "texcoord", 1, 0, 0, 0, SVGA3DOP_TEXCOORD, }, |
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| 109 | { "texkill", 1, 0, 0, 0, SVGA3DOP_TEXKILL, }, |
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| 110 | { "tex", 1, 0, 0, 0, SVGA3DOP_TEX, }, |
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| 111 | { "texbem", 1, 1, 0, 0, SVGA3DOP_TEXBEM, }, |
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| 112 | { "texbeml", 1, 1, 0, 0, SVGA3DOP_TEXBEML, }, |
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| 113 | { "texreg2ar", 1, 1, 0, 0, SVGA3DOP_TEXREG2AR, }, |
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| 114 | { "texreg2gb", 1, 1, 0, 0, SVGA3DOP_TEXREG2GB, }, |
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| 115 | { "texm3x2pad", 1, 1, 0, 0, SVGA3DOP_TEXM3x2PAD, }, |
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| 116 | { "texm3x2tex", 1, 1, 0, 0, SVGA3DOP_TEXM3x2TEX, }, |
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| 117 | { "texm3x3pad", 1, 1, 0, 0, SVGA3DOP_TEXM3x3PAD, }, |
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| 118 | { "texm3x3tex", 1, 1, 0, 0, SVGA3DOP_TEXM3x3TEX, }, |
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| 119 | { "reserved0", 0, 0, 0, 0, SVGA3DOP_RESERVED0, }, |
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| 120 | { "texm3x3spec", 1, 2, 0, 0, SVGA3DOP_TEXM3x3SPEC, }, |
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| 121 | { "texm3x3vspec", 1, 1, 0, 0, SVGA3DOP_TEXM3x3VSPEC,}, |
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| 122 | { "expp", 1, 1, 0, 0, SVGA3DOP_EXPP, }, |
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| 123 | { "logp", 1, 1, 0, 0, SVGA3DOP_LOGP, }, |
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| 124 | { "cnd", 1, 3, 0, 0, SVGA3DOP_CND, }, |
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| 125 | { "def", 0, 0, 0, 0, SVGA3DOP_DEF, }, |
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| 126 | { "texreg2rgb", 1, 1, 0, 0, SVGA3DOP_TEXREG2RGB, }, |
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| 127 | { "texdp3tex", 1, 1, 0, 0, SVGA3DOP_TEXDP3TEX, }, |
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| 128 | { "texm3x2depth", 1, 1, 0, 0, SVGA3DOP_TEXM3x2DEPTH,}, |
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| 129 | { "texdp3", 1, 1, 0, 0, SVGA3DOP_TEXDP3, }, |
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| 130 | { "texm3x3", 1, 1, 0, 0, SVGA3DOP_TEXM3x3, }, |
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| 131 | { "texdepth", 1, 0, 0, 0, SVGA3DOP_TEXDEPTH, }, |
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| 132 | { "cmp", 1, 3, 0, 0, SVGA3DOP_CMP, }, |
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| 133 | { "bem", 1, 2, 0, 0, SVGA3DOP_BEM, }, |
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| 134 | { "dp2add", 1, 3, 0, 0, SVGA3DOP_DP2ADD, }, |
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| 135 | { "dsx", 1, 1, 0, 0, SVGA3DOP_INVALID, }, |
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| 136 | { "dsy", 1, 1, 0, 0, SVGA3DOP_INVALID, }, |
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| 137 | { "texldd", 1, 4, 0, 0, SVGA3DOP_INVALID, }, |
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| 138 | { "setp", 1, 2, 0, 0, SVGA3DOP_SETP, }, |
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| 139 | { "texldl", 1, 2, 0, 0, SVGA3DOP_TEXLDL, }, |
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| 140 | { "breakp", 0, 1, 0, 0, SVGA3DOP_INVALID, }, |
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| 141 | }; |
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| 142 | |||
| 143 | const struct sh_opcode_info *svga_opcode_info( uint op ) |
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| 144 | { |
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| 145 | struct sh_opcode_info *info; |
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| 146 | |||
| 147 | if (op >= sizeof( opcode_info ) / sizeof( opcode_info[0] )) { |
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| 148 | /* The opcode is either PHASE, COMMENT, END or out of range. |
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| 149 | */ |
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| 150 | assert( 0 ); |
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| 151 | return NULL; |
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| 152 | } |
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| 153 | |||
| 154 | info = &opcode_info[op]; |
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| 155 | |||
| 156 | if (info->svga_opcode == SVGA3DOP_INVALID) { |
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| 157 | /* No valid information. Please provide number of dst/src registers. |
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| 158 | */ |
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| 159 | _debug_printf("Missing information for opcode %u, '%s'\n", op, |
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| 160 | opcode_info[op].mnemonic); |
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| 161 | assert( 0 ); |
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| 162 | return NULL; |
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| 163 | } |
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| 164 | |||
| 165 | /* Sanity check. |
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| 166 | */ |
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| 167 | assert( op == info->svga_opcode ); |
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| 168 | |||
| 169 | return info; |
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| 170 | } |