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4358 | Serge | 1 | /********************************************************** |
2 | * Copyright 2008-2009 VMware, Inc. All rights reserved. |
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3 | * |
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4 | * Permission is hereby granted, free of charge, to any person |
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5 | * obtaining a copy of this software and associated documentation |
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6 | * files (the "Software"), to deal in the Software without |
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7 | * restriction, including without limitation the rights to use, copy, |
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8 | * modify, merge, publish, distribute, sublicense, and/or sell copies |
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9 | * of the Software, and to permit persons to whom the Software is |
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10 | * furnished to do so, subject to the following conditions: |
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11 | * |
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12 | * The above copyright notice and this permission notice shall be |
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13 | * included in all copies or substantial portions of the Software. |
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14 | * |
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15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
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16 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
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17 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
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18 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS |
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19 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN |
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20 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
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21 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
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22 | * SOFTWARE. |
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23 | * |
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24 | **********************************************************/ |
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25 | |||
26 | #include "svga_cmd.h" |
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27 | |||
28 | #include "pipe/p_state.h" |
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29 | #include "pipe/p_defines.h" |
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30 | #include "util/u_inlines.h" |
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31 | #include "os/os_thread.h" |
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32 | #include "util/u_format.h" |
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33 | #include "util/u_math.h" |
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34 | #include "util/u_memory.h" |
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35 | #include "util/u_resource.h" |
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36 | |||
37 | #include "svga_format.h" |
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38 | #include "svga_screen.h" |
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39 | #include "svga_context.h" |
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40 | #include "svga_resource_texture.h" |
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41 | #include "svga_resource_buffer.h" |
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42 | #include "svga_sampler_view.h" |
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43 | #include "svga_winsys.h" |
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44 | #include "svga_debug.h" |
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45 | |||
46 | |||
47 | /* XXX: This isn't a real hardware flag, but just a hack for kernel to |
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48 | * know about primary surfaces. Find a better way to accomplish this. |
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49 | */ |
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50 | #define SVGA3D_SURFACE_HINT_SCANOUT (1 << 9) |
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51 | |||
52 | |||
53 | static INLINE void |
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54 | svga_transfer_dma_band(struct svga_context *svga, |
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55 | struct svga_transfer *st, |
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56 | SVGA3dTransferType transfer, |
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57 | unsigned y, unsigned h, unsigned srcy, |
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58 | SVGA3dSurfaceDMAFlags flags) |
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59 | { |
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60 | struct svga_texture *texture = svga_texture(st->base.resource); |
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61 | SVGA3dCopyBox box; |
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62 | enum pipe_error ret; |
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63 | |||
64 | box.x = st->base.box.x; |
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65 | box.y = y; |
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66 | box.z = st->base.box.z; |
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67 | box.w = st->base.box.width; |
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68 | box.h = h; |
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69 | box.d = 1; |
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70 | box.srcx = 0; |
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71 | box.srcy = srcy; |
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72 | box.srcz = 0; |
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73 | |||
74 | if (st->base.resource->target == PIPE_TEXTURE_CUBE) { |
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75 | st->face = st->base.box.z; |
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76 | box.z = 0; |
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77 | } |
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78 | else |
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79 | st->face = 0; |
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80 | |||
81 | SVGA_DBG(DEBUG_DMA, "dma %s sid %p, face %u, (%u, %u, %u) - (%u, %u, %u), %ubpp\n", |
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82 | transfer == SVGA3D_WRITE_HOST_VRAM ? "to" : "from", |
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83 | texture->handle, |
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84 | st->face, |
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85 | st->base.box.x, |
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86 | y, |
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87 | box.z, |
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88 | st->base.box.x + st->base.box.width, |
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89 | y + h, |
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90 | box.z + 1, |
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91 | util_format_get_blocksize(texture->b.b.format) * 8 / |
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92 | (util_format_get_blockwidth(texture->b.b.format)*util_format_get_blockheight(texture->b.b.format))); |
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93 | |||
94 | ret = SVGA3D_SurfaceDMA(svga->swc, st, transfer, &box, 1, flags); |
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95 | if(ret != PIPE_OK) { |
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96 | svga_context_flush(svga, NULL); |
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97 | ret = SVGA3D_SurfaceDMA(svga->swc, st, transfer, &box, 1, flags); |
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98 | assert(ret == PIPE_OK); |
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99 | } |
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100 | } |
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101 | |||
102 | |||
103 | static INLINE void |
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104 | svga_transfer_dma(struct svga_context *svga, |
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105 | struct svga_transfer *st, |
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106 | SVGA3dTransferType transfer, |
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107 | SVGA3dSurfaceDMAFlags flags) |
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108 | { |
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109 | struct svga_texture *texture = svga_texture(st->base.resource); |
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110 | struct svga_screen *screen = svga_screen(texture->b.b.screen); |
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111 | struct svga_winsys_screen *sws = screen->sws; |
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112 | struct pipe_fence_handle *fence = NULL; |
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113 | |||
114 | if (transfer == SVGA3D_READ_HOST_VRAM) { |
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115 | SVGA_DBG(DEBUG_PERF, "%s: readback transfer\n", __FUNCTION__); |
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116 | } |
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117 | |||
118 | /* Ensure any pending operations on host surfaces are queued on the command |
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119 | * buffer first. |
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120 | */ |
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121 | svga_surfaces_flush( svga ); |
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122 | |||
123 | if(!st->swbuf) { |
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124 | /* Do the DMA transfer in a single go */ |
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125 | |||
126 | svga_transfer_dma_band(svga, st, transfer, |
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127 | st->base.box.y, st->base.box.height, 0, |
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128 | flags); |
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129 | |||
130 | if(transfer == SVGA3D_READ_HOST_VRAM) { |
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131 | svga_context_flush(svga, &fence); |
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132 | sws->fence_finish(sws, fence, 0); |
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133 | sws->fence_reference(sws, &fence, NULL); |
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134 | } |
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135 | } |
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136 | else { |
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137 | int y, h, srcy; |
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138 | unsigned blockheight = util_format_get_blockheight(st->base.resource->format); |
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139 | h = st->hw_nblocksy * blockheight; |
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140 | srcy = 0; |
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141 | for(y = 0; y < st->base.box.height; y += h) { |
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142 | unsigned offset, length; |
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143 | void *hw, *sw; |
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144 | |||
145 | if (y + h > st->base.box.height) |
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146 | h = st->base.box.height - y; |
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147 | |||
148 | /* Transfer band must be aligned to pixel block boundaries */ |
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149 | assert(y % blockheight == 0); |
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150 | assert(h % blockheight == 0); |
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151 | |||
152 | offset = y * st->base.stride / blockheight; |
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153 | length = h * st->base.stride / blockheight; |
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154 | |||
155 | sw = (uint8_t *)st->swbuf + offset; |
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156 | |||
157 | if (transfer == SVGA3D_WRITE_HOST_VRAM) { |
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158 | unsigned usage = PIPE_TRANSFER_WRITE; |
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159 | |||
160 | /* Wait for the previous DMAs to complete */ |
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161 | /* TODO: keep one DMA (at half the size) in the background */ |
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162 | if (y) { |
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163 | svga_context_flush(svga, NULL); |
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164 | usage |= PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE; |
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165 | } |
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166 | |||
167 | hw = sws->buffer_map(sws, st->hwbuf, usage); |
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168 | assert(hw); |
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169 | if (hw) { |
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170 | memcpy(hw, sw, length); |
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171 | sws->buffer_unmap(sws, st->hwbuf); |
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172 | } |
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173 | } |
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174 | |||
175 | svga_transfer_dma_band(svga, st, transfer, y, h, srcy, flags); |
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176 | |||
177 | /* |
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178 | * Prevent the texture contents to be discarded on the next band |
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179 | * upload. |
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180 | */ |
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181 | |||
182 | flags.discard = FALSE; |
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183 | |||
184 | if(transfer == SVGA3D_READ_HOST_VRAM) { |
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185 | svga_context_flush(svga, &fence); |
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186 | sws->fence_finish(sws, fence, 0); |
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187 | |||
188 | hw = sws->buffer_map(sws, st->hwbuf, PIPE_TRANSFER_READ); |
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189 | assert(hw); |
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190 | if(hw) { |
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191 | memcpy(sw, hw, length); |
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192 | sws->buffer_unmap(sws, st->hwbuf); |
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193 | } |
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194 | } |
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195 | } |
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196 | } |
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197 | } |
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198 | |||
199 | |||
200 | static boolean |
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201 | svga_texture_get_handle(struct pipe_screen *screen, |
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202 | struct pipe_resource *texture, |
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203 | struct winsys_handle *whandle) |
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204 | { |
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205 | struct svga_winsys_screen *sws = svga_winsys_screen(texture->screen); |
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206 | unsigned stride; |
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207 | |||
208 | assert(svga_texture(texture)->key.cachable == 0); |
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209 | svga_texture(texture)->key.cachable = 0; |
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210 | stride = util_format_get_nblocksx(texture->format, texture->width0) * |
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211 | util_format_get_blocksize(texture->format); |
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212 | return sws->surface_get_handle(sws, svga_texture(texture)->handle, stride, whandle); |
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213 | } |
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214 | |||
215 | |||
216 | static void |
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217 | svga_texture_destroy(struct pipe_screen *screen, |
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218 | struct pipe_resource *pt) |
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219 | { |
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220 | struct svga_screen *ss = svga_screen(screen); |
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221 | struct svga_texture *tex = svga_texture(pt); |
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222 | |||
223 | ss->texture_timestamp++; |
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224 | |||
225 | svga_sampler_view_reference(&tex->cached_view, NULL); |
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226 | |||
227 | /* |
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228 | DBG("%s deleting %p\n", __FUNCTION__, (void *) tex); |
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229 | */ |
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230 | SVGA_DBG(DEBUG_DMA, "unref sid %p (texture)\n", tex->handle); |
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231 | svga_screen_surface_destroy(ss, &tex->key, &tex->handle); |
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232 | |||
233 | ss->total_resource_bytes -= tex->size; |
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234 | |||
235 | FREE(tex); |
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236 | } |
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237 | |||
238 | |||
239 | /* XXX: Still implementing this as if it was a screen function, but |
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240 | * can now modify it to queue transfers on the context. |
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241 | */ |
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242 | static void * |
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243 | svga_texture_transfer_map(struct pipe_context *pipe, |
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244 | struct pipe_resource *texture, |
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245 | unsigned level, |
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246 | unsigned usage, |
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247 | const struct pipe_box *box, |
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248 | struct pipe_transfer **ptransfer) |
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249 | { |
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250 | struct svga_context *svga = svga_context(pipe); |
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251 | struct svga_screen *ss = svga_screen(pipe->screen); |
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252 | struct svga_winsys_screen *sws = ss->sws; |
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253 | struct svga_transfer *st; |
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254 | unsigned nblocksx = util_format_get_nblocksx(texture->format, box->width); |
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255 | unsigned nblocksy = util_format_get_nblocksy(texture->format, box->height); |
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256 | |||
257 | /* We can't map texture storage directly */ |
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258 | if (usage & PIPE_TRANSFER_MAP_DIRECTLY) |
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259 | return NULL; |
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260 | |||
261 | st = CALLOC_STRUCT(svga_transfer); |
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262 | if (!st) |
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263 | return NULL; |
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264 | |||
265 | st->base.resource = texture; |
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266 | st->base.level = level; |
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267 | st->base.usage = usage; |
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268 | st->base.box = *box; |
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269 | st->base.stride = nblocksx*util_format_get_blocksize(texture->format); |
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270 | st->base.layer_stride = st->base.stride * nblocksy; |
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271 | |||
272 | st->hw_nblocksy = nblocksy; |
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273 | |||
274 | st->hwbuf = svga_winsys_buffer_create(svga, |
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275 | 1, |
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276 | 0, |
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277 | st->hw_nblocksy * st->base.stride * box->depth); |
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278 | while(!st->hwbuf && (st->hw_nblocksy /= 2)) { |
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279 | st->hwbuf = svga_winsys_buffer_create(svga, |
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280 | 1, |
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281 | 0, |
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282 | st->hw_nblocksy * st->base.stride * box->depth); |
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283 | } |
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284 | |||
285 | if(!st->hwbuf) |
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286 | goto no_hwbuf; |
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287 | |||
288 | if(st->hw_nblocksy < nblocksy) { |
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289 | /* We couldn't allocate a hardware buffer big enough for the transfer, |
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290 | * so allocate regular malloc memory instead */ |
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291 | if (0) { |
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292 | debug_printf("%s: failed to allocate %u KB of DMA, " |
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293 | "splitting into %u x %u KB DMA transfers\n", |
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294 | __FUNCTION__, |
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295 | (nblocksy*st->base.stride + 1023)/1024, |
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296 | (nblocksy + st->hw_nblocksy - 1)/st->hw_nblocksy, |
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297 | (st->hw_nblocksy*st->base.stride + 1023)/1024); |
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298 | } |
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299 | |||
300 | st->swbuf = MALLOC(nblocksy*st->base.stride); |
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301 | if(!st->swbuf) |
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302 | goto no_swbuf; |
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303 | } |
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304 | |||
305 | if (usage & PIPE_TRANSFER_READ) { |
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306 | SVGA3dSurfaceDMAFlags flags; |
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307 | memset(&flags, 0, sizeof flags); |
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308 | svga_transfer_dma(svga, st, SVGA3D_READ_HOST_VRAM, flags); |
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309 | } |
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310 | |||
311 | if (st->swbuf) { |
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312 | *ptransfer = &st->base; |
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313 | return st->swbuf; |
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314 | } else { |
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315 | /* The wait for read transfers already happened when svga_transfer_dma |
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316 | * was called. */ |
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317 | void *map = sws->buffer_map(sws, st->hwbuf, usage); |
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318 | if (!map) |
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319 | goto fail; |
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320 | |||
321 | *ptransfer = &st->base; |
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322 | return map; |
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323 | } |
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324 | |||
325 | fail: |
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326 | FREE(st->swbuf); |
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327 | no_swbuf: |
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328 | sws->buffer_destroy(sws, st->hwbuf); |
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329 | no_hwbuf: |
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330 | FREE(st); |
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331 | return NULL; |
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332 | } |
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333 | |||
334 | |||
335 | /* XXX: Still implementing this as if it was a screen function, but |
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336 | * can now modify it to queue transfers on the context. |
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337 | */ |
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338 | static void |
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339 | svga_texture_transfer_unmap(struct pipe_context *pipe, |
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340 | struct pipe_transfer *transfer) |
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341 | { |
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342 | struct svga_context *svga = svga_context(pipe); |
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343 | struct svga_screen *ss = svga_screen(pipe->screen); |
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344 | struct svga_winsys_screen *sws = ss->sws; |
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345 | struct svga_transfer *st = svga_transfer(transfer); |
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346 | struct svga_texture *tex = svga_texture(transfer->resource); |
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347 | |||
348 | if(!st->swbuf) |
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349 | sws->buffer_unmap(sws, st->hwbuf); |
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350 | |||
351 | if (st->base.usage & PIPE_TRANSFER_WRITE) { |
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352 | SVGA3dSurfaceDMAFlags flags; |
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353 | |||
354 | memset(&flags, 0, sizeof flags); |
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355 | if (transfer->usage & PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE) { |
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356 | flags.discard = TRUE; |
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357 | } |
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358 | if (transfer->usage & PIPE_TRANSFER_UNSYNCHRONIZED) { |
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359 | flags.unsynchronized = TRUE; |
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360 | } |
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361 | |||
362 | svga_transfer_dma(svga, st, SVGA3D_WRITE_HOST_VRAM, flags); |
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363 | ss->texture_timestamp++; |
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364 | svga_age_texture_view(tex, transfer->level); |
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365 | if (transfer->resource->target == PIPE_TEXTURE_CUBE) |
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366 | svga_define_texture_level(tex, transfer->box.z, transfer->level); |
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367 | else |
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368 | svga_define_texture_level(tex, 0, transfer->level); |
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369 | } |
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370 | |||
371 | FREE(st->swbuf); |
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372 | sws->buffer_destroy(sws, st->hwbuf); |
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373 | FREE(st); |
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374 | } |
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375 | |||
376 | |||
377 | struct u_resource_vtbl svga_texture_vtbl = |
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378 | { |
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379 | svga_texture_get_handle, /* get_handle */ |
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380 | svga_texture_destroy, /* resource_destroy */ |
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381 | svga_texture_transfer_map, /* transfer_map */ |
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382 | u_default_transfer_flush_region, /* transfer_flush_region */ |
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383 | svga_texture_transfer_unmap, /* transfer_unmap */ |
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384 | u_default_transfer_inline_write /* transfer_inline_write */ |
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385 | }; |
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386 | |||
387 | |||
388 | struct pipe_resource * |
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389 | svga_texture_create(struct pipe_screen *screen, |
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390 | const struct pipe_resource *template) |
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391 | { |
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392 | struct svga_screen *svgascreen = svga_screen(screen); |
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393 | struct svga_texture *tex = CALLOC_STRUCT(svga_texture); |
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394 | |||
395 | if (!tex) |
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396 | goto error1; |
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397 | |||
398 | tex->b.b = *template; |
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399 | tex->b.vtbl = &svga_texture_vtbl; |
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400 | pipe_reference_init(&tex->b.b.reference, 1); |
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401 | tex->b.b.screen = screen; |
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402 | |||
403 | assert(template->last_level < SVGA_MAX_TEXTURE_LEVELS); |
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404 | if(template->last_level >= SVGA_MAX_TEXTURE_LEVELS) |
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405 | goto error2; |
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406 | |||
407 | tex->key.flags = 0; |
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408 | tex->key.size.width = template->width0; |
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409 | tex->key.size.height = template->height0; |
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410 | tex->key.size.depth = template->depth0; |
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411 | |||
412 | if(template->target == PIPE_TEXTURE_CUBE) { |
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413 | tex->key.flags |= SVGA3D_SURFACE_CUBEMAP; |
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414 | tex->key.numFaces = 6; |
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415 | } |
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416 | else { |
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417 | tex->key.numFaces = 1; |
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418 | } |
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419 | |||
420 | if (template->target == PIPE_TEXTURE_3D) { |
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421 | tex->key.flags |= SVGA3D_SURFACE_HINT_VOLUME; |
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422 | } |
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423 | |||
424 | tex->key.cachable = 1; |
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425 | |||
426 | if (template->bind & PIPE_BIND_SAMPLER_VIEW) |
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427 | tex->key.flags |= SVGA3D_SURFACE_HINT_TEXTURE; |
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428 | |||
429 | if (template->bind & PIPE_BIND_DISPLAY_TARGET) { |
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430 | tex->key.cachable = 0; |
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431 | } |
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432 | |||
433 | if (template->bind & PIPE_BIND_SHARED) { |
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434 | tex->key.cachable = 0; |
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435 | } |
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436 | |||
437 | if (template->bind & (PIPE_BIND_SCANOUT | |
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438 | PIPE_BIND_CURSOR)) { |
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439 | tex->key.flags |= SVGA3D_SURFACE_HINT_SCANOUT; |
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440 | tex->key.cachable = 0; |
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441 | } |
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442 | |||
443 | /* |
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444 | * Note: Previously we never passed the |
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445 | * SVGA3D_SURFACE_HINT_RENDERTARGET hint. Mesa cannot |
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446 | * know beforehand whether a texture will be used as a rendertarget or not |
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447 | * and it always requests PIPE_BIND_RENDER_TARGET, therefore |
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448 | * passing the SVGA3D_SURFACE_HINT_RENDERTARGET here defeats its purpose. |
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449 | * |
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450 | * However, this was changed since other state trackers |
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451 | * (XA for example) uses it accurately and certain device versions |
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452 | * relies on it in certain situations to render correctly. |
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453 | */ |
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454 | if((template->bind & PIPE_BIND_RENDER_TARGET) && |
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455 | !util_format_is_s3tc(template->format)) |
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456 | tex->key.flags |= SVGA3D_SURFACE_HINT_RENDERTARGET; |
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457 | |||
458 | if(template->bind & PIPE_BIND_DEPTH_STENCIL) |
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459 | tex->key.flags |= SVGA3D_SURFACE_HINT_DEPTHSTENCIL; |
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460 | |||
461 | tex->key.numMipLevels = template->last_level + 1; |
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462 | |||
463 | tex->key.format = svga_translate_format(svgascreen, template->format, template->bind); |
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464 | if(tex->key.format == SVGA3D_FORMAT_INVALID) |
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465 | goto error2; |
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466 | |||
467 | SVGA_DBG(DEBUG_DMA, "surface_create for texture\n", tex->handle); |
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468 | tex->handle = svga_screen_surface_create(svgascreen, &tex->key); |
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469 | if (tex->handle) |
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470 | SVGA_DBG(DEBUG_DMA, " --> got sid %p (texture)\n", tex->handle); |
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471 | |||
472 | debug_reference(&tex->b.b.reference, |
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473 | (debug_reference_descriptor)debug_describe_resource, 0); |
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474 | |||
475 | tex->size = util_resource_size(template); |
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476 | svgascreen->total_resource_bytes += tex->size; |
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477 | |||
478 | return &tex->b.b; |
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479 | |||
480 | error2: |
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481 | FREE(tex); |
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482 | error1: |
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483 | return NULL; |
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484 | } |
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485 | |||
486 | |||
487 | struct pipe_resource * |
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488 | svga_texture_from_handle(struct pipe_screen *screen, |
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489 | const struct pipe_resource *template, |
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490 | struct winsys_handle *whandle) |
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491 | { |
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492 | struct svga_winsys_screen *sws = svga_winsys_screen(screen); |
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493 | struct svga_winsys_surface *srf; |
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494 | struct svga_texture *tex; |
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495 | enum SVGA3dSurfaceFormat format = 0; |
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496 | assert(screen); |
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497 | |||
498 | /* Only supports one type */ |
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499 | if ((template->target != PIPE_TEXTURE_2D && |
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500 | template->target != PIPE_TEXTURE_RECT) || |
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501 | template->last_level != 0 || |
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502 | template->depth0 != 1) { |
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503 | return NULL; |
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504 | } |
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505 | |||
506 | srf = sws->surface_from_handle(sws, whandle, &format); |
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507 | |||
508 | if (!srf) |
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509 | return NULL; |
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510 | |||
511 | if (svga_translate_format(svga_screen(screen), template->format, template->bind) != format) { |
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512 | unsigned f1 = svga_translate_format(svga_screen(screen), template->format, template->bind); |
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513 | unsigned f2 = format; |
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514 | |||
515 | /* It's okay for XRGB and ARGB or depth with/out stencil to get mixed up */ |
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516 | if ( !( (f1 == SVGA3D_X8R8G8B8 && f2 == SVGA3D_A8R8G8B8) || |
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517 | (f1 == SVGA3D_A8R8G8B8 && f2 == SVGA3D_X8R8G8B8) || |
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518 | (f1 == SVGA3D_Z_D24X8 && f2 == SVGA3D_Z_D24S8) || |
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519 | (f1 == SVGA3D_Z_DF24 && f2 == SVGA3D_Z_D24S8_INT) ) ) { |
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520 | debug_printf("%s wrong format %u != %u\n", __FUNCTION__, f1, f2); |
||
521 | return NULL; |
||
522 | } |
||
523 | } |
||
524 | |||
525 | tex = CALLOC_STRUCT(svga_texture); |
||
526 | if (!tex) |
||
527 | return NULL; |
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528 | |||
529 | tex->b.b = *template; |
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530 | tex->b.vtbl = &svga_texture_vtbl; |
||
531 | pipe_reference_init(&tex->b.b.reference, 1); |
||
532 | tex->b.b.screen = screen; |
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533 | |||
534 | SVGA_DBG(DEBUG_DMA, "wrap surface sid %p\n", srf); |
||
535 | |||
536 | tex->key.cachable = 0; |
||
537 | tex->handle = srf; |
||
538 | |||
539 | return &tex->b.b; |
||
540 | }>>>><> |