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4358 | Serge | 1 | #ifndef ADRENO_PM4_XML |
2 | #define ADRENO_PM4_XML |
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3 | |||
4 | /* Autogenerated file, DO NOT EDIT manually! |
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5 | |||
6 | This file was generated by the rules-ng-ng headergen tool in this git repository: |
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7 | http://0x04.net/cgit/index.cgi/rules-ng-ng |
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8 | git clone git://0x04.net/rules-ng-ng |
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9 | |||
10 | The rules-ng-ng source files this header was generated from are: |
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4401 | Serge | 11 | - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 327 bytes, from 2013-07-05 19:21:12) |
4358 | Serge | 12 | - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) |
4401 | Serge | 13 | - /home/robclark/src/freedreno/envytools/rnndb/a2xx/a2xx.xml ( 30005 bytes, from 2013-07-19 21:30:48) |
14 | - /home/robclark/src/freedreno/envytools/rnndb/adreno_common.xml ( 8983 bytes, from 2013-07-24 01:38:36) |
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4358 | Serge | 15 | - /home/robclark/src/freedreno/envytools/rnndb/adreno_pm4.xml ( 9712 bytes, from 2013-05-26 15:22:37) |
4401 | Serge | 16 | - /home/robclark/src/freedreno/envytools/rnndb/a3xx/a3xx.xml ( 51415 bytes, from 2013-08-03 14:26:05) |
4358 | Serge | 17 | |
18 | Copyright (C) 2013 by the following authors: |
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19 | - Rob Clark |
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20 | |||
21 | Permission is hereby granted, free of charge, to any person obtaining |
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22 | a copy of this software and associated documentation files (the |
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23 | "Software"), to deal in the Software without restriction, including |
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24 | without limitation the rights to use, copy, modify, merge, publish, |
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25 | distribute, sublicense, and/or sell copies of the Software, and to |
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26 | permit persons to whom the Software is furnished to do so, subject to |
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27 | the following conditions: |
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28 | |||
29 | The above copyright notice and this permission notice (including the |
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30 | next paragraph) shall be included in all copies or substantial |
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31 | portions of the Software. |
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32 | |||
33 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
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34 | EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
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35 | MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
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36 | IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE |
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37 | LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION |
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38 | OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION |
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39 | WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
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40 | */ |
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41 | |||
42 | |||
43 | enum vgt_event_type { |
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44 | VS_DEALLOC = 0, |
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45 | PS_DEALLOC = 1, |
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46 | VS_DONE_TS = 2, |
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47 | PS_DONE_TS = 3, |
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48 | CACHE_FLUSH_TS = 4, |
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49 | CONTEXT_DONE = 5, |
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50 | CACHE_FLUSH = 6, |
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51 | HLSQ_FLUSH = 7, |
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52 | VIZQUERY_START = 7, |
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53 | VIZQUERY_END = 8, |
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54 | SC_WAIT_WC = 9, |
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55 | RST_PIX_CNT = 13, |
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56 | RST_VTX_CNT = 14, |
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57 | TILE_FLUSH = 15, |
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58 | CACHE_FLUSH_AND_INV_TS_EVENT = 20, |
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59 | ZPASS_DONE = 21, |
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60 | CACHE_FLUSH_AND_INV_EVENT = 22, |
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61 | PERFCOUNTER_START = 23, |
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62 | PERFCOUNTER_STOP = 24, |
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63 | VS_FETCH_DONE = 27, |
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64 | FACENESS_FLUSH = 28, |
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65 | }; |
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66 | |||
67 | enum pc_di_primtype { |
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68 | DI_PT_NONE = 0, |
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69 | DI_PT_POINTLIST = 1, |
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70 | DI_PT_LINELIST = 2, |
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71 | DI_PT_LINESTRIP = 3, |
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72 | DI_PT_TRILIST = 4, |
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73 | DI_PT_TRIFAN = 5, |
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74 | DI_PT_TRISTRIP = 6, |
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75 | DI_PT_RECTLIST = 8, |
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76 | DI_PT_QUADLIST = 13, |
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77 | DI_PT_QUADSTRIP = 14, |
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78 | DI_PT_POLYGON = 15, |
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79 | DI_PT_2D_COPY_RECT_LIST_V0 = 16, |
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80 | DI_PT_2D_COPY_RECT_LIST_V1 = 17, |
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81 | DI_PT_2D_COPY_RECT_LIST_V2 = 18, |
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82 | DI_PT_2D_COPY_RECT_LIST_V3 = 19, |
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83 | DI_PT_2D_FILL_RECT_LIST = 20, |
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84 | DI_PT_2D_LINE_STRIP = 21, |
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85 | DI_PT_2D_TRI_STRIP = 22, |
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86 | }; |
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87 | |||
88 | enum pc_di_src_sel { |
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89 | DI_SRC_SEL_DMA = 0, |
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90 | DI_SRC_SEL_IMMEDIATE = 1, |
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91 | DI_SRC_SEL_AUTO_INDEX = 2, |
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92 | DI_SRC_SEL_RESERVED = 3, |
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93 | }; |
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94 | |||
95 | enum pc_di_index_size { |
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96 | INDEX_SIZE_IGN = 0, |
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97 | INDEX_SIZE_16_BIT = 0, |
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98 | INDEX_SIZE_32_BIT = 1, |
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99 | INDEX_SIZE_8_BIT = 2, |
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100 | INDEX_SIZE_INVALID = 0, |
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101 | }; |
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102 | |||
103 | enum pc_di_vis_cull_mode { |
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104 | IGNORE_VISIBILITY = 0, |
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105 | }; |
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106 | |||
107 | enum adreno_pm4_packet_type { |
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108 | CP_TYPE0_PKT = 0, |
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109 | CP_TYPE1_PKT = 0x40000000, |
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110 | CP_TYPE2_PKT = 0x80000000, |
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111 | CP_TYPE3_PKT = 0xc0000000, |
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112 | }; |
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113 | |||
114 | enum adreno_pm4_type3_packets { |
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115 | CP_ME_INIT = 72, |
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116 | CP_NOP = 16, |
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117 | CP_INDIRECT_BUFFER = 63, |
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118 | CP_INDIRECT_BUFFER_PFD = 55, |
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119 | CP_WAIT_FOR_IDLE = 38, |
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120 | CP_WAIT_REG_MEM = 60, |
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121 | CP_WAIT_REG_EQ = 82, |
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122 | CP_WAT_REG_GTE = 83, |
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123 | CP_WAIT_UNTIL_READ = 92, |
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124 | CP_WAIT_IB_PFD_COMPLETE = 93, |
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125 | CP_REG_RMW = 33, |
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126 | CP_SET_BIN_DATA = 47, |
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127 | CP_REG_TO_MEM = 62, |
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128 | CP_MEM_WRITE = 61, |
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129 | CP_MEM_WRITE_CNTR = 79, |
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130 | CP_COND_EXEC = 68, |
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131 | CP_COND_WRITE = 69, |
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132 | CP_EVENT_WRITE = 70, |
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133 | CP_EVENT_WRITE_SHD = 88, |
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134 | CP_EVENT_WRITE_CFL = 89, |
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135 | CP_EVENT_WRITE_ZPD = 91, |
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136 | CP_RUN_OPENCL = 49, |
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137 | CP_DRAW_INDX = 34, |
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138 | CP_DRAW_INDX_2 = 54, |
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139 | CP_DRAW_INDX_BIN = 52, |
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140 | CP_DRAW_INDX_2_BIN = 53, |
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141 | CP_VIZ_QUERY = 35, |
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142 | CP_SET_STATE = 37, |
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143 | CP_SET_CONSTANT = 45, |
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144 | CP_IM_LOAD = 39, |
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145 | CP_IM_LOAD_IMMEDIATE = 43, |
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146 | CP_LOAD_CONSTANT_CONTEXT = 46, |
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147 | CP_INVALIDATE_STATE = 59, |
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148 | CP_SET_SHADER_BASES = 74, |
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149 | CP_SET_BIN_MASK = 80, |
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150 | CP_SET_BIN_SELECT = 81, |
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151 | CP_CONTEXT_UPDATE = 94, |
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152 | CP_INTERRUPT = 64, |
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153 | CP_IM_STORE = 44, |
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154 | CP_SET_BIN_BASE_OFFSET = 75, |
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155 | CP_SET_DRAW_INIT_FLAGS = 75, |
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156 | CP_SET_PROTECTED_MODE = 95, |
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157 | CP_LOAD_STATE = 48, |
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158 | CP_COND_INDIRECT_BUFFER_PFE = 58, |
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159 | CP_COND_INDIRECT_BUFFER_PFD = 50, |
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160 | CP_INDIRECT_BUFFER_PFE = 63, |
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161 | CP_SET_BIN = 76, |
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162 | }; |
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163 | |||
164 | enum adreno_state_block { |
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165 | SB_VERT_TEX = 0, |
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166 | SB_VERT_MIPADDR = 1, |
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167 | SB_FRAG_TEX = 2, |
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168 | SB_FRAG_MIPADDR = 3, |
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169 | SB_VERT_SHADER = 4, |
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170 | SB_FRAG_SHADER = 6, |
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171 | }; |
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172 | |||
173 | enum adreno_state_type { |
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174 | ST_SHADER = 0, |
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175 | ST_CONSTANTS = 1, |
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176 | }; |
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177 | |||
178 | enum adreno_state_src { |
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179 | SS_DIRECT = 0, |
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180 | SS_INDIRECT = 4, |
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181 | }; |
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182 | |||
183 | #define REG_CP_LOAD_STATE_0 0x00000000 |
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184 | #define CP_LOAD_STATE_0_DST_OFF__MASK 0x0000ffff |
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185 | #define CP_LOAD_STATE_0_DST_OFF__SHIFT 0 |
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186 | static inline uint32_t CP_LOAD_STATE_0_DST_OFF(uint32_t val) |
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187 | { |
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188 | return ((val) << CP_LOAD_STATE_0_DST_OFF__SHIFT) & CP_LOAD_STATE_0_DST_OFF__MASK; |
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189 | } |
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190 | #define CP_LOAD_STATE_0_STATE_SRC__MASK 0x00070000 |
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191 | #define CP_LOAD_STATE_0_STATE_SRC__SHIFT 16 |
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192 | static inline uint32_t CP_LOAD_STATE_0_STATE_SRC(enum adreno_state_src val) |
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193 | { |
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194 | return ((val) << CP_LOAD_STATE_0_STATE_SRC__SHIFT) & CP_LOAD_STATE_0_STATE_SRC__MASK; |
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195 | } |
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196 | #define CP_LOAD_STATE_0_STATE_BLOCK__MASK 0x00380000 |
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197 | #define CP_LOAD_STATE_0_STATE_BLOCK__SHIFT 19 |
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198 | static inline uint32_t CP_LOAD_STATE_0_STATE_BLOCK(enum adreno_state_block val) |
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199 | { |
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200 | return ((val) << CP_LOAD_STATE_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE_0_STATE_BLOCK__MASK; |
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201 | } |
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202 | #define CP_LOAD_STATE_0_NUM_UNIT__MASK 0x7fc00000 |
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203 | #define CP_LOAD_STATE_0_NUM_UNIT__SHIFT 22 |
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204 | static inline uint32_t CP_LOAD_STATE_0_NUM_UNIT(uint32_t val) |
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205 | { |
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206 | return ((val) << CP_LOAD_STATE_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE_0_NUM_UNIT__MASK; |
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207 | } |
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208 | |||
209 | #define REG_CP_LOAD_STATE_1 0x00000001 |
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210 | #define CP_LOAD_STATE_1_STATE_TYPE__MASK 0x00000003 |
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211 | #define CP_LOAD_STATE_1_STATE_TYPE__SHIFT 0 |
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212 | static inline uint32_t CP_LOAD_STATE_1_STATE_TYPE(enum adreno_state_type val) |
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213 | { |
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214 | return ((val) << CP_LOAD_STATE_1_STATE_TYPE__SHIFT) & CP_LOAD_STATE_1_STATE_TYPE__MASK; |
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215 | } |
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216 | #define CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK 0xfffffffc |
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217 | #define CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT 2 |
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218 | static inline uint32_t CP_LOAD_STATE_1_EXT_SRC_ADDR(uint32_t val) |
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219 | { |
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220 | return ((val >> 2) << CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK; |
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221 | } |
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222 | |||
223 | #define REG_CP_SET_BIN_0 0x00000000 |
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224 | |||
225 | #define REG_CP_SET_BIN_1 0x00000001 |
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226 | #define CP_SET_BIN_1_X1__MASK 0x0000ffff |
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227 | #define CP_SET_BIN_1_X1__SHIFT 0 |
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228 | static inline uint32_t CP_SET_BIN_1_X1(uint32_t val) |
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229 | { |
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230 | return ((val) << CP_SET_BIN_1_X1__SHIFT) & CP_SET_BIN_1_X1__MASK; |
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231 | } |
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232 | #define CP_SET_BIN_1_Y1__MASK 0xffff0000 |
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233 | #define CP_SET_BIN_1_Y1__SHIFT 16 |
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234 | static inline uint32_t CP_SET_BIN_1_Y1(uint32_t val) |
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235 | { |
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236 | return ((val) << CP_SET_BIN_1_Y1__SHIFT) & CP_SET_BIN_1_Y1__MASK; |
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237 | } |
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238 | |||
239 | #define REG_CP_SET_BIN_2 0x00000002 |
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240 | #define CP_SET_BIN_2_X2__MASK 0x0000ffff |
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241 | #define CP_SET_BIN_2_X2__SHIFT 0 |
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242 | static inline uint32_t CP_SET_BIN_2_X2(uint32_t val) |
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243 | { |
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244 | return ((val) << CP_SET_BIN_2_X2__SHIFT) & CP_SET_BIN_2_X2__MASK; |
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245 | } |
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246 | #define CP_SET_BIN_2_Y2__MASK 0xffff0000 |
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247 | #define CP_SET_BIN_2_Y2__SHIFT 16 |
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248 | static inline uint32_t CP_SET_BIN_2_Y2(uint32_t val) |
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249 | { |
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250 | return ((val) << CP_SET_BIN_2_Y2__SHIFT) & CP_SET_BIN_2_Y2__MASK; |
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251 | } |
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252 | |||
253 | |||
254 | #endif /* ADRENO_PM4_XML */><>><>><>><>><>><>><>><>><>><> |