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4358 | Serge | 1 | #ifndef ADRENO_COMMON_XML |
2 | #define ADRENO_COMMON_XML |
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3 | |||
4 | /* Autogenerated file, DO NOT EDIT manually! |
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5 | |||
6 | This file was generated by the rules-ng-ng headergen tool in this git repository: |
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7 | http://0x04.net/cgit/index.cgi/rules-ng-ng |
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8 | git clone git://0x04.net/rules-ng-ng |
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9 | |||
10 | The rules-ng-ng source files this header was generated from are: |
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4401 | Serge | 11 | - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 327 bytes, from 2013-07-05 19:21:12) |
4358 | Serge | 12 | - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) |
4401 | Serge | 13 | - /home/robclark/src/freedreno/envytools/rnndb/a2xx/a2xx.xml ( 30005 bytes, from 2013-07-19 21:30:48) |
14 | - /home/robclark/src/freedreno/envytools/rnndb/adreno_common.xml ( 8983 bytes, from 2013-07-24 01:38:36) |
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4358 | Serge | 15 | - /home/robclark/src/freedreno/envytools/rnndb/adreno_pm4.xml ( 9712 bytes, from 2013-05-26 15:22:37) |
4401 | Serge | 16 | - /home/robclark/src/freedreno/envytools/rnndb/a3xx/a3xx.xml ( 51415 bytes, from 2013-08-03 14:26:05) |
4358 | Serge | 17 | |
18 | Copyright (C) 2013 by the following authors: |
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19 | - Rob Clark |
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20 | |||
21 | Permission is hereby granted, free of charge, to any person obtaining |
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22 | a copy of this software and associated documentation files (the |
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23 | "Software"), to deal in the Software without restriction, including |
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24 | without limitation the rights to use, copy, modify, merge, publish, |
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25 | distribute, sublicense, and/or sell copies of the Software, and to |
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26 | permit persons to whom the Software is furnished to do so, subject to |
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27 | the following conditions: |
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28 | |||
29 | The above copyright notice and this permission notice (including the |
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30 | next paragraph) shall be included in all copies or substantial |
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31 | portions of the Software. |
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32 | |||
33 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
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34 | EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
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35 | MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
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36 | IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE |
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37 | LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION |
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38 | OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION |
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39 | WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
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40 | */ |
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41 | |||
42 | |||
43 | enum adreno_pa_su_sc_draw { |
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44 | PC_DRAW_POINTS = 0, |
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45 | PC_DRAW_LINES = 1, |
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46 | PC_DRAW_TRIANGLES = 2, |
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47 | }; |
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48 | |||
49 | enum adreno_compare_func { |
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50 | FUNC_NEVER = 0, |
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51 | FUNC_LESS = 1, |
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52 | FUNC_EQUAL = 2, |
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53 | FUNC_LEQUAL = 3, |
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54 | FUNC_GREATER = 4, |
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55 | FUNC_NOTEQUAL = 5, |
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56 | FUNC_GEQUAL = 6, |
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57 | FUNC_ALWAYS = 7, |
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58 | }; |
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59 | |||
60 | enum adreno_stencil_op { |
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61 | STENCIL_KEEP = 0, |
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62 | STENCIL_ZERO = 1, |
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63 | STENCIL_REPLACE = 2, |
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64 | STENCIL_INCR_CLAMP = 3, |
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65 | STENCIL_DECR_CLAMP = 4, |
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66 | STENCIL_INVERT = 5, |
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67 | STENCIL_INCR_WRAP = 6, |
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68 | STENCIL_DECR_WRAP = 7, |
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69 | }; |
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70 | |||
71 | enum adreno_rb_blend_factor { |
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72 | FACTOR_ZERO = 0, |
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73 | FACTOR_ONE = 1, |
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74 | FACTOR_SRC_COLOR = 4, |
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75 | FACTOR_ONE_MINUS_SRC_COLOR = 5, |
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76 | FACTOR_SRC_ALPHA = 6, |
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77 | FACTOR_ONE_MINUS_SRC_ALPHA = 7, |
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78 | FACTOR_DST_COLOR = 8, |
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79 | FACTOR_ONE_MINUS_DST_COLOR = 9, |
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80 | FACTOR_DST_ALPHA = 10, |
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81 | FACTOR_ONE_MINUS_DST_ALPHA = 11, |
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82 | FACTOR_CONSTANT_COLOR = 12, |
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83 | FACTOR_ONE_MINUS_CONSTANT_COLOR = 13, |
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84 | FACTOR_CONSTANT_ALPHA = 14, |
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85 | FACTOR_ONE_MINUS_CONSTANT_ALPHA = 15, |
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86 | FACTOR_SRC_ALPHA_SATURATE = 16, |
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87 | }; |
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88 | |||
89 | enum adreno_rb_blend_opcode { |
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90 | BLEND_DST_PLUS_SRC = 0, |
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91 | BLEND_SRC_MINUS_DST = 1, |
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92 | BLEND_MIN_DST_SRC = 2, |
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93 | BLEND_MAX_DST_SRC = 3, |
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94 | BLEND_DST_MINUS_SRC = 4, |
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95 | BLEND_DST_PLUS_SRC_BIAS = 5, |
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96 | }; |
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97 | |||
98 | enum adreno_rb_surface_endian { |
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99 | ENDIAN_NONE = 0, |
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100 | ENDIAN_8IN16 = 1, |
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101 | ENDIAN_8IN32 = 2, |
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102 | ENDIAN_16IN32 = 3, |
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103 | ENDIAN_8IN64 = 4, |
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104 | ENDIAN_8IN128 = 5, |
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105 | }; |
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106 | |||
107 | enum adreno_rb_dither_mode { |
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108 | DITHER_DISABLE = 0, |
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109 | DITHER_ALWAYS = 1, |
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110 | DITHER_IF_ALPHA_OFF = 2, |
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111 | }; |
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112 | |||
113 | enum adreno_rb_depth_format { |
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114 | DEPTHX_16 = 0, |
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115 | DEPTHX_24_8 = 1, |
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116 | }; |
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117 | |||
4401 | Serge | 118 | enum adreno_mmu_clnt_beh { |
119 | BEH_NEVR = 0, |
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120 | BEH_TRAN_RNG = 1, |
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121 | BEH_TRAN_FLT = 2, |
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122 | }; |
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4358 | Serge | 123 | |
4401 | Serge | 124 | #define REG_AXXX_MH_MMU_CONFIG 0x00000040 |
125 | #define AXXX_MH_MMU_CONFIG_MMU_ENABLE 0x00000001 |
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126 | #define AXXX_MH_MMU_CONFIG_SPLIT_MODE_ENABLE 0x00000002 |
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127 | #define AXXX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__MASK 0x00000030 |
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128 | #define AXXX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__SHIFT 4 |
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129 | static inline uint32_t AXXX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) |
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130 | { |
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131 | return ((val) << AXXX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__MASK; |
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132 | } |
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133 | #define AXXX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__MASK 0x000000c0 |
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134 | #define AXXX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__SHIFT 6 |
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135 | static inline uint32_t AXXX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) |
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136 | { |
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137 | return ((val) << AXXX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__MASK; |
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138 | } |
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139 | #define AXXX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__MASK 0x00000300 |
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140 | #define AXXX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__SHIFT 8 |
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141 | static inline uint32_t AXXX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) |
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142 | { |
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143 | return ((val) << AXXX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__MASK; |
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144 | } |
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145 | #define AXXX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__MASK 0x00000c00 |
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146 | #define AXXX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__SHIFT 10 |
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147 | static inline uint32_t AXXX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) |
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148 | { |
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149 | return ((val) << AXXX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__MASK; |
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150 | } |
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151 | #define AXXX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__MASK 0x00003000 |
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152 | #define AXXX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__SHIFT 12 |
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153 | static inline uint32_t AXXX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) |
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154 | { |
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155 | return ((val) << AXXX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__MASK; |
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156 | } |
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157 | #define AXXX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__MASK 0x0000c000 |
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158 | #define AXXX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__SHIFT 14 |
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159 | static inline uint32_t AXXX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) |
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160 | { |
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161 | return ((val) << AXXX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__MASK; |
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162 | } |
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163 | #define AXXX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__MASK 0x00030000 |
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164 | #define AXXX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__SHIFT 16 |
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165 | static inline uint32_t AXXX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) |
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166 | { |
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167 | return ((val) << AXXX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__MASK; |
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168 | } |
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169 | #define AXXX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__MASK 0x000c0000 |
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170 | #define AXXX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__SHIFT 18 |
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171 | static inline uint32_t AXXX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) |
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172 | { |
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173 | return ((val) << AXXX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__MASK; |
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174 | } |
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175 | #define AXXX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__MASK 0x00300000 |
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176 | #define AXXX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__SHIFT 20 |
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177 | static inline uint32_t AXXX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) |
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178 | { |
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179 | return ((val) << AXXX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__MASK; |
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180 | } |
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181 | #define AXXX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__MASK 0x00c00000 |
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182 | #define AXXX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__SHIFT 22 |
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183 | static inline uint32_t AXXX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) |
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184 | { |
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185 | return ((val) << AXXX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__MASK; |
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186 | } |
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187 | #define AXXX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__MASK 0x03000000 |
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188 | #define AXXX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__SHIFT 24 |
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189 | static inline uint32_t AXXX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) |
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190 | { |
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191 | return ((val) << AXXX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__MASK; |
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192 | } |
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193 | |||
194 | #define REG_AXXX_MH_MMU_VA_RANGE 0x00000041 |
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195 | |||
196 | #define REG_AXXX_MH_MMU_PT_BASE 0x00000042 |
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197 | |||
198 | #define REG_AXXX_MH_MMU_PAGE_FAULT 0x00000043 |
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199 | |||
200 | #define REG_AXXX_MH_MMU_TRAN_ERROR 0x00000044 |
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201 | |||
202 | #define REG_AXXX_MH_MMU_INVALIDATE 0x00000045 |
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203 | |||
204 | #define REG_AXXX_MH_MMU_MPU_BASE 0x00000046 |
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205 | |||
206 | #define REG_AXXX_MH_MMU_MPU_END 0x00000047 |
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207 | |||
208 | #define REG_AXXX_CP_RB_BASE 0x000001c0 |
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209 | |||
210 | #define REG_AXXX_CP_RB_CNTL 0x000001c1 |
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211 | #define AXXX_CP_RB_CNTL_BUFSZ__MASK 0x0000003f |
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212 | #define AXXX_CP_RB_CNTL_BUFSZ__SHIFT 0 |
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213 | static inline uint32_t AXXX_CP_RB_CNTL_BUFSZ(uint32_t val) |
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214 | { |
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215 | return ((val) << AXXX_CP_RB_CNTL_BUFSZ__SHIFT) & AXXX_CP_RB_CNTL_BUFSZ__MASK; |
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216 | } |
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217 | #define AXXX_CP_RB_CNTL_BLKSZ__MASK 0x00003f00 |
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218 | #define AXXX_CP_RB_CNTL_BLKSZ__SHIFT 8 |
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219 | static inline uint32_t AXXX_CP_RB_CNTL_BLKSZ(uint32_t val) |
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220 | { |
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221 | return ((val) << AXXX_CP_RB_CNTL_BLKSZ__SHIFT) & AXXX_CP_RB_CNTL_BLKSZ__MASK; |
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222 | } |
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223 | #define AXXX_CP_RB_CNTL_BUF_SWAP__MASK 0x00030000 |
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224 | #define AXXX_CP_RB_CNTL_BUF_SWAP__SHIFT 16 |
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225 | static inline uint32_t AXXX_CP_RB_CNTL_BUF_SWAP(uint32_t val) |
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226 | { |
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227 | return ((val) << AXXX_CP_RB_CNTL_BUF_SWAP__SHIFT) & AXXX_CP_RB_CNTL_BUF_SWAP__MASK; |
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228 | } |
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229 | #define AXXX_CP_RB_CNTL_POLL_EN 0x00100000 |
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230 | #define AXXX_CP_RB_CNTL_NO_UPDATE 0x08000000 |
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231 | #define AXXX_CP_RB_CNTL_RPTR_WR_EN 0x80000000 |
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232 | |||
233 | #define REG_AXXX_CP_RB_RPTR_ADDR 0x000001c3 |
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234 | #define AXXX_CP_RB_RPTR_ADDR_SWAP__MASK 0x00000003 |
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235 | #define AXXX_CP_RB_RPTR_ADDR_SWAP__SHIFT 0 |
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236 | static inline uint32_t AXXX_CP_RB_RPTR_ADDR_SWAP(uint32_t val) |
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237 | { |
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238 | return ((val) << AXXX_CP_RB_RPTR_ADDR_SWAP__SHIFT) & AXXX_CP_RB_RPTR_ADDR_SWAP__MASK; |
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239 | } |
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240 | #define AXXX_CP_RB_RPTR_ADDR_ADDR__MASK 0xfffffffc |
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241 | #define AXXX_CP_RB_RPTR_ADDR_ADDR__SHIFT 2 |
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242 | static inline uint32_t AXXX_CP_RB_RPTR_ADDR_ADDR(uint32_t val) |
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243 | { |
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244 | return ((val >> 2) << AXXX_CP_RB_RPTR_ADDR_ADDR__SHIFT) & AXXX_CP_RB_RPTR_ADDR_ADDR__MASK; |
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245 | } |
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246 | |||
247 | #define REG_AXXX_CP_RB_RPTR 0x000001c4 |
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248 | |||
249 | #define REG_AXXX_CP_RB_WPTR 0x000001c5 |
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250 | |||
251 | #define REG_AXXX_CP_RB_WPTR_DELAY 0x000001c6 |
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252 | |||
253 | #define REG_AXXX_CP_RB_RPTR_WR 0x000001c7 |
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254 | |||
255 | #define REG_AXXX_CP_RB_WPTR_BASE 0x000001c8 |
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256 | |||
257 | #define REG_AXXX_CP_QUEUE_THRESHOLDS 0x000001d5 |
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258 | #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__MASK 0x0000000f |
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259 | #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__SHIFT 0 |
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260 | static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START(uint32_t val) |
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261 | { |
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262 | return ((val) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__MASK; |
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263 | } |
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264 | #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__MASK 0x00000f00 |
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265 | #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__SHIFT 8 |
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266 | static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START(uint32_t val) |
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267 | { |
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268 | return ((val) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__MASK; |
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269 | } |
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270 | #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__MASK 0x000f0000 |
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271 | #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__SHIFT 16 |
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272 | static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START(uint32_t val) |
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273 | { |
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274 | return ((val) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__MASK; |
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275 | } |
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276 | |||
277 | #define REG_AXXX_CP_MEQ_THRESHOLDS 0x000001d6 |
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278 | |||
279 | #define REG_AXXX_CP_CSQ_AVAIL 0x000001d7 |
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280 | #define AXXX_CP_CSQ_AVAIL_RING__MASK 0x0000007f |
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281 | #define AXXX_CP_CSQ_AVAIL_RING__SHIFT 0 |
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282 | static inline uint32_t AXXX_CP_CSQ_AVAIL_RING(uint32_t val) |
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283 | { |
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284 | return ((val) << AXXX_CP_CSQ_AVAIL_RING__SHIFT) & AXXX_CP_CSQ_AVAIL_RING__MASK; |
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285 | } |
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286 | #define AXXX_CP_CSQ_AVAIL_IB1__MASK 0x00007f00 |
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287 | #define AXXX_CP_CSQ_AVAIL_IB1__SHIFT 8 |
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288 | static inline uint32_t AXXX_CP_CSQ_AVAIL_IB1(uint32_t val) |
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289 | { |
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290 | return ((val) << AXXX_CP_CSQ_AVAIL_IB1__SHIFT) & AXXX_CP_CSQ_AVAIL_IB1__MASK; |
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291 | } |
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292 | #define AXXX_CP_CSQ_AVAIL_IB2__MASK 0x007f0000 |
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293 | #define AXXX_CP_CSQ_AVAIL_IB2__SHIFT 16 |
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294 | static inline uint32_t AXXX_CP_CSQ_AVAIL_IB2(uint32_t val) |
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295 | { |
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296 | return ((val) << AXXX_CP_CSQ_AVAIL_IB2__SHIFT) & AXXX_CP_CSQ_AVAIL_IB2__MASK; |
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297 | } |
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298 | |||
299 | #define REG_AXXX_CP_STQ_AVAIL 0x000001d8 |
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300 | #define AXXX_CP_STQ_AVAIL_ST__MASK 0x0000007f |
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301 | #define AXXX_CP_STQ_AVAIL_ST__SHIFT 0 |
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302 | static inline uint32_t AXXX_CP_STQ_AVAIL_ST(uint32_t val) |
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303 | { |
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304 | return ((val) << AXXX_CP_STQ_AVAIL_ST__SHIFT) & AXXX_CP_STQ_AVAIL_ST__MASK; |
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305 | } |
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306 | |||
307 | #define REG_AXXX_CP_MEQ_AVAIL 0x000001d9 |
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308 | #define AXXX_CP_MEQ_AVAIL_MEQ__MASK 0x0000001f |
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309 | #define AXXX_CP_MEQ_AVAIL_MEQ__SHIFT 0 |
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310 | static inline uint32_t AXXX_CP_MEQ_AVAIL_MEQ(uint32_t val) |
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311 | { |
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312 | return ((val) << AXXX_CP_MEQ_AVAIL_MEQ__SHIFT) & AXXX_CP_MEQ_AVAIL_MEQ__MASK; |
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313 | } |
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314 | |||
315 | #define REG_AXXX_SCRATCH_UMSK 0x000001dc |
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316 | #define AXXX_SCRATCH_UMSK_UMSK__MASK 0x000000ff |
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317 | #define AXXX_SCRATCH_UMSK_UMSK__SHIFT 0 |
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318 | static inline uint32_t AXXX_SCRATCH_UMSK_UMSK(uint32_t val) |
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319 | { |
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320 | return ((val) << AXXX_SCRATCH_UMSK_UMSK__SHIFT) & AXXX_SCRATCH_UMSK_UMSK__MASK; |
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321 | } |
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322 | #define AXXX_SCRATCH_UMSK_SWAP__MASK 0x00030000 |
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323 | #define AXXX_SCRATCH_UMSK_SWAP__SHIFT 16 |
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324 | static inline uint32_t AXXX_SCRATCH_UMSK_SWAP(uint32_t val) |
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325 | { |
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326 | return ((val) << AXXX_SCRATCH_UMSK_SWAP__SHIFT) & AXXX_SCRATCH_UMSK_SWAP__MASK; |
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327 | } |
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328 | |||
329 | #define REG_AXXX_SCRATCH_ADDR 0x000001dd |
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330 | |||
331 | #define REG_AXXX_CP_ME_RDADDR 0x000001ea |
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332 | |||
333 | #define REG_AXXX_CP_STATE_DEBUG_INDEX 0x000001ec |
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334 | |||
335 | #define REG_AXXX_CP_STATE_DEBUG_DATA 0x000001ed |
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336 | |||
337 | #define REG_AXXX_CP_INT_CNTL 0x000001f2 |
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338 | |||
339 | #define REG_AXXX_CP_INT_STATUS 0x000001f3 |
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340 | |||
341 | #define REG_AXXX_CP_INT_ACK 0x000001f4 |
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342 | |||
343 | #define REG_AXXX_CP_ME_CNTL 0x000001f6 |
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344 | |||
345 | #define REG_AXXX_CP_ME_STATUS 0x000001f7 |
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346 | |||
347 | #define REG_AXXX_CP_ME_RAM_WADDR 0x000001f8 |
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348 | |||
349 | #define REG_AXXX_CP_ME_RAM_RADDR 0x000001f9 |
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350 | |||
351 | #define REG_AXXX_CP_ME_RAM_DATA 0x000001fa |
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352 | |||
353 | #define REG_AXXX_CP_DEBUG 0x000001fc |
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354 | #define AXXX_CP_DEBUG_PREDICATE_DISABLE 0x00800000 |
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355 | #define AXXX_CP_DEBUG_PROG_END_PTR_ENABLE 0x01000000 |
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356 | #define AXXX_CP_DEBUG_MIU_128BIT_WRITE_ENABLE 0x02000000 |
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357 | #define AXXX_CP_DEBUG_PREFETCH_PASS_NOPS 0x04000000 |
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358 | #define AXXX_CP_DEBUG_DYNAMIC_CLK_DISABLE 0x08000000 |
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359 | #define AXXX_CP_DEBUG_PREFETCH_MATCH_DISABLE 0x10000000 |
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360 | #define AXXX_CP_DEBUG_SIMPLE_ME_FLOW_CONTROL 0x40000000 |
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361 | #define AXXX_CP_DEBUG_MIU_WRITE_PACK_DISABLE 0x80000000 |
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362 | |||
363 | #define REG_AXXX_CP_CSQ_RB_STAT 0x000001fd |
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364 | #define AXXX_CP_CSQ_RB_STAT_RPTR__MASK 0x0000007f |
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365 | #define AXXX_CP_CSQ_RB_STAT_RPTR__SHIFT 0 |
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366 | static inline uint32_t AXXX_CP_CSQ_RB_STAT_RPTR(uint32_t val) |
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367 | { |
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368 | return ((val) << AXXX_CP_CSQ_RB_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_RB_STAT_RPTR__MASK; |
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369 | } |
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370 | #define AXXX_CP_CSQ_RB_STAT_WPTR__MASK 0x007f0000 |
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371 | #define AXXX_CP_CSQ_RB_STAT_WPTR__SHIFT 16 |
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372 | static inline uint32_t AXXX_CP_CSQ_RB_STAT_WPTR(uint32_t val) |
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373 | { |
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374 | return ((val) << AXXX_CP_CSQ_RB_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_RB_STAT_WPTR__MASK; |
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375 | } |
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376 | |||
377 | #define REG_AXXX_CP_CSQ_IB1_STAT 0x000001fe |
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378 | #define AXXX_CP_CSQ_IB1_STAT_RPTR__MASK 0x0000007f |
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379 | #define AXXX_CP_CSQ_IB1_STAT_RPTR__SHIFT 0 |
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380 | static inline uint32_t AXXX_CP_CSQ_IB1_STAT_RPTR(uint32_t val) |
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381 | { |
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382 | return ((val) << AXXX_CP_CSQ_IB1_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_IB1_STAT_RPTR__MASK; |
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383 | } |
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384 | #define AXXX_CP_CSQ_IB1_STAT_WPTR__MASK 0x007f0000 |
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385 | #define AXXX_CP_CSQ_IB1_STAT_WPTR__SHIFT 16 |
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386 | static inline uint32_t AXXX_CP_CSQ_IB1_STAT_WPTR(uint32_t val) |
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387 | { |
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388 | return ((val) << AXXX_CP_CSQ_IB1_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_IB1_STAT_WPTR__MASK; |
||
389 | } |
||
390 | |||
391 | #define REG_AXXX_CP_CSQ_IB2_STAT 0x000001ff |
||
392 | #define AXXX_CP_CSQ_IB2_STAT_RPTR__MASK 0x0000007f |
||
393 | #define AXXX_CP_CSQ_IB2_STAT_RPTR__SHIFT 0 |
||
394 | static inline uint32_t AXXX_CP_CSQ_IB2_STAT_RPTR(uint32_t val) |
||
395 | { |
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396 | return ((val) << AXXX_CP_CSQ_IB2_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_IB2_STAT_RPTR__MASK; |
||
397 | } |
||
398 | #define AXXX_CP_CSQ_IB2_STAT_WPTR__MASK 0x007f0000 |
||
399 | #define AXXX_CP_CSQ_IB2_STAT_WPTR__SHIFT 16 |
||
400 | static inline uint32_t AXXX_CP_CSQ_IB2_STAT_WPTR(uint32_t val) |
||
401 | { |
||
402 | return ((val) << AXXX_CP_CSQ_IB2_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_IB2_STAT_WPTR__MASK; |
||
403 | } |
||
404 | |||
405 | #define REG_AXXX_CP_SCRATCH_REG0 0x00000578 |
||
406 | |||
407 | #define REG_AXXX_CP_SCRATCH_REG1 0x00000579 |
||
408 | |||
409 | #define REG_AXXX_CP_SCRATCH_REG2 0x0000057a |
||
410 | |||
411 | #define REG_AXXX_CP_SCRATCH_REG3 0x0000057b |
||
412 | |||
413 | #define REG_AXXX_CP_SCRATCH_REG4 0x0000057c |
||
414 | |||
415 | #define REG_AXXX_CP_SCRATCH_REG5 0x0000057d |
||
416 | |||
417 | #define REG_AXXX_CP_SCRATCH_REG6 0x0000057e |
||
418 | |||
419 | #define REG_AXXX_CP_SCRATCH_REG7 0x0000057f |
||
420 | |||
421 | #define REG_AXXX_CP_ME_CF_EVENT_SRC 0x0000060a |
||
422 | |||
423 | #define REG_AXXX_CP_ME_CF_EVENT_ADDR 0x0000060b |
||
424 | |||
425 | #define REG_AXXX_CP_ME_CF_EVENT_DATA 0x0000060c |
||
426 | |||
427 | #define REG_AXXX_CP_ME_NRT_ADDR 0x0000060d |
||
428 | |||
429 | #define REG_AXXX_CP_ME_NRT_DATA 0x0000060e |
||
430 | |||
431 | |||
4358 | Serge | 432 | #endif /* ADRENO_COMMON_XML */><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><> |