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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 4358 | Serge | 1 | /* |
| 2 | * Copyright (c) 2012 Rob Clark |
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| 3 | * |
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| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 5 | * copy of this software and associated documentation files (the "Software"), |
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| 6 | * to deal in the Software without restriction, including without limitation |
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| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 9 | * Software is furnished to do so, subject to the following conditions: |
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| 10 | * |
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| 11 | * The above copyright notice and this permission notice (including the next |
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| 12 | * paragraph) shall be included in all copies or substantial portions of the |
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| 13 | * Software. |
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| 14 | * |
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| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
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| 20 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
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| 21 | * SOFTWARE. |
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| 22 | */ |
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| 23 | |||
| 24 | #include "ir-a2xx.h" |
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| 25 | |||
| 26 | #include |
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| 27 | #include |
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| 28 | #include |
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| 29 | #include |
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| 30 | |||
| 31 | #include "freedreno_util.h" |
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| 32 | #include "instr-a2xx.h" |
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| 33 | |||
| 34 | #define DEBUG_MSG(f, ...) do { if (0) DBG(f, ##__VA_ARGS__); } while (0) |
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| 35 | #define WARN_MSG(f, ...) DBG("WARN: "f, ##__VA_ARGS__) |
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| 36 | #define ERROR_MSG(f, ...) DBG("ERROR: "f, ##__VA_ARGS__) |
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| 37 | |||
| 38 | #define REG_MASK 0x3f |
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| 39 | |||
| 40 | static int cf_emit(struct ir2_cf *cf, instr_cf_t *instr); |
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| 41 | |||
| 42 | static int instr_emit(struct ir2_instruction *instr, uint32_t *dwords, |
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| 43 | uint32_t idx, struct ir2_shader_info *info); |
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| 44 | |||
| 45 | static void reg_update_stats(struct ir2_register *reg, |
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| 46 | struct ir2_shader_info *info, bool dest); |
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| 47 | static uint32_t reg_fetch_src_swiz(struct ir2_register *reg, uint32_t n); |
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| 48 | static uint32_t reg_fetch_dst_swiz(struct ir2_register *reg); |
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| 49 | static uint32_t reg_alu_dst_swiz(struct ir2_register *reg); |
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| 50 | static uint32_t reg_alu_src_swiz(struct ir2_register *reg); |
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| 51 | |||
| 52 | /* simple allocator to carve allocations out of an up-front allocated heap, |
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| 53 | * so that we can free everything easily in one shot. |
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| 54 | */ |
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| 55 | static void * ir2_alloc(struct ir2_shader *shader, int sz) |
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| 56 | { |
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| 57 | void *ptr = &shader->heap[shader->heap_idx]; |
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| 58 | shader->heap_idx += align(sz, 4); |
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| 59 | return ptr; |
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| 60 | } |
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| 61 | |||
| 62 | static char * ir2_strdup(struct ir2_shader *shader, const char *str) |
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| 63 | { |
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| 64 | char *ptr = NULL; |
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| 65 | if (str) { |
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| 66 | int len = strlen(str); |
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| 67 | ptr = ir2_alloc(shader, len+1); |
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| 68 | memcpy(ptr, str, len); |
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| 69 | ptr[len] = '\0'; |
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| 70 | } |
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| 71 | return ptr; |
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| 72 | } |
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| 73 | |||
| 74 | struct ir2_shader * ir2_shader_create(void) |
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| 75 | { |
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| 76 | DEBUG_MSG(""); |
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| 77 | return calloc(1, sizeof(struct ir2_shader)); |
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| 78 | } |
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| 79 | |||
| 80 | void ir2_shader_destroy(struct ir2_shader *shader) |
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| 81 | { |
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| 82 | DEBUG_MSG(""); |
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| 83 | free(shader); |
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| 84 | } |
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| 85 | |||
| 86 | /* resolve addr/cnt/sequence fields in the individual CF's */ |
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| 87 | static int shader_resolve(struct ir2_shader *shader, struct ir2_shader_info *info) |
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| 88 | { |
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| 89 | uint32_t addr; |
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| 90 | unsigned i; |
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| 91 | int j; |
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| 92 | |||
| 93 | addr = shader->cfs_count / 2; |
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| 94 | for (i = 0; i < shader->cfs_count; i++) { |
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| 95 | struct ir2_cf *cf = shader->cfs[i]; |
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| 96 | if ((cf->cf_type == EXEC) || (cf->cf_type == EXEC_END)) { |
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| 97 | uint32_t sequence = 0; |
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| 98 | |||
| 99 | if (cf->exec.addr && (cf->exec.addr != addr)) |
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| 100 | WARN_MSG("invalid addr '%d' at CF %d", cf->exec.addr, i); |
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| 101 | if (cf->exec.cnt && (cf->exec.cnt != cf->exec.instrs_count)) |
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| 102 | WARN_MSG("invalid cnt '%d' at CF %d", cf->exec.cnt, i); |
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| 103 | |||
| 104 | for (j = cf->exec.instrs_count - 1; j >= 0; j--) { |
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| 105 | struct ir2_instruction *instr = cf->exec.instrs[j]; |
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| 106 | sequence <<= 2; |
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| 107 | if (instr->instr_type == IR2_FETCH) |
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| 108 | sequence |= 0x1; |
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| 109 | if (instr->sync) |
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| 110 | sequence |= 0x2; |
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| 111 | } |
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| 112 | |||
| 113 | cf->exec.addr = addr; |
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| 114 | cf->exec.cnt = cf->exec.instrs_count; |
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| 115 | cf->exec.sequence = sequence; |
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| 116 | |||
| 117 | addr += cf->exec.instrs_count; |
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| 118 | } |
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| 119 | } |
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| 120 | |||
| 121 | info->sizedwords = 3 * addr; |
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| 122 | |||
| 123 | return 0; |
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| 124 | } |
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| 125 | |||
| 126 | void * ir2_shader_assemble(struct ir2_shader *shader, struct ir2_shader_info *info) |
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| 127 | { |
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| 128 | uint32_t i, j; |
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| 129 | uint32_t *ptr, *dwords = NULL; |
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| 130 | uint32_t idx = 0; |
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| 131 | int ret; |
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| 132 | |||
| 133 | info->sizedwords = 0; |
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| 134 | info->max_reg = -1; |
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| 135 | info->max_input_reg = 0; |
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| 136 | info->regs_written = 0; |
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| 137 | |||
| 138 | /* we need an even # of CF's.. insert a NOP if needed */ |
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| 139 | if (shader->cfs_count != align(shader->cfs_count, 2)) |
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| 140 | ir2_cf_create(shader, NOP); |
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| 141 | |||
| 142 | /* first pass, resolve sizes and addresses: */ |
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| 143 | ret = shader_resolve(shader, info); |
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| 144 | if (ret) { |
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| 145 | ERROR_MSG("resolve failed: %d", ret); |
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| 146 | goto fail; |
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| 147 | } |
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| 148 | |||
| 149 | ptr = dwords = calloc(1, 4 * info->sizedwords); |
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| 150 | |||
| 151 | /* second pass, emit CF program in pairs: */ |
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| 152 | for (i = 0; i < shader->cfs_count; i += 2) { |
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| 153 | instr_cf_t *cfs = (instr_cf_t *)ptr; |
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| 154 | ret = cf_emit(shader->cfs[i], &cfs[0]); |
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| 155 | if (ret) { |
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| 156 | ERROR_MSG("CF emit failed: %d\n", ret); |
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| 157 | goto fail; |
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| 158 | } |
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| 159 | ret = cf_emit(shader->cfs[i+1], &cfs[1]); |
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| 160 | if (ret) { |
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| 161 | ERROR_MSG("CF emit failed: %d\n", ret); |
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| 162 | goto fail; |
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| 163 | } |
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| 164 | ptr += 3; |
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| 165 | assert((ptr - dwords) <= info->sizedwords); |
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| 166 | } |
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| 167 | |||
| 168 | /* third pass, emit ALU/FETCH: */ |
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| 169 | for (i = 0; i < shader->cfs_count; i++) { |
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| 170 | struct ir2_cf *cf = shader->cfs[i]; |
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| 171 | if ((cf->cf_type == EXEC) || (cf->cf_type == EXEC_END)) { |
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| 172 | for (j = 0; j < cf->exec.instrs_count; j++) { |
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| 173 | ret = instr_emit(cf->exec.instrs[j], ptr, idx++, info); |
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| 174 | if (ret) { |
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| 175 | ERROR_MSG("instruction emit failed: %d", ret); |
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| 176 | goto fail; |
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| 177 | } |
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| 178 | ptr += 3; |
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| 179 | assert((ptr - dwords) <= info->sizedwords); |
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| 180 | } |
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| 181 | } |
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| 182 | } |
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| 183 | |||
| 184 | return dwords; |
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| 185 | |||
| 186 | fail: |
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| 187 | free(dwords); |
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| 188 | return NULL; |
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| 189 | } |
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| 190 | |||
| 191 | |||
| 192 | struct ir2_cf * ir2_cf_create(struct ir2_shader *shader, instr_cf_opc_t cf_type) |
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| 193 | { |
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| 194 | struct ir2_cf *cf = ir2_alloc(shader, sizeof(struct ir2_cf)); |
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| 195 | DEBUG_MSG("%d", cf_type); |
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| 196 | cf->shader = shader; |
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| 197 | cf->cf_type = cf_type; |
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| 198 | assert(shader->cfs_count < ARRAY_SIZE(shader->cfs)); |
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| 199 | shader->cfs[shader->cfs_count++] = cf; |
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| 200 | return cf; |
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| 201 | } |
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| 202 | |||
| 203 | |||
| 204 | /* |
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| 205 | * CF instructions: |
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| 206 | */ |
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| 207 | |||
| 208 | static int cf_emit(struct ir2_cf *cf, instr_cf_t *instr) |
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| 209 | { |
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| 210 | memset(instr, 0, sizeof(*instr)); |
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| 211 | |||
| 212 | instr->opc = cf->cf_type; |
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| 213 | |||
| 214 | switch (cf->cf_type) { |
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| 215 | case NOP: |
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| 216 | break; |
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| 217 | case EXEC: |
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| 218 | case EXEC_END: |
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| 219 | assert(cf->exec.addr <= 0x1ff); |
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| 220 | assert(cf->exec.cnt <= 0x6); |
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| 221 | assert(cf->exec.sequence <= 0xfff); |
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| 222 | instr->exec.address = cf->exec.addr; |
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| 223 | instr->exec.count = cf->exec.cnt; |
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| 224 | instr->exec.serialize = cf->exec.sequence; |
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| 225 | break; |
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| 226 | case ALLOC: |
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| 227 | assert(cf->alloc.size <= 0xf); |
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| 228 | instr->alloc.size = cf->alloc.size; |
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| 229 | switch (cf->alloc.type) { |
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| 230 | case SQ_POSITION: |
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| 231 | case SQ_PARAMETER_PIXEL: |
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| 232 | instr->alloc.buffer_select = cf->alloc.type; |
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| 233 | break; |
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| 234 | default: |
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| 235 | ERROR_MSG("invalid alloc type: %d", cf->alloc.type); |
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| 236 | return -1; |
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| 237 | } |
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| 238 | break; |
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| 239 | case COND_EXEC: |
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| 240 | case COND_EXEC_END: |
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| 241 | case COND_PRED_EXEC: |
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| 242 | case COND_PRED_EXEC_END: |
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| 243 | case LOOP_START: |
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| 244 | case LOOP_END: |
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| 245 | case COND_CALL: |
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| 246 | case RETURN: |
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| 247 | case COND_JMP: |
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| 248 | case COND_EXEC_PRED_CLEAN: |
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| 249 | case COND_EXEC_PRED_CLEAN_END: |
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| 250 | case MARK_VS_FETCH_DONE: |
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| 251 | ERROR_MSG("TODO"); |
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| 252 | return -1; |
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| 253 | } |
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| 254 | |||
| 255 | return 0; |
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| 256 | } |
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| 257 | |||
| 258 | |||
| 259 | struct ir2_instruction * ir2_instr_create(struct ir2_cf *cf, int instr_type) |
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| 260 | { |
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| 261 | struct ir2_instruction *instr = |
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| 262 | ir2_alloc(cf->shader, sizeof(struct ir2_instruction)); |
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| 263 | DEBUG_MSG("%d", instr_type); |
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| 264 | instr->shader = cf->shader; |
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| 265 | instr->pred = cf->shader->pred; |
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| 266 | instr->instr_type = instr_type; |
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| 267 | assert(cf->exec.instrs_count < ARRAY_SIZE(cf->exec.instrs)); |
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| 268 | cf->exec.instrs[cf->exec.instrs_count++] = instr; |
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| 269 | return instr; |
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| 270 | } |
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| 271 | |||
| 272 | |||
| 273 | /* |
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| 274 | * FETCH instructions: |
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| 275 | */ |
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| 276 | |||
| 277 | static int instr_emit_fetch(struct ir2_instruction *instr, |
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| 278 | uint32_t *dwords, uint32_t idx, |
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| 279 | struct ir2_shader_info *info) |
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| 280 | { |
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| 281 | instr_fetch_t *fetch = (instr_fetch_t *)dwords; |
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| 282 | int reg = 0; |
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| 283 | struct ir2_register *dst_reg = instr->regs[reg++]; |
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| 284 | struct ir2_register *src_reg = instr->regs[reg++]; |
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| 285 | |||
| 286 | memset(fetch, 0, sizeof(*fetch)); |
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| 287 | |||
| 288 | reg_update_stats(dst_reg, info, true); |
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| 289 | reg_update_stats(src_reg, info, false); |
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| 290 | |||
| 291 | fetch->opc = instr->fetch.opc; |
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| 292 | |||
| 293 | if (instr->fetch.opc == VTX_FETCH) { |
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| 294 | instr_fetch_vtx_t *vtx = &fetch->vtx; |
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| 295 | |||
| 296 | assert(instr->fetch.stride <= 0xff); |
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| 297 | assert(instr->fetch.fmt <= 0x3f); |
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| 298 | assert(instr->fetch.const_idx <= 0x1f); |
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| 299 | assert(instr->fetch.const_idx_sel <= 0x3); |
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| 300 | |||
| 301 | vtx->src_reg = src_reg->num; |
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| 302 | vtx->src_swiz = reg_fetch_src_swiz(src_reg, 1); |
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| 303 | vtx->dst_reg = dst_reg->num; |
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| 304 | vtx->dst_swiz = reg_fetch_dst_swiz(dst_reg); |
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| 305 | vtx->must_be_one = 1; |
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| 306 | vtx->const_index = instr->fetch.const_idx; |
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| 307 | vtx->const_index_sel = instr->fetch.const_idx_sel; |
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| 308 | vtx->format_comp_all = !!instr->fetch.is_signed; |
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| 309 | vtx->num_format_all = !instr->fetch.is_normalized; |
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| 310 | vtx->format = instr->fetch.fmt; |
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| 311 | vtx->stride = instr->fetch.stride; |
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| 312 | vtx->offset = instr->fetch.offset; |
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| 313 | |||
| 314 | if (instr->pred != IR2_PRED_NONE) { |
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| 315 | vtx->pred_select = 1; |
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| 316 | vtx->pred_condition = (instr->pred == IR2_PRED_EQ) ? 1 : 0; |
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| 317 | } |
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| 318 | |||
| 319 | /* XXX seems like every FETCH but the first has |
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| 320 | * this bit set: |
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| 321 | */ |
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| 322 | vtx->reserved3 = (idx > 0) ? 0x1 : 0x0; |
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| 323 | vtx->reserved0 = (idx > 0) ? 0x2 : 0x3; |
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| 324 | } else if (instr->fetch.opc == TEX_FETCH) { |
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| 325 | instr_fetch_tex_t *tex = &fetch->tex; |
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| 326 | |||
| 327 | assert(instr->fetch.const_idx <= 0x1f); |
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| 328 | |||
| 329 | tex->src_reg = src_reg->num; |
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| 330 | tex->src_swiz = reg_fetch_src_swiz(src_reg, 3); |
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| 331 | tex->dst_reg = dst_reg->num; |
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| 332 | tex->dst_swiz = reg_fetch_dst_swiz(dst_reg); |
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| 333 | tex->const_idx = instr->fetch.const_idx; |
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| 334 | tex->mag_filter = TEX_FILTER_USE_FETCH_CONST; |
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| 335 | tex->min_filter = TEX_FILTER_USE_FETCH_CONST; |
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| 336 | tex->mip_filter = TEX_FILTER_USE_FETCH_CONST; |
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| 337 | tex->aniso_filter = ANISO_FILTER_USE_FETCH_CONST; |
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| 338 | tex->arbitrary_filter = ARBITRARY_FILTER_USE_FETCH_CONST; |
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| 339 | tex->vol_mag_filter = TEX_FILTER_USE_FETCH_CONST; |
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| 340 | tex->vol_min_filter = TEX_FILTER_USE_FETCH_CONST; |
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| 341 | tex->use_comp_lod = 1; |
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| 342 | tex->use_reg_lod = !instr->fetch.is_cube; |
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| 343 | tex->sample_location = SAMPLE_CENTER; |
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| 344 | |||
| 345 | if (instr->pred != IR2_PRED_NONE) { |
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| 346 | tex->pred_select = 1; |
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| 347 | tex->pred_condition = (instr->pred == IR2_PRED_EQ) ? 1 : 0; |
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| 348 | } |
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| 349 | |||
| 350 | } else { |
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| 351 | ERROR_MSG("invalid fetch opc: %d\n", instr->fetch.opc); |
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| 352 | return -1; |
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| 353 | } |
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| 354 | |||
| 355 | return 0; |
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| 356 | } |
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| 357 | |||
| 358 | /* |
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| 359 | * ALU instructions: |
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| 360 | */ |
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| 361 | |||
| 362 | static int instr_emit_alu(struct ir2_instruction *instr, uint32_t *dwords, |
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| 363 | struct ir2_shader_info *info) |
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| 364 | { |
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| 365 | int reg = 0; |
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| 366 | instr_alu_t *alu = (instr_alu_t *)dwords; |
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| 367 | struct ir2_register *dst_reg = instr->regs[reg++]; |
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| 368 | struct ir2_register *src1_reg; |
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| 369 | struct ir2_register *src2_reg; |
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| 370 | struct ir2_register *src3_reg; |
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| 371 | |||
| 372 | memset(alu, 0, sizeof(*alu)); |
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| 373 | |||
| 374 | /* handle instructions w/ 3 src operands: */ |
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| 375 | switch (instr->alu.vector_opc) { |
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| 376 | case MULADDv: |
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| 377 | case CNDEv: |
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| 378 | case CNDGTEv: |
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| 379 | case CNDGTv: |
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| 380 | case DOT2ADDv: |
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| 381 | /* note: disassembler lists 3rd src first, ie: |
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| 382 | * MULADDv Rdst = Rsrc3 + (Rsrc1 * Rsrc2) |
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| 383 | * which is the reason for this strange ordering. |
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| 384 | */ |
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| 385 | src3_reg = instr->regs[reg++]; |
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| 386 | break; |
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| 387 | default: |
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| 388 | src3_reg = NULL; |
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| 389 | break; |
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| 390 | } |
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| 391 | |||
| 392 | src1_reg = instr->regs[reg++]; |
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| 393 | src2_reg = instr->regs[reg++]; |
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| 394 | |||
| 395 | reg_update_stats(dst_reg, info, true); |
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| 396 | reg_update_stats(src1_reg, info, false); |
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| 397 | reg_update_stats(src2_reg, info, false); |
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| 398 | |||
| 399 | assert((dst_reg->flags & ~IR2_REG_EXPORT) == 0); |
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| 400 | assert(!dst_reg->swizzle || (strlen(dst_reg->swizzle) == 4)); |
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| 401 | assert((src1_reg->flags & IR2_REG_EXPORT) == 0); |
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| 402 | assert(!src1_reg->swizzle || (strlen(src1_reg->swizzle) == 4)); |
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| 403 | assert((src2_reg->flags & IR2_REG_EXPORT) == 0); |
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| 404 | assert(!src2_reg->swizzle || (strlen(src2_reg->swizzle) == 4)); |
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| 405 | |||
| 406 | if (instr->alu.vector_opc == ~0) { |
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| 407 | alu->vector_opc = MAXv; |
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| 408 | alu->vector_write_mask = 0; |
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| 409 | } else { |
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| 410 | alu->vector_opc = instr->alu.vector_opc; |
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| 411 | alu->vector_write_mask = reg_alu_dst_swiz(dst_reg); |
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| 412 | } |
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| 413 | |||
| 414 | alu->vector_dest = dst_reg->num; |
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| 415 | alu->export_data = !!(dst_reg->flags & IR2_REG_EXPORT); |
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| 416 | |||
| 417 | // TODO predicate case/condition.. need to add to parser |
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| 418 | |||
| 419 | alu->src2_reg = src2_reg->num; |
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| 420 | alu->src2_swiz = reg_alu_src_swiz(src2_reg); |
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| 421 | alu->src2_reg_negate = !!(src2_reg->flags & IR2_REG_NEGATE); |
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| 422 | alu->src2_reg_abs = !!(src2_reg->flags & IR2_REG_ABS); |
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| 423 | alu->src2_sel = !(src2_reg->flags & IR2_REG_CONST); |
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| 424 | |||
| 425 | alu->src1_reg = src1_reg->num; |
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| 426 | alu->src1_swiz = reg_alu_src_swiz(src1_reg); |
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| 427 | alu->src1_reg_negate = !!(src1_reg->flags & IR2_REG_NEGATE); |
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| 428 | alu->src1_reg_abs = !!(src1_reg->flags & IR2_REG_ABS); |
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| 429 | alu->src1_sel = !(src1_reg->flags & IR2_REG_CONST); |
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| 430 | |||
| 431 | alu->vector_clamp = instr->alu.vector_clamp; |
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| 432 | alu->scalar_clamp = instr->alu.scalar_clamp; |
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| 433 | |||
| 434 | if (instr->alu.scalar_opc != ~0) { |
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| 435 | struct ir2_register *sdst_reg = instr->regs[reg++]; |
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| 436 | |||
| 437 | reg_update_stats(sdst_reg, info, true); |
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| 438 | |||
| 439 | assert(sdst_reg->flags == dst_reg->flags); |
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| 440 | |||
| 441 | if (src3_reg) { |
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| 442 | assert(src3_reg == instr->regs[reg++]); |
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| 443 | } else { |
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| 444 | src3_reg = instr->regs[reg++]; |
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| 445 | } |
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| 446 | |||
| 447 | alu->scalar_dest = sdst_reg->num; |
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| 448 | alu->scalar_write_mask = reg_alu_dst_swiz(sdst_reg); |
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| 449 | alu->scalar_opc = instr->alu.scalar_opc; |
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| 450 | } else { |
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| 451 | /* not sure if this is required, but adreno compiler seems |
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| 452 | * to always set scalar opc to MAXs if it is not used: |
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| 453 | */ |
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| 454 | alu->scalar_opc = MAXs; |
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| 455 | } |
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| 456 | |||
| 457 | if (src3_reg) { |
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| 458 | reg_update_stats(src3_reg, info, false); |
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| 459 | |||
| 460 | alu->src3_reg = src3_reg->num; |
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| 461 | alu->src3_swiz = reg_alu_src_swiz(src3_reg); |
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| 462 | alu->src3_reg_negate = !!(src3_reg->flags & IR2_REG_NEGATE); |
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| 463 | alu->src3_reg_abs = !!(src3_reg->flags & IR2_REG_ABS); |
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| 464 | alu->src3_sel = !(src3_reg->flags & IR2_REG_CONST); |
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| 465 | } else { |
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| 466 | /* not sure if this is required, but adreno compiler seems |
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| 467 | * to always set register bank for 3rd src if unused: |
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| 468 | */ |
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| 469 | alu->src3_sel = 1; |
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| 470 | } |
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| 471 | |||
| 472 | if (instr->pred != IR2_PRED_NONE) { |
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| 473 | alu->pred_select = (instr->pred == IR2_PRED_EQ) ? 3 : 2; |
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| 474 | } |
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| 475 | |||
| 476 | return 0; |
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| 477 | } |
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| 478 | |||
| 479 | static int instr_emit(struct ir2_instruction *instr, uint32_t *dwords, |
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| 480 | uint32_t idx, struct ir2_shader_info *info) |
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| 481 | { |
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| 482 | switch (instr->instr_type) { |
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| 483 | case IR2_FETCH: return instr_emit_fetch(instr, dwords, idx, info); |
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| 484 | case IR2_ALU: return instr_emit_alu(instr, dwords, info); |
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| 485 | } |
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| 486 | return -1; |
||
| 487 | } |
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| 488 | |||
| 489 | |||
| 490 | struct ir2_register * ir2_reg_create(struct ir2_instruction *instr, |
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| 491 | int num, const char *swizzle, int flags) |
||
| 492 | { |
||
| 493 | struct ir2_register *reg = |
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| 494 | ir2_alloc(instr->shader, sizeof(struct ir2_register)); |
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| 495 | DEBUG_MSG("%x, %d, %s", flags, num, swizzle); |
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| 496 | assert(num <= REG_MASK); |
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| 497 | reg->flags = flags; |
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| 498 | reg->num = num; |
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| 499 | reg->swizzle = ir2_strdup(instr->shader, swizzle); |
||
| 500 | assert(instr->regs_count < ARRAY_SIZE(instr->regs)); |
||
| 501 | instr->regs[instr->regs_count++] = reg; |
||
| 502 | return reg; |
||
| 503 | } |
||
| 504 | |||
| 505 | static void reg_update_stats(struct ir2_register *reg, |
||
| 506 | struct ir2_shader_info *info, bool dest) |
||
| 507 | { |
||
| 508 | if (!(reg->flags & (IR2_REG_CONST|IR2_REG_EXPORT))) { |
||
| 509 | info->max_reg = MAX2(info->max_reg, reg->num); |
||
| 510 | |||
| 511 | if (dest) { |
||
| 512 | info->regs_written |= (1 << reg->num); |
||
| 513 | } else if (!(info->regs_written & (1 << reg->num))) { |
||
| 514 | /* for registers that haven't been written, they must be an |
||
| 515 | * input register that the thread scheduler (presumably?) |
||
| 516 | * needs to know about: |
||
| 517 | */ |
||
| 518 | info->max_input_reg = MAX2(info->max_input_reg, reg->num); |
||
| 519 | } |
||
| 520 | } |
||
| 521 | } |
||
| 522 | |||
| 523 | static uint32_t reg_fetch_src_swiz(struct ir2_register *reg, uint32_t n) |
||
| 524 | { |
||
| 525 | uint32_t swiz = 0; |
||
| 526 | int i; |
||
| 527 | |||
| 528 | assert(reg->flags == 0); |
||
| 529 | assert(reg->swizzle); |
||
| 530 | |||
| 531 | DEBUG_MSG("fetch src R%d.%s", reg->num, reg->swizzle); |
||
| 532 | |||
| 533 | for (i = n-1; i >= 0; i--) { |
||
| 534 | swiz <<= 2; |
||
| 535 | switch (reg->swizzle[i]) { |
||
| 536 | default: |
||
| 537 | ERROR_MSG("invalid fetch src swizzle: %s", reg->swizzle); |
||
| 538 | case 'x': swiz |= 0x0; break; |
||
| 539 | case 'y': swiz |= 0x1; break; |
||
| 540 | case 'z': swiz |= 0x2; break; |
||
| 541 | case 'w': swiz |= 0x3; break; |
||
| 542 | } |
||
| 543 | } |
||
| 544 | |||
| 545 | return swiz; |
||
| 546 | } |
||
| 547 | |||
| 548 | static uint32_t reg_fetch_dst_swiz(struct ir2_register *reg) |
||
| 549 | { |
||
| 550 | uint32_t swiz = 0; |
||
| 551 | int i; |
||
| 552 | |||
| 553 | assert(reg->flags == 0); |
||
| 554 | assert(!reg->swizzle || (strlen(reg->swizzle) == 4)); |
||
| 555 | |||
| 556 | DEBUG_MSG("fetch dst R%d.%s", reg->num, reg->swizzle); |
||
| 557 | |||
| 558 | if (reg->swizzle) { |
||
| 559 | for (i = 3; i >= 0; i--) { |
||
| 560 | swiz <<= 3; |
||
| 561 | switch (reg->swizzle[i]) { |
||
| 562 | default: |
||
| 563 | ERROR_MSG("invalid dst swizzle: %s", reg->swizzle); |
||
| 564 | case 'x': swiz |= 0x0; break; |
||
| 565 | case 'y': swiz |= 0x1; break; |
||
| 566 | case 'z': swiz |= 0x2; break; |
||
| 567 | case 'w': swiz |= 0x3; break; |
||
| 568 | case '0': swiz |= 0x4; break; |
||
| 569 | case '1': swiz |= 0x5; break; |
||
| 570 | case '_': swiz |= 0x7; break; |
||
| 571 | } |
||
| 572 | } |
||
| 573 | } else { |
||
| 574 | swiz = 0x688; |
||
| 575 | } |
||
| 576 | |||
| 577 | return swiz; |
||
| 578 | } |
||
| 579 | |||
| 580 | /* actually, a write-mask */ |
||
| 581 | static uint32_t reg_alu_dst_swiz(struct ir2_register *reg) |
||
| 582 | { |
||
| 583 | uint32_t swiz = 0; |
||
| 584 | int i; |
||
| 585 | |||
| 586 | assert((reg->flags & ~IR2_REG_EXPORT) == 0); |
||
| 587 | assert(!reg->swizzle || (strlen(reg->swizzle) == 4)); |
||
| 588 | |||
| 589 | DEBUG_MSG("alu dst R%d.%s", reg->num, reg->swizzle); |
||
| 590 | |||
| 591 | if (reg->swizzle) { |
||
| 592 | for (i = 3; i >= 0; i--) { |
||
| 593 | swiz <<= 1; |
||
| 594 | if (reg->swizzle[i] == "xyzw"[i]) { |
||
| 595 | swiz |= 0x1; |
||
| 596 | } else if (reg->swizzle[i] != '_') { |
||
| 597 | ERROR_MSG("invalid dst swizzle: %s", reg->swizzle); |
||
| 598 | break; |
||
| 599 | } |
||
| 600 | } |
||
| 601 | } else { |
||
| 602 | swiz = 0xf; |
||
| 603 | } |
||
| 604 | |||
| 605 | return swiz; |
||
| 606 | } |
||
| 607 | |||
| 608 | static uint32_t reg_alu_src_swiz(struct ir2_register *reg) |
||
| 609 | { |
||
| 610 | uint32_t swiz = 0; |
||
| 611 | int i; |
||
| 612 | |||
| 613 | assert((reg->flags & IR2_REG_EXPORT) == 0); |
||
| 614 | assert(!reg->swizzle || (strlen(reg->swizzle) == 4)); |
||
| 615 | |||
| 616 | DEBUG_MSG("vector src R%d.%s", reg->num, reg->swizzle); |
||
| 617 | |||
| 618 | if (reg->swizzle) { |
||
| 619 | for (i = 3; i >= 0; i--) { |
||
| 620 | swiz <<= 2; |
||
| 621 | switch (reg->swizzle[i]) { |
||
| 622 | default: |
||
| 623 | ERROR_MSG("invalid vector src swizzle: %s", reg->swizzle); |
||
| 624 | case 'x': swiz |= (0x0 - i) & 0x3; break; |
||
| 625 | case 'y': swiz |= (0x1 - i) & 0x3; break; |
||
| 626 | case 'z': swiz |= (0x2 - i) & 0x3; break; |
||
| 627 | case 'w': swiz |= (0x3 - i) & 0x3; break; |
||
| 628 | } |
||
| 629 | } |
||
| 630 | } else { |
||
| 631 | swiz = 0x0; |
||
| 632 | } |
||
| 633 | |||
| 634 | return swiz; |
||
| 635 | } |