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Rev | Author | Line No. | Line |
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5563 | serge | 1 | /************************************************************************** |
2 | |||
3 | Copyright (C) 2004 Nicolai Haehnle. |
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4 | Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. |
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5 | |||
6 | The Weather Channel (TM) funded Tungsten Graphics to develop the |
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7 | initial release of the Radeon 8500 driver under the XFree86 license. |
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8 | This notice must be preserved. |
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9 | |||
10 | All Rights Reserved. |
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11 | |||
12 | Permission is hereby granted, free of charge, to any person obtaining a |
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13 | copy of this software and associated documentation files (the "Software"), |
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14 | to deal in the Software without restriction, including without limitation |
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15 | on the rights to use, copy, modify, merge, publish, distribute, sub |
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16 | license, and/or sell copies of the Software, and to permit persons to whom |
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17 | the Software is furnished to do so, subject to the following conditions: |
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18 | |||
19 | The above copyright notice and this permission notice (including the next |
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20 | paragraph) shall be included in all copies or substantial portions of the |
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21 | Software. |
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22 | |||
23 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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24 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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25 | FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL |
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26 | ATI, VA LINUX SYSTEMS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, |
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27 | DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR |
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28 | OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE |
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29 | USE OR OTHER DEALINGS IN THE SOFTWARE. |
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30 | |||
31 | **************************************************************************/ |
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32 | |||
33 | #include |
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34 | #include "radeon_common.h" |
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35 | #include "radeon_fog.h" |
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36 | #include "main/simple_list.h" |
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37 | |||
38 | #if defined(USE_X86_ASM) |
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39 | #define COPY_DWORDS( dst, src, nr ) \ |
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40 | do { \ |
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41 | int __tmp; \ |
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42 | __asm__ __volatile__( "rep ; movsl" \ |
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43 | : "=%c" (__tmp), "=D" (dst), "=S" (__tmp) \ |
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44 | : "0" (nr), \ |
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45 | "D" ((long)dst), \ |
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46 | "S" ((long)src) ); \ |
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47 | } while (0) |
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48 | #else |
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49 | #define COPY_DWORDS( dst, src, nr ) \ |
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50 | do { \ |
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51 | int j; \ |
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52 | for ( j = 0 ; j < nr ; j++ ) \ |
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53 | dst[j] = ((int *)src)[j]; \ |
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54 | dst += nr; \ |
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55 | } while (0) |
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56 | #endif |
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57 | |||
58 | void radeonEmitVec4(uint32_t *out, const GLvoid * data, int stride, int count) |
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59 | { |
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60 | int i; |
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61 | |||
62 | if (RADEON_DEBUG & RADEON_VERTS) |
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63 | fprintf(stderr, "%s count %d stride %d out %p data %p\n", |
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64 | __FUNCTION__, count, stride, (void *)out, (void *)data); |
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65 | |||
66 | if (stride == 4) |
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67 | COPY_DWORDS(out, data, count); |
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68 | else |
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69 | for (i = 0; i < count; i++) { |
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70 | out[0] = *(int *)data; |
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71 | out++; |
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72 | data += stride; |
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73 | } |
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74 | } |
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75 | |||
76 | void radeonEmitVec8(uint32_t *out, const GLvoid * data, int stride, int count) |
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77 | { |
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78 | int i; |
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79 | |||
80 | if (RADEON_DEBUG & RADEON_VERTS) |
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81 | fprintf(stderr, "%s count %d stride %d out %p data %p\n", |
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82 | __FUNCTION__, count, stride, (void *)out, (void *)data); |
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83 | |||
84 | if (stride == 8) |
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85 | COPY_DWORDS(out, data, count * 2); |
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86 | else |
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87 | for (i = 0; i < count; i++) { |
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88 | out[0] = *(int *)data; |
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89 | out[1] = *(int *)(data + 4); |
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90 | out += 2; |
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91 | data += stride; |
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92 | } |
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93 | } |
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94 | |||
95 | void radeonEmitVec12(uint32_t *out, const GLvoid * data, int stride, int count) |
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96 | { |
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97 | int i; |
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98 | |||
99 | if (RADEON_DEBUG & RADEON_VERTS) |
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100 | fprintf(stderr, "%s count %d stride %d out %p data %p\n", |
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101 | __FUNCTION__, count, stride, (void *)out, (void *)data); |
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102 | |||
103 | if (stride == 12) { |
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104 | COPY_DWORDS(out, data, count * 3); |
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105 | } |
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106 | else |
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107 | for (i = 0; i < count; i++) { |
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108 | out[0] = *(int *)data; |
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109 | out[1] = *(int *)(data + 4); |
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110 | out[2] = *(int *)(data + 8); |
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111 | out += 3; |
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112 | data += stride; |
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113 | } |
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114 | } |
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115 | |||
116 | void radeonEmitVec16(uint32_t *out, const GLvoid * data, int stride, int count) |
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117 | { |
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118 | int i; |
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119 | |||
120 | if (RADEON_DEBUG & RADEON_VERTS) |
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121 | fprintf(stderr, "%s count %d stride %d out %p data %p\n", |
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122 | __FUNCTION__, count, stride, (void *)out, (void *)data); |
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123 | |||
124 | if (stride == 16) |
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125 | COPY_DWORDS(out, data, count * 4); |
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126 | else |
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127 | for (i = 0; i < count; i++) { |
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128 | out[0] = *(int *)data; |
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129 | out[1] = *(int *)(data + 4); |
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130 | out[2] = *(int *)(data + 8); |
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131 | out[3] = *(int *)(data + 12); |
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132 | out += 4; |
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133 | data += stride; |
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134 | } |
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135 | } |
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136 | |||
137 | void rcommon_emit_vector(struct gl_context * ctx, struct radeon_aos *aos, |
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138 | const GLvoid * data, int size, int stride, int count) |
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139 | { |
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140 | radeonContextPtr rmesa = RADEON_CONTEXT(ctx); |
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141 | uint32_t *out; |
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142 | |||
143 | if (stride == 0) { |
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144 | radeonAllocDmaRegion(rmesa, &aos->bo, &aos->offset, size * 4, 32); |
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145 | count = 1; |
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146 | aos->stride = 0; |
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147 | } else { |
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148 | radeonAllocDmaRegion(rmesa, &aos->bo, &aos->offset, size * count * 4, 32); |
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149 | aos->stride = size; |
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150 | } |
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151 | |||
152 | aos->components = size; |
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153 | aos->count = count; |
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154 | |||
155 | radeon_bo_map(aos->bo, 1); |
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156 | out = (uint32_t*)((char*)aos->bo->ptr + aos->offset); |
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157 | switch (size) { |
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158 | case 1: radeonEmitVec4(out, data, stride, count); break; |
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159 | case 2: radeonEmitVec8(out, data, stride, count); break; |
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160 | case 3: radeonEmitVec12(out, data, stride, count); break; |
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161 | case 4: radeonEmitVec16(out, data, stride, count); break; |
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162 | default: |
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163 | assert(0); |
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164 | break; |
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165 | } |
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166 | radeon_bo_unmap(aos->bo); |
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167 | } |
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168 | |||
169 | void rcommon_emit_vecfog(struct gl_context *ctx, struct radeon_aos *aos, |
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170 | GLvoid *data, int stride, int count) |
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171 | { |
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172 | int i; |
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173 | float *out; |
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174 | int size = 1; |
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175 | radeonContextPtr rmesa = RADEON_CONTEXT(ctx); |
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176 | |||
177 | if (RADEON_DEBUG & RADEON_VERTS) |
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178 | fprintf(stderr, "%s count %d stride %d\n", |
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179 | __FUNCTION__, count, stride); |
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180 | |||
181 | if (stride == 0) { |
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182 | radeonAllocDmaRegion( rmesa, &aos->bo, &aos->offset, size * 4, 32 ); |
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183 | count = 1; |
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184 | aos->stride = 0; |
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185 | } else { |
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186 | radeonAllocDmaRegion(rmesa, &aos->bo, &aos->offset, size * count * 4, 32); |
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187 | aos->stride = size; |
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188 | } |
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189 | |||
190 | aos->components = size; |
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191 | aos->count = count; |
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192 | |||
193 | /* Emit the data */ |
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194 | radeon_bo_map(aos->bo, 1); |
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195 | out = (float*)((char*)aos->bo->ptr + aos->offset); |
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196 | for (i = 0; i < count; i++) { |
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197 | out[0] = radeonComputeFogBlendFactor( ctx, *(GLfloat *)data ); |
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198 | out++; |
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199 | data += stride; |
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200 | } |
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201 | radeon_bo_unmap(aos->bo); |
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202 | } |
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203 | |||
204 | void radeon_init_dma(radeonContextPtr rmesa) |
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205 | { |
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206 | make_empty_list(&rmesa->dma.free); |
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207 | make_empty_list(&rmesa->dma.wait); |
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208 | make_empty_list(&rmesa->dma.reserved); |
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209 | rmesa->dma.minimum_size = MAX_DMA_BUF_SZ; |
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210 | } |
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211 | |||
212 | void radeonRefillCurrentDmaRegion(radeonContextPtr rmesa, int size) |
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213 | { |
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214 | struct radeon_dma_bo *dma_bo = NULL; |
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215 | /* we set minimum sizes to at least requested size |
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216 | aligned to next 16 bytes. */ |
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217 | if (size > rmesa->dma.minimum_size) |
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218 | rmesa->dma.minimum_size = (size + 15) & (~15); |
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219 | |||
220 | radeon_print(RADEON_DMA, RADEON_NORMAL, "%s size %d minimum_size %Zi\n", |
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221 | __FUNCTION__, size, rmesa->dma.minimum_size); |
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222 | |||
223 | if (is_empty_list(&rmesa->dma.free) |
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224 | || last_elem(&rmesa->dma.free)->bo->size < size) { |
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225 | dma_bo = CALLOC_STRUCT(radeon_dma_bo); |
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226 | assert(dma_bo); |
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227 | |||
228 | again_alloc: |
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229 | dma_bo->bo = radeon_bo_open(rmesa->radeonScreen->bom, |
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230 | 0, rmesa->dma.minimum_size, 4, |
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231 | RADEON_GEM_DOMAIN_GTT, 0); |
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232 | |||
233 | if (!dma_bo->bo) { |
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234 | rcommonFlushCmdBuf(rmesa, __FUNCTION__); |
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235 | goto again_alloc; |
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236 | } |
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237 | insert_at_head(&rmesa->dma.reserved, dma_bo); |
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238 | } else { |
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239 | /* We push and pop buffers from end of list so we can keep |
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240 | counter on unused buffers for later freeing them from |
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241 | begin of list */ |
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242 | dma_bo = last_elem(&rmesa->dma.free); |
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243 | remove_from_list(dma_bo); |
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244 | insert_at_head(&rmesa->dma.reserved, dma_bo); |
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245 | } |
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246 | |||
247 | rmesa->dma.current_used = 0; |
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248 | rmesa->dma.current_vertexptr = 0; |
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249 | |||
250 | if (radeon_cs_space_check_with_bo(rmesa->cmdbuf.cs, |
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251 | first_elem(&rmesa->dma.reserved)->bo, |
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252 | RADEON_GEM_DOMAIN_GTT, 0)) |
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253 | fprintf(stderr,"failure to revalidate BOs - badness\n"); |
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254 | |||
255 | if (is_empty_list(&rmesa->dma.reserved)) { |
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256 | /* Cmd buff have been flushed in radeon_revalidate_bos */ |
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257 | goto again_alloc; |
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258 | } |
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259 | radeon_bo_map(first_elem(&rmesa->dma.reserved)->bo, 1); |
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260 | } |
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261 | |||
262 | /* Allocates a region from rmesa->dma.current. If there isn't enough |
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263 | * space in current, grab a new buffer (and discard what was left of current) |
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264 | */ |
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265 | void radeonAllocDmaRegion(radeonContextPtr rmesa, |
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266 | struct radeon_bo **pbo, int *poffset, |
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267 | int bytes, int alignment) |
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268 | { |
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269 | if (RADEON_DEBUG & RADEON_IOCTL) |
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270 | fprintf(stderr, "%s %d\n", __FUNCTION__, bytes); |
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271 | |||
272 | if (rmesa->dma.flush) |
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273 | rmesa->dma.flush(&rmesa->glCtx); |
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274 | |||
275 | assert(rmesa->dma.current_used == rmesa->dma.current_vertexptr); |
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276 | |||
277 | alignment--; |
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278 | rmesa->dma.current_used = (rmesa->dma.current_used + alignment) & ~alignment; |
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279 | |||
280 | if (is_empty_list(&rmesa->dma.reserved) |
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281 | || rmesa->dma.current_used + bytes > first_elem(&rmesa->dma.reserved)->bo->size) |
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282 | radeonRefillCurrentDmaRegion(rmesa, bytes); |
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283 | |||
284 | *poffset = rmesa->dma.current_used; |
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285 | *pbo = first_elem(&rmesa->dma.reserved)->bo; |
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286 | radeon_bo_ref(*pbo); |
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287 | |||
288 | /* Always align to at least 16 bytes */ |
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289 | rmesa->dma.current_used = (rmesa->dma.current_used + bytes + 15) & ~15; |
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290 | rmesa->dma.current_vertexptr = rmesa->dma.current_used; |
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291 | |||
292 | assert(rmesa->dma.current_used <= first_elem(&rmesa->dma.reserved)->bo->size); |
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293 | } |
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294 | |||
295 | void radeonFreeDmaRegions(radeonContextPtr rmesa) |
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296 | { |
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297 | struct radeon_dma_bo *dma_bo; |
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298 | struct radeon_dma_bo *temp; |
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299 | if (RADEON_DEBUG & RADEON_DMA) |
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300 | fprintf(stderr, "%s\n", __FUNCTION__); |
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301 | |||
302 | foreach_s(dma_bo, temp, &rmesa->dma.free) { |
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303 | remove_from_list(dma_bo); |
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304 | radeon_bo_unref(dma_bo->bo); |
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305 | free(dma_bo); |
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306 | } |
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307 | |||
308 | foreach_s(dma_bo, temp, &rmesa->dma.wait) { |
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309 | remove_from_list(dma_bo); |
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310 | radeon_bo_unref(dma_bo->bo); |
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311 | free(dma_bo); |
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312 | } |
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313 | |||
314 | foreach_s(dma_bo, temp, &rmesa->dma.reserved) { |
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315 | remove_from_list(dma_bo); |
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316 | radeon_bo_unref(dma_bo->bo); |
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317 | free(dma_bo); |
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318 | } |
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319 | } |
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320 | |||
321 | void radeonReturnDmaRegion(radeonContextPtr rmesa, int return_bytes) |
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322 | { |
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323 | if (is_empty_list(&rmesa->dma.reserved)) |
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324 | return; |
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325 | |||
326 | if (RADEON_DEBUG & RADEON_IOCTL) |
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327 | fprintf(stderr, "%s %d\n", __FUNCTION__, return_bytes); |
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328 | rmesa->dma.current_used -= return_bytes; |
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329 | rmesa->dma.current_vertexptr = rmesa->dma.current_used; |
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330 | } |
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331 | |||
332 | static int radeon_bo_is_idle(struct radeon_bo* bo) |
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333 | { |
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334 | uint32_t domain; |
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335 | int ret = radeon_bo_is_busy(bo, &domain); |
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336 | if (ret == -EINVAL) { |
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337 | WARN_ONCE("Your libdrm or kernel doesn't have support for busy query.\n" |
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338 | "This may cause small performance drop for you.\n"); |
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339 | } |
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340 | return ret != -EBUSY; |
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341 | } |
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342 | |||
343 | void radeonReleaseDmaRegions(radeonContextPtr rmesa) |
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344 | { |
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345 | struct radeon_dma_bo *dma_bo; |
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346 | struct radeon_dma_bo *temp; |
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347 | const int expire_at = ++rmesa->dma.free.expire_counter + DMA_BO_FREE_TIME; |
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348 | const int time = rmesa->dma.free.expire_counter; |
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349 | |||
350 | if (RADEON_DEBUG & RADEON_DMA) { |
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351 | size_t free = 0, |
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352 | wait = 0, |
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353 | reserved = 0; |
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354 | foreach(dma_bo, &rmesa->dma.free) |
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355 | ++free; |
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356 | |||
357 | foreach(dma_bo, &rmesa->dma.wait) |
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358 | ++wait; |
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359 | |||
360 | foreach(dma_bo, &rmesa->dma.reserved) |
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361 | ++reserved; |
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362 | |||
363 | fprintf(stderr, "%s: free %zu, wait %zu, reserved %zu, minimum_size: %zu\n", |
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364 | __FUNCTION__, free, wait, reserved, rmesa->dma.minimum_size); |
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365 | } |
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366 | |||
367 | /* move waiting bos to free list. |
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368 | wait list provides gpu time to handle data before reuse */ |
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369 | foreach_s(dma_bo, temp, &rmesa->dma.wait) { |
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370 | if (dma_bo->expire_counter == time) { |
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371 | WARN_ONCE("Leaking dma buffer object!\n"); |
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372 | radeon_bo_unref(dma_bo->bo); |
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373 | remove_from_list(dma_bo); |
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374 | free(dma_bo); |
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375 | continue; |
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376 | } |
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377 | /* free objects that are too small to be used because of large request */ |
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378 | if (dma_bo->bo->size < rmesa->dma.minimum_size) { |
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379 | radeon_bo_unref(dma_bo->bo); |
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380 | remove_from_list(dma_bo); |
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381 | free(dma_bo); |
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382 | continue; |
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383 | } |
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384 | if (!radeon_bo_is_idle(dma_bo->bo)) { |
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385 | break; |
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386 | } |
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387 | remove_from_list(dma_bo); |
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388 | dma_bo->expire_counter = expire_at; |
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389 | insert_at_tail(&rmesa->dma.free, dma_bo); |
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390 | } |
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391 | |||
392 | /* move reserved to wait list */ |
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393 | foreach_s(dma_bo, temp, &rmesa->dma.reserved) { |
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394 | radeon_bo_unmap(dma_bo->bo); |
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395 | /* free objects that are too small to be used because of large request */ |
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396 | if (dma_bo->bo->size < rmesa->dma.minimum_size) { |
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397 | radeon_bo_unref(dma_bo->bo); |
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398 | remove_from_list(dma_bo); |
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399 | free(dma_bo); |
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400 | continue; |
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401 | } |
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402 | remove_from_list(dma_bo); |
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403 | dma_bo->expire_counter = expire_at; |
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404 | insert_at_tail(&rmesa->dma.wait, dma_bo); |
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405 | } |
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406 | |||
407 | /* free bos that have been unused for some time */ |
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408 | foreach_s(dma_bo, temp, &rmesa->dma.free) { |
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409 | if (dma_bo->expire_counter != time) |
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410 | break; |
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411 | remove_from_list(dma_bo); |
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412 | radeon_bo_unref(dma_bo->bo); |
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413 | free(dma_bo); |
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414 | } |
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415 | |||
416 | } |
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417 | |||
418 | |||
419 | /* Flush vertices in the current dma region. |
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420 | */ |
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421 | void rcommon_flush_last_swtcl_prim( struct gl_context *ctx ) |
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422 | { |
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423 | radeonContextPtr rmesa = RADEON_CONTEXT(ctx); |
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424 | struct radeon_dma *dma = &rmesa->dma; |
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425 | |||
426 | if (RADEON_DEBUG & RADEON_IOCTL) |
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427 | fprintf(stderr, "%s\n", __FUNCTION__); |
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428 | dma->flush = NULL; |
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429 | |||
430 | radeon_bo_unmap(rmesa->swtcl.bo); |
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431 | |||
432 | if (!is_empty_list(&dma->reserved)) { |
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433 | GLuint current_offset = dma->current_used; |
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434 | |||
435 | assert (dma->current_used + |
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436 | rmesa->swtcl.numverts * rmesa->swtcl.vertex_size * 4 == |
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437 | dma->current_vertexptr); |
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438 | |||
439 | if (dma->current_used != dma->current_vertexptr) { |
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440 | dma->current_used = dma->current_vertexptr; |
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441 | |||
442 | rmesa->vtbl.swtcl_flush(ctx, current_offset); |
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443 | } |
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444 | rmesa->swtcl.numverts = 0; |
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445 | } |
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446 | radeon_bo_unref(rmesa->swtcl.bo); |
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447 | rmesa->swtcl.bo = NULL; |
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448 | } |
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449 | /* Alloc space in the current dma region. |
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450 | */ |
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451 | void * |
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452 | rcommonAllocDmaLowVerts( radeonContextPtr rmesa, int nverts, int vsize ) |
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453 | { |
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454 | GLuint bytes = vsize * nverts; |
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455 | void *head; |
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456 | if (RADEON_DEBUG & RADEON_IOCTL) |
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457 | fprintf(stderr, "%s\n", __FUNCTION__); |
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458 | |||
459 | if(is_empty_list(&rmesa->dma.reserved) |
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460 | ||rmesa->dma.current_vertexptr + bytes > first_elem(&rmesa->dma.reserved)->bo->size) { |
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461 | if (rmesa->dma.flush) { |
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462 | rmesa->dma.flush(&rmesa->glCtx); |
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463 | } |
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464 | |||
465 | radeonRefillCurrentDmaRegion(rmesa, bytes); |
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466 | |||
467 | return NULL; |
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468 | } |
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469 | |||
470 | if (!rmesa->dma.flush) { |
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471 | /* if cmdbuf flushed DMA restart */ |
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472 | rmesa->glCtx.Driver.NeedFlush |= FLUSH_STORED_VERTICES; |
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473 | rmesa->dma.flush = rcommon_flush_last_swtcl_prim; |
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474 | } |
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475 | |||
476 | ASSERT( vsize == rmesa->swtcl.vertex_size * 4 ); |
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477 | ASSERT( rmesa->dma.flush == rcommon_flush_last_swtcl_prim ); |
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478 | ASSERT( rmesa->dma.current_used + |
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479 | rmesa->swtcl.numverts * rmesa->swtcl.vertex_size * 4 == |
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480 | rmesa->dma.current_vertexptr ); |
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481 | |||
482 | if (!rmesa->swtcl.bo) { |
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483 | rmesa->swtcl.bo = first_elem(&rmesa->dma.reserved)->bo; |
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484 | radeon_bo_ref(rmesa->swtcl.bo); |
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485 | radeon_bo_map(rmesa->swtcl.bo, 1); |
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486 | } |
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487 | |||
488 | head = (rmesa->swtcl.bo->ptr + rmesa->dma.current_vertexptr); |
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489 | rmesa->dma.current_vertexptr += bytes; |
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490 | rmesa->swtcl.numverts += nverts; |
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491 | return head; |
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492 | } |
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493 | |||
494 | void radeonReleaseArrays( struct gl_context *ctx, GLuint newinputs ) |
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495 | { |
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496 | radeonContextPtr radeon = RADEON_CONTEXT( ctx ); |
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497 | int i; |
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498 | if (RADEON_DEBUG & RADEON_IOCTL) |
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499 | fprintf(stderr, "%s\n", __FUNCTION__); |
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500 | |||
501 | if (radeon->dma.flush) { |
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502 | radeon->dma.flush(&radeon->glCtx); |
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503 | } |
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504 | for (i = 0; i < radeon->tcl.aos_count; i++) { |
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505 | if (radeon->tcl.aos[i].bo) { |
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506 | radeon_bo_unref(radeon->tcl.aos[i].bo); |
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507 | radeon->tcl.aos[i].bo = NULL; |
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508 | |||
509 | } |
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510 | } |
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511 | }>>>=>>>>>>>> |