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5563 serge 1
/*
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 * Copyright © 2011 Intel Corporation
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a
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 * copy of this software and associated documentation files (the "Software"),
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 * to deal in the Software without restriction, including without limitation
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 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
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 * and/or sell copies of the Software, and to permit persons to whom the
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 * Software is furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice (including the next
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 * paragraph) shall be included in all copies or substantial portions of the
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 * Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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 * IN THE SOFTWARE.
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 */
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#include "brw_context.h"
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#include "brw_state.h"
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#include "brw_defines.h"
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#include "brw_util.h"
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#include "program/prog_parameter.h"
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#include "program/prog_statevars.h"
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#include "intel_batchbuffer.h"
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static void
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upload_vs_state(struct brw_context *brw)
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{
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   struct gl_context *ctx = &brw->ctx;
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   uint32_t floating_point_mode = 0;
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   const int max_threads_shift = brw->is_haswell ?
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      HSW_VS_MAX_THREADS_SHIFT : GEN6_VS_MAX_THREADS_SHIFT;
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   gen7_emit_vs_workaround_flush(brw);
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   /* BRW_NEW_VS_BINDING_TABLE */
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   BEGIN_BATCH(2);
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   OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS_VS << 16 | (2 - 2));
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   OUT_BATCH(brw->vs.bind_bo_offset);
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   ADVANCE_BATCH();
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   /* CACHE_NEW_SAMPLER */
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   BEGIN_BATCH(2);
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   OUT_BATCH(_3DSTATE_SAMPLER_STATE_POINTERS_VS << 16 | (2 - 2));
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   OUT_BATCH(brw->sampler.offset);
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   ADVANCE_BATCH();
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   if (brw->vs.push_const_size == 0) {
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      /* Disable the push constant buffers. */
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      BEGIN_BATCH(7);
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      OUT_BATCH(_3DSTATE_CONSTANT_VS << 16 | (7 - 2));
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      OUT_BATCH(0);
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      OUT_BATCH(0);
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      OUT_BATCH(0);
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      OUT_BATCH(0);
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      OUT_BATCH(0);
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      OUT_BATCH(0);
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      ADVANCE_BATCH();
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   } else {
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      uint8_t mocs = brw->is_haswell ? GEN7_MOCS_L3 : 0;
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      BEGIN_BATCH(7);
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      OUT_BATCH(_3DSTATE_CONSTANT_VS << 16 | (7 - 2));
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      OUT_BATCH(brw->vs.push_const_size);
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      OUT_BATCH(0);
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      /* Pointer to the VS constant buffer.  Covered by the set of
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       * state flags from gen6_prepare_wm_contants
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       */
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      OUT_BATCH(brw->vs.push_const_offset | mocs);
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      OUT_BATCH(0);
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      OUT_BATCH(0);
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      OUT_BATCH(0);
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      ADVANCE_BATCH();
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   }
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   /* Use ALT floating point mode for ARB vertex programs, because they
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    * require 0^0 == 1.
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    */
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   if (ctx->Shader.CurrentVertexProgram == NULL)
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      floating_point_mode = GEN6_VS_FLOATING_POINT_MODE_ALT;
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   BEGIN_BATCH(6);
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   OUT_BATCH(_3DSTATE_VS << 16 | (6 - 2));
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   OUT_BATCH(brw->vs.prog_offset);
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   OUT_BATCH(floating_point_mode |
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	     ((ALIGN(brw->sampler.count, 4)/4) << GEN6_VS_SAMPLER_COUNT_SHIFT));
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   if (brw->vs.prog_data->base.total_scratch) {
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      OUT_RELOC(brw->vs.scratch_bo,
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		I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
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		ffs(brw->vs.prog_data->base.total_scratch) - 11);
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   } else {
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      OUT_BATCH(0);
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   }
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   OUT_BATCH((1 << GEN6_VS_DISPATCH_START_GRF_SHIFT) |
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	     (brw->vs.prog_data->base.urb_read_length << GEN6_VS_URB_READ_LENGTH_SHIFT) |
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	     (0 << GEN6_VS_URB_ENTRY_READ_OFFSET_SHIFT));
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   OUT_BATCH(((brw->max_vs_threads - 1) << max_threads_shift) |
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	     GEN6_VS_STATISTICS_ENABLE |
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	     GEN6_VS_ENABLE);
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   ADVANCE_BATCH();
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}
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const struct brw_tracked_state gen7_vs_state = {
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   .dirty = {
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      .mesa  = _NEW_TRANSFORM | _NEW_PROGRAM_CONSTANTS,
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      .brw   = (BRW_NEW_CONTEXT |
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		BRW_NEW_VERTEX_PROGRAM |
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		BRW_NEW_VS_BINDING_TABLE |
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		BRW_NEW_BATCH),
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      .cache = CACHE_NEW_VS_PROG | CACHE_NEW_SAMPLER
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   },
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   .emit = upload_vs_state,
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};