WebSVN – Kolibri OS – Blame – /contrib/sdk/sources/Mesa/mesa-9.2.5/src/gallium/drivers/r600/evergreen_state.c

Rev	Author	Line No.	Line
5563	serge	1	/*
		2	* Copyright 2010 Jerome Glisse
		3	*
		4	* Permission is hereby granted, free of charge, to any person obtaining a
		5	* copy of this software and associated documentation files (the "Software"),
		6	* to deal in the Software without restriction, including without limitation
		7	* on the rights to use, copy, modify, merge, publish, distribute, sub
		8	* license, and/or sell copies of the Software, and to permit persons to whom
		9	* the Software is furnished to do so, subject to the following conditions:
		10	*
		11	* The above copyright notice and this permission notice (including the next
		12	* paragraph) shall be included in all copies or substantial portions of the
		13	* Software.
		14	*
		15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		17	* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
		18	* THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
		19	* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
		20	* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
		21	* USE OR OTHER DEALINGS IN THE SOFTWARE.
		22	*/
		23	#include "r600_formats.h"
		24	#include "r600_shader.h"
		25	#include "evergreend.h"
		26
		27	#include "pipe/p_shader_tokens.h"
		28	#include "util/u_pack_color.h"
		29	#include "util/u_memory.h"
		30	#include "util/u_framebuffer.h"
		31	#include "util/u_dual_blend.h"
		32	#include "evergreen_compute.h"
		33	#include "util/u_math.h"
		34
		35	static INLINE unsigned evergreen_array_mode(unsigned mode)
		36	{
		37	switch (mode) {
		38	case RADEON_SURF_MODE_LINEAR_ALIGNED: return V_028C70_ARRAY_LINEAR_ALIGNED;
		39	break;
		40	case RADEON_SURF_MODE_1D: return V_028C70_ARRAY_1D_TILED_THIN1;
		41	break;
		42	case RADEON_SURF_MODE_2D: return V_028C70_ARRAY_2D_TILED_THIN1;
		43	default:
		44	case RADEON_SURF_MODE_LINEAR: return V_028C70_ARRAY_LINEAR_GENERAL;
		45	}
		46	}
		47
		48	static uint32_t eg_num_banks(uint32_t nbanks)
		49	{
		50	switch (nbanks) {
		51	case 2:
		52	return 0;
		53	case 4:
		54	return 1;
		55	case 8:
		56	default:
		57	return 2;
		58	case 16:
		59	return 3;
		60	}
		61	}
		62
		63
		64	static unsigned eg_tile_split(unsigned tile_split)
		65	{
		66	switch (tile_split) {
		67	case 64: tile_split = 0; break;
		68	case 128: tile_split = 1; break;
		69	case 256: tile_split = 2; break;
		70	case 512: tile_split = 3; break;
		71	default:
		72	case 1024: tile_split = 4; break;
		73	case 2048: tile_split = 5; break;
		74	case 4096: tile_split = 6; break;
		75	}
		76	return tile_split;
		77	}
		78
		79	static unsigned eg_macro_tile_aspect(unsigned macro_tile_aspect)
		80	{
		81	switch (macro_tile_aspect) {
		82	default:
		83	case 1: macro_tile_aspect = 0; break;
		84	case 2: macro_tile_aspect = 1; break;
		85	case 4: macro_tile_aspect = 2; break;
		86	case 8: macro_tile_aspect = 3; break;
		87	}
		88	return macro_tile_aspect;
		89	}
		90
		91	static unsigned eg_bank_wh(unsigned bankwh)
		92	{
		93	switch (bankwh) {
		94	default:
		95	case 1: bankwh = 0; break;
		96	case 2: bankwh = 1; break;
		97	case 4: bankwh = 2; break;
		98	case 8: bankwh = 3; break;
		99	}
		100	return bankwh;
		101	}
		102
		103	static uint32_t r600_translate_blend_function(int blend_func)
		104	{
		105	switch (blend_func) {
		106	case PIPE_BLEND_ADD:
		107	return V_028780_COMB_DST_PLUS_SRC;
		108	case PIPE_BLEND_SUBTRACT:
		109	return V_028780_COMB_SRC_MINUS_DST;
		110	case PIPE_BLEND_REVERSE_SUBTRACT:
		111	return V_028780_COMB_DST_MINUS_SRC;
		112	case PIPE_BLEND_MIN:
		113	return V_028780_COMB_MIN_DST_SRC;
		114	case PIPE_BLEND_MAX:
		115	return V_028780_COMB_MAX_DST_SRC;
		116	default:
		117	R600_ERR("Unknown blend function %d\n", blend_func);
		118	assert(0);
		119	break;
		120	}
		121	return 0;
		122	}
		123
		124	static uint32_t r600_translate_blend_factor(int blend_fact)
		125	{
		126	switch (blend_fact) {
		127	case PIPE_BLENDFACTOR_ONE:
		128	return V_028780_BLEND_ONE;
		129	case PIPE_BLENDFACTOR_SRC_COLOR:
		130	return V_028780_BLEND_SRC_COLOR;
		131	case PIPE_BLENDFACTOR_SRC_ALPHA:
		132	return V_028780_BLEND_SRC_ALPHA;
		133	case PIPE_BLENDFACTOR_DST_ALPHA:
		134	return V_028780_BLEND_DST_ALPHA;
		135	case PIPE_BLENDFACTOR_DST_COLOR:
		136	return V_028780_BLEND_DST_COLOR;
		137	case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
		138	return V_028780_BLEND_SRC_ALPHA_SATURATE;
		139	case PIPE_BLENDFACTOR_CONST_COLOR:
		140	return V_028780_BLEND_CONST_COLOR;
		141	case PIPE_BLENDFACTOR_CONST_ALPHA:
		142	return V_028780_BLEND_CONST_ALPHA;
		143	case PIPE_BLENDFACTOR_ZERO:
		144	return V_028780_BLEND_ZERO;
		145	case PIPE_BLENDFACTOR_INV_SRC_COLOR:
		146	return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
		147	case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
		148	return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
		149	case PIPE_BLENDFACTOR_INV_DST_ALPHA:
		150	return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
		151	case PIPE_BLENDFACTOR_INV_DST_COLOR:
		152	return V_028780_BLEND_ONE_MINUS_DST_COLOR;
		153	case PIPE_BLENDFACTOR_INV_CONST_COLOR:
		154	return V_028780_BLEND_ONE_MINUS_CONST_COLOR;
		155	case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
		156	return V_028780_BLEND_ONE_MINUS_CONST_ALPHA;
		157	case PIPE_BLENDFACTOR_SRC1_COLOR:
		158	return V_028780_BLEND_SRC1_COLOR;
		159	case PIPE_BLENDFACTOR_SRC1_ALPHA:
		160	return V_028780_BLEND_SRC1_ALPHA;
		161	case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
		162	return V_028780_BLEND_INV_SRC1_COLOR;
		163	case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
		164	return V_028780_BLEND_INV_SRC1_ALPHA;
		165	default:
		166	R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
		167	assert(0);
		168	break;
		169	}
		170	return 0;
		171	}
		172
		173	static unsigned r600_tex_dim(unsigned dim, unsigned nr_samples)
		174	{
		175	switch (dim) {
		176	default:
		177	case PIPE_TEXTURE_1D:
		178	return V_030000_SQ_TEX_DIM_1D;
		179	case PIPE_TEXTURE_1D_ARRAY:
		180	return V_030000_SQ_TEX_DIM_1D_ARRAY;
		181	case PIPE_TEXTURE_2D:
		182	case PIPE_TEXTURE_RECT:
		183	return nr_samples > 1 ? V_030000_SQ_TEX_DIM_2D_MSAA :
		184	V_030000_SQ_TEX_DIM_2D;
		185	case PIPE_TEXTURE_2D_ARRAY:
		186	return nr_samples > 1 ? V_030000_SQ_TEX_DIM_2D_ARRAY_MSAA :
		187	V_030000_SQ_TEX_DIM_2D_ARRAY;
		188	case PIPE_TEXTURE_3D:
		189	return V_030000_SQ_TEX_DIM_3D;
		190	case PIPE_TEXTURE_CUBE:
		191	case PIPE_TEXTURE_CUBE_ARRAY:
		192	return V_030000_SQ_TEX_DIM_CUBEMAP;
		193	}
		194	}
		195
		196	static uint32_t r600_translate_dbformat(enum pipe_format format)
		197	{
		198	switch (format) {
		199	case PIPE_FORMAT_Z16_UNORM:
		200	return V_028040_Z_16;
		201	case PIPE_FORMAT_Z24X8_UNORM:
		202	case PIPE_FORMAT_Z24_UNORM_S8_UINT:
		203	case PIPE_FORMAT_X8Z24_UNORM:
		204	case PIPE_FORMAT_S8_UINT_Z24_UNORM:
		205	return V_028040_Z_24;
		206	case PIPE_FORMAT_Z32_FLOAT:
		207	case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
		208	return V_028040_Z_32_FLOAT;
		209	default:
		210	return ~0U;
		211	}
		212	}
		213
		214	static uint32_t r600_translate_colorswap(enum pipe_format format)
		215	{
		216	switch (format) {
		217	/* 8-bit buffers. */
		218	case PIPE_FORMAT_L4A4_UNORM:
		219	case PIPE_FORMAT_A4R4_UNORM:
		220	return V_028C70_SWAP_ALT;
		221
		222	case PIPE_FORMAT_A8_UNORM:
		223	case PIPE_FORMAT_A8_SNORM:
		224	case PIPE_FORMAT_A8_UINT:
		225	case PIPE_FORMAT_A8_SINT:
		226	case PIPE_FORMAT_A16_UNORM:
		227	case PIPE_FORMAT_A16_SNORM:
		228	case PIPE_FORMAT_A16_UINT:
		229	case PIPE_FORMAT_A16_SINT:
		230	case PIPE_FORMAT_A16_FLOAT:
		231	case PIPE_FORMAT_A32_UINT:
		232	case PIPE_FORMAT_A32_SINT:
		233	case PIPE_FORMAT_A32_FLOAT:
		234	case PIPE_FORMAT_R4A4_UNORM:
		235	return V_028C70_SWAP_ALT_REV;
		236	case PIPE_FORMAT_I8_UNORM:
		237	case PIPE_FORMAT_I8_SNORM:
		238	case PIPE_FORMAT_I8_UINT:
		239	case PIPE_FORMAT_I8_SINT:
		240	case PIPE_FORMAT_I16_UNORM:
		241	case PIPE_FORMAT_I16_SNORM:
		242	case PIPE_FORMAT_I16_UINT:
		243	case PIPE_FORMAT_I16_SINT:
		244	case PIPE_FORMAT_I16_FLOAT:
		245	case PIPE_FORMAT_I32_UINT:
		246	case PIPE_FORMAT_I32_SINT:
		247	case PIPE_FORMAT_I32_FLOAT:
		248	case PIPE_FORMAT_L8_UNORM:
		249	case PIPE_FORMAT_L8_SNORM:
		250	case PIPE_FORMAT_L8_UINT:
		251	case PIPE_FORMAT_L8_SINT:
		252	case PIPE_FORMAT_L8_SRGB:
		253	case PIPE_FORMAT_L16_UNORM:
		254	case PIPE_FORMAT_L16_SNORM:
		255	case PIPE_FORMAT_L16_UINT:
		256	case PIPE_FORMAT_L16_SINT:
		257	case PIPE_FORMAT_L16_FLOAT:
		258	case PIPE_FORMAT_L32_UINT:
		259	case PIPE_FORMAT_L32_SINT:
		260	case PIPE_FORMAT_L32_FLOAT:
		261	case PIPE_FORMAT_R8_UNORM:
		262	case PIPE_FORMAT_R8_SNORM:
		263	case PIPE_FORMAT_R8_UINT:
		264	case PIPE_FORMAT_R8_SINT:
		265	return V_028C70_SWAP_STD;
		266
		267	/* 16-bit buffers. */
		268	case PIPE_FORMAT_B5G6R5_UNORM:
		269	return V_028C70_SWAP_STD_REV;
		270
		271	case PIPE_FORMAT_B5G5R5A1_UNORM:
		272	case PIPE_FORMAT_B5G5R5X1_UNORM:
		273	return V_028C70_SWAP_ALT;
		274
		275	case PIPE_FORMAT_B4G4R4A4_UNORM:
		276	case PIPE_FORMAT_B4G4R4X4_UNORM:
		277	return V_028C70_SWAP_ALT;
		278
		279	case PIPE_FORMAT_Z16_UNORM:
		280	return V_028C70_SWAP_STD;
		281
		282	case PIPE_FORMAT_L8A8_UNORM:
		283	case PIPE_FORMAT_L8A8_SNORM:
		284	case PIPE_FORMAT_L8A8_UINT:
		285	case PIPE_FORMAT_L8A8_SINT:
		286	case PIPE_FORMAT_L8A8_SRGB:
		287	case PIPE_FORMAT_L16A16_UNORM:
		288	case PIPE_FORMAT_L16A16_SNORM:
		289	case PIPE_FORMAT_L16A16_UINT:
		290	case PIPE_FORMAT_L16A16_SINT:
		291	case PIPE_FORMAT_L16A16_FLOAT:
		292	case PIPE_FORMAT_L32A32_UINT:
		293	case PIPE_FORMAT_L32A32_SINT:
		294	case PIPE_FORMAT_L32A32_FLOAT:
		295	case PIPE_FORMAT_R8A8_UNORM:
		296	case PIPE_FORMAT_R8A8_SNORM:
		297	case PIPE_FORMAT_R8A8_UINT:
		298	case PIPE_FORMAT_R8A8_SINT:
		299	case PIPE_FORMAT_R16A16_UNORM:
		300	case PIPE_FORMAT_R16A16_SNORM:
		301	case PIPE_FORMAT_R16A16_UINT:
		302	case PIPE_FORMAT_R16A16_SINT:
		303	case PIPE_FORMAT_R16A16_FLOAT:
		304	case PIPE_FORMAT_R32A32_UINT:
		305	case PIPE_FORMAT_R32A32_SINT:
		306	case PIPE_FORMAT_R32A32_FLOAT:
		307	return V_028C70_SWAP_ALT;
		308	case PIPE_FORMAT_R8G8_UNORM:
		309	case PIPE_FORMAT_R8G8_SNORM:
		310	case PIPE_FORMAT_R8G8_UINT:
		311	case PIPE_FORMAT_R8G8_SINT:
		312	return V_028C70_SWAP_STD;
		313
		314	case PIPE_FORMAT_R16_UNORM:
		315	case PIPE_FORMAT_R16_SNORM:
		316	case PIPE_FORMAT_R16_UINT:
		317	case PIPE_FORMAT_R16_SINT:
		318	case PIPE_FORMAT_R16_FLOAT:
		319	return V_028C70_SWAP_STD;
		320
		321	/* 32-bit buffers. */
		322	case PIPE_FORMAT_A8B8G8R8_SRGB:
		323	return V_028C70_SWAP_STD_REV;
		324	case PIPE_FORMAT_B8G8R8A8_SRGB:
		325	return V_028C70_SWAP_ALT;
		326
		327	case PIPE_FORMAT_B8G8R8A8_UNORM:
		328	case PIPE_FORMAT_B8G8R8X8_UNORM:
		329	return V_028C70_SWAP_ALT;
		330
		331	case PIPE_FORMAT_A8R8G8B8_UNORM:
		332	case PIPE_FORMAT_X8R8G8B8_UNORM:
		333	return V_028C70_SWAP_ALT_REV;
		334	case PIPE_FORMAT_R8G8B8A8_SNORM:
		335	case PIPE_FORMAT_R8G8B8A8_UNORM:
		336	case PIPE_FORMAT_R8G8B8A8_SINT:
		337	case PIPE_FORMAT_R8G8B8A8_UINT:
		338	case PIPE_FORMAT_R8G8B8X8_UNORM:
		339	case PIPE_FORMAT_R8G8B8X8_SNORM:
		340	case PIPE_FORMAT_R8G8B8X8_SRGB:
		341	case PIPE_FORMAT_R8G8B8X8_UINT:
		342	case PIPE_FORMAT_R8G8B8X8_SINT:
		343	return V_028C70_SWAP_STD;
		344
		345	case PIPE_FORMAT_A8B8G8R8_UNORM:
		346	case PIPE_FORMAT_X8B8G8R8_UNORM:
		347	/* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
		348	return V_028C70_SWAP_STD_REV;
		349
		350	case PIPE_FORMAT_Z24X8_UNORM:
		351	case PIPE_FORMAT_Z24_UNORM_S8_UINT:
		352	return V_028C70_SWAP_STD;
		353
		354	case PIPE_FORMAT_X8Z24_UNORM:
		355	case PIPE_FORMAT_S8_UINT_Z24_UNORM:
		356	return V_028C70_SWAP_STD_REV;
		357
		358	case PIPE_FORMAT_R10G10B10A2_UNORM:
		359	case PIPE_FORMAT_R10G10B10X2_SNORM:
		360	case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
		361	return V_028C70_SWAP_STD;
		362
		363	case PIPE_FORMAT_B10G10R10A2_UNORM:
		364	case PIPE_FORMAT_B10G10R10A2_UINT:
		365	case PIPE_FORMAT_B10G10R10X2_UNORM:
		366	return V_028C70_SWAP_ALT;
		367
		368	case PIPE_FORMAT_R11G11B10_FLOAT:
		369	case PIPE_FORMAT_R32_FLOAT:
		370	case PIPE_FORMAT_R32_UINT:
		371	case PIPE_FORMAT_R32_SINT:
		372	case PIPE_FORMAT_Z32_FLOAT:
		373	case PIPE_FORMAT_R16G16_FLOAT:
		374	case PIPE_FORMAT_R16G16_UNORM:
		375	case PIPE_FORMAT_R16G16_SNORM:
		376	case PIPE_FORMAT_R16G16_UINT:
		377	case PIPE_FORMAT_R16G16_SINT:
		378	return V_028C70_SWAP_STD;
		379
		380	/* 64-bit buffers. */
		381	case PIPE_FORMAT_R32G32_FLOAT:
		382	case PIPE_FORMAT_R32G32_UINT:
		383	case PIPE_FORMAT_R32G32_SINT:
		384	case PIPE_FORMAT_R16G16B16A16_UNORM:
		385	case PIPE_FORMAT_R16G16B16A16_SNORM:
		386	case PIPE_FORMAT_R16G16B16A16_UINT:
		387	case PIPE_FORMAT_R16G16B16A16_SINT:
		388	case PIPE_FORMAT_R16G16B16A16_FLOAT:
		389	case PIPE_FORMAT_R16G16B16X16_UNORM:
		390	case PIPE_FORMAT_R16G16B16X16_SNORM:
		391	case PIPE_FORMAT_R16G16B16X16_FLOAT:
		392	case PIPE_FORMAT_R16G16B16X16_UINT:
		393	case PIPE_FORMAT_R16G16B16X16_SINT:
		394	case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
		395
		396	/* 128-bit buffers. */
		397	case PIPE_FORMAT_R32G32B32A32_FLOAT:
		398	case PIPE_FORMAT_R32G32B32A32_SNORM:
		399	case PIPE_FORMAT_R32G32B32A32_UNORM:
		400	case PIPE_FORMAT_R32G32B32A32_SINT:
		401	case PIPE_FORMAT_R32G32B32A32_UINT:
		402	case PIPE_FORMAT_R32G32B32X32_FLOAT:
		403	case PIPE_FORMAT_R32G32B32X32_UINT:
		404	case PIPE_FORMAT_R32G32B32X32_SINT:
		405	return V_028C70_SWAP_STD;
		406	default:
		407	R600_ERR("unsupported colorswap format %d\n", format);
		408	return ~0U;
		409	}
		410	return ~0U;
		411	}
		412
		413	static uint32_t r600_translate_colorformat(enum pipe_format format)
		414	{
		415	switch (format) {
		416	/* 8-bit buffers. */
		417	case PIPE_FORMAT_A8_UNORM:
		418	case PIPE_FORMAT_A8_SNORM:
		419	case PIPE_FORMAT_A8_UINT:
		420	case PIPE_FORMAT_A8_SINT:
		421	case PIPE_FORMAT_I8_UNORM:
		422	case PIPE_FORMAT_I8_SNORM:
		423	case PIPE_FORMAT_I8_UINT:
		424	case PIPE_FORMAT_I8_SINT:
		425	case PIPE_FORMAT_L8_UNORM:
		426	case PIPE_FORMAT_L8_SNORM:
		427	case PIPE_FORMAT_L8_UINT:
		428	case PIPE_FORMAT_L8_SINT:
		429	case PIPE_FORMAT_L8_SRGB:
		430	case PIPE_FORMAT_R8_UNORM:
		431	case PIPE_FORMAT_R8_SNORM:
		432	case PIPE_FORMAT_R8_UINT:
		433	case PIPE_FORMAT_R8_SINT:
		434	return V_028C70_COLOR_8;
		435
		436	/* 16-bit buffers. */
		437	case PIPE_FORMAT_B5G6R5_UNORM:
		438	return V_028C70_COLOR_5_6_5;
		439
		440	case PIPE_FORMAT_B5G5R5A1_UNORM:
		441	case PIPE_FORMAT_B5G5R5X1_UNORM:
		442	return V_028C70_COLOR_1_5_5_5;
		443
		444	case PIPE_FORMAT_B4G4R4A4_UNORM:
		445	case PIPE_FORMAT_B4G4R4X4_UNORM:
		446	return V_028C70_COLOR_4_4_4_4;
		447
		448	case PIPE_FORMAT_Z16_UNORM:
		449	return V_028C70_COLOR_16;
		450
		451	case PIPE_FORMAT_L8A8_UNORM:
		452	case PIPE_FORMAT_L8A8_SNORM:
		453	case PIPE_FORMAT_L8A8_UINT:
		454	case PIPE_FORMAT_L8A8_SINT:
		455	case PIPE_FORMAT_L8A8_SRGB:
		456	case PIPE_FORMAT_R8G8_UNORM:
		457	case PIPE_FORMAT_R8G8_SNORM:
		458	case PIPE_FORMAT_R8G8_UINT:
		459	case PIPE_FORMAT_R8G8_SINT:
		460	case PIPE_FORMAT_R8A8_UNORM:
		461	case PIPE_FORMAT_R8A8_SNORM:
		462	case PIPE_FORMAT_R8A8_UINT:
		463	case PIPE_FORMAT_R8A8_SINT:
		464	return V_028C70_COLOR_8_8;
		465
		466	case PIPE_FORMAT_R16_UNORM:
		467	case PIPE_FORMAT_R16_SNORM:
		468	case PIPE_FORMAT_R16_UINT:
		469	case PIPE_FORMAT_R16_SINT:
		470	case PIPE_FORMAT_A16_UNORM:
		471	case PIPE_FORMAT_A16_SNORM:
		472	case PIPE_FORMAT_A16_UINT:
		473	case PIPE_FORMAT_A16_SINT:
		474	case PIPE_FORMAT_L16_UNORM:
		475	case PIPE_FORMAT_L16_SNORM:
		476	case PIPE_FORMAT_L16_UINT:
		477	case PIPE_FORMAT_L16_SINT:
		478	case PIPE_FORMAT_I16_UNORM:
		479	case PIPE_FORMAT_I16_SNORM:
		480	case PIPE_FORMAT_I16_UINT:
		481	case PIPE_FORMAT_I16_SINT:
		482	return V_028C70_COLOR_16;
		483
		484	case PIPE_FORMAT_R16_FLOAT:
		485	case PIPE_FORMAT_A16_FLOAT:
		486	case PIPE_FORMAT_L16_FLOAT:
		487	case PIPE_FORMAT_I16_FLOAT:
		488	return V_028C70_COLOR_16_FLOAT;
		489
		490	/* 32-bit buffers. */
		491	case PIPE_FORMAT_A8B8G8R8_SRGB:
		492	case PIPE_FORMAT_A8B8G8R8_UNORM:
		493	case PIPE_FORMAT_A8R8G8B8_UNORM:
		494	case PIPE_FORMAT_B8G8R8A8_SRGB:
		495	case PIPE_FORMAT_B8G8R8A8_UNORM:
		496	case PIPE_FORMAT_B8G8R8X8_UNORM:
		497	case PIPE_FORMAT_R8G8B8A8_SNORM:
		498	case PIPE_FORMAT_R8G8B8A8_UNORM:
		499	case PIPE_FORMAT_R8G8B8X8_UNORM:
		500	case PIPE_FORMAT_R8G8B8X8_SNORM:
		501	case PIPE_FORMAT_R8G8B8X8_SRGB:
		502	case PIPE_FORMAT_R8G8B8X8_UINT:
		503	case PIPE_FORMAT_R8G8B8X8_SINT:
		504	case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
		505	case PIPE_FORMAT_X8B8G8R8_UNORM:
		506	case PIPE_FORMAT_X8R8G8B8_UNORM:
		507	case PIPE_FORMAT_R8G8B8_UNORM:
		508	case PIPE_FORMAT_R8G8B8A8_SINT:
		509	case PIPE_FORMAT_R8G8B8A8_UINT:
		510	return V_028C70_COLOR_8_8_8_8;
		511
		512	case PIPE_FORMAT_R10G10B10A2_UNORM:
		513	case PIPE_FORMAT_R10G10B10X2_SNORM:
		514	case PIPE_FORMAT_B10G10R10A2_UNORM:
		515	case PIPE_FORMAT_B10G10R10A2_UINT:
		516	case PIPE_FORMAT_B10G10R10X2_UNORM:
		517	case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
		518	return V_028C70_COLOR_2_10_10_10;
		519
		520	case PIPE_FORMAT_Z24X8_UNORM:
		521	case PIPE_FORMAT_Z24_UNORM_S8_UINT:
		522	return V_028C70_COLOR_8_24;
		523
		524	case PIPE_FORMAT_X8Z24_UNORM:
		525	case PIPE_FORMAT_S8_UINT_Z24_UNORM:
		526	return V_028C70_COLOR_24_8;
		527
		528	case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
		529	return V_028C70_COLOR_X24_8_32_FLOAT;
		530
		531	case PIPE_FORMAT_R32_UINT:
		532	case PIPE_FORMAT_R32_SINT:
		533	case PIPE_FORMAT_A32_UINT:
		534	case PIPE_FORMAT_A32_SINT:
		535	case PIPE_FORMAT_L32_UINT:
		536	case PIPE_FORMAT_L32_SINT:
		537	case PIPE_FORMAT_I32_UINT:
		538	case PIPE_FORMAT_I32_SINT:
		539	return V_028C70_COLOR_32;
		540
		541	case PIPE_FORMAT_R32_FLOAT:
		542	case PIPE_FORMAT_A32_FLOAT:
		543	case PIPE_FORMAT_L32_FLOAT:
		544	case PIPE_FORMAT_I32_FLOAT:
		545	case PIPE_FORMAT_Z32_FLOAT:
		546	return V_028C70_COLOR_32_FLOAT;
		547
		548	case PIPE_FORMAT_R16G16_FLOAT:
		549	case PIPE_FORMAT_L16A16_FLOAT:
		550	case PIPE_FORMAT_R16A16_FLOAT:
		551	return V_028C70_COLOR_16_16_FLOAT;
		552
		553	case PIPE_FORMAT_R16G16_UNORM:
		554	case PIPE_FORMAT_R16G16_SNORM:
		555	case PIPE_FORMAT_R16G16_UINT:
		556	case PIPE_FORMAT_R16G16_SINT:
		557	case PIPE_FORMAT_L16A16_UNORM:
		558	case PIPE_FORMAT_L16A16_SNORM:
		559	case PIPE_FORMAT_L16A16_UINT:
		560	case PIPE_FORMAT_L16A16_SINT:
		561	case PIPE_FORMAT_R16A16_UNORM:
		562	case PIPE_FORMAT_R16A16_SNORM:
		563	case PIPE_FORMAT_R16A16_UINT:
		564	case PIPE_FORMAT_R16A16_SINT:
		565	return V_028C70_COLOR_16_16;
		566
		567	case PIPE_FORMAT_R11G11B10_FLOAT:
		568	return V_028C70_COLOR_10_11_11_FLOAT;
		569
		570	/* 64-bit buffers. */
		571	case PIPE_FORMAT_R16G16B16A16_UINT:
		572	case PIPE_FORMAT_R16G16B16A16_SINT:
		573	case PIPE_FORMAT_R16G16B16A16_UNORM:
		574	case PIPE_FORMAT_R16G16B16A16_SNORM:
		575	case PIPE_FORMAT_R16G16B16X16_UNORM:
		576	case PIPE_FORMAT_R16G16B16X16_SNORM:
		577	case PIPE_FORMAT_R16G16B16X16_UINT:
		578	case PIPE_FORMAT_R16G16B16X16_SINT:
		579	return V_028C70_COLOR_16_16_16_16;
		580
		581	case PIPE_FORMAT_R16G16B16A16_FLOAT:
		582	case PIPE_FORMAT_R16G16B16X16_FLOAT:
		583	return V_028C70_COLOR_16_16_16_16_FLOAT;
		584
		585	case PIPE_FORMAT_R32G32_FLOAT:
		586	case PIPE_FORMAT_L32A32_FLOAT:
		587	case PIPE_FORMAT_R32A32_FLOAT:
		588	return V_028C70_COLOR_32_32_FLOAT;
		589
		590	case PIPE_FORMAT_R32G32_SINT:
		591	case PIPE_FORMAT_R32G32_UINT:
		592	case PIPE_FORMAT_L32A32_UINT:
		593	case PIPE_FORMAT_L32A32_SINT:
		594	return V_028C70_COLOR_32_32;
		595
		596	/* 128-bit buffers. */
		597	case PIPE_FORMAT_R32G32B32A32_SNORM:
		598	case PIPE_FORMAT_R32G32B32A32_UNORM:
		599	case PIPE_FORMAT_R32G32B32A32_SINT:
		600	case PIPE_FORMAT_R32G32B32A32_UINT:
		601	case PIPE_FORMAT_R32G32B32X32_UINT:
		602	case PIPE_FORMAT_R32G32B32X32_SINT:
		603	return V_028C70_COLOR_32_32_32_32;
		604	case PIPE_FORMAT_R32G32B32A32_FLOAT:
		605	case PIPE_FORMAT_R32G32B32X32_FLOAT:
		606	return V_028C70_COLOR_32_32_32_32_FLOAT;
		607
		608	/* YUV buffers. */
		609	case PIPE_FORMAT_UYVY:
		610	case PIPE_FORMAT_YUYV:
		611	default:
		612	return ~0U; /* Unsupported. */
		613	}
		614	}
		615
		616	static uint32_t r600_colorformat_endian_swap(uint32_t colorformat)
		617	{
		618	if (R600_BIG_ENDIAN) {
		619	switch(colorformat) {
		620
		621	/* 8-bit buffers. */
		622	case V_028C70_COLOR_8:
		623	return ENDIAN_NONE;
		624
		625	/* 16-bit buffers. */
		626	case V_028C70_COLOR_5_6_5:
		627	case V_028C70_COLOR_1_5_5_5:
		628	case V_028C70_COLOR_4_4_4_4:
		629	case V_028C70_COLOR_16:
		630	case V_028C70_COLOR_8_8:
		631	return ENDIAN_8IN16;
		632
		633	/* 32-bit buffers. */
		634	case V_028C70_COLOR_8_8_8_8:
		635	case V_028C70_COLOR_2_10_10_10:
		636	case V_028C70_COLOR_8_24:
		637	case V_028C70_COLOR_24_8:
		638	case V_028C70_COLOR_32_FLOAT:
		639	case V_028C70_COLOR_16_16_FLOAT:
		640	case V_028C70_COLOR_16_16:
		641	return ENDIAN_8IN32;
		642
		643	/* 64-bit buffers. */
		644	case V_028C70_COLOR_16_16_16_16:
		645	case V_028C70_COLOR_16_16_16_16_FLOAT:
		646	return ENDIAN_8IN16;
		647
		648	case V_028C70_COLOR_32_32_FLOAT:
		649	case V_028C70_COLOR_32_32:
		650	case V_028C70_COLOR_X24_8_32_FLOAT:
		651	return ENDIAN_8IN32;
		652
		653	/* 96-bit buffers. */
		654	case V_028C70_COLOR_32_32_32_FLOAT:
		655	/* 128-bit buffers. */
		656	case V_028C70_COLOR_32_32_32_32_FLOAT:
		657	case V_028C70_COLOR_32_32_32_32:
		658	return ENDIAN_8IN32;
		659	default:
		660	return ENDIAN_NONE; /* Unsupported. */
		661	}
		662	} else {
		663	return ENDIAN_NONE;
		664	}
		665	}
		666
		667	static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
		668	{
		669	return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U;
		670	}
		671
		672	static bool r600_is_colorbuffer_format_supported(enum pipe_format format)
		673	{
		674	return r600_translate_colorformat(format) != ~0U &&
		675	r600_translate_colorswap(format) != ~0U;
		676	}
		677
		678	static bool r600_is_zs_format_supported(enum pipe_format format)
		679	{
		680	return r600_translate_dbformat(format) != ~0U;
		681	}
		682
		683	boolean evergreen_is_format_supported(struct pipe_screen *screen,
		684	enum pipe_format format,
		685	enum pipe_texture_target target,
		686	unsigned sample_count,
		687	unsigned usage)
		688	{
		689	struct r600_screen rscreen = (struct r600_screen)screen;
		690	unsigned retval = 0;
		691
		692	if (target >= PIPE_MAX_TEXTURE_TYPES) {
		693	R600_ERR("r600: unsupported texture type %d\n", target);
		694	return FALSE;
		695	}
		696
		697	if (!util_format_is_supported(format, usage))
		698	return FALSE;
		699
		700	if (sample_count > 1) {
		701	if (!rscreen->has_msaa)
		702	return FALSE;
		703
		704	switch (sample_count) {
		705	case 2:
		706	case 4:
		707	case 8:
		708	break;
		709	default:
		710	return FALSE;
		711	}
		712	}
		713
		714	if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
		715	r600_is_sampler_format_supported(screen, format)) {
		716	retval \|= PIPE_BIND_SAMPLER_VIEW;
		717	}
		718
		719	if ((usage & (PIPE_BIND_RENDER_TARGET \|
		720	PIPE_BIND_DISPLAY_TARGET \|
		721	PIPE_BIND_SCANOUT \|
		722	PIPE_BIND_SHARED)) &&
		723	r600_is_colorbuffer_format_supported(format)) {
		724	retval \|= usage &
		725	(PIPE_BIND_RENDER_TARGET \|
		726	PIPE_BIND_DISPLAY_TARGET \|
		727	PIPE_BIND_SCANOUT \|
		728	PIPE_BIND_SHARED);
		729	}
		730
		731	if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
		732	r600_is_zs_format_supported(format)) {
		733	retval \|= PIPE_BIND_DEPTH_STENCIL;
		734	}
		735
		736	if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
		737	r600_is_vertex_format_supported(format)) {
		738	retval \|= PIPE_BIND_VERTEX_BUFFER;
		739	}
		740
		741	if (usage & PIPE_BIND_TRANSFER_READ)
		742	retval \|= PIPE_BIND_TRANSFER_READ;
		743	if (usage & PIPE_BIND_TRANSFER_WRITE)
		744	retval \|= PIPE_BIND_TRANSFER_WRITE;
		745
		746	return retval == usage;
		747	}
		748
		749	static void evergreen_create_blend_state_mode(struct pipe_context ctx,
		750	const struct pipe_blend_state *state, int mode)
		751	{
		752	uint32_t color_control = 0, target_mask = 0;
		753	struct r600_blend_state *blend = CALLOC_STRUCT(r600_blend_state);
		754
		755	if (!blend) {
		756	return NULL;
		757	}
		758
		759	r600_init_command_buffer(&blend->buffer, 20);
		760	r600_init_command_buffer(&blend->buffer_no_blend, 20);
		761
		762	if (state->logicop_enable) {
		763	color_control \|= (state->logicop_func << 16) \| (state->logicop_func << 20);
		764	} else {
		765	color_control \|= (0xcc << 16);
		766	}
		767	/* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
		768	if (state->independent_blend_enable) {
		769	for (int i = 0; i < 8; i++) {
		770	target_mask \|= (state->rt[i].colormask << (4 * i));
		771	}
		772	} else {
		773	for (int i = 0; i < 8; i++) {
		774	target_mask \|= (state->rt[0].colormask << (4 * i));
		775	}
		776	}
		777
		778	/* only have dual source on MRT0 */
		779	blend->dual_src_blend = util_blend_state_is_dual(state, 0);
		780	blend->cb_target_mask = target_mask;
		781	blend->alpha_to_one = state->alpha_to_one;
		782
		783	if (target_mask)
		784	color_control \|= S_028808_MODE(mode);
		785	else
		786	color_control \|= S_028808_MODE(V_028808_CB_DISABLE);
		787
		788
		789	r600_store_context_reg(&blend->buffer, R_028808_CB_COLOR_CONTROL, color_control);
		790	r600_store_context_reg(&blend->buffer, R_028B70_DB_ALPHA_TO_MASK,
		791	S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) \|
		792	S_028B70_ALPHA_TO_MASK_OFFSET0(2) \|
		793	S_028B70_ALPHA_TO_MASK_OFFSET1(2) \|
		794	S_028B70_ALPHA_TO_MASK_OFFSET2(2) \|
		795	S_028B70_ALPHA_TO_MASK_OFFSET3(2));
		796	r600_store_context_reg_seq(&blend->buffer, R_028780_CB_BLEND0_CONTROL, 8);
		797
		798	/* Copy over the dwords set so far into buffer_no_blend.
		799	* Only the CB_BLENDi_CONTROL registers must be set after this. */
		800	memcpy(blend->buffer_no_blend.buf, blend->buffer.buf, blend->buffer.num_dw * 4);
		801	blend->buffer_no_blend.num_dw = blend->buffer.num_dw;
		802
		803	for (int i = 0; i < 8; i++) {
		804	/* state->rt entries > 0 only written if independent blending */
		805	const int j = state->independent_blend_enable ? i : 0;
		806
		807	unsigned eqRGB = state->rt[j].rgb_func;
		808	unsigned srcRGB = state->rt[j].rgb_src_factor;
		809	unsigned dstRGB = state->rt[j].rgb_dst_factor;
		810	unsigned eqA = state->rt[j].alpha_func;
		811	unsigned srcA = state->rt[j].alpha_src_factor;
		812	unsigned dstA = state->rt[j].alpha_dst_factor;
		813	uint32_t bc = 0;
		814
		815	r600_store_value(&blend->buffer_no_blend, 0);
		816
		817	if (!state->rt[j].blend_enable) {
		818	r600_store_value(&blend->buffer, 0);
		819	continue;
		820	}
		821
		822	bc \|= S_028780_BLEND_CONTROL_ENABLE(1);
		823	bc \|= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
		824	bc \|= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
		825	bc \|= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
		826
		827	if (srcA != srcRGB \|\| dstA != dstRGB \|\| eqA != eqRGB) {
		828	bc \|= S_028780_SEPARATE_ALPHA_BLEND(1);
		829	bc \|= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
		830	bc \|= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
		831	bc \|= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
		832	}
		833	r600_store_value(&blend->buffer, bc);
		834	}
		835	return blend;
		836	}
		837
		838	static void evergreen_create_blend_state(struct pipe_context ctx,
		839	const struct pipe_blend_state *state)
		840	{
		841
		842	return evergreen_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
		843	}
		844
		845	static void evergreen_create_dsa_state(struct pipe_context ctx,
		846	const struct pipe_depth_stencil_alpha_state *state)
		847	{
		848	unsigned db_depth_control, alpha_test_control, alpha_ref;
		849	struct r600_dsa_state *dsa = CALLOC_STRUCT(r600_dsa_state);
		850
		851	if (dsa == NULL) {
		852	return NULL;
		853	}
		854
		855	r600_init_command_buffer(&dsa->buffer, 3);
		856
		857	dsa->valuemask[0] = state->stencil[0].valuemask;
		858	dsa->valuemask[1] = state->stencil[1].valuemask;
		859	dsa->writemask[0] = state->stencil[0].writemask;
		860	dsa->writemask[1] = state->stencil[1].writemask;
		861	dsa->zwritemask = state->depth.writemask;
		862
		863	db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) \|
		864	S_028800_Z_WRITE_ENABLE(state->depth.writemask) \|
		865	S_028800_ZFUNC(state->depth.func);
		866
		867	/* stencil */
		868	if (state->stencil[0].enabled) {
		869	db_depth_control \|= S_028800_STENCIL_ENABLE(1);
		870	db_depth_control \|= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
		871	db_depth_control \|= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
		872	db_depth_control \|= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
		873	db_depth_control \|= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
		874
		875	if (state->stencil[1].enabled) {
		876	db_depth_control \|= S_028800_BACKFACE_ENABLE(1);
		877	db_depth_control \|= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
		878	db_depth_control \|= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
		879	db_depth_control \|= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
		880	db_depth_control \|= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
		881	}
		882	}
		883
		884	/* alpha */
		885	alpha_test_control = 0;
		886	alpha_ref = 0;
		887	if (state->alpha.enabled) {
		888	alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
		889	alpha_test_control \|= S_028410_ALPHA_TEST_ENABLE(1);
		890	alpha_ref = fui(state->alpha.ref_value);
		891	}
		892	dsa->sx_alpha_test_control = alpha_test_control & 0xff;
		893	dsa->alpha_ref = alpha_ref;
		894
		895	/* misc */
		896	r600_store_context_reg(&dsa->buffer, R_028800_DB_DEPTH_CONTROL, db_depth_control);
		897	return dsa;
		898	}
		899
		900	static void evergreen_create_rs_state(struct pipe_context ctx,
		901	const struct pipe_rasterizer_state *state)
		902	{
		903	struct r600_context rctx = (struct r600_context )ctx;
		904	unsigned tmp, spi_interp;
		905	float psize_min, psize_max;
		906	struct r600_rasterizer_state *rs = CALLOC_STRUCT(r600_rasterizer_state);
		907
		908	if (rs == NULL) {
		909	return NULL;
		910	}
		911
		912	r600_init_command_buffer(&rs->buffer, 30);
		913
		914	rs->flatshade = state->flatshade;
		915	rs->sprite_coord_enable = state->sprite_coord_enable;
		916	rs->two_side = state->light_twoside;
		917	rs->clip_plane_enable = state->clip_plane_enable;
		918	rs->pa_sc_line_stipple = state->line_stipple_enable ?
		919	S_028A0C_LINE_PATTERN(state->line_stipple_pattern) \|
		920	S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
		921	rs->pa_cl_clip_cntl =
		922	S_028810_PS_UCP_MODE(3) \|
		923	S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) \|
		924	S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) \|
		925	S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
		926	rs->multisample_enable = state->multisample;
		927
		928	/* offset */
		929	rs->offset_units = state->offset_units;
		930	rs->offset_scale = state->offset_scale * 12.0f;
		931	rs->offset_enable = state->offset_point \|\| state->offset_line \|\| state->offset_tri;
		932
		933	if (state->point_size_per_vertex) {
		934	psize_min = util_get_min_point_size(state);
		935	psize_max = 8192;
		936	} else {
		937	/* Force the point size to be as if the vertex output was disabled. */
		938	psize_min = state->point_size;
		939	psize_max = state->point_size;
		940	}
		941
		942	spi_interp = S_0286D4_FLAT_SHADE_ENA(1);
		943	if (state->sprite_coord_enable) {
		944	spi_interp \|= S_0286D4_PNT_SPRITE_ENA(1) \|
		945	S_0286D4_PNT_SPRITE_OVRD_X(2) \|
		946	S_0286D4_PNT_SPRITE_OVRD_Y(3) \|
		947	S_0286D4_PNT_SPRITE_OVRD_Z(0) \|
		948	S_0286D4_PNT_SPRITE_OVRD_W(1);
		949	if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
		950	spi_interp \|= S_0286D4_PNT_SPRITE_TOP_1(1);
		951	}
		952	}
		953
		954	r600_store_context_reg_seq(&rs->buffer, R_028A00_PA_SU_POINT_SIZE, 3);
		955	/* point size 12.4 fixed point (divide by two, because 0.5 = 1 pixel) */
		956	tmp = r600_pack_float_12p4(state->point_size/2);
		957	r600_store_value(&rs->buffer, /* R_028A00_PA_SU_POINT_SIZE */
		958	S_028A00_HEIGHT(tmp) \| S_028A00_WIDTH(tmp));
		959	r600_store_value(&rs->buffer, /* R_028A04_PA_SU_POINT_MINMAX */
		960	S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) \|
		961	S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
		962	r600_store_value(&rs->buffer, /* R_028A08_PA_SU_LINE_CNTL */
		963	S_028A08_WIDTH((unsigned)(state->line_width * 8)));
		964
		965	r600_store_context_reg(&rs->buffer, R_0286D4_SPI_INTERP_CONTROL_0, spi_interp);
		966	r600_store_context_reg(&rs->buffer, R_028A48_PA_SC_MODE_CNTL_0,
		967	S_028A48_MSAA_ENABLE(state->multisample) \|
		968	S_028A48_VPORT_SCISSOR_ENABLE(state->scissor) \|
		969	S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable));
		970
		971	if (rctx->chip_class == CAYMAN) {
		972	r600_store_context_reg(&rs->buffer, CM_R_028BE4_PA_SU_VTX_CNTL,
		973	S_028C08_PIX_CENTER_HALF(state->half_pixel_center) \|
		974	S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
		975	} else {
		976	r600_store_context_reg(&rs->buffer, R_028C08_PA_SU_VTX_CNTL,
		977	S_028C08_PIX_CENTER_HALF(state->half_pixel_center) \|
		978	S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
		979	}
		980
		981	r600_store_context_reg(&rs->buffer, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
		982	r600_store_context_reg(&rs->buffer, R_028814_PA_SU_SC_MODE_CNTL,
		983	S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) \|
		984	S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) \|
		985	S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) \|
		986	S_028814_FACE(!state->front_ccw) \|
		987	S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) \|
		988	S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) \|
		989	S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) \|
		990	S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL \|\|
		991	state->fill_back != PIPE_POLYGON_MODE_FILL) \|
		992	S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) \|
		993	S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)));
		994	r600_store_context_reg(&rs->buffer, R_028350_SX_MISC, S_028350_MULTIPASS(state->rasterizer_discard));
		995	return rs;
		996	}
		997
		998	static void evergreen_create_sampler_state(struct pipe_context ctx,
		999	const struct pipe_sampler_state *state)
		1000	{
		1001	struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state);
		1002	unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
		1003
		1004	if (ss == NULL) {
		1005	return NULL;
		1006	}
		1007
		1008	ss->border_color_use = sampler_state_needs_border_color(state);
		1009
		1010	/* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */
		1011	ss->tex_sampler_words[0] =
		1012	S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) \|
		1013	S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) \|
		1014	S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) \|
		1015	S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) \| aniso_flag_offset) \|
		1016	S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) \| aniso_flag_offset) \|
		1017	S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) \|
		1018	S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) \|
		1019	S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) \|
		1020	S_03C000_BORDER_COLOR_TYPE(ss->border_color_use ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0);
		1021	/* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */
		1022	ss->tex_sampler_words[1] =
		1023	S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) \|
		1024	S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8));
		1025	/* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */
		1026	ss->tex_sampler_words[2] =
		1027	S_03C008_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) \|
		1028	(state->seamless_cube_map ? 0 : S_03C008_DISABLE_CUBE_WRAP(1)) \|
		1029	S_03C008_TYPE(1);
		1030
		1031	if (ss->border_color_use) {
		1032	memcpy(&ss->border_color, &state->border_color, sizeof(state->border_color));
		1033	}
		1034	return ss;
		1035	}
		1036
		1037	static struct pipe_sampler_view *
		1038	texture_buffer_sampler_view(struct r600_pipe_sampler_view *view,
		1039	unsigned width0, unsigned height0)
		1040
		1041	{
		1042	struct pipe_context *ctx = view->base.context;
		1043	struct r600_texture tmp = (struct r600_texture)view->base.texture;
		1044	uint64_t va;
		1045	int stride = util_format_get_blocksize(view->base.format);
		1046	unsigned format, num_format, format_comp, endian;
		1047	unsigned swizzle_res;
		1048	unsigned char swizzle[4];
		1049	const struct util_format_description *desc;
		1050	unsigned offset = view->base.u.buf.first_element * stride;
		1051	unsigned size = (view->base.u.buf.last_element - view->base.u.buf.first_element + 1) * stride;
		1052
		1053	swizzle[0] = view->base.swizzle_r;
		1054	swizzle[1] = view->base.swizzle_g;
		1055	swizzle[2] = view->base.swizzle_b;
		1056	swizzle[3] = view->base.swizzle_a;
		1057
		1058	r600_vertex_data_type(view->base.format,
		1059	&format, &num_format, &format_comp,
		1060	&endian);
		1061
		1062	desc = util_format_description(view->base.format);
		1063
		1064	swizzle_res = r600_get_swizzle_combined(desc->swizzle, swizzle, TRUE);
		1065
		1066	va = r600_resource_va(ctx->screen, view->base.texture) + offset;
		1067	view->tex_resource = &tmp->resource;
		1068
		1069	view->skip_mip_address_reloc = true;
		1070	view->tex_resource_words[0] = va;
		1071	view->tex_resource_words[1] = size - 1;
		1072	view->tex_resource_words[2] = S_030008_BASE_ADDRESS_HI(va >> 32UL) \|
		1073	S_030008_STRIDE(stride) \|
		1074	S_030008_DATA_FORMAT(format) \|
		1075	S_030008_NUM_FORMAT_ALL(num_format) \|
		1076	S_030008_FORMAT_COMP_ALL(format_comp) \|
		1077	S_030008_SRF_MODE_ALL(1) \|
		1078	S_030008_ENDIAN_SWAP(endian);
		1079	view->tex_resource_words[3] = swizzle_res;
		1080	/*
		1081	* in theory dword 4 is for number of elements, for use with resinfo,
		1082	* but it seems to utterly fail to work, the amd gpu shader analyser
		1083	* uses a const buffer to store the element sizes for buffer txq
		1084	*/
		1085	view->tex_resource_words[4] = 0;
		1086	view->tex_resource_words[5] = view->tex_resource_words[6] = 0;
		1087	view->tex_resource_words[7] = S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_BUFFER);
		1088	return &view->base;
		1089	}
		1090
		1091	struct pipe_sampler_view *
		1092	evergreen_create_sampler_view_custom(struct pipe_context *ctx,
		1093	struct pipe_resource *texture,
		1094	const struct pipe_sampler_view *state,
		1095	unsigned width0, unsigned height0)
		1096	{
		1097	struct r600_screen rscreen = (struct r600_screen)ctx->screen;
		1098	struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
		1099	struct r600_texture tmp = (struct r600_texture)texture;
		1100	unsigned format, endian;
		1101	uint32_t word4 = 0, yuv_format = 0, pitch = 0;
		1102	unsigned char swizzle[4], array_mode = 0, non_disp_tiling = 0;
		1103	unsigned height, depth, width;
		1104	unsigned macro_aspect, tile_split, bankh, bankw, nbanks, fmask_bankh;
		1105	enum pipe_format pipe_format = state->format;
		1106	struct radeon_surface_level *surflevel;
		1107
		1108	if (view == NULL)
		1109	return NULL;
		1110
		1111	/* initialize base object */
		1112	view->base = *state;
		1113	view->base.texture = NULL;
		1114	pipe_reference(NULL, &texture->reference);
		1115	view->base.texture = texture;
		1116	view->base.reference.count = 1;
		1117	view->base.context = ctx;
		1118
		1119	if (texture->target == PIPE_BUFFER)
		1120	return texture_buffer_sampler_view(view, width0, height0);
		1121
		1122	swizzle[0] = state->swizzle_r;
		1123	swizzle[1] = state->swizzle_g;
		1124	swizzle[2] = state->swizzle_b;
		1125	swizzle[3] = state->swizzle_a;
		1126
		1127	tile_split = tmp->surface.tile_split;
		1128	surflevel = tmp->surface.level;
		1129
		1130	/* Texturing with separate depth and stencil. */
		1131	if (tmp->is_depth && !tmp->is_flushing_texture) {
		1132	switch (pipe_format) {
		1133	case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
		1134	pipe_format = PIPE_FORMAT_Z32_FLOAT;
		1135	break;
		1136	case PIPE_FORMAT_X8Z24_UNORM:
		1137	case PIPE_FORMAT_S8_UINT_Z24_UNORM:
		1138	/* Z24 is always stored like this. */
		1139	pipe_format = PIPE_FORMAT_Z24X8_UNORM;
		1140	break;
		1141	case PIPE_FORMAT_X24S8_UINT:
		1142	case PIPE_FORMAT_S8X24_UINT:
		1143	case PIPE_FORMAT_X32_S8X24_UINT:
		1144	pipe_format = PIPE_FORMAT_S8_UINT;
		1145	tile_split = tmp->surface.stencil_tile_split;
		1146	surflevel = tmp->surface.stencil_level;
		1147	break;
		1148	default:;
		1149	}
		1150	}
		1151
		1152	format = r600_translate_texformat(ctx->screen, pipe_format,
		1153	swizzle,
		1154	&word4, &yuv_format);
		1155	assert(format != ~0);
		1156	if (format == ~0) {
		1157	FREE(view);
		1158	return NULL;
		1159	}
		1160
		1161	endian = r600_colorformat_endian_swap(format);
		1162
		1163	width = width0;
		1164	height = height0;
		1165	depth = texture->depth0;
		1166	pitch = surflevel[0].nblk_x * util_format_get_blockwidth(pipe_format);
		1167	non_disp_tiling = tmp->non_disp_tiling;
		1168
		1169	switch (surflevel[0].mode) {
		1170	case RADEON_SURF_MODE_LINEAR_ALIGNED:
		1171	array_mode = V_028C70_ARRAY_LINEAR_ALIGNED;
		1172	break;
		1173	case RADEON_SURF_MODE_2D:
		1174	array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
		1175	break;
		1176	case RADEON_SURF_MODE_1D:
		1177	array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
		1178	break;
		1179	case RADEON_SURF_MODE_LINEAR:
		1180	default:
		1181	array_mode = V_028C70_ARRAY_LINEAR_GENERAL;
		1182	break;
		1183	}
		1184	macro_aspect = tmp->surface.mtilea;
		1185	bankw = tmp->surface.bankw;
		1186	bankh = tmp->surface.bankh;
		1187	tile_split = eg_tile_split(tile_split);
		1188	macro_aspect = eg_macro_tile_aspect(macro_aspect);
		1189	bankw = eg_bank_wh(bankw);
		1190	bankh = eg_bank_wh(bankh);
		1191	fmask_bankh = eg_bank_wh(tmp->fmask_bank_height);
		1192
		1193	/* 128 bit formats require tile type = 1 */
		1194	if (rscreen->chip_class == CAYMAN) {
		1195	if (util_format_get_blocksize(pipe_format) >= 16)
		1196	non_disp_tiling = 1;
		1197	}
		1198	nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
		1199
		1200	if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
		1201	height = 1;
		1202	depth = texture->array_size;
		1203	} else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
		1204	depth = texture->array_size;
		1205	} else if (texture->target == PIPE_TEXTURE_CUBE_ARRAY)
		1206	depth = texture->array_size / 6;
		1207
		1208	view->tex_resource = &tmp->resource;
		1209	view->tex_resource_words[0] = (S_030000_DIM(r600_tex_dim(texture->target, texture->nr_samples)) \|
		1210	S_030000_PITCH((pitch / 8) - 1) \|
		1211	S_030000_TEX_WIDTH(width - 1));
		1212	if (rscreen->chip_class == CAYMAN)
		1213	view->tex_resource_words[0] \|= CM_S_030000_NON_DISP_TILING_ORDER(non_disp_tiling);
		1214	else
		1215	view->tex_resource_words[0] \|= S_030000_NON_DISP_TILING_ORDER(non_disp_tiling);
		1216	view->tex_resource_words[1] = (S_030004_TEX_HEIGHT(height - 1) \|
		1217	S_030004_TEX_DEPTH(depth - 1) \|
		1218	S_030004_ARRAY_MODE(array_mode));
		1219	view->tex_resource_words[2] = (surflevel[0].offset + r600_resource_va(ctx->screen, texture)) >> 8;
		1220
		1221	/* TEX_RESOURCE_WORD3.MIP_ADDRESS */
		1222	if (texture->nr_samples > 1 && rscreen->has_compressed_msaa_texturing) {
		1223	if (tmp->is_depth) {
		1224	/* disable FMASK (0 = disabled) */
		1225	view->tex_resource_words[3] = 0;
		1226	view->skip_mip_address_reloc = true;
		1227	} else {
		1228	/* FMASK should be in MIP_ADDRESS for multisample textures */
		1229	view->tex_resource_words[3] = (tmp->fmask_offset + r600_resource_va(ctx->screen, texture)) >> 8;
		1230	}
		1231	} else if (state->u.tex.last_level && texture->nr_samples <= 1) {
		1232	view->tex_resource_words[3] = (surflevel[1].offset + r600_resource_va(ctx->screen, texture)) >> 8;
		1233	} else {
		1234	view->tex_resource_words[3] = (surflevel[0].offset + r600_resource_va(ctx->screen, texture)) >> 8;
		1235	}
		1236
		1237	view->tex_resource_words[4] = (word4 \|
		1238	S_030010_SRF_MODE_ALL(V_030010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) \|
		1239	S_030010_ENDIAN_SWAP(endian));
		1240	view->tex_resource_words[5] = S_030014_BASE_ARRAY(state->u.tex.first_layer) \|
		1241	S_030014_LAST_ARRAY(state->u.tex.last_layer);
		1242	view->tex_resource_words[6] = S_030018_TILE_SPLIT(tile_split);
		1243
		1244	if (texture->nr_samples > 1) {
		1245	unsigned log_samples = util_logbase2(texture->nr_samples);
		1246	if (rscreen->chip_class == CAYMAN) {
		1247	view->tex_resource_words[4] \|= S_030010_LOG2_NUM_FRAGMENTS(log_samples);
		1248	}
		1249	/* LAST_LEVEL holds log2(nr_samples) for multisample textures */
		1250	view->tex_resource_words[5] \|= S_030014_LAST_LEVEL(log_samples);
		1251	view->tex_resource_words[6] \|= S_030018_FMASK_BANK_HEIGHT(fmask_bankh);
		1252	} else {
		1253	view->tex_resource_words[4] \|= S_030010_BASE_LEVEL(state->u.tex.first_level);
		1254	view->tex_resource_words[5] \|= S_030014_LAST_LEVEL(state->u.tex.last_level);
		1255	/* aniso max 16 samples */
		1256	view->tex_resource_words[6] \|= S_030018_MAX_ANISO(4);
		1257	}
		1258
		1259	view->tex_resource_words[7] = S_03001C_DATA_FORMAT(format) \|
		1260	S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE) \|
		1261	S_03001C_BANK_WIDTH(bankw) \|
		1262	S_03001C_BANK_HEIGHT(bankh) \|
		1263	S_03001C_MACRO_TILE_ASPECT(macro_aspect) \|
		1264	S_03001C_NUM_BANKS(nbanks) \|
		1265	S_03001C_DEPTH_SAMPLE_ORDER(tmp->is_depth && !tmp->is_flushing_texture);
		1266	return &view->base;
		1267	}
		1268
		1269	static struct pipe_sampler_view *
		1270	evergreen_create_sampler_view(struct pipe_context *ctx,
		1271	struct pipe_resource *tex,
		1272	const struct pipe_sampler_view *state)
		1273	{
		1274	return evergreen_create_sampler_view_custom(ctx, tex, state,
		1275	tex->width0, tex->height0);
		1276	}
		1277
		1278	static void evergreen_emit_clip_state(struct r600_context rctx, struct r600_atom atom)
		1279	{
		1280	struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
		1281	struct pipe_clip_state *state = &rctx->clip_state.state;
		1282
		1283	r600_write_context_reg_seq(cs, R_0285BC_PA_CL_UCP0_X, 6*4);
		1284	r600_write_array(cs, 64, (unsigned)state);
		1285	}
		1286
		1287	static void evergreen_set_polygon_stipple(struct pipe_context *ctx,
		1288	const struct pipe_poly_stipple *state)
		1289	{
		1290	}
		1291
		1292	static void evergreen_get_scissor_rect(struct r600_context *rctx,
		1293	unsigned tl_x, unsigned tl_y, unsigned br_x, unsigned br_y,
		1294	uint32_t tl, uint32_t br)
		1295	{
		1296	/* EG hw workaround */
		1297	if (br_x == 0)
		1298	tl_x = 1;
		1299	if (br_y == 0)
		1300	tl_y = 1;
		1301
		1302	/* cayman hw workaround */
		1303	if (rctx->chip_class == CAYMAN) {
		1304	if (br_x == 1 && br_y == 1)
		1305	br_x = 2;
		1306	}
		1307
		1308	*tl = S_028240_TL_X(tl_x) \| S_028240_TL_Y(tl_y);
		1309	*br = S_028244_BR_X(br_x) \| S_028244_BR_Y(br_y);
		1310	}
		1311
		1312	static void evergreen_set_scissor_states(struct pipe_context *ctx,
		1313	unsigned start_slot,
		1314	unsigned num_scissors,
		1315	const struct pipe_scissor_state *state)
		1316	{
		1317	struct r600_context rctx = (struct r600_context )ctx;
		1318
		1319	rctx->scissor.scissor = *state;
		1320	rctx->scissor.atom.dirty = true;
		1321	}
		1322
		1323	static void evergreen_emit_scissor_state(struct r600_context rctx, struct r600_atom atom)
		1324	{
		1325	struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
		1326	struct pipe_scissor_state *state = &rctx->scissor.scissor;
		1327	uint32_t tl, br;
		1328
		1329	evergreen_get_scissor_rect(rctx, state->minx, state->miny, state->maxx, state->maxy, &tl, &br);
		1330
		1331	r600_write_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL, 2);
		1332	r600_write_value(cs, tl);
		1333	r600_write_value(cs, br);
		1334	}
		1335
		1336	/**
		1337	* This function intializes the CB* register values for RATs. It is meant
		1338	* to be used for 1D aligned buffers that do not have an associated
		1339	* radeon_surface.
		1340	*/
		1341	void evergreen_init_color_surface_rat(struct r600_context *rctx,
		1342	struct r600_surface *surf)
		1343	{
		1344	struct pipe_resource *pipe_buffer = surf->base.texture;
		1345	unsigned format = r600_translate_colorformat(surf->base.format);
		1346	unsigned endian = r600_colorformat_endian_swap(format);
		1347	unsigned swap = r600_translate_colorswap(surf->base.format);
		1348	unsigned block_size =
		1349	align(util_format_get_blocksize(pipe_buffer->format), 4);
		1350	unsigned pitch_alignment =
		1351	MAX2(64, rctx->screen->tiling_info.group_bytes / block_size);
		1352	unsigned pitch = align(pipe_buffer->width0, pitch_alignment);
		1353
		1354	/* XXX: This is copied from evergreen_init_color_surface(). I don't
		1355	* know why this is necessary.
		1356	*/
		1357	if (pipe_buffer->usage == PIPE_USAGE_STAGING) {
		1358	endian = ENDIAN_NONE;
		1359	}
		1360
		1361	surf->cb_color_base =
		1362	r600_resource_va(rctx->context.screen, pipe_buffer) >> 8;
		1363
		1364	surf->cb_color_pitch = (pitch / 8) - 1;
		1365
		1366	surf->cb_color_slice = 0;
		1367
		1368	surf->cb_color_view = 0;
		1369
		1370	surf->cb_color_info =
		1371	S_028C70_ENDIAN(endian)
		1372	\| S_028C70_FORMAT(format)
		1373	\| S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED)
		1374	\| S_028C70_NUMBER_TYPE(V_028C70_NUMBER_UINT)
		1375	\| S_028C70_COMP_SWAP(swap)
		1376	\| S_028C70_BLEND_BYPASS(1) /* We must set this bit because we
		1377	* are using NUMBER_UINT */
		1378	\| S_028C70_RAT(1)
		1379	;
		1380
		1381	surf->cb_color_attrib = S_028C74_NON_DISP_TILING_ORDER(1);
		1382
		1383	/* For buffers, CB_COLOR0_DIM needs to be set to the number of
		1384	* elements. */
		1385	surf->cb_color_dim = pipe_buffer->width0;
		1386
		1387	/* Set the buffer range the GPU will have access to: */
		1388	util_range_add(&r600_resource(pipe_buffer)->valid_buffer_range,
		1389	0, pipe_buffer->width0);
		1390
		1391	surf->cb_color_cmask = surf->cb_color_base;
		1392	surf->cb_color_cmask_slice = 0;
		1393	surf->cb_color_fmask = surf->cb_color_base;
		1394	surf->cb_color_fmask_slice = 0;
		1395	}
		1396
		1397	void evergreen_init_color_surface(struct r600_context *rctx,
		1398	struct r600_surface *surf)
		1399	{
		1400	struct r600_screen *rscreen = rctx->screen;
		1401	struct r600_texture rtex = (struct r600_texture)surf->base.texture;
		1402	struct pipe_resource *pipe_tex = surf->base.texture;
		1403	unsigned level = surf->base.u.tex.level;
		1404	unsigned pitch, slice;
		1405	unsigned color_info, color_attrib, color_dim = 0;
		1406	unsigned format, swap, ntype, endian;
		1407	uint64_t offset, base_offset;
		1408	unsigned non_disp_tiling, macro_aspect, tile_split, bankh, bankw, fmask_bankh, nbanks;
		1409	const struct util_format_description *desc;
		1410	int i;
		1411	bool blend_clamp = 0, blend_bypass = 0;
		1412
		1413	offset = rtex->surface.level[level].offset;
		1414	if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
		1415	offset += rtex->surface.level[level].slice_size *
		1416	surf->base.u.tex.first_layer;
		1417	}
		1418	pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
		1419	slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
		1420	if (slice) {
		1421	slice = slice - 1;
		1422	}
		1423	color_info = 0;
		1424	switch (rtex->surface.level[level].mode) {
		1425	case RADEON_SURF_MODE_LINEAR_ALIGNED:
		1426	color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED);
		1427	non_disp_tiling = 1;
		1428	break;
		1429	case RADEON_SURF_MODE_1D:
		1430	color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_1D_TILED_THIN1);
		1431	non_disp_tiling = rtex->non_disp_tiling;
		1432	break;
		1433	case RADEON_SURF_MODE_2D:
		1434	color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_2D_TILED_THIN1);
		1435	non_disp_tiling = rtex->non_disp_tiling;
		1436	break;
		1437	case RADEON_SURF_MODE_LINEAR:
		1438	default:
		1439	color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_GENERAL);
		1440	non_disp_tiling = 1;
		1441	break;
		1442	}
		1443	tile_split = rtex->surface.tile_split;
		1444	macro_aspect = rtex->surface.mtilea;
		1445	bankw = rtex->surface.bankw;
		1446	bankh = rtex->surface.bankh;
		1447	fmask_bankh = rtex->fmask_bank_height;
		1448	tile_split = eg_tile_split(tile_split);
		1449	macro_aspect = eg_macro_tile_aspect(macro_aspect);
		1450	bankw = eg_bank_wh(bankw);
		1451	bankh = eg_bank_wh(bankh);
		1452	fmask_bankh = eg_bank_wh(fmask_bankh);
		1453
		1454	/* 128 bit formats require tile type = 1 */
		1455	if (rscreen->chip_class == CAYMAN) {
		1456	if (util_format_get_blocksize(surf->base.format) >= 16)
		1457	non_disp_tiling = 1;
		1458	}
		1459	nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
		1460	desc = util_format_description(surf->base.format);
		1461	for (i = 0; i < 4; i++) {
		1462	if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
		1463	break;
		1464	}
		1465	}
		1466
		1467	color_attrib = S_028C74_TILE_SPLIT(tile_split)\|
		1468	S_028C74_NUM_BANKS(nbanks) \|
		1469	S_028C74_BANK_WIDTH(bankw) \|
		1470	S_028C74_BANK_HEIGHT(bankh) \|
		1471	S_028C74_MACRO_TILE_ASPECT(macro_aspect) \|
		1472	S_028C74_NON_DISP_TILING_ORDER(non_disp_tiling) \|
		1473	S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
		1474
		1475	if (rctx->chip_class == CAYMAN) {
		1476	color_attrib \|= S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] ==
		1477	UTIL_FORMAT_SWIZZLE_1);
		1478
		1479	if (rtex->resource.b.b.nr_samples > 1) {
		1480	unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
		1481	color_attrib \|= S_028C74_NUM_SAMPLES(log_samples) \|
		1482	S_028C74_NUM_FRAGMENTS(log_samples);
		1483	}
		1484	}
		1485
		1486	ntype = V_028C70_NUMBER_UNORM;
		1487	if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
		1488	ntype = V_028C70_NUMBER_SRGB;
		1489	else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
		1490	if (desc->channel[i].normalized)
		1491	ntype = V_028C70_NUMBER_SNORM;
		1492	else if (desc->channel[i].pure_integer)
		1493	ntype = V_028C70_NUMBER_SINT;
		1494	} else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
		1495	if (desc->channel[i].normalized)
		1496	ntype = V_028C70_NUMBER_UNORM;
		1497	else if (desc->channel[i].pure_integer)
		1498	ntype = V_028C70_NUMBER_UINT;
		1499	}
		1500
		1501	format = r600_translate_colorformat(surf->base.format);
		1502	assert(format != ~0);
		1503
		1504	swap = r600_translate_colorswap(surf->base.format);
		1505	assert(swap != ~0);
		1506
		1507	if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
		1508	endian = ENDIAN_NONE;
		1509	} else {
		1510	endian = r600_colorformat_endian_swap(format);
		1511	}
		1512
		1513	/* blend clamp should be set for all NORM/SRGB types */
		1514	if (ntype == V_028C70_NUMBER_UNORM \|\| ntype == V_028C70_NUMBER_SNORM \|\|
		1515	ntype == V_028C70_NUMBER_SRGB)
		1516	blend_clamp = 1;
		1517
		1518	/* set blend bypass according to docs if SINT/UINT or
		1519	8/24 COLOR variants */
		1520	if (ntype == V_028C70_NUMBER_UINT \|\| ntype == V_028C70_NUMBER_SINT \|\|
		1521	format == V_028C70_COLOR_8_24 \|\| format == V_028C70_COLOR_24_8 \|\|
		1522	format == V_028C70_COLOR_X24_8_32_FLOAT) {
		1523	blend_clamp = 0;
		1524	blend_bypass = 1;
		1525	}
		1526
		1527	surf->alphatest_bypass = ntype == V_028C70_NUMBER_UINT \|\| ntype == V_028C70_NUMBER_SINT;
		1528
		1529	color_info \|= S_028C70_FORMAT(format) \|
		1530	S_028C70_COMP_SWAP(swap) \|
		1531	S_028C70_BLEND_CLAMP(blend_clamp) \|
		1532	S_028C70_BLEND_BYPASS(blend_bypass) \|
		1533	S_028C70_NUMBER_TYPE(ntype) \|
		1534	S_028C70_ENDIAN(endian);
		1535
		1536	if (rtex->is_rat) {
		1537	color_info \|= S_028C70_RAT(1);
		1538	color_dim = S_028C78_WIDTH_MAX(pipe_tex->width0 & 0xffff)
		1539	\| S_028C78_HEIGHT_MAX((pipe_tex->width0 >> 16) & 0xffff);
		1540	}
		1541
		1542	/* EXPORT_NORM is an optimzation that can be enabled for better
		1543	* performance in certain cases.
		1544	* EXPORT_NORM can be enabled if:
		1545	* - 11-bit or smaller UNORM/SNORM/SRGB
		1546	* - 16-bit or smaller FLOAT
		1547	*/
		1548	if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
		1549	((desc->channel[i].size < 12 &&
		1550	desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
		1551	ntype != V_028C70_NUMBER_UINT && ntype != V_028C70_NUMBER_SINT) \|\|
		1552	(desc->channel[i].size < 17 &&
		1553	desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
		1554	color_info \|= S_028C70_SOURCE_FORMAT(V_028C70_EXPORT_4C_16BPC);
		1555	surf->export_16bpc = true;
		1556	}
		1557
		1558	if (rtex->fmask_size && rtex->cmask_size) {
		1559	color_info \|= S_028C70_COMPRESSION(1) \| S_028C70_FAST_CLEAR(1);
		1560	}
		1561
		1562	base_offset = r600_resource_va(rctx->context.screen, pipe_tex);
		1563
		1564	/* XXX handle enabling of CB beyond BASE8 which has different offset */
		1565	surf->cb_color_base = (base_offset + offset) >> 8;
		1566	surf->cb_color_dim = color_dim;
		1567	surf->cb_color_info = color_info;
		1568	surf->cb_color_pitch = S_028C64_PITCH_TILE_MAX(pitch);
		1569	surf->cb_color_slice = S_028C68_SLICE_TILE_MAX(slice);
		1570	if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
		1571	surf->cb_color_view = 0;
		1572	} else {
		1573	surf->cb_color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) \|
		1574	S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
		1575	}
		1576	surf->cb_color_attrib = color_attrib;
		1577	if (rtex->fmask_size && rtex->cmask_size) {
		1578	surf->cb_color_fmask = (base_offset + rtex->fmask_offset) >> 8;
		1579	surf->cb_color_cmask = (base_offset + rtex->cmask_offset) >> 8;
		1580	} else {
		1581	surf->cb_color_fmask = surf->cb_color_base;
		1582	surf->cb_color_cmask = surf->cb_color_base;
		1583	}
		1584	surf->cb_color_fmask_slice = S_028C88_TILE_MAX(rtex->fmask_slice_tile_max);
		1585	surf->cb_color_cmask_slice = S_028C80_TILE_MAX(rtex->cmask_slice_tile_max);
		1586
		1587	surf->color_initialized = true;
		1588	}
		1589
		1590	static void evergreen_init_depth_surface(struct r600_context *rctx,
		1591	struct r600_surface *surf)
		1592	{
		1593	struct r600_screen *rscreen = rctx->screen;
		1594	struct pipe_screen *screen = &rscreen->screen;
		1595	struct r600_texture rtex = (struct r600_texture)surf->base.texture;
		1596	uint64_t offset;
		1597	unsigned level, pitch, slice, format, array_mode;
		1598	unsigned macro_aspect, tile_split, bankh, bankw, nbanks;
		1599
		1600	level = surf->base.u.tex.level;
		1601	format = r600_translate_dbformat(surf->base.format);
		1602	assert(format != ~0);
		1603
		1604	offset = r600_resource_va(screen, surf->base.texture);
		1605	offset += rtex->surface.level[level].offset;
		1606	pitch = (rtex->surface.level[level].nblk_x / 8) - 1;
		1607	slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
		1608	if (slice) {
		1609	slice = slice - 1;
		1610	}
		1611	switch (rtex->surface.level[level].mode) {
		1612	case RADEON_SURF_MODE_2D:
		1613	array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
		1614	break;
		1615	case RADEON_SURF_MODE_1D:
		1616	case RADEON_SURF_MODE_LINEAR_ALIGNED:
		1617	case RADEON_SURF_MODE_LINEAR:
		1618	default:
		1619	array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
		1620	break;
		1621	}
		1622	tile_split = rtex->surface.tile_split;
		1623	macro_aspect = rtex->surface.mtilea;
		1624	bankw = rtex->surface.bankw;
		1625	bankh = rtex->surface.bankh;
		1626	tile_split = eg_tile_split(tile_split);
		1627	macro_aspect = eg_macro_tile_aspect(macro_aspect);
		1628	bankw = eg_bank_wh(bankw);
		1629	bankh = eg_bank_wh(bankh);
		1630	nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
		1631	offset >>= 8;
		1632
		1633	surf->db_depth_info = S_028040_ARRAY_MODE(array_mode) \|
		1634	S_028040_FORMAT(format) \|
		1635	S_028040_TILE_SPLIT(tile_split)\|
		1636	S_028040_NUM_BANKS(nbanks) \|
		1637	S_028040_BANK_WIDTH(bankw) \|
		1638	S_028040_BANK_HEIGHT(bankh) \|
		1639	S_028040_MACRO_TILE_ASPECT(macro_aspect);
		1640	if (rscreen->chip_class == CAYMAN && rtex->resource.b.b.nr_samples > 1) {
		1641	surf->db_depth_info \|= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
		1642	}
		1643	surf->db_depth_base = offset;
		1644	surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) \|
		1645	S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
		1646	surf->db_depth_size = S_028058_PITCH_TILE_MAX(pitch);
		1647	surf->db_depth_slice = S_02805C_SLICE_TILE_MAX(slice);
		1648
		1649	switch (surf->base.format) {
		1650	case PIPE_FORMAT_Z24X8_UNORM:
		1651	case PIPE_FORMAT_Z24_UNORM_S8_UINT:
		1652	case PIPE_FORMAT_X8Z24_UNORM:
		1653	case PIPE_FORMAT_S8_UINT_Z24_UNORM:
		1654	surf->pa_su_poly_offset_db_fmt_cntl =
		1655	S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-24);
		1656	break;
		1657	case PIPE_FORMAT_Z32_FLOAT:
		1658	case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
		1659	surf->pa_su_poly_offset_db_fmt_cntl =
		1660	S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-23) \|
		1661	S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
		1662	break;
		1663	case PIPE_FORMAT_Z16_UNORM:
		1664	surf->pa_su_poly_offset_db_fmt_cntl =
		1665	S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-16);
		1666	break;
		1667	default:;
		1668	}
		1669
		1670	if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
		1671	uint64_t stencil_offset;
		1672	unsigned stile_split = rtex->surface.stencil_tile_split;
		1673
		1674	stile_split = eg_tile_split(stile_split);
		1675
		1676	stencil_offset = rtex->surface.stencil_level[level].offset;
		1677	stencil_offset += r600_resource_va(screen, surf->base.texture);
		1678
		1679	surf->db_stencil_base = stencil_offset >> 8;
		1680	surf->db_stencil_info = S_028044_FORMAT(V_028044_STENCIL_8) \|
		1681	S_028044_TILE_SPLIT(stile_split);
		1682	} else {
		1683	surf->db_stencil_base = offset;
		1684	/* DRM 2.6.18 allows the INVALID format to disable stencil.
		1685	* Older kernels are out of luck. */
		1686	surf->db_stencil_info = rctx->screen->info.drm_minor >= 18 ?
		1687	S_028044_FORMAT(V_028044_STENCIL_INVALID) :
		1688	S_028044_FORMAT(V_028044_STENCIL_8);
		1689	}
		1690
		1691	surf->htile_enabled = 0;
		1692	/* use htile only for first level */
		1693	if (rtex->htile && !level) {
		1694	uint64_t va = r600_resource_va(&rctx->screen->screen, &rtex->htile->b.b);
		1695	surf->htile_enabled = 1;
		1696	surf->db_htile_data_base = va >> 8;
		1697	surf->db_htile_surface = S_028ABC_HTILE_WIDTH(1) \|
		1698	S_028ABC_HTILE_HEIGHT(1) \|
		1699	S_028ABC_FULL_CACHE(1) \|
		1700	S_028ABC_LINEAR(1);
		1701	surf->db_depth_info \|= S_028040_TILE_SURFACE_ENABLE(1);
		1702	surf->db_preload_control = 0;
		1703	}
		1704
		1705	surf->depth_initialized = true;
		1706	}
		1707
		1708	static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
		1709	const struct pipe_framebuffer_state *state)
		1710	{
		1711	struct r600_context rctx = (struct r600_context )ctx;
		1712	struct r600_surface *surf;
		1713	struct r600_texture *rtex;
		1714	uint32_t i, log_samples;
		1715
		1716	if (rctx->framebuffer.state.nr_cbufs) {
		1717	rctx->flags \|= R600_CONTEXT_WAIT_3D_IDLE \| R600_CONTEXT_FLUSH_AND_INV;
		1718	rctx->flags \|= R600_CONTEXT_FLUSH_AND_INV_CB;
		1719
		1720	if (rctx->framebuffer.state.cbufs[0]->texture->nr_samples > 1) {
		1721	rctx->flags \|= R600_CONTEXT_FLUSH_AND_INV_CB_META;
		1722	}
		1723	}
		1724	if (rctx->framebuffer.state.zsbuf) {
		1725	rctx->flags \|= R600_CONTEXT_WAIT_3D_IDLE \| R600_CONTEXT_FLUSH_AND_INV;
		1726	rctx->flags \|= R600_CONTEXT_FLUSH_AND_INV_DB;
		1727
		1728	rtex = (struct r600_texture*)rctx->framebuffer.state.zsbuf->texture;
		1729	if (rtex->htile) {
		1730	rctx->flags \|= R600_CONTEXT_FLUSH_AND_INV_DB_META;
		1731	}
		1732	}
		1733
		1734	util_copy_framebuffer_state(&rctx->framebuffer.state, state);
		1735
		1736	/* Colorbuffers. */
		1737	rctx->framebuffer.export_16bpc = state->nr_cbufs != 0;
		1738	rctx->framebuffer.cb0_is_integer = state->nr_cbufs &&
		1739	util_format_is_pure_integer(state->cbufs[0]->format);
		1740	rctx->framebuffer.compressed_cb_mask = 0;
		1741
		1742	if (state->nr_cbufs)
		1743	rctx->framebuffer.nr_samples = state->cbufs[0]->texture->nr_samples;
		1744	else if (state->zsbuf)
		1745	rctx->framebuffer.nr_samples = state->zsbuf->texture->nr_samples;
		1746	else
		1747	rctx->framebuffer.nr_samples = 0;
		1748
		1749	for (i = 0; i < state->nr_cbufs; i++) {
		1750	surf = (struct r600_surface*)state->cbufs[i];
		1751	rtex = (struct r600_texture*)surf->base.texture;
		1752
		1753	r600_context_add_resource_size(ctx, state->cbufs[i]->texture);
		1754
		1755	if (!surf->color_initialized) {
		1756	evergreen_init_color_surface(rctx, surf);
		1757	}
		1758
		1759	if (!surf->export_16bpc) {
		1760	rctx->framebuffer.export_16bpc = false;
		1761	}
		1762
		1763	if (rtex->fmask_size && rtex->cmask_size) {
		1764	rctx->framebuffer.compressed_cb_mask \|= 1 << i;
		1765	}
		1766	}
		1767
		1768	/* Update alpha-test state dependencies.
		1769	* Alpha-test is done on the first colorbuffer only. */
		1770	if (state->nr_cbufs) {
		1771	surf = (struct r600_surface*)state->cbufs[0];
		1772	if (rctx->alphatest_state.bypass != surf->alphatest_bypass) {
		1773	rctx->alphatest_state.bypass = surf->alphatest_bypass;
		1774	rctx->alphatest_state.atom.dirty = true;
		1775	}
		1776	if (rctx->alphatest_state.cb0_export_16bpc != surf->export_16bpc) {
		1777	rctx->alphatest_state.cb0_export_16bpc = surf->export_16bpc;
		1778	rctx->alphatest_state.atom.dirty = true;
		1779	}
		1780	}
		1781
		1782	/* ZS buffer. */
		1783	if (state->zsbuf) {
		1784	surf = (struct r600_surface*)state->zsbuf;
		1785
		1786	r600_context_add_resource_size(ctx, state->zsbuf->texture);
		1787
		1788	if (!surf->depth_initialized) {
		1789	evergreen_init_depth_surface(rctx, surf);
		1790	}
		1791
		1792	if (state->zsbuf->format != rctx->poly_offset_state.zs_format) {
		1793	rctx->poly_offset_state.zs_format = state->zsbuf->format;
		1794	rctx->poly_offset_state.atom.dirty = true;
		1795	}
		1796
		1797	if (rctx->db_state.rsurf != surf) {
		1798	rctx->db_state.rsurf = surf;
		1799	rctx->db_state.atom.dirty = true;
		1800	rctx->db_misc_state.atom.dirty = true;
		1801	}
		1802	} else if (rctx->db_state.rsurf) {
		1803	rctx->db_state.rsurf = NULL;
		1804	rctx->db_state.atom.dirty = true;
		1805	rctx->db_misc_state.atom.dirty = true;
		1806	}
		1807
		1808	if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs) {
		1809	rctx->cb_misc_state.nr_cbufs = state->nr_cbufs;
		1810	rctx->cb_misc_state.atom.dirty = true;
		1811	}
		1812
		1813	if (state->nr_cbufs == 0 && rctx->alphatest_state.bypass) {
		1814	rctx->alphatest_state.bypass = false;
		1815	rctx->alphatest_state.atom.dirty = true;
		1816	}
		1817
		1818	log_samples = util_logbase2(rctx->framebuffer.nr_samples);
		1819	if (rctx->chip_class == CAYMAN && rctx->db_misc_state.log_samples != log_samples) {
		1820	rctx->db_misc_state.log_samples = log_samples;
		1821	rctx->db_misc_state.atom.dirty = true;
		1822	}
		1823
		1824	evergreen_update_db_shader_control(rctx);
		1825
		1826	/* Calculate the CS size. */
		1827	rctx->framebuffer.atom.num_dw = 4; /* SCISSOR */
		1828
		1829	/* MSAA. */
		1830	if (rctx->chip_class == EVERGREEN) {
		1831	switch (rctx->framebuffer.nr_samples) {
		1832	case 2:
		1833	case 4:
		1834	rctx->framebuffer.atom.num_dw += 6;
		1835	break;
		1836	case 8:
		1837	rctx->framebuffer.atom.num_dw += 10;
		1838	break;
		1839	}
		1840	rctx->framebuffer.atom.num_dw += 4;
		1841	} else {
		1842	switch (rctx->framebuffer.nr_samples) {
		1843	case 2:
		1844	case 4:
		1845	rctx->framebuffer.atom.num_dw += 12;
		1846	break;
		1847	case 8:
		1848	rctx->framebuffer.atom.num_dw += 16;
		1849	break;
		1850	case 16:
		1851	rctx->framebuffer.atom.num_dw += 18;
		1852	break;
		1853	}
		1854	rctx->framebuffer.atom.num_dw += 7;
		1855	}
		1856
		1857	/* Colorbuffers. */
		1858	rctx->framebuffer.atom.num_dw += state->nr_cbufs * 23;
		1859	if (rctx->keep_tiling_flags)
		1860	rctx->framebuffer.atom.num_dw += state->nr_cbufs * 2;
		1861	rctx->framebuffer.atom.num_dw += (12 - state->nr_cbufs) * 3;
		1862
		1863	/* ZS buffer. */
		1864	if (state->zsbuf) {
		1865	rctx->framebuffer.atom.num_dw += 24;
		1866	if (rctx->keep_tiling_flags)
		1867	rctx->framebuffer.atom.num_dw += 2;
		1868	} else if (rctx->screen->info.drm_minor >= 18) {
		1869	rctx->framebuffer.atom.num_dw += 4;
		1870	}
		1871
		1872	rctx->framebuffer.atom.dirty = true;
		1873	}
		1874
		1875	#define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
		1876	(((s0x) & 0xf) \| (((s0y) & 0xf) << 4) \| \
		1877	(((s1x) & 0xf) << 8) \| (((s1y) & 0xf) << 12) \| \
		1878	(((s2x) & 0xf) << 16) \| (((s2y) & 0xf) << 20) \| \
		1879	(((s3x) & 0xf) << 24) \| (((s3y) & 0xf) << 28))
		1880
		1881	/* 2xMSAA
		1882	* There are two locations (-4, 4), (4, -4). */
		1883	static uint32_t sample_locs_2x[] = {
		1884	FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
		1885	FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
		1886	FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
		1887	FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
		1888	};
		1889	static unsigned max_dist_2x = 4;
		1890	/* 4xMSAA
		1891	* There are 4 locations: (-2, -2), (2, 2), (-6, 6), (6, -6). */
		1892	static uint32_t sample_locs_4x[] = {
		1893	FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
		1894	FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
		1895	FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
		1896	FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
		1897	};
		1898	static unsigned max_dist_4x = 6;
		1899	/* 8xMSAA */
		1900	static uint32_t sample_locs_8x[] = {
		1901	FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
		1902	FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
		1903	FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
		1904	FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
		1905	FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
		1906	FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
		1907	FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
		1908	FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
		1909	};
		1910	static unsigned max_dist_8x = 7;
		1911
		1912	static void evergreen_get_sample_position(struct pipe_context *ctx,
		1913	unsigned sample_count,
		1914	unsigned sample_index,
		1915	float *out_value)
		1916	{
		1917	int offset, index;
		1918	struct {
		1919	int idx:4;
		1920	} val;
		1921	switch (sample_count) {
		1922	case 1:
		1923	default:
		1924	out_value[0] = out_value[1] = 0.5;
		1925	break;
		1926	case 2:
		1927	offset = 4 * (sample_index * 2);
		1928	val.idx = (sample_locs_2x[0] >> offset) & 0xf;
		1929	out_value[0] = (float)(val.idx + 8) / 16.0f;
		1930	val.idx = (sample_locs_2x[0] >> (offset + 4)) & 0xf;
		1931	out_value[1] = (float)(val.idx + 8) / 16.0f;
		1932	break;
		1933	case 4:
		1934	offset = 4 * (sample_index * 2);
		1935	val.idx = (sample_locs_4x[0] >> offset) & 0xf;
		1936	out_value[0] = (float)(val.idx + 8) / 16.0f;
		1937	val.idx = (sample_locs_4x[0] >> (offset + 4)) & 0xf;
		1938	out_value[1] = (float)(val.idx + 8) / 16.0f;
		1939	break;
		1940	case 8:
		1941	offset = 4 * (sample_index % 4 * 2);
		1942	index = (sample_index / 4);
		1943	val.idx = (sample_locs_8x[index] >> offset) & 0xf;
		1944	out_value[0] = (float)(val.idx + 8) / 16.0f;
		1945	val.idx = (sample_locs_8x[index] >> (offset + 4)) & 0xf;
		1946	out_value[1] = (float)(val.idx + 8) / 16.0f;
		1947	break;
		1948	}
		1949	}
		1950
		1951	static void evergreen_emit_msaa_state(struct r600_context *rctx, int nr_samples)
		1952	{
		1953
		1954	struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
		1955	unsigned max_dist = 0;
		1956
		1957	switch (nr_samples) {
		1958	default:
		1959	nr_samples = 0;
		1960	break;
		1961	case 2:
		1962	r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, Elements(sample_locs_2x));
		1963	r600_write_array(cs, Elements(sample_locs_2x), sample_locs_2x);
		1964	max_dist = max_dist_2x;
		1965	break;
		1966	case 4:
		1967	r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, Elements(sample_locs_4x));
		1968	r600_write_array(cs, Elements(sample_locs_4x), sample_locs_4x);
		1969	max_dist = max_dist_4x;
		1970	break;
		1971	case 8:
		1972	r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, Elements(sample_locs_8x));
		1973	r600_write_array(cs, Elements(sample_locs_8x), sample_locs_8x);
		1974	max_dist = max_dist_8x;
		1975	break;
		1976	}
		1977
		1978	if (nr_samples > 1) {
		1979	r600_write_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
		1980	r600_write_value(cs, S_028C00_LAST_PIXEL(1) \|
		1981	S_028C00_EXPAND_LINE_WIDTH(1)); /* R_028C00_PA_SC_LINE_CNTL */
		1982	r600_write_value(cs, S_028C04_MSAA_NUM_SAMPLES(util_logbase2(nr_samples)) \|
		1983	S_028C04_MAX_SAMPLE_DIST(max_dist)); /* R_028C04_PA_SC_AA_CONFIG */
		1984	} else {
		1985	r600_write_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
		1986	r600_write_value(cs, S_028C00_LAST_PIXEL(1)); /* R_028C00_PA_SC_LINE_CNTL */
		1987	r600_write_value(cs, 0); /* R_028C04_PA_SC_AA_CONFIG */
		1988	}
		1989	}
		1990
		1991	/* Cayman 8xMSAA */
		1992	static uint32_t cm_sample_locs_8x[] = {
		1993	FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
		1994	FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
		1995	FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
		1996	FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
		1997	FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
		1998	FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
		1999	FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
		2000	FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
		2001	};
		2002	static unsigned cm_max_dist_8x = 8;
		2003	/* Cayman 16xMSAA */
		2004	static uint32_t cm_sample_locs_16x[] = {
		2005	FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
		2006	FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
		2007	FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
		2008	FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
		2009	FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
		2010	FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
		2011	FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
		2012	FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
		2013	FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
		2014	FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
		2015	FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
		2016	FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
		2017	FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
		2018	FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
		2019	FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
		2020	FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
		2021	};
		2022	static unsigned cm_max_dist_16x = 8;
		2023	static void cayman_get_sample_position(struct pipe_context *ctx,
		2024	unsigned sample_count,
		2025	unsigned sample_index,
		2026	float *out_value)
		2027	{
		2028	int offset, index;
		2029	struct {
		2030	int idx:4;
		2031	} val;
		2032	switch (sample_count) {
		2033	case 1:
		2034	default:
		2035	out_value[0] = out_value[1] = 0.5;
		2036	break;
		2037	case 2:
		2038	offset = 4 * (sample_index * 2);
		2039	val.idx = (sample_locs_2x[0] >> offset) & 0xf;
		2040	out_value[0] = (float)(val.idx + 8) / 16.0f;
		2041	val.idx = (sample_locs_2x[0] >> (offset + 4)) & 0xf;
		2042	out_value[1] = (float)(val.idx + 8) / 16.0f;
		2043	break;
		2044	case 4:
		2045	offset = 4 * (sample_index * 2);
		2046	val.idx = (sample_locs_4x[0] >> offset) & 0xf;
		2047	out_value[0] = (float)(val.idx + 8) / 16.0f;
		2048	val.idx = (sample_locs_4x[0] >> (offset + 4)) & 0xf;
		2049	out_value[1] = (float)(val.idx + 8) / 16.0f;
		2050	break;
		2051	case 8:
		2052	offset = 4 * (sample_index % 4 * 2);
		2053	index = (sample_index / 4) * 4;
		2054	val.idx = (cm_sample_locs_8x[index] >> offset) & 0xf;
		2055	out_value[0] = (float)(val.idx + 8) / 16.0f;
		2056	val.idx = (cm_sample_locs_8x[index] >> (offset + 4)) & 0xf;
		2057	out_value[1] = (float)(val.idx + 8) / 16.0f;
		2058	break;
		2059	case 16:
		2060	offset = 4 * (sample_index % 4 * 2);
		2061	index = (sample_index / 4) * 4;
		2062	val.idx = (cm_sample_locs_16x[index] >> offset) & 0xf;
		2063	out_value[0] = (float)(val.idx + 8) / 16.0f;
		2064	val.idx = (cm_sample_locs_16x[index] >> (offset + 4)) & 0xf;
		2065	out_value[1] = (float)(val.idx + 8) / 16.0f;
		2066	break;
		2067	}
		2068	}
		2069
		2070	static void cayman_emit_msaa_state(struct r600_context *rctx, int nr_samples)
		2071	{
		2072
		2073
		2074	struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
		2075	unsigned max_dist = 0;
		2076
		2077	switch (nr_samples) {
		2078	default:
		2079	nr_samples = 0;
		2080	break;
		2081	case 2:
		2082	r600_write_context_reg(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_2x[0]);
		2083	r600_write_context_reg(cs, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_2x[1]);
		2084	r600_write_context_reg(cs, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_2x[2]);
		2085	r600_write_context_reg(cs, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_2x[3]);
		2086	max_dist = max_dist_2x;
		2087	break;
		2088	case 4:
		2089	r600_write_context_reg(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_4x[0]);
		2090	r600_write_context_reg(cs, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_4x[1]);
		2091	r600_write_context_reg(cs, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_4x[2]);
		2092	r600_write_context_reg(cs, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_4x[3]);
		2093	max_dist = max_dist_4x;
		2094	break;
		2095	case 8:
		2096	r600_write_context_reg_seq(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 14);
		2097	r600_write_value(cs, cm_sample_locs_8x[0]);
		2098	r600_write_value(cs, cm_sample_locs_8x[4]);
		2099	r600_write_value(cs, 0);
		2100	r600_write_value(cs, 0);
		2101	r600_write_value(cs, cm_sample_locs_8x[1]);
		2102	r600_write_value(cs, cm_sample_locs_8x[5]);
		2103	r600_write_value(cs, 0);
		2104	r600_write_value(cs, 0);
		2105	r600_write_value(cs, cm_sample_locs_8x[2]);
		2106	r600_write_value(cs, cm_sample_locs_8x[6]);
		2107	r600_write_value(cs, 0);
		2108	r600_write_value(cs, 0);
		2109	r600_write_value(cs, cm_sample_locs_8x[3]);
		2110	r600_write_value(cs, cm_sample_locs_8x[7]);
		2111	max_dist = cm_max_dist_8x;
		2112	break;
		2113	case 16:
		2114	r600_write_context_reg_seq(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 16);
		2115	r600_write_value(cs, cm_sample_locs_16x[0]);
		2116	r600_write_value(cs, cm_sample_locs_16x[4]);
		2117	r600_write_value(cs, cm_sample_locs_16x[8]);
		2118	r600_write_value(cs, cm_sample_locs_16x[12]);
		2119	r600_write_value(cs, cm_sample_locs_16x[1]);
		2120	r600_write_value(cs, cm_sample_locs_16x[5]);
		2121	r600_write_value(cs, cm_sample_locs_16x[9]);
		2122	r600_write_value(cs, cm_sample_locs_16x[13]);
		2123	r600_write_value(cs, cm_sample_locs_16x[2]);
		2124	r600_write_value(cs, cm_sample_locs_16x[6]);
		2125	r600_write_value(cs, cm_sample_locs_16x[10]);
		2126	r600_write_value(cs, cm_sample_locs_16x[14]);
		2127	r600_write_value(cs, cm_sample_locs_16x[3]);
		2128	r600_write_value(cs, cm_sample_locs_16x[7]);
		2129	r600_write_value(cs, cm_sample_locs_16x[11]);
		2130	r600_write_value(cs, cm_sample_locs_16x[15]);
		2131	max_dist = cm_max_dist_16x;
		2132	break;
		2133	}
		2134
		2135	if (nr_samples > 1) {
		2136	unsigned log_samples = util_logbase2(nr_samples);
		2137
		2138	r600_write_context_reg_seq(cs, CM_R_028BDC_PA_SC_LINE_CNTL, 2);
		2139	r600_write_value(cs, S_028C00_LAST_PIXEL(1) \|
		2140	S_028C00_EXPAND_LINE_WIDTH(1)); /* CM_R_028BDC_PA_SC_LINE_CNTL */
		2141	r600_write_value(cs, S_028BE0_MSAA_NUM_SAMPLES(log_samples) \|
		2142	S_028BE0_MAX_SAMPLE_DIST(max_dist) \|
		2143	S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples)); /* CM_R_028BE0_PA_SC_AA_CONFIG */
		2144
		2145	r600_write_context_reg(cs, CM_R_028804_DB_EQAA,
		2146	S_028804_MAX_ANCHOR_SAMPLES(log_samples) \|
		2147	S_028804_PS_ITER_SAMPLES(log_samples) \|
		2148	S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) \|
		2149	S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples) \|
		2150	S_028804_HIGH_QUALITY_INTERSECTIONS(1) \|
		2151	S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
		2152	} else {
		2153	r600_write_context_reg_seq(cs, CM_R_028BDC_PA_SC_LINE_CNTL, 2);
		2154	r600_write_value(cs, S_028C00_LAST_PIXEL(1)); /* CM_R_028BDC_PA_SC_LINE_CNTL */
		2155	r600_write_value(cs, 0); /* CM_R_028BE0_PA_SC_AA_CONFIG */
		2156
		2157	r600_write_context_reg(cs, CM_R_028804_DB_EQAA,
		2158	S_028804_HIGH_QUALITY_INTERSECTIONS(1) \|
		2159	S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
		2160	}
		2161	}
		2162
		2163	static void evergreen_emit_framebuffer_state(struct r600_context rctx, struct r600_atom atom)
		2164	{
		2165	struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
		2166	struct pipe_framebuffer_state *state = &rctx->framebuffer.state;
		2167	unsigned nr_cbufs = state->nr_cbufs;
		2168	unsigned i, tl, br;
		2169
		2170	/* XXX support more colorbuffers once we need them */
		2171	assert(nr_cbufs <= 8);
		2172	if (nr_cbufs > 8)
		2173	nr_cbufs = 8;
		2174
		2175	/* Colorbuffers. */
		2176	for (i = 0; i < nr_cbufs; i++) {
		2177	struct r600_surface cb = (struct r600_surface)state->cbufs[i];
		2178	struct r600_texture tex = (struct r600_texture )cb->base.texture;
		2179	unsigned reloc = r600_context_bo_reloc(rctx,
		2180	&rctx->rings.gfx,
		2181	(struct r600_resource*)cb->base.texture,
		2182	RADEON_USAGE_READWRITE);
		2183
		2184	r600_write_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 13);
		2185	r600_write_value(cs, cb->cb_color_base); /* R_028C60_CB_COLOR0_BASE */
		2186	r600_write_value(cs, cb->cb_color_pitch); /* R_028C64_CB_COLOR0_PITCH */
		2187	r600_write_value(cs, cb->cb_color_slice); /* R_028C68_CB_COLOR0_SLICE */
		2188	r600_write_value(cs, cb->cb_color_view); /* R_028C6C_CB_COLOR0_VIEW */
		2189	r600_write_value(cs, cb->cb_color_info); /* R_028C70_CB_COLOR0_INFO */
		2190	r600_write_value(cs, cb->cb_color_attrib); /* R_028C74_CB_COLOR0_ATTRIB */
		2191	r600_write_value(cs, cb->cb_color_dim); /* R_028C78_CB_COLOR0_DIM */
		2192	r600_write_value(cs, cb->cb_color_cmask); /* R_028C7C_CB_COLOR0_CMASK */
		2193	r600_write_value(cs, cb->cb_color_cmask_slice); /* R_028C80_CB_COLOR0_CMASK_SLICE */
		2194	r600_write_value(cs, cb->cb_color_fmask); /* R_028C84_CB_COLOR0_FMASK */
		2195	r600_write_value(cs, cb->cb_color_fmask_slice); /* R_028C88_CB_COLOR0_FMASK_SLICE */
		2196	r600_write_value(cs, tex->color_clear_value[0]); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
		2197	r600_write_value(cs, tex->color_clear_value[1]); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
		2198
		2199	r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C60_CB_COLOR0_BASE */
		2200	r600_write_value(cs, reloc);
		2201
		2202	if (!rctx->keep_tiling_flags) {
		2203	r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C70_CB_COLOR0_INFO */
		2204	r600_write_value(cs, reloc);
		2205	}
		2206
		2207	r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C74_CB_COLOR0_ATTRIB */
		2208	r600_write_value(cs, reloc);
		2209
		2210	r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C7C_CB_COLOR0_CMASK */
		2211	r600_write_value(cs, reloc);
		2212
		2213	r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C84_CB_COLOR0_FMASK */
		2214	r600_write_value(cs, reloc);
		2215	}
		2216	/* set CB_COLOR1_INFO for possible dual-src blending */
		2217	if (i == 1 && !((struct r600_texture*)state->cbufs[0]->texture)->is_rat) {
		2218	r600_write_context_reg(cs, R_028C70_CB_COLOR0_INFO + 1 * 0x3C,
		2219	((struct r600_surface*)state->cbufs[0])->cb_color_info);
		2220
		2221	if (!rctx->keep_tiling_flags) {
		2222	unsigned reloc = r600_context_bo_reloc(rctx,
		2223	&rctx->rings.gfx,
		2224	(struct r600_resource*)state->cbufs[0]->texture,
		2225	RADEON_USAGE_READWRITE);
		2226
		2227	r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C70_CB_COLOR0_INFO */
		2228	r600_write_value(cs, reloc);
		2229	}
		2230	i++;
		2231	}
		2232	if (rctx->keep_tiling_flags) {
		2233	for (; i < 8 ; i++) {
		2234	r600_write_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
		2235	}
		2236	for (; i < 12; i++) {
		2237	r600_write_context_reg(cs, R_028E50_CB_COLOR8_INFO + (i - 8) * 0x1C, 0);
		2238	}
		2239	}
		2240
		2241	/* ZS buffer. */
		2242	if (state->zsbuf) {
		2243	struct r600_surface zb = (struct r600_surface)state->zsbuf;
		2244	unsigned reloc = r600_context_bo_reloc(rctx,
		2245	&rctx->rings.gfx,
		2246	(struct r600_resource*)state->zsbuf->texture,
		2247	RADEON_USAGE_READWRITE);
		2248
		2249	r600_write_context_reg(cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
		2250	zb->pa_su_poly_offset_db_fmt_cntl);
		2251	r600_write_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
		2252
		2253	r600_write_context_reg_seq(cs, R_028040_DB_Z_INFO, 8);
		2254	r600_write_value(cs, zb->db_depth_info); /* R_028040_DB_Z_INFO */
		2255	r600_write_value(cs, zb->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
		2256	r600_write_value(cs, zb->db_depth_base); /* R_028048_DB_Z_READ_BASE */
		2257	r600_write_value(cs, zb->db_stencil_base); /* R_02804C_DB_STENCIL_READ_BASE */
		2258	r600_write_value(cs, zb->db_depth_base); /* R_028050_DB_Z_WRITE_BASE */
		2259	r600_write_value(cs, zb->db_stencil_base); /* R_028054_DB_STENCIL_WRITE_BASE */
		2260	r600_write_value(cs, zb->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
		2261	r600_write_value(cs, zb->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
		2262
		2263	if (!rctx->keep_tiling_flags) {
		2264	r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028040_DB_Z_INFO */
		2265	r600_write_value(cs, reloc);
		2266	}
		2267
		2268	r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028048_DB_Z_READ_BASE */
		2269	r600_write_value(cs, reloc);
		2270
		2271	r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_02804C_DB_STENCIL_READ_BASE */
		2272	r600_write_value(cs, reloc);
		2273
		2274	r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028050_DB_Z_WRITE_BASE */
		2275	r600_write_value(cs, reloc);
		2276
		2277	r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028054_DB_STENCIL_WRITE_BASE */
		2278	r600_write_value(cs, reloc);
		2279	} else if (rctx->screen->info.drm_minor >= 18) {
		2280	/* DRM 2.6.18 allows the INVALID format to disable depth/stencil.
		2281	* Older kernels are out of luck. */
		2282	r600_write_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
		2283	r600_write_value(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
		2284	r600_write_value(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
		2285	}
		2286
		2287	/* Framebuffer dimensions. */
		2288	evergreen_get_scissor_rect(rctx, 0, 0, state->width, state->height, &tl, &br);
		2289
		2290	r600_write_context_reg_seq(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL, 2);
		2291	r600_write_value(cs, tl); /* R_028204_PA_SC_WINDOW_SCISSOR_TL */
		2292	r600_write_value(cs, br); /* R_028208_PA_SC_WINDOW_SCISSOR_BR */
		2293
		2294	if (rctx->chip_class == EVERGREEN) {
		2295	evergreen_emit_msaa_state(rctx, rctx->framebuffer.nr_samples);
		2296	} else {
		2297	cayman_emit_msaa_state(rctx, rctx->framebuffer.nr_samples);
		2298	}
		2299	}
		2300
		2301	static void evergreen_emit_polygon_offset(struct r600_context rctx, struct r600_atom a)
		2302	{
		2303	struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
		2304	struct r600_poly_offset_state state = (struct r600_poly_offset_state)a;
		2305	float offset_units = state->offset_units;
		2306	float offset_scale = state->offset_scale;
		2307
		2308	switch (state->zs_format) {
		2309	case PIPE_FORMAT_Z24X8_UNORM:
		2310	case PIPE_FORMAT_Z24_UNORM_S8_UINT:
		2311	case PIPE_FORMAT_X8Z24_UNORM:
		2312	case PIPE_FORMAT_S8_UINT_Z24_UNORM:
		2313	offset_units *= 2.0f;
		2314	break;
		2315	case PIPE_FORMAT_Z16_UNORM:
		2316	offset_units *= 4.0f;
		2317	break;
		2318	default:;
		2319	}
		2320
		2321	r600_write_context_reg_seq(cs, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE, 4);
		2322	r600_write_value(cs, fui(offset_scale));
		2323	r600_write_value(cs, fui(offset_units));
		2324	r600_write_value(cs, fui(offset_scale));
		2325	r600_write_value(cs, fui(offset_units));
		2326	}
		2327
		2328	static void evergreen_emit_cb_misc_state(struct r600_context rctx, struct r600_atom atom)
		2329	{
		2330	struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
		2331	struct r600_cb_misc_state a = (struct r600_cb_misc_state)atom;
		2332	unsigned fb_colormask = (1ULL << ((unsigned)a->nr_cbufs * 4)) - 1;
		2333	unsigned ps_colormask = (1ULL << ((unsigned)a->nr_ps_color_outputs * 4)) - 1;
		2334
		2335	r600_write_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
		2336	r600_write_value(cs, a->blend_colormask & fb_colormask); /* R_028238_CB_TARGET_MASK */
		2337	/* Always enable the first colorbuffer in CB_SHADER_MASK. This
		2338	* will assure that the alpha-test will work even if there is
		2339	* no colorbuffer bound. */
		2340	r600_write_value(cs, 0xf \| (a->dual_src_blend ? ps_colormask : 0) \| fb_colormask); /* R_02823C_CB_SHADER_MASK */
		2341	}
		2342
		2343	static void evergreen_emit_db_state(struct r600_context rctx, struct r600_atom atom)
		2344	{
		2345	struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
		2346	struct r600_db_state a = (struct r600_db_state)atom;
		2347
		2348	if (a->rsurf && a->rsurf->htile_enabled) {
		2349	struct r600_texture rtex = (struct r600_texture )a->rsurf->base.texture;
		2350	unsigned reloc_idx;
		2351
		2352	r600_write_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(rtex->depth_clear));
		2353	r600_write_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, a->rsurf->db_htile_surface);
		2354	r600_write_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, a->rsurf->db_preload_control);
		2355	r600_write_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, a->rsurf->db_htile_data_base);
		2356	reloc_idx = r600_context_bo_reloc(rctx, &rctx->rings.gfx, rtex->htile, RADEON_USAGE_READWRITE);
		2357	cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
		2358	cs->buf[cs->cdw++] = reloc_idx;
		2359	} else {
		2360	r600_write_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, 0);
		2361	r600_write_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, 0);
		2362	}
		2363	}
		2364
		2365	static void evergreen_emit_db_misc_state(struct r600_context rctx, struct r600_atom atom)
		2366	{
		2367	struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
		2368	struct r600_db_misc_state a = (struct r600_db_misc_state)atom;
		2369	unsigned db_render_control = 0;
		2370	unsigned db_count_control = 0;
		2371	unsigned db_render_override =
		2372	S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) \|
		2373	S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
		2374
		2375	if (a->occlusion_query_enabled) {
		2376	db_count_control \|= S_028004_PERFECT_ZPASS_COUNTS(1);
		2377	if (rctx->chip_class == CAYMAN) {
		2378	db_count_control \|= S_028004_SAMPLE_RATE(a->log_samples);
		2379	}
		2380	db_render_override \|= S_02800C_NOOP_CULL_DISABLE(1);
		2381	}
		2382	/* FIXME we should be able to use hyperz even if we are not writing to
		2383	* zbuffer but somehow this trigger GPU lockup. See :
		2384	*
		2385	* https://bugs.freedesktop.org/show_bug.cgi?id=60848
		2386	*
		2387	* Disable hyperz for now if not writing to zbuffer.
		2388	*/
		2389	if (rctx->db_state.rsurf && rctx->db_state.rsurf->htile_enabled && rctx->zwritemask) {
		2390	/* FORCE_OFF means HiZ/HiS are determined by DB_SHADER_CONTROL */
		2391	db_render_override \|= S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_OFF);
		2392	/* This is to fix a lockup when hyperz and alpha test are enabled at
		2393	* the same time somehow GPU get confuse on which order to pick for
		2394	* z test
		2395	*/
		2396	if (rctx->alphatest_state.sx_alpha_test_control) {
		2397	db_render_override \|= S_02800C_FORCE_SHADER_Z_ORDER(1);
		2398	}
		2399	} else {
		2400	db_render_override \|= S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE);
		2401	}
		2402	if (a->flush_depthstencil_through_cb) {
		2403	assert(a->copy_depth \|\| a->copy_stencil);
		2404
		2405	db_render_control \|= S_028000_DEPTH_COPY_ENABLE(a->copy_depth) \|
		2406	S_028000_STENCIL_COPY_ENABLE(a->copy_stencil) \|
		2407	S_028000_COPY_CENTROID(1) \|
		2408	S_028000_COPY_SAMPLE(a->copy_sample);
		2409	} else if (a->flush_depthstencil_in_place) {
		2410	db_render_control \|= S_028000_DEPTH_COMPRESS_DISABLE(1) \|
		2411	S_028000_STENCIL_COMPRESS_DISABLE(1);
		2412	db_render_override \|= S_02800C_DISABLE_PIXEL_RATE_TILES(1);
		2413	}
		2414	if (a->htile_clear) {
		2415	/* FIXME we might want to disable cliprect here */
		2416	db_render_control \|= S_028000_DEPTH_CLEAR_ENABLE(1);
		2417	}
		2418
		2419	r600_write_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
		2420	r600_write_value(cs, db_render_control); /* R_028000_DB_RENDER_CONTROL */
		2421	r600_write_value(cs, db_count_control); /* R_028004_DB_COUNT_CONTROL */
		2422	r600_write_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
		2423	r600_write_context_reg(cs, R_02880C_DB_SHADER_CONTROL, a->db_shader_control);
		2424	}
		2425
		2426	static void evergreen_emit_vertex_buffers(struct r600_context *rctx,
		2427	struct r600_vertexbuf_state *state,
		2428	unsigned resource_offset,
		2429	unsigned pkt_flags)
		2430	{
		2431	struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
		2432	uint32_t dirty_mask = state->dirty_mask;
		2433
		2434	while (dirty_mask) {
		2435	struct pipe_vertex_buffer *vb;
		2436	struct r600_resource *rbuffer;
		2437	uint64_t va;
		2438	unsigned buffer_index = u_bit_scan(&dirty_mask);
		2439
		2440	vb = &state->vb[buffer_index];
		2441	rbuffer = (struct r600_resource*)vb->buffer;
		2442	assert(rbuffer);
		2443
		2444	va = r600_resource_va(&rctx->screen->screen, &rbuffer->b.b);
		2445	va += vb->buffer_offset;
		2446
		2447	/* fetch resources start at index 992 */
		2448	r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) \| pkt_flags);
		2449	r600_write_value(cs, (resource_offset + buffer_index) * 8);
		2450	r600_write_value(cs, va); /* RESOURCEi_WORD0 */
		2451	r600_write_value(cs, rbuffer->buf->size - vb->buffer_offset - 1); /* RESOURCEi_WORD1 */
		2452	r600_write_value(cs, /* RESOURCEi_WORD2 */
		2453	S_030008_ENDIAN_SWAP(r600_endian_swap(32)) \|
		2454	S_030008_STRIDE(vb->stride) \|
		2455	S_030008_BASE_ADDRESS_HI(va >> 32UL));
		2456	r600_write_value(cs, /* RESOURCEi_WORD3 */
		2457	S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) \|
		2458	S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) \|
		2459	S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) \|
		2460	S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W));
		2461	r600_write_value(cs, 0); /* RESOURCEi_WORD4 */
		2462	r600_write_value(cs, 0); /* RESOURCEi_WORD5 */
		2463	r600_write_value(cs, 0); /* RESOURCEi_WORD6 */
		2464	r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD7 */
		2465
		2466	r600_write_value(cs, PKT3(PKT3_NOP, 0, 0) \| pkt_flags);
		2467	r600_write_value(cs, r600_context_bo_reloc(rctx, &rctx->rings.gfx, rbuffer, RADEON_USAGE_READ));
		2468	}
		2469	state->dirty_mask = 0;
		2470	}
		2471
		2472	static void evergreen_fs_emit_vertex_buffers(struct r600_context rctx, struct r600_atom atom)
		2473	{
		2474	evergreen_emit_vertex_buffers(rctx, &rctx->vertex_buffer_state, 992, 0);
		2475	}
		2476
		2477	static void evergreen_cs_emit_vertex_buffers(struct r600_context rctx, struct r600_atom atom)
		2478	{
		2479	evergreen_emit_vertex_buffers(rctx, &rctx->cs_vertex_buffer_state, 816,
		2480	RADEON_CP_PACKET3_COMPUTE_MODE);
		2481	}
		2482
		2483	static void evergreen_emit_constant_buffers(struct r600_context *rctx,
		2484	struct r600_constbuf_state *state,
		2485	unsigned buffer_id_base,
		2486	unsigned reg_alu_constbuf_size,
		2487	unsigned reg_alu_const_cache,
		2488	unsigned pkt_flags)
		2489	{
		2490	struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
		2491	uint32_t dirty_mask = state->dirty_mask;
		2492
		2493	while (dirty_mask) {
		2494	struct pipe_constant_buffer *cb;
		2495	struct r600_resource *rbuffer;
		2496	uint64_t va;
		2497	unsigned buffer_index = ffs(dirty_mask) - 1;
		2498
		2499	cb = &state->cb[buffer_index];
		2500	rbuffer = (struct r600_resource*)cb->buffer;
		2501	assert(rbuffer);
		2502
		2503	va = r600_resource_va(&rctx->screen->screen, &rbuffer->b.b);
		2504	va += cb->buffer_offset;
		2505
		2506	r600_write_context_reg_flag(cs, reg_alu_constbuf_size + buffer_index * 4,
		2507	ALIGN_DIVUP(cb->buffer_size >> 4, 16), pkt_flags);
		2508	r600_write_context_reg_flag(cs, reg_alu_const_cache + buffer_index * 4, va >> 8,
		2509	pkt_flags);
		2510
		2511	r600_write_value(cs, PKT3(PKT3_NOP, 0, 0) \| pkt_flags);
		2512	r600_write_value(cs, r600_context_bo_reloc(rctx, &rctx->rings.gfx, rbuffer, RADEON_USAGE_READ));
		2513
		2514	r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) \| pkt_flags);
		2515	r600_write_value(cs, (buffer_id_base + buffer_index) * 8);
		2516	r600_write_value(cs, va); /* RESOURCEi_WORD0 */
		2517	r600_write_value(cs, rbuffer->buf->size - cb->buffer_offset - 1); /* RESOURCEi_WORD1 */
		2518	r600_write_value(cs, /* RESOURCEi_WORD2 */
		2519	S_030008_ENDIAN_SWAP(r600_endian_swap(32)) \|
		2520	S_030008_STRIDE(16) \|
		2521	S_030008_BASE_ADDRESS_HI(va >> 32UL));
		2522	r600_write_value(cs, /* RESOURCEi_WORD3 */
		2523	S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) \|
		2524	S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) \|
		2525	S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) \|
		2526	S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W));
		2527	r600_write_value(cs, 0); /* RESOURCEi_WORD4 */
		2528	r600_write_value(cs, 0); /* RESOURCEi_WORD5 */
		2529	r600_write_value(cs, 0); /* RESOURCEi_WORD6 */
		2530	r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD7 */
		2531
		2532	r600_write_value(cs, PKT3(PKT3_NOP, 0, 0) \| pkt_flags);
		2533	r600_write_value(cs, r600_context_bo_reloc(rctx, &rctx->rings.gfx, rbuffer, RADEON_USAGE_READ));
		2534
		2535	dirty_mask &= ~(1 << buffer_index);
		2536	}
		2537	state->dirty_mask = 0;
		2538	}
		2539
		2540	static void evergreen_emit_vs_constant_buffers(struct r600_context rctx, struct r600_atom atom)
		2541	{
		2542	evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX], 176,
		2543	R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
		2544	R_028980_ALU_CONST_CACHE_VS_0,
		2545
		2546	}
		2547
		2548	static void evergreen_emit_gs_constant_buffers(struct r600_context rctx, struct r600_atom atom)
		2549	{
		2550	evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY], 336,
		2551	R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0,
		2552	R_0289C0_ALU_CONST_CACHE_GS_0,
		2553
		2554	}
		2555
		2556	static void evergreen_emit_ps_constant_buffers(struct r600_context rctx, struct r600_atom atom)
		2557	{
		2558	evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT], 0,
		2559	R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
		2560	R_028940_ALU_CONST_CACHE_PS_0,
		2561
		2562	}
		2563
		2564	static void evergreen_emit_cs_constant_buffers(struct r600_context rctx, struct r600_atom atom)
		2565	{
		2566	evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_COMPUTE], 816,
		2567	R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0,
		2568	R_028F40_ALU_CONST_CACHE_LS_0,
		2569	RADEON_CP_PACKET3_COMPUTE_MODE);
		2570	}
		2571
		2572	static void evergreen_emit_sampler_views(struct r600_context *rctx,
		2573	struct r600_samplerview_state *state,
		2574	unsigned resource_id_base)
		2575	{
		2576	struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
		2577	uint32_t dirty_mask = state->dirty_mask;
		2578
		2579	while (dirty_mask) {
		2580	struct r600_pipe_sampler_view *rview;
		2581	unsigned resource_index = u_bit_scan(&dirty_mask);
		2582	unsigned reloc;
		2583
		2584	rview = state->views[resource_index];
		2585	assert(rview);
		2586
		2587	r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 8, 0));
		2588	r600_write_value(cs, (resource_id_base + resource_index) * 8);
		2589	r600_write_array(cs, 8, rview->tex_resource_words);
		2590
		2591	reloc = r600_context_bo_reloc(rctx, &rctx->rings.gfx, rview->tex_resource,
		2592	RADEON_USAGE_READ);
		2593	r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
		2594	r600_write_value(cs, reloc);
		2595
		2596	if (!rview->skip_mip_address_reloc) {
		2597	r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
		2598	r600_write_value(cs, reloc);
		2599	}
		2600	}
		2601	state->dirty_mask = 0;
		2602	}
		2603
		2604	static void evergreen_emit_vs_sampler_views(struct r600_context rctx, struct r600_atom atom)
		2605	{
		2606	evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views, 176 + R600_MAX_CONST_BUFFERS);
		2607	}
		2608
		2609	static void evergreen_emit_gs_sampler_views(struct r600_context rctx, struct r600_atom atom)
		2610	{
		2611	evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views, 336 + R600_MAX_CONST_BUFFERS);
		2612	}
		2613
		2614	static void evergreen_emit_ps_sampler_views(struct r600_context rctx, struct r600_atom atom)
		2615	{
		2616	evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views, R600_MAX_CONST_BUFFERS);
		2617	}
		2618
		2619	static void evergreen_emit_sampler_states(struct r600_context *rctx,
		2620	struct r600_textures_info *texinfo,
		2621	unsigned resource_id_base,
		2622	unsigned border_index_reg)
		2623	{
		2624	struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
		2625	uint32_t dirty_mask = texinfo->states.dirty_mask;
		2626
		2627	while (dirty_mask) {
		2628	struct r600_pipe_sampler_state *rstate;
		2629	unsigned i = u_bit_scan(&dirty_mask);
		2630
		2631	rstate = texinfo->states.states[i];
		2632	assert(rstate);
		2633
		2634	r600_write_value(cs, PKT3(PKT3_SET_SAMPLER, 3, 0));
		2635	r600_write_value(cs, (resource_id_base + i) * 3);
		2636	r600_write_array(cs, 3, rstate->tex_sampler_words);
		2637
		2638	if (rstate->border_color_use) {
		2639	r600_write_config_reg_seq(cs, border_index_reg, 5);
		2640	r600_write_value(cs, i);
		2641	r600_write_array(cs, 4, rstate->border_color.ui);
		2642	}
		2643	}
		2644	texinfo->states.dirty_mask = 0;
		2645	}
		2646
		2647	static void evergreen_emit_vs_sampler_states(struct r600_context rctx, struct r600_atom atom)
		2648	{
		2649	evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_VERTEX], 18, R_00A414_TD_VS_SAMPLER0_BORDER_INDEX);
		2650	}
		2651
		2652	static void evergreen_emit_gs_sampler_states(struct r600_context rctx, struct r600_atom atom)
		2653	{
		2654	evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY], 36, R_00A428_TD_GS_SAMPLER0_BORDER_INDEX);
		2655	}
		2656
		2657	static void evergreen_emit_ps_sampler_states(struct r600_context rctx, struct r600_atom atom)
		2658	{
		2659	evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT], 0, R_00A400_TD_PS_SAMPLER0_BORDER_INDEX);
		2660	}
		2661
		2662	static void evergreen_emit_sample_mask(struct r600_context rctx, struct r600_atom a)
		2663	{
		2664	struct r600_sample_mask s = (struct r600_sample_mask)a;
		2665	uint8_t mask = s->sample_mask;
		2666
		2667	r600_write_context_reg(rctx->rings.gfx.cs, R_028C3C_PA_SC_AA_MASK,
		2668	mask \| (mask << 8) \| (mask << 16) \| (mask << 24));
		2669	}
		2670
		2671	static void cayman_emit_sample_mask(struct r600_context rctx, struct r600_atom a)
		2672	{
		2673	struct r600_sample_mask s = (struct r600_sample_mask)a;
		2674	struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
		2675	uint16_t mask = s->sample_mask;
		2676
		2677	r600_write_context_reg_seq(cs, CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
		2678	r600_write_value(cs, mask \| (mask << 16)); /* X0Y0_X1Y0 */
		2679	r600_write_value(cs, mask \| (mask << 16)); /* X0Y1_X1Y1 */
		2680	}
		2681
		2682	static void evergreen_emit_vertex_fetch_shader(struct r600_context rctx, struct r600_atom a)
		2683	{
		2684	struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
		2685	struct r600_cso_state state = (struct r600_cso_state)a;
		2686	struct r600_fetch_shader shader = (struct r600_fetch_shader)state->cso;
		2687
		2688	r600_write_context_reg(cs, R_0288A4_SQ_PGM_START_FS,
		2689	(r600_resource_va(rctx->context.screen, &shader->buffer->b.b) + shader->offset) >> 8);
		2690	r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
		2691	r600_write_value(cs, r600_context_bo_reloc(rctx, &rctx->rings.gfx, shader->buffer, RADEON_USAGE_READ));
		2692	}
		2693
		2694	void cayman_init_common_regs(struct r600_command_buffer *cb,
		2695	enum chip_class ctx_chip_class,
		2696	enum radeon_family ctx_family,
		2697	int ctx_drm_minor)
		2698	{
		2699	r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 2);
		2700	r600_store_value(cb, S_008C00_EXPORT_SRC_C(1)); /* R_008C00_SQ_CONFIG */
		2701	/* always set the temp clauses */
		2702	r600_store_value(cb, S_008C04_NUM_CLAUSE_TEMP_GPRS(4)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
		2703
		2704	r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
		2705	r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
		2706	r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
		2707
		2708	r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8));
		2709
		2710	r600_store_context_reg(cb, R_028A4C_PA_SC_MODE_CNTL_1, 0);
		2711
		2712	r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
		2713
		2714	r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
		2715	}
		2716
		2717	static void cayman_init_atom_start_cs(struct r600_context *rctx)
		2718	{
		2719	struct r600_command_buffer *cb = &rctx->start_cs_cmd;
		2720
		2721	r600_init_command_buffer(cb, 256);
		2722
		2723	/* This must be first. */
		2724	r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
		2725	r600_store_value(cb, 0x80000000);
		2726	r600_store_value(cb, 0x80000000);
		2727
		2728	/* We're setting config registers here. */
		2729	r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
		2730	r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) \| EVENT_INDEX(4));
		2731
		2732	cayman_init_common_regs(cb, rctx->chip_class,
		2733	rctx->family, rctx->screen->info.drm_minor);
		2734
		2735	r600_store_config_reg(cb, R_009100_SPI_CONFIG_CNTL, 0);
		2736	r600_store_config_reg(cb, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4));
		2737
		2738	r600_store_context_reg_seq(cb, R_028900_SQ_ESGS_RING_ITEMSIZE, 6);
		2739	r600_store_value(cb, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
		2740	r600_store_value(cb, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
		2741	r600_store_value(cb, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
		2742	r600_store_value(cb, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
		2743	r600_store_value(cb, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
		2744	r600_store_value(cb, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
		2745
		2746	r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
		2747	r600_store_value(cb, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
		2748	r600_store_value(cb, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
		2749	r600_store_value(cb, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
		2750	r600_store_value(cb, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
		2751
		2752	r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
		2753	r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
		2754	r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
		2755	r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
		2756	r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
		2757	r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
		2758	r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
		2759	r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
		2760	r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
		2761	r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
		2762	r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
		2763	r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
		2764	r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
		2765	r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
		2766
		2767	r600_store_context_reg_seq(cb, R_028B94_VGT_STRMOUT_CONFIG, 2);
		2768	r600_store_value(cb, 0); /* R_028B94_VGT_STRMOUT_CONFIG */
		2769	r600_store_value(cb, 0); /* R_028B98_VGT_STRMOUT_BUFFER_CONFIG */
		2770
		2771	r600_store_context_reg_seq(cb, R_028AB4_VGT_REUSE_OFF, 2);
		2772	r600_store_value(cb, 0); /* R_028AB4_VGT_REUSE_OFF */
		2773	r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
		2774
		2775	r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) \| 1);
		2776
		2777	r600_store_context_reg(cb, CM_R_028AA8_IA_MULTI_VGT_PARAM, S_028AA8_SWITCH_ON_EOP(1) \| S_028AA8_PARTIAL_VS_WAVE_ON(1) \| S_028AA8_PRIMGROUP_SIZE(63));
		2778
		2779	r600_store_context_reg_seq(cb, CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
		2780	r600_store_value(cb, 0x76543210); /* CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0 */
		2781	r600_store_value(cb, 0xfedcba98); /* CM_R_028BD8_PA_SC_CENTROID_PRIORITY_1 */
		2782
		2783	r600_store_context_reg_seq(cb, CM_R_0288E8_SQ_LDS_ALLOC, 2);
		2784	r600_store_value(cb, 0); /* CM_R_0288E8_SQ_LDS_ALLOC */
		2785	r600_store_value(cb, 0); /* R_0288EC_SQ_LDS_ALLOC_PS */
		2786
		2787	r600_store_context_reg(cb, R_0288F0_SQ_VTX_SEMANTIC_CLEAR, ~0);
		2788
		2789	r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2);
		2790	r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
		2791	r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
		2792
		2793	r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
		2794
		2795	r600_store_context_reg(cb, R_028028_DB_STENCIL_CLEAR, 0);
		2796
		2797	r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
		2798
		2799	r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
		2800	r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
		2801	r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
		2802	r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
		2803
		2804	r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
		2805	r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
		2806
		2807	r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
		2808	r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
		2809	r600_store_value(cb, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
		2810
		2811	r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
		2812	r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 0x0000043F);
		2813	r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
		2814
		2815	r600_store_context_reg_seq(cb, CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 4);
		2816	r600_store_value(cb, 0x3F800000); /* CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ */
		2817	r600_store_value(cb, 0x3F800000); /* CM_R_028BEC_PA_CL_GB_VERT_DISC_ADJ */
		2818	r600_store_value(cb, 0x3F800000); /* CM_R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ */
		2819	r600_store_value(cb, 0x3F800000); /* CM_R_028BF4_PA_CL_GB_HORZ_DISC_ADJ */
		2820
		2821	r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
		2822	r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
		2823	r600_store_value(cb, S_028244_BR_X(16384) \| S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
		2824
		2825	r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
		2826	r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
		2827	r600_store_value(cb, S_028034_BR_X(16384) \| S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
		2828
		2829	r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
		2830	r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
		2831	r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
		2832
		2833	/* to avoid GPU doing any preloading of constant from random address */
		2834	r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 16);
		2835	r600_store_value(cb, 0); /* R_028140_ALU_CONST_BUFFER_SIZE_PS_0 */
		2836	r600_store_value(cb, 0);
		2837	r600_store_value(cb, 0);
		2838	r600_store_value(cb, 0);
		2839	r600_store_value(cb, 0);
		2840	r600_store_value(cb, 0);
		2841	r600_store_value(cb, 0);
		2842	r600_store_value(cb, 0);
		2843	r600_store_value(cb, 0);
		2844	r600_store_value(cb, 0);
		2845	r600_store_value(cb, 0);
		2846	r600_store_value(cb, 0);
		2847	r600_store_value(cb, 0);
		2848	r600_store_value(cb, 0);
		2849	r600_store_value(cb, 0);
		2850	r600_store_value(cb, 0);
		2851
		2852	r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 16);
		2853	r600_store_value(cb, 0); /* R_028180_ALU_CONST_BUFFER_SIZE_VS_0 */
		2854	r600_store_value(cb, 0);
		2855	r600_store_value(cb, 0);
		2856	r600_store_value(cb, 0);
		2857	r600_store_value(cb, 0);
		2858	r600_store_value(cb, 0);
		2859	r600_store_value(cb, 0);
		2860	r600_store_value(cb, 0);
		2861	r600_store_value(cb, 0);
		2862	r600_store_value(cb, 0);
		2863	r600_store_value(cb, 0);
		2864	r600_store_value(cb, 0);
		2865	r600_store_value(cb, 0);
		2866	r600_store_value(cb, 0);
		2867	r600_store_value(cb, 0);
		2868	r600_store_value(cb, 0);
		2869
		2870	if (rctx->screen->has_streamout) {
		2871	r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
		2872	}
		2873
		2874	r600_store_context_reg(cb, R_028010_DB_RENDER_OVERRIDE2, 0);
		2875	r600_store_context_reg(cb, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
		2876	r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
		2877	r600_store_context_reg_seq(cb, R_0286E4_SPI_PS_IN_CONTROL_2, 2);
		2878	r600_store_value(cb, 0); /* R_0286E4_SPI_PS_IN_CONTROL_2 */
		2879	r600_store_value(cb, 0); /* R_0286E8_SPI_COMPUTE_INPUT_CNTL */
		2880	r600_store_context_reg(cb, R_028B54_VGT_SHADER_STAGES_EN, 0);
		2881
		2882	eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
		2883	eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
		2884	}
		2885
		2886	void evergreen_init_common_regs(struct r600_command_buffer *cb,
		2887	enum chip_class ctx_chip_class,
		2888	enum radeon_family ctx_family,
		2889	int ctx_drm_minor)
		2890	{
		2891	int ps_prio;
		2892	int vs_prio;
		2893	int gs_prio;
		2894	int es_prio;
		2895
		2896	int hs_prio;
		2897	int cs_prio;
		2898	int ls_prio;
		2899
		2900	int num_ps_gprs;
		2901	int num_vs_gprs;
		2902	int num_gs_gprs;
		2903	int num_es_gprs;
		2904	int num_hs_gprs;
		2905	int num_ls_gprs;
		2906	int num_temp_gprs;
		2907
		2908	unsigned tmp;
		2909
		2910	ps_prio = 0;
		2911	vs_prio = 1;
		2912	gs_prio = 2;
		2913	es_prio = 3;
		2914	hs_prio = 0;
		2915	ls_prio = 0;
		2916	cs_prio = 0;
		2917
		2918	num_ps_gprs = 93;
		2919	num_vs_gprs = 46;
		2920	num_temp_gprs = 4;
		2921	num_gs_gprs = 31;
		2922	num_es_gprs = 31;
		2923	num_hs_gprs = 23;
		2924	num_ls_gprs = 23;
		2925
		2926	tmp = 0;
		2927	switch (ctx_family) {
		2928	case CHIP_CEDAR:
		2929	case CHIP_PALM:
		2930	case CHIP_SUMO:
		2931	case CHIP_SUMO2:
		2932	case CHIP_CAICOS:
		2933	break;
		2934	default:
		2935	tmp \|= S_008C00_VC_ENABLE(1);
		2936	break;
		2937	}
		2938	tmp \|= S_008C00_EXPORT_SRC_C(1);
		2939	tmp \|= S_008C00_CS_PRIO(cs_prio);
		2940	tmp \|= S_008C00_LS_PRIO(ls_prio);
		2941	tmp \|= S_008C00_HS_PRIO(hs_prio);
		2942	tmp \|= S_008C00_PS_PRIO(ps_prio);
		2943	tmp \|= S_008C00_VS_PRIO(vs_prio);
		2944	tmp \|= S_008C00_GS_PRIO(gs_prio);
		2945	tmp \|= S_008C00_ES_PRIO(es_prio);
		2946
		2947	/* enable dynamic GPR resource management */
		2948	if (ctx_drm_minor >= 7) {
		2949	r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 2);
		2950	r600_store_value(cb, tmp); /* R_008C00_SQ_CONFIG */
		2951	/* always set temp clauses */
		2952	r600_store_value(cb, S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
		2953	r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
		2954	r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
		2955	r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
		2956	r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8));
		2957	r600_store_context_reg(cb, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1,
		2958	S_028838_PS_GPRS(0x1e) \|
		2959	S_028838_VS_GPRS(0x1e) \|
		2960	S_028838_GS_GPRS(0x1e) \|
		2961	S_028838_ES_GPRS(0x1e) \|
		2962	S_028838_HS_GPRS(0x1e) \|
		2963	S_028838_LS_GPRS(0x1e)); /* workaround for hw issues with dyn gpr - must set all limits to 240 instead of 0, 0x1e == 240 / 8*/
		2964	} else {
		2965	r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 4);
		2966	r600_store_value(cb, tmp); /* R_008C00_SQ_CONFIG */
		2967
		2968	tmp = S_008C04_NUM_PS_GPRS(num_ps_gprs);
		2969	tmp \|= S_008C04_NUM_VS_GPRS(num_vs_gprs);
		2970	tmp \|= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
		2971	r600_store_value(cb, tmp); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
		2972
		2973	tmp = S_008C08_NUM_GS_GPRS(num_gs_gprs);
		2974	tmp \|= S_008C08_NUM_ES_GPRS(num_es_gprs);
		2975	r600_store_value(cb, tmp); /* R_008C08_SQ_GPR_RESOURCE_MGMT_2 */
		2976
		2977	tmp = S_008C0C_NUM_HS_GPRS(num_hs_gprs);
		2978	tmp \|= S_008C0C_NUM_HS_GPRS(num_ls_gprs);
		2979	r600_store_value(cb, tmp); /* R_008C0C_SQ_GPR_RESOURCE_MGMT_3 */
		2980	}
		2981
		2982	r600_store_context_reg(cb, R_028A4C_PA_SC_MODE_CNTL_1, 0);
		2983
		2984	/* The cs checker requires this register to be set. */
		2985	r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
		2986
		2987	r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
		2988
		2989	return;
		2990	}
		2991
		2992	void evergreen_init_atom_start_cs(struct r600_context *rctx)
		2993	{
		2994	struct r600_command_buffer *cb = &rctx->start_cs_cmd;
		2995	int num_ps_threads;
		2996	int num_vs_threads;
		2997	int num_gs_threads;
		2998	int num_es_threads;
		2999	int num_hs_threads;
		3000	int num_ls_threads;
		3001
		3002	int num_ps_stack_entries;
		3003	int num_vs_stack_entries;
		3004	int num_gs_stack_entries;
		3005	int num_es_stack_entries;
		3006	int num_hs_stack_entries;
		3007	int num_ls_stack_entries;
		3008	enum radeon_family family;
		3009	unsigned tmp;
		3010
		3011	if (rctx->chip_class == CAYMAN) {
		3012	cayman_init_atom_start_cs(rctx);
		3013	return;
		3014	}
		3015
		3016	r600_init_command_buffer(cb, 256);
		3017
		3018	/* This must be first. */
		3019	r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
		3020	r600_store_value(cb, 0x80000000);
		3021	r600_store_value(cb, 0x80000000);
		3022
		3023	/* We're setting config registers here. */
		3024	r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
		3025	r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) \| EVENT_INDEX(4));
		3026
		3027	evergreen_init_common_regs(cb, rctx->chip_class,
		3028	rctx->family, rctx->screen->info.drm_minor);
		3029
		3030	family = rctx->family;
		3031	switch (family) {
		3032	case CHIP_CEDAR:
		3033	default:
		3034	num_ps_threads = 96;
		3035	num_vs_threads = 16;
		3036	num_gs_threads = 16;
		3037	num_es_threads = 16;
		3038	num_hs_threads = 16;
		3039	num_ls_threads = 16;
		3040	num_ps_stack_entries = 42;
		3041	num_vs_stack_entries = 42;
		3042	num_gs_stack_entries = 42;
		3043	num_es_stack_entries = 42;
		3044	num_hs_stack_entries = 42;
		3045	num_ls_stack_entries = 42;
		3046	break;
		3047	case CHIP_REDWOOD:
		3048	num_ps_threads = 128;
		3049	num_vs_threads = 20;
		3050	num_gs_threads = 20;
		3051	num_es_threads = 20;
		3052	num_hs_threads = 20;
		3053	num_ls_threads = 20;
		3054	num_ps_stack_entries = 42;
		3055	num_vs_stack_entries = 42;
		3056	num_gs_stack_entries = 42;
		3057	num_es_stack_entries = 42;
		3058	num_hs_stack_entries = 42;
		3059	num_ls_stack_entries = 42;
		3060	break;
		3061	case CHIP_JUNIPER:
		3062	num_ps_threads = 128;
		3063	num_vs_threads = 20;
		3064	num_gs_threads = 20;
		3065	num_es_threads = 20;
		3066	num_hs_threads = 20;
		3067	num_ls_threads = 20;
		3068	num_ps_stack_entries = 85;
		3069	num_vs_stack_entries = 85;
		3070	num_gs_stack_entries = 85;
		3071	num_es_stack_entries = 85;
		3072	num_hs_stack_entries = 85;
		3073	num_ls_stack_entries = 85;
		3074	break;
		3075	case CHIP_CYPRESS:
		3076	case CHIP_HEMLOCK:
		3077	num_ps_threads = 128;
		3078	num_vs_threads = 20;
		3079	num_gs_threads = 20;
		3080	num_es_threads = 20;
		3081	num_hs_threads = 20;
		3082	num_ls_threads = 20;
		3083	num_ps_stack_entries = 85;
		3084	num_vs_stack_entries = 85;
		3085	num_gs_stack_entries = 85;
		3086	num_es_stack_entries = 85;
		3087	num_hs_stack_entries = 85;
		3088	num_ls_stack_entries = 85;
		3089	break;
		3090	case CHIP_PALM:
		3091	num_ps_threads = 96;
		3092	num_vs_threads = 16;
		3093	num_gs_threads = 16;
		3094	num_es_threads = 16;
		3095	num_hs_threads = 16;
		3096	num_ls_threads = 16;
		3097	num_ps_stack_entries = 42;
		3098	num_vs_stack_entries = 42;
		3099	num_gs_stack_entries = 42;
		3100	num_es_stack_entries = 42;
		3101	num_hs_stack_entries = 42;
		3102	num_ls_stack_entries = 42;
		3103	break;
		3104	case CHIP_SUMO:
		3105	num_ps_threads = 96;
		3106	num_vs_threads = 25;
		3107	num_gs_threads = 25;
		3108	num_es_threads = 25;
		3109	num_hs_threads = 25;
		3110	num_ls_threads = 25;
		3111	num_ps_stack_entries = 42;
		3112	num_vs_stack_entries = 42;
		3113	num_gs_stack_entries = 42;
		3114	num_es_stack_entries = 42;
		3115	num_hs_stack_entries = 42;
		3116	num_ls_stack_entries = 42;
		3117	break;
		3118	case CHIP_SUMO2:
		3119	num_ps_threads = 96;
		3120	num_vs_threads = 25;
		3121	num_gs_threads = 25;
		3122	num_es_threads = 25;
		3123	num_hs_threads = 25;
		3124	num_ls_threads = 25;
		3125	num_ps_stack_entries = 85;
		3126	num_vs_stack_entries = 85;
		3127	num_gs_stack_entries = 85;
		3128	num_es_stack_entries = 85;
		3129	num_hs_stack_entries = 85;
		3130	num_ls_stack_entries = 85;
		3131	break;
		3132	case CHIP_BARTS:
		3133	num_ps_threads = 128;
		3134	num_vs_threads = 20;
		3135	num_gs_threads = 20;
		3136	num_es_threads = 20;
		3137	num_hs_threads = 20;
		3138	num_ls_threads = 20;
		3139	num_ps_stack_entries = 85;
		3140	num_vs_stack_entries = 85;
		3141	num_gs_stack_entries = 85;
		3142	num_es_stack_entries = 85;
		3143	num_hs_stack_entries = 85;
		3144	num_ls_stack_entries = 85;
		3145	break;
		3146	case CHIP_TURKS:
		3147	num_ps_threads = 128;
		3148	num_vs_threads = 20;
		3149	num_gs_threads = 20;
		3150	num_es_threads = 20;
		3151	num_hs_threads = 20;
		3152	num_ls_threads = 20;
		3153	num_ps_stack_entries = 42;
		3154	num_vs_stack_entries = 42;
		3155	num_gs_stack_entries = 42;
		3156	num_es_stack_entries = 42;
		3157	num_hs_stack_entries = 42;
		3158	num_ls_stack_entries = 42;
		3159	break;
		3160	case CHIP_CAICOS:
		3161	num_ps_threads = 128;
		3162	num_vs_threads = 10;
		3163	num_gs_threads = 10;
		3164	num_es_threads = 10;
		3165	num_hs_threads = 10;
		3166	num_ls_threads = 10;
		3167	num_ps_stack_entries = 42;
		3168	num_vs_stack_entries = 42;
		3169	num_gs_stack_entries = 42;
		3170	num_es_stack_entries = 42;
		3171	num_hs_stack_entries = 42;
		3172	num_ls_stack_entries = 42;
		3173	break;
		3174	}
		3175
		3176	tmp = S_008C18_NUM_PS_THREADS(num_ps_threads);
		3177	tmp \|= S_008C18_NUM_VS_THREADS(num_vs_threads);
		3178	tmp \|= S_008C18_NUM_GS_THREADS(num_gs_threads);
		3179	tmp \|= S_008C18_NUM_ES_THREADS(num_es_threads);
		3180
		3181	r600_store_config_reg_seq(cb, R_008C18_SQ_THREAD_RESOURCE_MGMT_1, 5);
		3182	r600_store_value(cb, tmp); /* R_008C18_SQ_THREAD_RESOURCE_MGMT_1 */
		3183
		3184	tmp = S_008C1C_NUM_HS_THREADS(num_hs_threads);
		3185	tmp \|= S_008C1C_NUM_LS_THREADS(num_ls_threads);
		3186	r600_store_value(cb, tmp); /* R_008C1C_SQ_THREAD_RESOURCE_MGMT_2 */
		3187
		3188	tmp = S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
		3189	tmp \|= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
		3190	r600_store_value(cb, tmp); /* R_008C20_SQ_STACK_RESOURCE_MGMT_1 */
		3191
		3192	tmp = S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
		3193	tmp \|= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
		3194	r600_store_value(cb, tmp); /* R_008C24_SQ_STACK_RESOURCE_MGMT_2 */
		3195
		3196	tmp = S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries);
		3197	tmp \|= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries);
		3198	r600_store_value(cb, tmp); /* R_008C28_SQ_STACK_RESOURCE_MGMT_3 */
		3199
		3200	r600_store_config_reg(cb, R_008E2C_SQ_LDS_RESOURCE_MGMT,
		3201	S_008E2C_NUM_PS_LDS(0x1000) \| S_008E2C_NUM_LS_LDS(0x1000));
		3202
		3203	r600_store_config_reg(cb, R_009100_SPI_CONFIG_CNTL, 0);
		3204	r600_store_config_reg(cb, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4));
		3205
		3206	r600_store_context_reg_seq(cb, R_028900_SQ_ESGS_RING_ITEMSIZE, 6);
		3207	r600_store_value(cb, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
		3208	r600_store_value(cb, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
		3209	r600_store_value(cb, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
		3210	r600_store_value(cb, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
		3211	r600_store_value(cb, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
		3212	r600_store_value(cb, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
		3213
		3214	r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
		3215	r600_store_value(cb, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
		3216	r600_store_value(cb, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
		3217	r600_store_value(cb, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
		3218	r600_store_value(cb, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
		3219
		3220	r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
		3221	r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
		3222	r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
		3223	r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
		3224	r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
		3225	r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
		3226	r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
		3227	r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
		3228	r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
		3229	r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
		3230	r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
		3231	r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
		3232	r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
		3233	r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
		3234
		3235	r600_store_context_reg_seq(cb, R_028AB4_VGT_REUSE_OFF, 2);
		3236	r600_store_value(cb, 0); /* R_028AB4_VGT_REUSE_OFF */
		3237	r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
		3238
		3239	r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) \| 1);
		3240
		3241	r600_store_context_reg(cb, R_0288F0_SQ_VTX_SEMANTIC_CLEAR, ~0);
		3242
		3243	r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2);
		3244	r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
		3245	r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
		3246
		3247	r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
		3248
		3249	r600_store_context_reg(cb, R_028028_DB_STENCIL_CLEAR, 0);
		3250
		3251	r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
		3252	r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
		3253	r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
		3254
		3255	r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
		3256	r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
		3257	r600_store_value(cb, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
		3258
		3259	r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
		3260	r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 0x0000043F);
		3261	r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
		3262
		3263	r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
		3264	r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
		3265	r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
		3266	r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
		3267
		3268	r600_store_context_reg_seq(cb, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 4);
		3269	r600_store_value(cb, 0x3F800000); /* R_028C0C_PA_CL_GB_VERT_CLIP_ADJ */
		3270	r600_store_value(cb, 0x3F800000); /* R_028C10_PA_CL_GB_VERT_DISC_ADJ */
		3271	r600_store_value(cb, 0x3F800000); /* R_028C14_PA_CL_GB_HORZ_CLIP_ADJ */
		3272	r600_store_value(cb, 0x3F800000); /* R_028C18_PA_CL_GB_HORZ_DISC_ADJ */
		3273
		3274	r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
		3275	r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
		3276	r600_store_value(cb, S_028244_BR_X(16384) \| S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
		3277
		3278	r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
		3279	r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
		3280	r600_store_value(cb, S_028034_BR_X(16384) \| S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
		3281
		3282	r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
		3283	r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
		3284	r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
		3285
		3286	/* to avoid GPU doing any preloading of constant from random address */
		3287	r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 16);
		3288	r600_store_value(cb, 0); /* R_028140_ALU_CONST_BUFFER_SIZE_PS_0 */
		3289	r600_store_value(cb, 0);
		3290	r600_store_value(cb, 0);
		3291	r600_store_value(cb, 0);
		3292	r600_store_value(cb, 0);
		3293	r600_store_value(cb, 0);
		3294	r600_store_value(cb, 0);
		3295	r600_store_value(cb, 0);
		3296	r600_store_value(cb, 0);
		3297	r600_store_value(cb, 0);
		3298	r600_store_value(cb, 0);
		3299	r600_store_value(cb, 0);
		3300	r600_store_value(cb, 0);
		3301	r600_store_value(cb, 0);
		3302	r600_store_value(cb, 0);
		3303	r600_store_value(cb, 0);
		3304
		3305	r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 16);
		3306	r600_store_value(cb, 0); /* R_028180_ALU_CONST_BUFFER_SIZE_VS_0 */
		3307	r600_store_value(cb, 0);
		3308	r600_store_value(cb, 0);
		3309	r600_store_value(cb, 0);
		3310	r600_store_value(cb, 0);
		3311	r600_store_value(cb, 0);
		3312	r600_store_value(cb, 0);
		3313	r600_store_value(cb, 0);
		3314	r600_store_value(cb, 0);
		3315	r600_store_value(cb, 0);
		3316	r600_store_value(cb, 0);
		3317	r600_store_value(cb, 0);
		3318	r600_store_value(cb, 0);
		3319	r600_store_value(cb, 0);
		3320	r600_store_value(cb, 0);
		3321	r600_store_value(cb, 0);
		3322
		3323	r600_store_context_reg_seq(cb, R_028B94_VGT_STRMOUT_CONFIG, 2);
		3324	r600_store_value(cb, 0); /* R_028B94_VGT_STRMOUT_CONFIG */
		3325	r600_store_value(cb, 0); /* R_028B98_VGT_STRMOUT_BUFFER_CONFIG */
		3326
		3327	if (rctx->screen->has_streamout) {
		3328	r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
		3329	}
		3330
		3331	r600_store_context_reg(cb, R_028010_DB_RENDER_OVERRIDE2, 0);
		3332	r600_store_context_reg(cb, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
		3333	r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
		3334	r600_store_context_reg_seq(cb, R_0286E4_SPI_PS_IN_CONTROL_2, 2);
		3335	r600_store_value(cb, 0); /* R_0286E4_SPI_PS_IN_CONTROL_2 */
		3336	r600_store_value(cb, 0); /* R_0286E8_SPI_COMPUTE_INPUT_CNTL */
		3337	r600_store_context_reg(cb, R_0288EC_SQ_LDS_ALLOC_PS, 0);
		3338	r600_store_context_reg(cb, R_028B54_VGT_SHADER_STAGES_EN, 0);
		3339
		3340	eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
		3341	eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
		3342	}
		3343
		3344	void evergreen_update_ps_state(struct pipe_context ctx, struct r600_pipe_shader shader)
		3345	{
		3346	struct r600_context rctx = (struct r600_context )ctx;
		3347	struct r600_command_buffer *cb = &shader->command_buffer;
		3348	struct r600_shader *rshader = &shader->shader;
		3349	unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control = 0;
		3350	int pos_index = -1, face_index = -1;
		3351	int ninterp = 0;
		3352	boolean have_linear = FALSE, have_centroid = FALSE, have_perspective = FALSE;
		3353	unsigned spi_baryc_cntl, sid, tmp, num = 0;
		3354	unsigned z_export = 0, stencil_export = 0;
		3355	unsigned sprite_coord_enable = rctx->rasterizer ? rctx->rasterizer->sprite_coord_enable : 0;
		3356	uint32_t spi_ps_input_cntl[32];
		3357
		3358	if (!cb->buf) {
		3359	r600_init_command_buffer(cb, 64);
		3360	} else {
		3361	cb->num_dw = 0;
		3362	}
		3363
		3364	for (i = 0; i < rshader->ninput; i++) {
		3365	/* evergreen NUM_INTERP only contains values interpolated into the LDS,
		3366	POSITION goes via GPRs from the SC so isn't counted */
		3367	if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
		3368	pos_index = i;
		3369	else if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
		3370	face_index = i;
		3371	else {
		3372	ninterp++;
		3373	if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR)
		3374	have_linear = TRUE;
		3375	if (rshader->input[i].interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
		3376	have_perspective = TRUE;
		3377	if (rshader->input[i].centroid)
		3378	have_centroid = TRUE;
		3379	}
		3380
		3381	sid = rshader->input[i].spi_sid;
		3382
		3383	if (sid) {
		3384	tmp = S_028644_SEMANTIC(sid);
		3385
		3386	if (rshader->input[i].name == TGSI_SEMANTIC_POSITION \|\|
		3387	rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT \|\|
		3388	(rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
		3389	rctx->rasterizer && rctx->rasterizer->flatshade)) {
		3390	tmp \|= S_028644_FLAT_SHADE(1);
		3391	}
		3392
		3393	if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
		3394	(sprite_coord_enable & (1 << rshader->input[i].sid))) {
		3395	tmp \|= S_028644_PT_SPRITE_TEX(1);
		3396	}
		3397
		3398	spi_ps_input_cntl[num++] = tmp;
		3399	}
		3400	}
		3401
		3402	r600_store_context_reg_seq(cb, R_028644_SPI_PS_INPUT_CNTL_0, num);
		3403	r600_store_array(cb, num, spi_ps_input_cntl);
		3404
		3405	for (i = 0; i < rshader->noutput; i++) {
		3406	if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
		3407	z_export = 1;
		3408	if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
		3409	stencil_export = 1;
		3410	}
		3411	if (rshader->uses_kill)
		3412	db_shader_control \|= S_02880C_KILL_ENABLE(1);
		3413
		3414	db_shader_control \|= S_02880C_Z_EXPORT_ENABLE(z_export);
		3415	db_shader_control \|= S_02880C_STENCIL_EXPORT_ENABLE(stencil_export);
		3416
		3417	exports_ps = 0;
		3418	for (i = 0; i < rshader->noutput; i++) {
		3419	if (rshader->output[i].name == TGSI_SEMANTIC_POSITION \|\|
		3420	rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
		3421	exports_ps \|= 1;
		3422	}
		3423
		3424	num_cout = rshader->nr_ps_color_exports;
		3425
		3426	exports_ps \|= S_02884C_EXPORT_COLORS(num_cout);
		3427	if (!exports_ps) {
		3428	/* always at least export 1 component per pixel */
		3429	exports_ps = 2;
		3430	}
		3431	shader->nr_ps_color_outputs = num_cout;
		3432	if (ninterp == 0) {
		3433	ninterp = 1;
		3434	have_perspective = TRUE;
		3435	}
		3436
		3437	if (!have_perspective && !have_linear)
		3438	have_perspective = TRUE;
		3439
		3440	spi_ps_in_control_0 = S_0286CC_NUM_INTERP(ninterp) \|
		3441	S_0286CC_PERSP_GRADIENT_ENA(have_perspective) \|
		3442	S_0286CC_LINEAR_GRADIENT_ENA(have_linear);
		3443	spi_input_z = 0;
		3444	if (pos_index != -1) {
		3445	spi_ps_in_control_0 \|= S_0286CC_POSITION_ENA(1) \|
		3446	S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) \|
		3447	S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr);
		3448	spi_input_z \|= S_0286D8_PROVIDE_Z_TO_SPI(1);
		3449	}
		3450
		3451	spi_ps_in_control_1 = 0;
		3452	if (face_index != -1) {
		3453	spi_ps_in_control_1 \|= S_0286D0_FRONT_FACE_ENA(1) \|
		3454	S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
		3455	}
		3456
		3457	spi_baryc_cntl = 0;
		3458	if (have_perspective)
		3459	spi_baryc_cntl \|= S_0286E0_PERSP_CENTER_ENA(1) \|
		3460	S_0286E0_PERSP_CENTROID_ENA(have_centroid);
		3461	if (have_linear)
		3462	spi_baryc_cntl \|= S_0286E0_LINEAR_CENTER_ENA(1) \|
		3463	S_0286E0_LINEAR_CENTROID_ENA(have_centroid);
		3464
		3465	r600_store_context_reg_seq(cb, R_0286CC_SPI_PS_IN_CONTROL_0, 2);
		3466	r600_store_value(cb, spi_ps_in_control_0); /* R_0286CC_SPI_PS_IN_CONTROL_0 */
		3467	r600_store_value(cb, spi_ps_in_control_1); /* R_0286D0_SPI_PS_IN_CONTROL_1 */
		3468
		3469	r600_store_context_reg(cb, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
		3470	r600_store_context_reg(cb, R_0286D8_SPI_INPUT_Z, spi_input_z);
		3471	r600_store_context_reg(cb, R_02884C_SQ_PGM_EXPORTS_PS, exports_ps);
		3472
		3473	r600_store_context_reg_seq(cb, R_028840_SQ_PGM_START_PS, 2);
		3474	r600_store_value(cb, r600_resource_va(ctx->screen, (void *)shader->bo) >> 8);
		3475	r600_store_value(cb, /* R_028844_SQ_PGM_RESOURCES_PS */
		3476	S_028844_NUM_GPRS(rshader->bc.ngpr) \|
		3477	S_028844_PRIME_CACHE_ON_DRAW(1) \|
		3478	S_028844_STACK_SIZE(rshader->bc.nstack));
		3479	/* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
		3480
		3481	shader->db_shader_control = db_shader_control;
		3482	shader->ps_depth_export = z_export \| stencil_export;
		3483
		3484	shader->sprite_coord_enable = sprite_coord_enable;
		3485	if (rctx->rasterizer)
		3486	shader->flatshade = rctx->rasterizer->flatshade;
		3487	}
		3488
		3489	void evergreen_update_vs_state(struct pipe_context ctx, struct r600_pipe_shader shader)
		3490	{
		3491	struct r600_command_buffer *cb = &shader->command_buffer;
		3492	struct r600_shader *rshader = &shader->shader;
		3493	unsigned spi_vs_out_id[10] = {};
		3494	unsigned i, tmp, nparams = 0;
		3495
		3496	for (i = 0; i < rshader->noutput; i++) {
		3497	if (rshader->output[i].spi_sid) {
		3498	tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
		3499	spi_vs_out_id[nparams / 4] \|= tmp;
		3500	nparams++;
		3501	}
		3502	}
		3503
		3504	r600_init_command_buffer(cb, 32);
		3505
		3506	r600_store_context_reg_seq(cb, R_02861C_SPI_VS_OUT_ID_0, 10);
		3507	for (i = 0; i < 10; i++) {
		3508	r600_store_value(cb, spi_vs_out_id[i]);
		3509	}
		3510
		3511	/* Certain attributes (position, psize, etc.) don't count as params.
		3512	* VS is required to export at least one param and r600_shader_from_tgsi()
		3513	* takes care of adding a dummy export.
		3514	*/
		3515	if (nparams < 1)
		3516	nparams = 1;
		3517
		3518	r600_store_context_reg(cb, R_0286C4_SPI_VS_OUT_CONFIG,
		3519	S_0286C4_VS_EXPORT_COUNT(nparams - 1));
		3520	r600_store_context_reg(cb, R_028860_SQ_PGM_RESOURCES_VS,
		3521	S_028860_NUM_GPRS(rshader->bc.ngpr) \|
		3522	S_028860_STACK_SIZE(rshader->bc.nstack));
		3523	r600_store_context_reg(cb, R_02885C_SQ_PGM_START_VS,
		3524	r600_resource_va(ctx->screen, (void *)shader->bo) >> 8);
		3525	/* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
		3526
		3527	shader->pa_cl_vs_out_cntl =
		3528	S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) \|
		3529	S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) \|
		3530	S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) \|
		3531	S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size);
		3532	}
		3533
		3534	void evergreen_create_resolve_blend(struct r600_context rctx)
		3535	{
		3536	struct pipe_blend_state blend;
		3537
		3538	memset(&blend, 0, sizeof(blend));
		3539	blend.independent_blend_enable = true;
		3540	blend.rt[0].colormask = 0xf;
		3541	return evergreen_create_blend_state_mode(&rctx->context, &blend, V_028808_CB_RESOLVE);
		3542	}
		3543
		3544	void evergreen_create_decompress_blend(struct r600_context rctx)
		3545	{
		3546	struct pipe_blend_state blend;
		3547	unsigned mode = rctx->screen->has_compressed_msaa_texturing ?
		3548	V_028808_CB_FMASK_DECOMPRESS : V_028808_CB_DECOMPRESS;
		3549
		3550	memset(&blend, 0, sizeof(blend));
		3551	blend.independent_blend_enable = true;
		3552	blend.rt[0].colormask = 0xf;
		3553	return evergreen_create_blend_state_mode(&rctx->context, &blend, mode);
		3554	}
		3555
		3556	void evergreen_create_db_flush_dsa(struct r600_context rctx)
		3557	{
		3558	struct pipe_depth_stencil_alpha_state dsa = {{0}};
		3559
		3560	return rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
		3561	}
		3562
		3563	void evergreen_update_db_shader_control(struct r600_context * rctx)
		3564	{
		3565	bool dual_export = rctx->framebuffer.export_16bpc &&
		3566	!rctx->ps_shader->current->ps_depth_export;
		3567
		3568	unsigned db_shader_control = rctx->ps_shader->current->db_shader_control \|
		3569	S_02880C_DUAL_EXPORT_ENABLE(dual_export) \|
		3570	S_02880C_DB_SOURCE_FORMAT(dual_export ? V_02880C_EXPORT_DB_TWO :
		3571	V_02880C_EXPORT_DB_FULL) \|
		3572	S_02880C_ALPHA_TO_MASK_DISABLE(rctx->framebuffer.cb0_is_integer);
		3573
		3574	/* When alpha test is enabled we can't trust the hw to make the proper
		3575	* decision on the order in which ztest should be run related to fragment
		3576	* shader execution.
		3577	*
		3578	* If alpha test is enabled perform early z rejection (RE_Z) but don't early
		3579	* write to the zbuffer. Write to zbuffer is delayed after fragment shader
		3580	* execution and thus after alpha test so if discarded by the alpha test
		3581	* the z value is not written.
		3582	* If ReZ is enabled, and the zfunc/zenable/zwrite values change you can
		3583	* get a hang unless you flush the DB in between. For now just use
		3584	* LATE_Z.
		3585	*/
		3586	if (rctx->alphatest_state.sx_alpha_test_control) {
		3587	db_shader_control \|= S_02880C_Z_ORDER(V_02880C_LATE_Z);
		3588	} else {
		3589	db_shader_control \|= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
		3590	}
		3591
		3592	if (db_shader_control != rctx->db_misc_state.db_shader_control) {
		3593	rctx->db_misc_state.db_shader_control = db_shader_control;
		3594	rctx->db_misc_state.atom.dirty = true;
		3595	}
		3596	}
		3597
		3598	static void evergreen_dma_copy_tile(struct r600_context *rctx,
		3599	struct pipe_resource *dst,
		3600	unsigned dst_level,
		3601	unsigned dst_x,
		3602	unsigned dst_y,
		3603	unsigned dst_z,
		3604	struct pipe_resource *src,
		3605	unsigned src_level,
		3606	unsigned src_x,
		3607	unsigned src_y,
		3608	unsigned src_z,
		3609	unsigned copy_height,
		3610	unsigned pitch,
		3611	unsigned bpp)
		3612	{
		3613	struct radeon_winsys_cs *cs = rctx->rings.dma.cs;
		3614	struct r600_texture rsrc = (struct r600_texture)src;
		3615	struct r600_texture rdst = (struct r600_texture)dst;
		3616	unsigned array_mode, lbpp, pitch_tile_max, slice_tile_max, size;
		3617	unsigned ncopy, height, cheight, detile, i, x, y, z, src_mode, dst_mode;
		3618	unsigned sub_cmd, bank_h, bank_w, mt_aspect, nbanks, tile_split, non_disp_tiling = 0;
		3619	uint64_t base, addr;
		3620
		3621	/* make sure that the dma ring is only one active */
		3622	rctx->rings.gfx.flush(rctx, RADEON_FLUSH_ASYNC);
		3623
		3624	dst_mode = rdst->surface.level[dst_level].mode;
		3625	src_mode = rsrc->surface.level[src_level].mode;
		3626	/* downcast linear aligned to linear to simplify test */
		3627	src_mode = src_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : src_mode;
		3628	dst_mode = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : dst_mode;
		3629	assert(dst_mode != src_mode);
		3630
		3631	/* non_disp_tiling bit needs to be set for depth, stencil, and fmask surfaces */
		3632	if (util_format_has_depth(util_format_description(src->format)))
		3633	non_disp_tiling = 1;
		3634
		3635	y = 0;
		3636	sub_cmd = 0x8;
		3637	lbpp = util_logbase2(bpp);
		3638	pitch_tile_max = ((pitch / bpp) >> 3) - 1;
		3639	nbanks = eg_num_banks(rctx->screen->tiling_info.num_banks);
		3640
		3641	if (dst_mode == RADEON_SURF_MODE_LINEAR) {
		3642	/* T2L */
		3643	array_mode = evergreen_array_mode(src_mode);
		3644	slice_tile_max = (rsrc->surface.level[src_level].nblk_x * rsrc->surface.level[src_level].nblk_y) >> 6;
		3645	slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
		3646	/* linear height must be the same as the slice tile max height, it's ok even
		3647	* if the linear destination/source have smaller heigh as the size of the
		3648	* dma packet will be using the copy_height which is always smaller or equal
		3649	* to the linear height
		3650	*/
		3651	height = rsrc->surface.level[src_level].npix_y;
		3652	detile = 1;
		3653	x = src_x;
		3654	y = src_y;
		3655	z = src_z;
		3656	base = rsrc->surface.level[src_level].offset;
		3657	addr = rdst->surface.level[dst_level].offset;
		3658	addr += rdst->surface.level[dst_level].slice_size * dst_z;
		3659	addr += dst_y * pitch + dst_x * bpp;
		3660	bank_h = eg_bank_wh(rsrc->surface.bankh);
		3661	bank_w = eg_bank_wh(rsrc->surface.bankw);
		3662	mt_aspect = eg_macro_tile_aspect(rsrc->surface.mtilea);
		3663	tile_split = eg_tile_split(rsrc->surface.tile_split);
		3664	base += r600_resource_va(&rctx->screen->screen, src);
		3665	addr += r600_resource_va(&rctx->screen->screen, dst);
		3666	} else {
		3667	/* L2T */
		3668	array_mode = evergreen_array_mode(dst_mode);
		3669	slice_tile_max = (rdst->surface.level[dst_level].nblk_x * rdst->surface.level[dst_level].nblk_y) >> 6;
		3670	slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
		3671	/* linear height must be the same as the slice tile max height, it's ok even
		3672	* if the linear destination/source have smaller heigh as the size of the
		3673	* dma packet will be using the copy_height which is always smaller or equal
		3674	* to the linear height
		3675	*/
		3676	height = rdst->surface.level[dst_level].npix_y;
		3677	detile = 0;
		3678	x = dst_x;
		3679	y = dst_y;
		3680	z = dst_z;
		3681	base = rdst->surface.level[dst_level].offset;
		3682	addr = rsrc->surface.level[src_level].offset;
		3683	addr += rsrc->surface.level[src_level].slice_size * src_z;
		3684	addr += src_y * pitch + src_x * bpp;
		3685	bank_h = eg_bank_wh(rdst->surface.bankh);
		3686	bank_w = eg_bank_wh(rdst->surface.bankw);
		3687	mt_aspect = eg_macro_tile_aspect(rdst->surface.mtilea);
		3688	tile_split = eg_tile_split(rdst->surface.tile_split);
		3689	base += r600_resource_va(&rctx->screen->screen, dst);
		3690	addr += r600_resource_va(&rctx->screen->screen, src);
		3691	}
		3692
		3693	size = (copy_height * pitch) >> 2;
		3694	ncopy = (size / 0x000fffff) + !!(size % 0x000fffff);
		3695	r600_need_dma_space(rctx, ncopy * 9);
		3696
		3697	for (i = 0; i < ncopy; i++) {
		3698	cheight = copy_height;
		3699	if (((cheight * pitch) >> 2) > 0x000fffff) {
		3700	cheight = (0x000fffff << 2) / pitch;
		3701	}
		3702	size = (cheight * pitch) >> 2;
		3703	/* emit reloc before writting cs so that cs is always in consistent state */
		3704	r600_context_bo_reloc(rctx, &rctx->rings.dma, &rsrc->resource, RADEON_USAGE_READ);
		3705	r600_context_bo_reloc(rctx, &rctx->rings.dma, &rdst->resource, RADEON_USAGE_WRITE);
		3706	cs->buf[cs->cdw++] = DMA_PACKET(DMA_PACKET_COPY, sub_cmd, size);
		3707	cs->buf[cs->cdw++] = base >> 8;
		3708	cs->buf[cs->cdw++] = (detile << 31) \| (array_mode << 27) \|
		3709	(lbpp << 24) \| (bank_h << 21) \|
		3710	(bank_w << 18) \| (mt_aspect << 16);
		3711	cs->buf[cs->cdw++] = (pitch_tile_max << 0) \| ((height - 1) << 16);
		3712	cs->buf[cs->cdw++] = (slice_tile_max << 0);
		3713	cs->buf[cs->cdw++] = (x << 0) \| (z << 18);
		3714	cs->buf[cs->cdw++] = (y << 0) \| (tile_split << 21) \| (nbanks << 25) \| (non_disp_tiling << 28);
		3715	cs->buf[cs->cdw++] = addr & 0xfffffffc;
		3716	cs->buf[cs->cdw++] = (addr >> 32UL) & 0xff;
		3717	copy_height -= cheight;
		3718	addr += cheight * pitch;
		3719	y += cheight;
		3720	}
		3721	}
		3722
		3723	boolean evergreen_dma_blit(struct pipe_context *ctx,
		3724	struct pipe_resource *dst,
		3725	unsigned dst_level,
		3726	unsigned dst_x, unsigned dst_y, unsigned dst_z,
		3727	struct pipe_resource *src,
		3728	unsigned src_level,
		3729	const struct pipe_box *src_box)
		3730	{
		3731	struct r600_context rctx = (struct r600_context )ctx;
		3732	struct r600_texture rsrc = (struct r600_texture)src;
		3733	struct r600_texture rdst = (struct r600_texture)dst;
		3734	unsigned dst_pitch, src_pitch, bpp, dst_mode, src_mode, copy_height;
		3735	unsigned src_w, dst_w;
		3736	unsigned src_x, src_y;
		3737
		3738	if (rctx->rings.dma.cs == NULL) {
		3739	return FALSE;
		3740	}
		3741	if (src->format != dst->format) {
		3742	return FALSE;
		3743	}
		3744
		3745	src_x = util_format_get_nblocksx(src->format, src_box->x);
		3746	dst_x = util_format_get_nblocksx(src->format, dst_x);
		3747	src_y = util_format_get_nblocksy(src->format, src_box->y);
		3748	dst_y = util_format_get_nblocksy(src->format, dst_y);
		3749
		3750	bpp = rdst->surface.bpe;
		3751	dst_pitch = rdst->surface.level[dst_level].pitch_bytes;
		3752	src_pitch = rsrc->surface.level[src_level].pitch_bytes;
		3753	src_w = rsrc->surface.level[src_level].npix_x;
		3754	dst_w = rdst->surface.level[dst_level].npix_x;
		3755	copy_height = src_box->height / rsrc->surface.blk_h;
		3756
		3757	dst_mode = rdst->surface.level[dst_level].mode;
		3758	src_mode = rsrc->surface.level[src_level].mode;
		3759	/* downcast linear aligned to linear to simplify test */
		3760	src_mode = src_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : src_mode;
		3761	dst_mode = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : dst_mode;
		3762
		3763	if (src_pitch != dst_pitch \|\| src_box->x \|\| dst_x \|\| src_w != dst_w) {
		3764	/* FIXME evergreen can do partial blit */
		3765	return FALSE;
		3766	}
		3767	/* the x test here are currently useless (because we don't support partial blit)
		3768	* but keep them around so we don't forget about those
		3769	*/
		3770	if ((src_pitch & 0x7) \|\| (src_box->x & 0x7) \|\| (dst_x & 0x7) \|\| (src_box->y & 0x7) \|\| (dst_y & 0x7)) {
		3771	return FALSE;
		3772	}
		3773
		3774	/* 128 bpp surfaces require non_disp_tiling for both
		3775	* tiled and linear buffers on cayman. However, async
		3776	* DMA only supports it on the tiled side. As such
		3777	* the tile order is backwards after a L2T/T2L packet.
		3778	*/
		3779	if ((rctx->chip_class == CAYMAN) &&
		3780	(src_mode != dst_mode) &&
		3781	(util_format_get_blocksize(src->format) >= 16)) {
		3782	return FALSE;
		3783	}
		3784
		3785	if (src_mode == dst_mode) {
		3786	uint64_t dst_offset, src_offset;
		3787	/* simple dma blit would do NOTE code here assume :
		3788	* src_box.x/y == 0
		3789	* dst_x/y == 0
		3790	* dst_pitch == src_pitch
		3791	*/
		3792	src_offset= rsrc->surface.level[src_level].offset;
		3793	src_offset += rsrc->surface.level[src_level].slice_size * src_box->z;
		3794	src_offset += src_y * src_pitch + src_x * bpp;
		3795	dst_offset = rdst->surface.level[dst_level].offset;
		3796	dst_offset += rdst->surface.level[dst_level].slice_size * dst_z;
		3797	dst_offset += dst_y * dst_pitch + dst_x * bpp;
		3798	evergreen_dma_copy(rctx, dst, src, dst_offset, src_offset,
		3799	src_box->height * src_pitch);
		3800	} else {
		3801	evergreen_dma_copy_tile(rctx, dst, dst_level, dst_x, dst_y, dst_z,
		3802	src, src_level, src_x, src_y, src_box->z,
		3803	copy_height, dst_pitch, bpp);
		3804	}
		3805	return TRUE;
		3806	}
		3807
		3808	void evergreen_init_state_functions(struct r600_context *rctx)
		3809	{
		3810	unsigned id = 4;
		3811
		3812	/* !!!
		3813	* To avoid GPU lockup registers must be emited in a specific order
		3814	* (no kidding ...). The order below is important and have been
		3815	* partialy infered from analyzing fglrx command stream.
		3816	*
		3817	* Don't reorder atom without carefully checking the effect (GPU lockup
		3818	* or piglit regression).
		3819	* !!!
		3820	*/
		3821
		3822	r600_init_atom(rctx, &rctx->framebuffer.atom, id++, evergreen_emit_framebuffer_state, 0);
		3823	/* shader const */
		3824	r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX].atom, id++, evergreen_emit_vs_constant_buffers, 0);
		3825	r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY].atom, id++, evergreen_emit_gs_constant_buffers, 0);
		3826	r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT].atom, id++, evergreen_emit_ps_constant_buffers, 0);
		3827	r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_COMPUTE].atom, id++, evergreen_emit_cs_constant_buffers, 0);
		3828	/* shader program */
		3829	r600_init_atom(rctx, &rctx->cs_shader_state.atom, id++, evergreen_emit_cs_shader, 0);
		3830	/* sampler */
		3831	r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].states.atom, id++, evergreen_emit_vs_sampler_states, 0);
		3832	r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].states.atom, id++, evergreen_emit_gs_sampler_states, 0);
		3833	r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].states.atom, id++, evergreen_emit_ps_sampler_states, 0);
		3834	/* resources */
		3835	r600_init_atom(rctx, &rctx->vertex_buffer_state.atom, id++, evergreen_fs_emit_vertex_buffers, 0);
		3836	r600_init_atom(rctx, &rctx->cs_vertex_buffer_state.atom, id++, evergreen_cs_emit_vertex_buffers, 0);
		3837	r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views.atom, id++, evergreen_emit_vs_sampler_views, 0);
		3838	r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views.atom, id++, evergreen_emit_gs_sampler_views, 0);
		3839	r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views.atom, id++, evergreen_emit_ps_sampler_views, 0);
		3840
		3841	r600_init_atom(rctx, &rctx->vgt_state.atom, id++, r600_emit_vgt_state, 7);
		3842
		3843	if (rctx->chip_class == EVERGREEN) {
		3844	r600_init_atom(rctx, &rctx->sample_mask.atom, id++, evergreen_emit_sample_mask, 3);
		3845	} else {
		3846	r600_init_atom(rctx, &rctx->sample_mask.atom, id++, cayman_emit_sample_mask, 4);
		3847	}
		3848	rctx->sample_mask.sample_mask = ~0;
		3849
		3850	r600_init_atom(rctx, &rctx->alphatest_state.atom, id++, r600_emit_alphatest_state, 6);
		3851	r600_init_atom(rctx, &rctx->blend_color.atom, id++, r600_emit_blend_color, 6);
		3852	r600_init_atom(rctx, &rctx->blend_state.atom, id++, r600_emit_cso_state, 0);
		3853	r600_init_atom(rctx, &rctx->cb_misc_state.atom, id++, evergreen_emit_cb_misc_state, 4);
		3854	r600_init_atom(rctx, &rctx->clip_misc_state.atom, id++, r600_emit_clip_misc_state, 6);
		3855	r600_init_atom(rctx, &rctx->clip_state.atom, id++, evergreen_emit_clip_state, 26);
		3856	r600_init_atom(rctx, &rctx->db_misc_state.atom, id++, evergreen_emit_db_misc_state, 10);
		3857	r600_init_atom(rctx, &rctx->db_state.atom, id++, evergreen_emit_db_state, 14);
		3858	r600_init_atom(rctx, &rctx->dsa_state.atom, id++, r600_emit_cso_state, 0);
		3859	r600_init_atom(rctx, &rctx->poly_offset_state.atom, id++, evergreen_emit_polygon_offset, 6);
		3860	r600_init_atom(rctx, &rctx->rasterizer_state.atom, id++, r600_emit_cso_state, 0);
		3861	r600_init_atom(rctx, &rctx->scissor.atom, id++, evergreen_emit_scissor_state, 4);
		3862	r600_init_atom(rctx, &rctx->stencil_ref.atom, id++, r600_emit_stencil_ref, 4);
		3863	r600_init_atom(rctx, &rctx->viewport.atom, id++, r600_emit_viewport_state, 8);
		3864	r600_init_atom(rctx, &rctx->vertex_fetch_shader.atom, id++, evergreen_emit_vertex_fetch_shader, 5);
		3865	r600_init_atom(rctx, &rctx->streamout.begin_atom, id++, r600_emit_streamout_begin, 0);
		3866	r600_init_atom(rctx, &rctx->vertex_shader.atom, id++, r600_emit_shader, 23);
		3867	r600_init_atom(rctx, &rctx->pixel_shader.atom, id++, r600_emit_shader, 0);
		3868
		3869	rctx->context.create_blend_state = evergreen_create_blend_state;
		3870	rctx->context.create_depth_stencil_alpha_state = evergreen_create_dsa_state;
		3871	rctx->context.create_rasterizer_state = evergreen_create_rs_state;
		3872	rctx->context.create_sampler_state = evergreen_create_sampler_state;
		3873	rctx->context.create_sampler_view = evergreen_create_sampler_view;
		3874	rctx->context.set_framebuffer_state = evergreen_set_framebuffer_state;
		3875	rctx->context.set_polygon_stipple = evergreen_set_polygon_stipple;
		3876	rctx->context.set_scissor_states = evergreen_set_scissor_states;
		3877
		3878	if (rctx->chip_class == EVERGREEN)
		3879	rctx->context.get_sample_position = evergreen_get_sample_position;
		3880	else
		3881	rctx->context.get_sample_position = cayman_get_sample_position;
		3882	evergreen_init_compute_state_functions(rctx);
		3883	}

Subversion Repositories Kolibri OS

(root)/contrib/sdk/sources/Mesa/mesa-9.2.5/src/gallium/drivers/r600/evergreen_state.c – Rev 5563