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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 5563 | serge | 1 | /************************************************************************** |
| 2 | * |
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| 3 | * Copyright 2007 Tungsten Graphics, Inc., Cedar Park, Texas. |
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| 4 | * All Rights Reserved. |
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| 5 | * |
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| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 7 | * copy of this software and associated documentation files (the |
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| 8 | * "Software"), to deal in the Software without restriction, including |
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| 9 | * without limitation the rights to use, copy, modify, merge, publish, |
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| 10 | * distribute, sub license, and/or sell copies of the Software, and to |
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| 11 | * permit persons to whom the Software is furnished to do so, subject to |
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| 12 | * the following conditions: |
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| 13 | * |
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| 14 | * The above copyright notice and this permission notice (including the |
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| 15 | * next paragraph) shall be included in all copies or substantial portions |
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| 16 | * of the Software. |
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| 17 | * |
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| 18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
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| 19 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
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| 20 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
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| 21 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR |
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| 22 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
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| 23 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
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| 24 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
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| 25 | * |
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| 26 | **************************************************************************/ |
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| 27 | |||
| 28 | /* Authors: |
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| 29 | * Brian Paul |
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| 30 | */ |
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| 31 | |||
| 32 | |||
| 33 | #include "util/u_clear.h" |
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| 34 | #include "util/u_format.h" |
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| 35 | #include "util/u_pack_color.h" |
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| 36 | #include "i915_context.h" |
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| 37 | #include "i915_screen.h" |
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| 38 | #include "i915_reg.h" |
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| 39 | #include "i915_batch.h" |
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| 40 | #include "i915_resource.h" |
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| 41 | #include "i915_state.h" |
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| 42 | |||
| 43 | void |
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| 44 | i915_clear_emit(struct pipe_context *pipe, unsigned buffers, |
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| 45 | const union pipe_color_union *color, |
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| 46 | double depth, unsigned stencil, |
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| 47 | unsigned destx, unsigned desty, unsigned width, unsigned height) |
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| 48 | { |
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| 49 | struct i915_context *i915 = i915_context(pipe); |
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| 50 | uint32_t clear_params, clear_color, clear_depth, clear_stencil, |
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| 51 | clear_color8888, packed_z_stencil; |
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| 52 | union util_color u_color; |
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| 53 | float f_depth = depth; |
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| 54 | struct i915_texture *cbuf_tex, *depth_tex; |
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| 55 | int depth_clear_bbp, color_clear_bbp; |
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| 56 | |||
| 57 | cbuf_tex = depth_tex = NULL; |
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| 58 | clear_params = 0; |
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| 59 | depth_clear_bbp = color_clear_bbp = 0; |
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| 60 | |||
| 61 | if (buffers & PIPE_CLEAR_COLOR) { |
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| 62 | struct pipe_surface *cbuf = i915->framebuffer.cbufs[0]; |
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| 63 | |||
| 64 | clear_params |= CLEARPARAM_WRITE_COLOR; |
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| 65 | cbuf_tex = i915_texture(cbuf->texture); |
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| 66 | |||
| 67 | util_pack_color(color->f, cbuf->format, &u_color); |
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| 68 | if (util_format_get_blocksize(cbuf_tex->b.b.format) == 4) { |
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| 69 | clear_color = u_color.ui; |
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| 70 | color_clear_bbp = 32; |
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| 71 | } else { |
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| 72 | clear_color = (u_color.ui & 0xffff) | (u_color.ui << 16); |
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| 73 | color_clear_bbp = 16; |
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| 74 | } |
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| 75 | |||
| 76 | /* correctly swizzle clear value */ |
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| 77 | if (i915->current.target_fixup_format) |
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| 78 | util_pack_color(color->f, cbuf->format, &u_color); |
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| 79 | else |
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| 80 | util_pack_color(color->f, PIPE_FORMAT_B8G8R8A8_UNORM, &u_color); |
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| 81 | clear_color8888 = u_color.ui; |
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| 82 | } else |
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| 83 | clear_color = clear_color8888 = 0; |
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| 84 | |||
| 85 | clear_depth = clear_stencil = 0; |
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| 86 | if (buffers & PIPE_CLEAR_DEPTH) { |
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| 87 | struct pipe_surface *zbuf = i915->framebuffer.zsbuf; |
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| 88 | |||
| 89 | clear_params |= CLEARPARAM_WRITE_DEPTH; |
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| 90 | depth_tex = i915_texture(zbuf->texture); |
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| 91 | packed_z_stencil = util_pack_z_stencil(depth_tex->b.b.format, depth, stencil); |
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| 92 | |||
| 93 | if (util_format_get_blocksize(depth_tex->b.b.format) == 4) { |
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| 94 | /* Avoid read-modify-write if there's no stencil. */ |
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| 95 | if (buffers & PIPE_CLEAR_STENCIL |
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| 96 | || depth_tex->b.b.format != PIPE_FORMAT_Z24_UNORM_S8_UINT) { |
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| 97 | clear_params |= CLEARPARAM_WRITE_STENCIL; |
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| 98 | clear_stencil = packed_z_stencil >> 24; |
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| 99 | } |
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| 100 | |||
| 101 | clear_depth = packed_z_stencil & 0xffffff; |
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| 102 | depth_clear_bbp = 32; |
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| 103 | } else { |
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| 104 | clear_depth = (packed_z_stencil & 0xffff) | (packed_z_stencil << 16); |
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| 105 | depth_clear_bbp = 16; |
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| 106 | } |
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| 107 | } else if (buffers & PIPE_CLEAR_STENCIL) { |
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| 108 | struct pipe_surface *zbuf = i915->framebuffer.zsbuf; |
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| 109 | |||
| 110 | clear_params |= CLEARPARAM_WRITE_STENCIL; |
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| 111 | depth_tex = i915_texture(zbuf->texture); |
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| 112 | assert(depth_tex->b.b.format == PIPE_FORMAT_Z24_UNORM_S8_UINT); |
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| 113 | |||
| 114 | packed_z_stencil = util_pack_z_stencil(depth_tex->b.b.format, depth, stencil); |
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| 115 | depth_clear_bbp = 32; |
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| 116 | clear_stencil = packed_z_stencil >> 24; |
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| 117 | } |
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| 118 | |||
| 119 | /* hw can't fastclear both depth and color if their bbp mismatch. */ |
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| 120 | if (color_clear_bbp && depth_clear_bbp |
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| 121 | && color_clear_bbp != depth_clear_bbp) { |
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| 122 | if (i915->hardware_dirty) |
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| 123 | i915_emit_hardware_state(i915); |
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| 124 | |||
| 125 | if (!BEGIN_BATCH(1 + 2*(7 + 7))) { |
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| 126 | FLUSH_BATCH(NULL, I915_FLUSH_ASYNC); |
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| 127 | |||
| 128 | i915_emit_hardware_state(i915); |
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| 129 | i915->vbo_flushed = 1; |
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| 130 | |||
| 131 | assert(BEGIN_BATCH(1 + 2*(7 + 7))); |
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| 132 | } |
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| 133 | |||
| 134 | OUT_BATCH(_3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT); |
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| 135 | |||
| 136 | OUT_BATCH(_3DSTATE_CLEAR_PARAMETERS); |
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| 137 | OUT_BATCH(CLEARPARAM_WRITE_COLOR | CLEARPARAM_CLEAR_RECT); |
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| 138 | /* Used for zone init prim */ |
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| 139 | OUT_BATCH(clear_color); |
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| 140 | OUT_BATCH(clear_depth); |
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| 141 | /* Used for clear rect prim */ |
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| 142 | OUT_BATCH(clear_color8888); |
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| 143 | OUT_BATCH_F(f_depth); |
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| 144 | OUT_BATCH(clear_stencil); |
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| 145 | |||
| 146 | OUT_BATCH(_3DPRIMITIVE | PRIM3D_CLEAR_RECT | 5); |
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| 147 | OUT_BATCH_F(destx + width); |
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| 148 | OUT_BATCH_F(desty + height); |
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| 149 | OUT_BATCH_F(destx); |
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| 150 | OUT_BATCH_F(desty + height); |
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| 151 | OUT_BATCH_F(destx); |
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| 152 | OUT_BATCH_F(desty); |
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| 153 | |||
| 154 | OUT_BATCH(_3DSTATE_CLEAR_PARAMETERS); |
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| 155 | OUT_BATCH((clear_params & ~CLEARPARAM_WRITE_COLOR) | |
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| 156 | CLEARPARAM_CLEAR_RECT); |
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| 157 | /* Used for zone init prim */ |
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| 158 | OUT_BATCH(clear_color); |
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| 159 | OUT_BATCH(clear_depth); |
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| 160 | /* Used for clear rect prim */ |
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| 161 | OUT_BATCH(clear_color8888); |
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| 162 | OUT_BATCH_F(f_depth); |
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| 163 | OUT_BATCH(clear_stencil); |
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| 164 | |||
| 165 | OUT_BATCH(_3DPRIMITIVE | PRIM3D_CLEAR_RECT | 5); |
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| 166 | OUT_BATCH_F(destx + width); |
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| 167 | OUT_BATCH_F(desty + height); |
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| 168 | OUT_BATCH_F(destx); |
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| 169 | OUT_BATCH_F(desty + height); |
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| 170 | OUT_BATCH_F(destx); |
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| 171 | OUT_BATCH_F(desty); |
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| 172 | } else { |
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| 173 | if (i915->hardware_dirty) |
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| 174 | i915_emit_hardware_state(i915); |
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| 175 | |||
| 176 | if (!BEGIN_BATCH(1 + 7 + 7)) { |
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| 177 | FLUSH_BATCH(NULL, I915_FLUSH_ASYNC); |
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| 178 | |||
| 179 | i915_emit_hardware_state(i915); |
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| 180 | i915->vbo_flushed = 1; |
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| 181 | |||
| 182 | assert(BEGIN_BATCH(1 + 7 + 7)); |
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| 183 | } |
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| 184 | |||
| 185 | OUT_BATCH(_3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT); |
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| 186 | |||
| 187 | OUT_BATCH(_3DSTATE_CLEAR_PARAMETERS); |
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| 188 | OUT_BATCH(clear_params | CLEARPARAM_CLEAR_RECT); |
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| 189 | /* Used for zone init prim */ |
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| 190 | OUT_BATCH(clear_color); |
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| 191 | OUT_BATCH(clear_depth); |
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| 192 | /* Used for clear rect prim */ |
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| 193 | OUT_BATCH(clear_color8888); |
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| 194 | OUT_BATCH_F(f_depth); |
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| 195 | OUT_BATCH(clear_stencil); |
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| 196 | |||
| 197 | OUT_BATCH(_3DPRIMITIVE | PRIM3D_CLEAR_RECT | 5); |
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| 198 | OUT_BATCH_F(destx + width); |
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| 199 | OUT_BATCH_F(desty + height); |
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| 200 | OUT_BATCH_F(destx); |
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| 201 | OUT_BATCH_F(desty + height); |
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| 202 | OUT_BATCH_F(destx); |
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| 203 | OUT_BATCH_F(desty); |
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| 204 | } |
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| 205 | |||
| 206 | /* Flush after clear, its expected to be a costly operation. |
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| 207 | * This is not required, just a heuristic, but without the flush we'd need to |
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| 208 | * clobber the SCISSOR_ENABLE dynamic state. */ |
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| 209 | FLUSH_BATCH(NULL, I915_FLUSH_ASYNC); |
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| 210 | |||
| 211 | i915->last_fired_vertices = i915->fired_vertices; |
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| 212 | i915->fired_vertices = 0; |
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| 213 | } |
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| 214 | |||
| 215 | /** |
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| 216 | * Clear the given buffers to the specified values. |
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| 217 | * No masking, no scissor (clear entire buffer). |
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| 218 | */ |
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| 219 | void |
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| 220 | i915_clear_blitter(struct pipe_context *pipe, unsigned buffers, |
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| 221 | const union pipe_color_union *color, |
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| 222 | double depth, unsigned stencil) |
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| 223 | { |
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| 224 | util_clear(pipe, &i915_context(pipe)->framebuffer, buffers, color, depth, |
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| 225 | stencil); |
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| 226 | } |
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| 227 | |||
| 228 | void |
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| 229 | i915_clear_render(struct pipe_context *pipe, unsigned buffers, |
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| 230 | const union pipe_color_union *color, |
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| 231 | double depth, unsigned stencil) |
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| 232 | { |
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| 233 | struct i915_context *i915 = i915_context(pipe); |
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| 234 | |||
| 235 | if (i915->dirty) |
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| 236 | i915_update_derived(i915); |
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| 237 | |||
| 238 | i915_clear_emit(pipe, buffers, color, depth, stencil, |
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| 239 | 0, 0, i915->framebuffer.width, i915->framebuffer.height); |
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| 240 | } |