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5563 | serge | 1 | /* |
2 | * Copyright (c) 2012 Rob Clark |
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3 | * |
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4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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5 | * copy of this software and associated documentation files (the "Software"), |
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6 | * to deal in the Software without restriction, including without limitation |
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7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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8 | * and/or sell copies of the Software, and to permit persons to whom the |
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9 | * Software is furnished to do so, subject to the following conditions: |
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10 | * |
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11 | * The above copyright notice and this permission notice (including the next |
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12 | * paragraph) shall be included in all copies or substantial portions of the |
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13 | * Software. |
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14 | * |
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15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
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20 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
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21 | * SOFTWARE. |
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22 | */ |
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23 | |||
24 | #ifndef IR2_H_ |
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25 | #define IR2_H_ |
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26 | |||
27 | #include |
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28 | #include |
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29 | |||
30 | #include "instr-a2xx.h" |
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31 | |||
32 | /* low level intermediate representation of an adreno a2xx shader program */ |
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33 | |||
34 | struct ir2_shader; |
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35 | |||
36 | struct ir2_shader_info { |
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37 | uint16_t sizedwords; |
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38 | int8_t max_reg; /* highest GPR # used by shader */ |
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39 | uint8_t max_input_reg; |
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40 | uint64_t regs_written; |
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41 | }; |
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42 | |||
43 | struct ir2_register { |
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44 | enum { |
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45 | IR2_REG_CONST = 0x1, |
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46 | IR2_REG_EXPORT = 0x2, |
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47 | IR2_REG_NEGATE = 0x4, |
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48 | IR2_REG_ABS = 0x8, |
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49 | } flags; |
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50 | int num; |
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51 | char *swizzle; |
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52 | }; |
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53 | |||
54 | enum ir2_pred { |
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55 | IR2_PRED_NONE = 0, |
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56 | IR2_PRED_EQ = 1, |
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57 | IR2_PRED_NE = 2, |
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58 | }; |
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59 | |||
60 | struct ir2_instruction { |
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61 | struct ir2_shader *shader; |
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62 | enum { |
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63 | IR2_FETCH, |
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64 | IR2_ALU, |
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65 | } instr_type; |
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66 | enum ir2_pred pred; |
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67 | int sync; |
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68 | unsigned regs_count; |
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69 | struct ir2_register *regs[5]; |
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70 | union { |
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71 | /* FETCH specific: */ |
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72 | struct { |
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73 | instr_fetch_opc_t opc; |
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74 | unsigned const_idx; |
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75 | /* texture fetch specific: */ |
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76 | bool is_cube : 1; |
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77 | /* vertex fetch specific: */ |
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78 | unsigned const_idx_sel; |
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79 | enum a2xx_sq_surfaceformat fmt; |
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80 | bool is_signed : 1; |
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81 | bool is_normalized : 1; |
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82 | uint32_t stride; |
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83 | uint32_t offset; |
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84 | } fetch; |
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85 | /* ALU specific: */ |
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86 | struct { |
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87 | instr_vector_opc_t vector_opc; |
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88 | instr_scalar_opc_t scalar_opc; |
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89 | bool vector_clamp : 1; |
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90 | bool scalar_clamp : 1; |
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91 | } alu; |
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92 | }; |
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93 | }; |
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94 | |||
95 | struct ir2_cf { |
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96 | struct ir2_shader *shader; |
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97 | instr_cf_opc_t cf_type; |
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98 | |||
99 | union { |
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100 | /* EXEC/EXEC_END specific: */ |
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101 | struct { |
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102 | unsigned instrs_count; |
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103 | struct ir2_instruction *instrs[6]; |
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104 | uint32_t addr, cnt, sequence; |
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105 | } exec; |
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106 | /* ALLOC specific: */ |
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107 | struct { |
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108 | instr_alloc_type_t type; /* SQ_POSITION or SQ_PARAMETER_PIXEL */ |
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109 | int size; |
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110 | } alloc; |
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111 | }; |
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112 | }; |
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113 | |||
114 | struct ir2_shader { |
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115 | unsigned cfs_count; |
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116 | struct ir2_cf *cfs[0x56]; |
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117 | uint32_t heap[100 * 4096]; |
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118 | unsigned heap_idx; |
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119 | |||
120 | enum ir2_pred pred; /* pred inherited by newly created instrs */ |
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121 | }; |
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122 | |||
123 | struct ir2_shader * ir2_shader_create(void); |
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124 | void ir2_shader_destroy(struct ir2_shader *shader); |
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125 | void * ir2_shader_assemble(struct ir2_shader *shader, |
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126 | struct ir2_shader_info *info); |
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127 | |||
128 | struct ir2_cf * ir2_cf_create(struct ir2_shader *shader, instr_cf_opc_t cf_type); |
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129 | |||
130 | struct ir2_instruction * ir2_instr_create(struct ir2_cf *cf, int instr_type); |
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131 | |||
132 | struct ir2_register * ir2_reg_create(struct ir2_instruction *instr, |
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133 | int num, const char *swizzle, int flags); |
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134 | |||
135 | /* some helper fxns: */ |
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136 | |||
137 | static inline struct ir2_cf * |
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138 | ir2_cf_create_alloc(struct ir2_shader *shader, instr_alloc_type_t type, int size) |
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139 | { |
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140 | struct ir2_cf *cf = ir2_cf_create(shader, ALLOC); |
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141 | if (!cf) |
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142 | return cf; |
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143 | cf->alloc.type = type; |
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144 | cf->alloc.size = size; |
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145 | return cf; |
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146 | } |
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147 | static inline struct ir2_instruction * |
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148 | ir2_instr_create_alu(struct ir2_cf *cf, instr_vector_opc_t vop, instr_scalar_opc_t sop) |
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149 | { |
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150 | struct ir2_instruction *instr = ir2_instr_create(cf, IR2_ALU); |
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151 | if (!instr) |
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152 | return instr; |
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153 | instr->alu.vector_opc = vop; |
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154 | instr->alu.scalar_opc = sop; |
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155 | return instr; |
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156 | } |
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157 | static inline struct ir2_instruction * |
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158 | ir2_instr_create_vtx_fetch(struct ir2_cf *cf, int ci, int cis, |
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159 | enum a2xx_sq_surfaceformat fmt, bool is_signed, int stride) |
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160 | { |
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161 | struct ir2_instruction *instr = instr = ir2_instr_create(cf, IR2_FETCH); |
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162 | instr->fetch.opc = VTX_FETCH; |
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163 | instr->fetch.const_idx = ci; |
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164 | instr->fetch.const_idx_sel = cis; |
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165 | instr->fetch.fmt = fmt; |
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166 | instr->fetch.is_signed = is_signed; |
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167 | instr->fetch.stride = stride; |
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168 | return instr; |
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169 | } |
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170 | static inline struct ir2_instruction * |
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171 | ir2_instr_create_tex_fetch(struct ir2_cf *cf, int ci) |
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172 | { |
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173 | struct ir2_instruction *instr = instr = ir2_instr_create(cf, IR2_FETCH); |
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174 | instr->fetch.opc = TEX_FETCH; |
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175 | instr->fetch.const_idx = ci; |
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176 | return instr; |
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177 | } |
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178 | |||
179 | |||
180 | #endif /* IR2_H_ */ |