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5564 | serge | 1 | /* |
2 | Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. |
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3 | |||
4 | The Weather Channel (TM) funded Tungsten Graphics to develop the |
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5 | initial release of the Radeon 8500 driver under the XFree86 license. |
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6 | This notice must be preserved. |
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7 | |||
8 | Permission is hereby granted, free of charge, to any person obtaining |
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9 | a copy of this software and associated documentation files (the |
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10 | "Software"), to deal in the Software without restriction, including |
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11 | without limitation the rights to use, copy, modify, merge, publish, |
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12 | distribute, sublicense, and/or sell copies of the Software, and to |
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13 | permit persons to whom the Software is furnished to do so, subject to |
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14 | the following conditions: |
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15 | |||
16 | The above copyright notice and this permission notice (including the |
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17 | next paragraph) shall be included in all copies or substantial |
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18 | portions of the Software. |
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19 | |||
20 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
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21 | EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
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22 | MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
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23 | IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE |
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24 | LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION |
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25 | OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION |
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26 | WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
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27 | |||
28 | **************************************************************************/ |
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29 | |||
30 | /* |
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31 | * Authors: |
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32 | * Keith Whitwell |
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33 | */ |
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34 | |||
35 | #ifndef __R200_IOCTL_H__ |
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36 | #define __R200_IOCTL_H__ |
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37 | |||
38 | #include "util/simple_list.h" |
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39 | |||
40 | #include "radeon_bo_gem.h" |
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41 | #include "radeon_cs_gem.h" |
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42 | |||
43 | #include "xf86drm.h" |
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44 | #include "drm.h" |
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45 | #include "radeon_drm.h" |
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46 | |||
47 | extern void r200EmitMaxVtxIndex(r200ContextPtr rmesa, int count); |
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48 | extern void r200EmitVertexAOS( r200ContextPtr rmesa, |
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49 | GLuint vertex_size, |
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50 | struct radeon_bo *bo, |
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51 | GLuint offset ); |
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52 | |||
53 | extern void r200EmitVbufPrim( r200ContextPtr rmesa, |
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54 | GLuint primitive, |
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55 | GLuint vertex_nr ); |
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56 | |||
57 | extern void r200FlushElts(struct gl_context *ctx); |
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58 | |||
59 | extern GLushort *r200AllocEltsOpenEnded( r200ContextPtr rmesa, |
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60 | GLuint primitive, |
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61 | GLuint min_nr ); |
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62 | |||
63 | extern void r200EmitAOS(r200ContextPtr rmesa, GLuint nr, GLuint offset); |
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64 | |||
65 | extern void r200InitIoctlFuncs( struct dd_function_table *functions ); |
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66 | |||
67 | void r200SetUpAtomList( r200ContextPtr rmesa ); |
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68 | |||
69 | /* ================================================================ |
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70 | * Helper macros: |
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71 | */ |
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72 | |||
73 | /* Close off the last primitive, if it exists. |
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74 | */ |
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75 | #define R200_NEWPRIM( rmesa ) \ |
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76 | do { \ |
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77 | if ( rmesa->radeon.dma.flush ) \ |
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78 | rmesa->radeon.dma.flush( &rmesa->radeon.glCtx ); \ |
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79 | } while (0) |
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80 | |||
81 | /* Can accommodate several state changes and primitive changes without |
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82 | * actually firing the buffer. |
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83 | */ |
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84 | #define R200_STATECHANGE( rmesa, ATOM ) \ |
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85 | do { \ |
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86 | R200_NEWPRIM( rmesa ); \ |
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87 | rmesa->hw.ATOM.dirty = GL_TRUE; \ |
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88 | rmesa->radeon.hw.is_dirty = GL_TRUE; \ |
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89 | } while (0) |
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90 | |||
91 | #define R200_SET_STATE( rmesa, ATOM, index, newvalue ) \ |
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92 | do { \ |
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93 | uint32_t __index = (index); \ |
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94 | uint32_t __dword = (newvalue); \ |
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95 | if (__dword != (rmesa)->hw.ATOM.cmd[__index]) { \ |
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96 | R200_STATECHANGE( (rmesa), ATOM ); \ |
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97 | (rmesa)->hw.ATOM.cmd[__index] = __dword; \ |
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98 | } \ |
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99 | } while(0) |
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100 | |||
101 | #define R200_DB_STATE( ATOM ) \ |
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102 | memcpy( rmesa->hw.ATOM.lastcmd, rmesa->hw.ATOM.cmd, \ |
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103 | rmesa->hw.ATOM.cmd_size * 4) |
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104 | |||
105 | static inline int R200_DB_STATECHANGE( |
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106 | r200ContextPtr rmesa, |
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107 | struct radeon_state_atom *atom ) |
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108 | { |
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109 | if (memcmp(atom->cmd, atom->lastcmd, atom->cmd_size*4)) { |
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110 | GLuint *tmp; |
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111 | R200_NEWPRIM( rmesa ); |
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112 | atom->dirty = GL_TRUE; |
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113 | rmesa->radeon.hw.is_dirty = GL_TRUE; |
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114 | tmp = atom->cmd; |
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115 | atom->cmd = atom->lastcmd; |
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116 | atom->lastcmd = tmp; |
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117 | return 1; |
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118 | } |
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119 | else |
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120 | return 0; |
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121 | } |
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122 | |||
123 | |||
124 | /* Command lengths. Note that any time you ensure ELTS_BUFSZ or VBUF_BUFSZ |
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125 | * are available, you will also be adding an rmesa->state.max_state_size because |
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126 | * r200EmitState is called from within r200EmitVbufPrim and r200FlushElts. |
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127 | */ |
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128 | #define AOS_BUFSZ(nr) ((3 + ((nr / 2) * 3) + ((nr & 1) * 2) + nr*2)) |
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129 | #define VERT_AOS_BUFSZ (5) |
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130 | #define ELTS_BUFSZ(nr) (12 + nr * 2) |
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131 | #define VBUF_BUFSZ (3) |
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132 | #define SCISSOR_BUFSZ (8) |
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133 | #define INDEX_BUFSZ (8+2) |
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134 | |||
135 | static inline uint32_t cmdpacket3(int cmd_type) |
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136 | { |
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137 | drm_radeon_cmd_header_t cmd; |
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138 | |||
139 | cmd.i = 0; |
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140 | cmd.header.cmd_type = cmd_type; |
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141 | |||
142 | return (uint32_t)cmd.i; |
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143 | |||
144 | } |
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145 | |||
146 | #define OUT_BATCH_PACKET3(packet, num_extra) do { \ |
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147 | OUT_BATCH(CP_PACKET2); \ |
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148 | OUT_BATCH(CP_PACKET3((packet), (num_extra))); \ |
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149 | } while(0) |
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150 | |||
151 | #define OUT_BATCH_PACKET3_CLIP(packet, num_extra) do { \ |
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152 | OUT_BATCH(CP_PACKET2); \ |
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153 | OUT_BATCH(CP_PACKET3((packet), (num_extra))); \ |
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154 | } while(0) |
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155 | |||
156 | |||
157 | #endif /* __R200_IOCTL_H__ */ |