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| Rev | Author | Line No. | Line |
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| 5564 | serge | 1 | /* |
| 2 | * Copyright © 2014 Broadcom |
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| 3 | * |
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| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 5 | * copy of this software and associated documentation files (the "Software"), |
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| 6 | * to deal in the Software without restriction, including without limitation |
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| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 9 | * Software is furnished to do so, subject to the following conditions: |
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| 10 | * |
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| 11 | * The above copyright notice and this permission notice (including the next |
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| 12 | * paragraph) shall be included in all copies or substantial portions of the |
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| 13 | * Software. |
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| 14 | * |
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| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
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| 21 | * IN THE SOFTWARE. |
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| 22 | */ |
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| 23 | |||
| 24 | #ifndef VC4_QPU_H |
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| 25 | #define VC4_QPU_H |
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| 26 | |||
| 27 | #include |
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| 28 | |||
| 29 | #include "util/u_math.h" |
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| 30 | |||
| 31 | #include "vc4_qpu_defines.h" |
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| 32 | |||
| 33 | struct vc4_compile; |
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| 34 | |||
| 35 | struct qpu_reg { |
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| 36 | enum qpu_mux mux; |
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| 37 | uint8_t addr; |
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| 38 | }; |
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| 39 | |||
| 40 | static inline struct qpu_reg |
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| 41 | qpu_rn(int n) |
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| 42 | { |
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| 43 | struct qpu_reg r = { |
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| 44 | QPU_MUX_R0 + n, |
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| 45 | 0, |
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| 46 | }; |
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| 47 | |||
| 48 | return r; |
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| 49 | } |
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| 50 | |||
| 51 | static inline struct qpu_reg |
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| 52 | qpu_ra(int addr) |
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| 53 | { |
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| 54 | struct qpu_reg r = { |
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| 55 | QPU_MUX_A, |
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| 56 | addr, |
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| 57 | }; |
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| 58 | |||
| 59 | return r; |
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| 60 | } |
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| 61 | |||
| 62 | static inline struct qpu_reg |
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| 63 | qpu_rb(int addr) |
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| 64 | { |
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| 65 | struct qpu_reg r = { |
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| 66 | QPU_MUX_B, |
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| 67 | addr, |
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| 68 | }; |
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| 69 | |||
| 70 | return r; |
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| 71 | } |
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| 72 | |||
| 73 | static inline struct qpu_reg |
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| 74 | qpu_vary() |
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| 75 | { |
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| 76 | struct qpu_reg r = { |
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| 77 | QPU_MUX_A, |
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| 78 | QPU_R_VARY, |
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| 79 | }; |
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| 80 | |||
| 81 | return r; |
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| 82 | } |
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| 83 | |||
| 84 | static inline struct qpu_reg |
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| 85 | qpu_unif() |
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| 86 | { |
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| 87 | struct qpu_reg r = { |
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| 88 | QPU_MUX_A, |
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| 89 | QPU_R_UNIF, |
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| 90 | }; |
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| 91 | |||
| 92 | return r; |
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| 93 | } |
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| 94 | |||
| 95 | static inline struct qpu_reg |
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| 96 | qpu_vrsetup() |
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| 97 | { |
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| 98 | return qpu_ra(QPU_W_VPMVCD_SETUP); |
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| 99 | } |
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| 100 | |||
| 101 | static inline struct qpu_reg |
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| 102 | qpu_vwsetup() |
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| 103 | { |
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| 104 | return qpu_rb(QPU_W_VPMVCD_SETUP); |
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| 105 | } |
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| 106 | |||
| 107 | static inline struct qpu_reg |
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| 108 | qpu_tlbc() |
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| 109 | { |
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| 110 | struct qpu_reg r = { |
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| 111 | QPU_MUX_A, |
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| 112 | QPU_W_TLB_COLOR_ALL, |
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| 113 | }; |
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| 114 | |||
| 115 | return r; |
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| 116 | } |
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| 117 | |||
| 118 | static inline struct qpu_reg qpu_r0(void) { return qpu_rn(0); } |
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| 119 | static inline struct qpu_reg qpu_r1(void) { return qpu_rn(1); } |
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| 120 | static inline struct qpu_reg qpu_r2(void) { return qpu_rn(2); } |
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| 121 | static inline struct qpu_reg qpu_r3(void) { return qpu_rn(3); } |
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| 122 | static inline struct qpu_reg qpu_r4(void) { return qpu_rn(4); } |
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| 123 | static inline struct qpu_reg qpu_r5(void) { return qpu_rn(5); } |
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| 124 | |||
| 125 | uint64_t qpu_NOP(void); |
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| 126 | uint64_t qpu_a_MOV(struct qpu_reg dst, struct qpu_reg src); |
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| 127 | uint64_t qpu_m_MOV(struct qpu_reg dst, struct qpu_reg src); |
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| 128 | uint64_t qpu_a_alu2(enum qpu_op_add op, struct qpu_reg dst, |
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| 129 | struct qpu_reg src0, struct qpu_reg src1); |
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| 130 | uint64_t qpu_m_alu2(enum qpu_op_mul op, struct qpu_reg dst, |
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| 131 | struct qpu_reg src0, struct qpu_reg src1); |
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| 132 | uint64_t qpu_merge_inst(uint64_t a, uint64_t b); |
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| 133 | uint64_t qpu_load_imm_ui(struct qpu_reg dst, uint32_t val); |
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| 134 | uint64_t qpu_set_sig(uint64_t inst, uint32_t sig); |
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| 135 | uint64_t qpu_set_cond_add(uint64_t inst, uint32_t cond); |
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| 136 | uint64_t qpu_set_cond_mul(uint64_t inst, uint32_t cond); |
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| 137 | uint32_t qpu_encode_small_immediate(uint32_t i); |
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| 138 | |||
| 139 | bool qpu_waddr_is_tlb(uint32_t waddr); |
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| 140 | bool qpu_inst_is_tlb(uint64_t inst); |
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| 141 | int qpu_num_sf_accesses(uint64_t inst); |
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| 142 | void qpu_serialize_one_inst(struct vc4_compile *c, uint64_t inst); |
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| 143 | |||
| 144 | static inline uint64_t |
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| 145 | qpu_load_imm_f(struct qpu_reg dst, float val) |
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| 146 | { |
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| 147 | return qpu_load_imm_ui(dst, fui(val)); |
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| 148 | } |
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| 149 | |||
| 150 | #define A_ALU2(op) \ |
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| 151 | static inline uint64_t \ |
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| 152 | qpu_a_##op(struct qpu_reg dst, struct qpu_reg src0, struct qpu_reg src1) \ |
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| 153 | { \ |
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| 154 | return qpu_a_alu2(QPU_A_##op, dst, src0, src1); \ |
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| 155 | } |
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| 156 | |||
| 157 | #define M_ALU2(op) \ |
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| 158 | static inline uint64_t \ |
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| 159 | qpu_m_##op(struct qpu_reg dst, struct qpu_reg src0, struct qpu_reg src1) \ |
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| 160 | { \ |
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| 161 | return qpu_m_alu2(QPU_M_##op, dst, src0, src1); \ |
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| 162 | } |
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| 163 | |||
| 164 | #define A_ALU1(op) \ |
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| 165 | static inline uint64_t \ |
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| 166 | qpu_a_##op(struct qpu_reg dst, struct qpu_reg src0) \ |
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| 167 | { \ |
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| 168 | return qpu_a_alu2(QPU_A_##op, dst, src0, src0); \ |
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| 169 | } |
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| 170 | |||
| 171 | /*A_ALU2(NOP) */ |
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| 172 | A_ALU2(FADD) |
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| 173 | A_ALU2(FSUB) |
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| 174 | A_ALU2(FMIN) |
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| 175 | A_ALU2(FMAX) |
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| 176 | A_ALU2(FMINABS) |
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| 177 | A_ALU2(FMAXABS) |
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| 178 | A_ALU1(FTOI) |
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| 179 | A_ALU1(ITOF) |
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| 180 | A_ALU2(ADD) |
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| 181 | A_ALU2(SUB) |
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| 182 | A_ALU2(SHR) |
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| 183 | A_ALU2(ASR) |
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| 184 | A_ALU2(ROR) |
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| 185 | A_ALU2(SHL) |
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| 186 | A_ALU2(MIN) |
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| 187 | A_ALU2(MAX) |
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| 188 | A_ALU2(AND) |
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| 189 | A_ALU2(OR) |
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| 190 | A_ALU2(XOR) |
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| 191 | A_ALU1(NOT) |
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| 192 | A_ALU1(CLZ) |
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| 193 | A_ALU2(V8ADDS) |
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| 194 | A_ALU2(V8SUBS) |
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| 195 | |||
| 196 | /* M_ALU2(NOP) */ |
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| 197 | M_ALU2(FMUL) |
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| 198 | M_ALU2(MUL24) |
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| 199 | M_ALU2(V8MULD) |
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| 200 | M_ALU2(V8MIN) |
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| 201 | M_ALU2(V8MAX) |
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| 202 | M_ALU2(V8ADDS) |
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| 203 | M_ALU2(V8SUBS) |
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| 204 | |||
| 205 | void |
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| 206 | vc4_qpu_disasm(const uint64_t *instructions, int num_instructions); |
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| 207 | |||
| 208 | void |
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| 209 | vc4_qpu_validate(uint64_t *insts, uint32_t num_inst); |
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| 210 | |||
| 211 | #endif /* VC4_QPU_H */ |