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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 5564 | serge | 1 | /* |
| 2 | * Copyright © 2014 Broadcom |
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| 3 | * |
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| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 5 | * copy of this software and associated documentation files (the "Software"), |
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| 6 | * to deal in the Software without restriction, including without limitation |
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| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 9 | * Software is furnished to do so, subject to the following conditions: |
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| 10 | * |
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| 11 | * The above copyright notice and this permission notice (including the next |
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| 12 | * paragraph) shall be included in all copies or substantial portions of the |
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| 13 | * Software. |
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| 14 | * |
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| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
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| 21 | * IN THE SOFTWARE. |
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| 22 | */ |
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| 23 | |||
| 24 | /** |
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| 25 | * Command list validator for VC4. |
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| 26 | * |
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| 27 | * The VC4 has no IOMMU between it and system memory. So, a user with |
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| 28 | * access to execute command lists could escalate privilege by |
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| 29 | * overwriting system memory (drawing to it as a framebuffer) or |
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| 30 | * reading system memory it shouldn't (reading it as a texture, or |
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| 31 | * uniform data, or vertex data). |
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| 32 | * |
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| 33 | * This validates command lists to ensure that all accesses are within |
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| 34 | * the bounds of the GEM objects referenced. It explicitly whitelists |
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| 35 | * packets, and looks at the offsets in any address fields to make |
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| 36 | * sure they're constrained within the BOs they reference. |
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| 37 | * |
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| 38 | * Note that because of the validation that's happening anyway, this |
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| 39 | * is where GEM relocation processing happens. |
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| 40 | */ |
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| 41 | |||
| 42 | #include "vc4_drv.h" |
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| 43 | #include "vc4_packet.h" |
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| 44 | |||
| 45 | #define VALIDATE_ARGS \ |
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| 46 | struct vc4_exec_info *exec, \ |
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| 47 | void *validated, \ |
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| 48 | void *untrusted |
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| 49 | |||
| 50 | |||
| 51 | /** Return the width in pixels of a 64-byte microtile. */ |
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| 52 | static uint32_t |
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| 53 | utile_width(int cpp) |
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| 54 | { |
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| 55 | switch (cpp) { |
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| 56 | case 1: |
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| 57 | case 2: |
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| 58 | return 8; |
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| 59 | case 4: |
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| 60 | return 4; |
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| 61 | case 8: |
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| 62 | return 2; |
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| 63 | default: |
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| 64 | DRM_ERROR("unknown cpp: %d\n", cpp); |
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| 65 | return 1; |
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| 66 | } |
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| 67 | } |
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| 68 | |||
| 69 | /** Return the height in pixels of a 64-byte microtile. */ |
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| 70 | static uint32_t |
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| 71 | utile_height(int cpp) |
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| 72 | { |
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| 73 | switch (cpp) { |
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| 74 | case 1: |
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| 75 | return 8; |
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| 76 | case 2: |
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| 77 | case 4: |
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| 78 | case 8: |
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| 79 | return 4; |
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| 80 | default: |
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| 81 | DRM_ERROR("unknown cpp: %d\n", cpp); |
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| 82 | return 1; |
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| 83 | } |
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| 84 | } |
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| 85 | |||
| 86 | /** |
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| 87 | * The texture unit decides what tiling format a particular miplevel is using |
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| 88 | * this function, so we lay out our miptrees accordingly. |
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| 89 | */ |
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| 90 | static bool |
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| 91 | size_is_lt(uint32_t width, uint32_t height, int cpp) |
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| 92 | { |
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| 93 | return (width <= 4 * utile_width(cpp) || |
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| 94 | height <= 4 * utile_height(cpp)); |
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| 95 | } |
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| 96 | |||
| 97 | static bool |
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| 98 | vc4_use_bo(struct vc4_exec_info *exec, |
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| 99 | uint32_t hindex, |
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| 100 | enum vc4_bo_mode mode, |
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| 101 | struct drm_gem_cma_object **obj) |
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| 102 | { |
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| 103 | *obj = NULL; |
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| 104 | |||
| 105 | if (hindex >= exec->bo_count) { |
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| 106 | DRM_ERROR("BO index %d greater than BO count %d\n", |
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| 107 | hindex, exec->bo_count); |
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| 108 | return false; |
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| 109 | } |
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| 110 | |||
| 111 | if (exec->bo[hindex].mode != mode) { |
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| 112 | if (exec->bo[hindex].mode == VC4_MODE_UNDECIDED) { |
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| 113 | exec->bo[hindex].mode = mode; |
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| 114 | } else { |
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| 115 | DRM_ERROR("BO index %d reused with mode %d vs %d\n", |
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| 116 | hindex, exec->bo[hindex].mode, mode); |
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| 117 | return false; |
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| 118 | } |
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| 119 | } |
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| 120 | |||
| 121 | *obj = exec->bo[hindex].bo; |
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| 122 | return true; |
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| 123 | } |
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| 124 | |||
| 125 | static bool |
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| 126 | vc4_use_handle(struct vc4_exec_info *exec, |
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| 127 | uint32_t gem_handles_packet_index, |
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| 128 | enum vc4_bo_mode mode, |
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| 129 | struct drm_gem_cma_object **obj) |
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| 130 | { |
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| 131 | return vc4_use_bo(exec, exec->bo_index[gem_handles_packet_index], |
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| 132 | mode, obj); |
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| 133 | } |
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| 134 | |||
| 135 | static uint32_t |
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| 136 | gl_shader_rec_size(uint32_t pointer_bits) |
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| 137 | { |
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| 138 | uint32_t attribute_count = pointer_bits & 7; |
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| 139 | bool extended = pointer_bits & 8; |
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| 140 | |||
| 141 | if (attribute_count == 0) |
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| 142 | attribute_count = 8; |
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| 143 | |||
| 144 | if (extended) |
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| 145 | return 100 + attribute_count * 4; |
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| 146 | else |
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| 147 | return 36 + attribute_count * 8; |
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| 148 | } |
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| 149 | |||
| 150 | static bool |
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| 151 | check_tex_size(struct vc4_exec_info *exec, struct drm_gem_cma_object *fbo, |
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| 152 | uint32_t offset, uint8_t tiling_format, |
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| 153 | uint32_t width, uint32_t height, uint8_t cpp) |
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| 154 | { |
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| 155 | uint32_t aligned_width, aligned_height, stride, size; |
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| 156 | uint32_t utile_w = utile_width(cpp); |
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| 157 | uint32_t utile_h = utile_height(cpp); |
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| 158 | |||
| 159 | /* The values are limited by the packet/texture parameter bitfields, |
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| 160 | * so we don't need to worry as much about integer overflow. |
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| 161 | */ |
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| 162 | BUG_ON(width > 65535); |
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| 163 | BUG_ON(height > 65535); |
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| 164 | |||
| 165 | switch (tiling_format) { |
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| 166 | case VC4_TILING_FORMAT_LINEAR: |
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| 167 | aligned_width = roundup(width, utile_w); |
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| 168 | aligned_height = height; |
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| 169 | break; |
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| 170 | case VC4_TILING_FORMAT_T: |
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| 171 | aligned_width = roundup(width, utile_w * 8); |
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| 172 | aligned_height = roundup(height, utile_h * 8); |
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| 173 | break; |
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| 174 | case VC4_TILING_FORMAT_LT: |
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| 175 | aligned_width = roundup(width, utile_w); |
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| 176 | aligned_height = roundup(height, utile_h); |
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| 177 | break; |
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| 178 | default: |
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| 179 | DRM_ERROR("buffer tiling %d unsupported\n", tiling_format); |
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| 180 | return false; |
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| 181 | } |
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| 182 | |||
| 183 | stride = aligned_width * cpp; |
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| 184 | |||
| 185 | if (INT_MAX / stride < aligned_height) { |
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| 186 | DRM_ERROR("Overflow in fbo size (%dx%d -> %dx%d)\n", |
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| 187 | width, height, |
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| 188 | aligned_width, aligned_height); |
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| 189 | return false; |
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| 190 | } |
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| 191 | size = stride * aligned_height; |
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| 192 | |||
| 193 | if (size + offset < size || |
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| 194 | size + offset > fbo->base.size) { |
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| 195 | DRM_ERROR("Overflow in %dx%d (%dx%d) fbo size (%d + %d > %d)\n", |
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| 196 | width, height, |
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| 197 | aligned_width, aligned_height, |
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| 198 | size, offset, fbo->base.size); |
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| 199 | return false; |
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| 200 | } |
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| 201 | |||
| 202 | return true; |
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| 203 | } |
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| 204 | |||
| 205 | static int |
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| 206 | validate_flush_all(VALIDATE_ARGS) |
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| 207 | { |
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| 208 | if (exec->found_increment_semaphore_packet) { |
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| 209 | DRM_ERROR("VC4_PACKET_FLUSH_ALL after " |
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| 210 | "VC4_PACKET_INCREMENT_SEMAPHORE\n"); |
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| 211 | return -EINVAL; |
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| 212 | } |
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| 213 | |||
| 214 | return 0; |
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| 215 | } |
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| 216 | |||
| 217 | static int |
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| 218 | validate_start_tile_binning(VALIDATE_ARGS) |
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| 219 | { |
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| 220 | if (exec->found_start_tile_binning_packet) { |
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| 221 | DRM_ERROR("Duplicate VC4_PACKET_START_TILE_BINNING\n"); |
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| 222 | return -EINVAL; |
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| 223 | } |
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| 224 | exec->found_start_tile_binning_packet = true; |
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| 225 | |||
| 226 | if (!exec->found_tile_binning_mode_config_packet) { |
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| 227 | DRM_ERROR("missing VC4_PACKET_TILE_BINNING_MODE_CONFIG\n"); |
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| 228 | return -EINVAL; |
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| 229 | } |
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| 230 | |||
| 231 | return 0; |
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| 232 | } |
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| 233 | |||
| 234 | static int |
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| 235 | validate_increment_semaphore(VALIDATE_ARGS) |
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| 236 | { |
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| 237 | if (exec->found_increment_semaphore_packet) { |
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| 238 | DRM_ERROR("Duplicate VC4_PACKET_INCREMENT_SEMAPHORE\n"); |
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| 239 | return -EINVAL; |
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| 240 | } |
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| 241 | exec->found_increment_semaphore_packet = true; |
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| 242 | |||
| 243 | /* Once we've found the semaphore increment, there should be one FLUSH |
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| 244 | * then the end of the command list. The FLUSH actually triggers the |
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| 245 | * increment, so we only need to make sure there |
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| 246 | */ |
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| 247 | |||
| 248 | return 0; |
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| 249 | } |
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| 250 | |||
| 251 | static int |
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| 252 | validate_wait_on_semaphore(VALIDATE_ARGS) |
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| 253 | { |
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| 254 | if (exec->found_wait_on_semaphore_packet) { |
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| 255 | DRM_ERROR("Duplicate VC4_PACKET_WAIT_ON_SEMAPHORE\n"); |
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| 256 | return -EINVAL; |
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| 257 | } |
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| 258 | exec->found_wait_on_semaphore_packet = true; |
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| 259 | |||
| 260 | if (!exec->found_increment_semaphore_packet) { |
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| 261 | DRM_ERROR("VC4_PACKET_WAIT_ON_SEMAPHORE without " |
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| 262 | "VC4_PACKET_INCREMENT_SEMAPHORE\n"); |
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| 263 | return -EINVAL; |
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| 264 | } |
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| 265 | |||
| 266 | return 0; |
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| 267 | } |
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| 268 | |||
| 269 | static int |
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| 270 | validate_branch_to_sublist(VALIDATE_ARGS) |
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| 271 | { |
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| 272 | struct drm_gem_cma_object *target; |
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| 273 | uint32_t offset; |
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| 274 | |||
| 275 | if (!vc4_use_handle(exec, 0, VC4_MODE_TILE_ALLOC, &target)) |
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| 276 | return -EINVAL; |
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| 277 | |||
| 278 | if (target != exec->tile_alloc_bo) { |
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| 279 | DRM_ERROR("Jumping to BOs other than tile alloc unsupported\n"); |
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| 280 | return -EINVAL; |
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| 281 | } |
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| 282 | |||
| 283 | if (!exec->found_wait_on_semaphore_packet) { |
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| 284 | DRM_ERROR("Jumping to tile alloc before binning finished.\n"); |
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| 285 | return -EINVAL; |
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| 286 | } |
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| 287 | |||
| 288 | offset = *(uint32_t *)(untrusted + 0); |
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| 289 | if (offset % exec->tile_alloc_init_block_size || |
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| 290 | offset / exec->tile_alloc_init_block_size >= |
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| 291 | exec->bin_tiles_x * exec->bin_tiles_y) { |
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| 292 | DRM_ERROR("VC4_PACKET_BRANCH_TO_SUB_LIST must jump to initial " |
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| 293 | "tile allocation space.\n"); |
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| 294 | return -EINVAL; |
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| 295 | } |
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| 296 | |||
| 297 | *(uint32_t *)(validated + 0) = target->paddr + offset; |
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| 298 | |||
| 299 | return 0; |
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| 300 | } |
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| 301 | |||
| 302 | /** |
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| 303 | * validate_loadstore_tile_buffer_general() - Validation for |
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| 304 | * VC4_PACKET_LOAD_TILE_BUFFER_GENERAL and |
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| 305 | * VC4_PACKET_STORE_TILE_BUFFER_GENERAL. |
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| 306 | * |
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| 307 | * The two packets are nearly the same, except for the TLB-clearing management |
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| 308 | * bits not being present for loads. Additionally, while stores are executed |
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| 309 | * immediately (using the current tile coordinates), loads are queued to be |
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| 310 | * executed when the tile coordinates packet occurs. |
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| 311 | * |
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| 312 | * Note that coordinates packets are validated to be within the declared |
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| 313 | * bin_x/y, which themselves are verified to match the rendering-configuration |
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| 314 | * FB width and height (which the hardware uses to clip loads and stores). |
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| 315 | */ |
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| 316 | static int |
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| 317 | validate_loadstore_tile_buffer_general(VALIDATE_ARGS) |
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| 318 | { |
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| 319 | uint32_t packet_b0 = *(uint8_t *)(untrusted + 0); |
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| 320 | uint32_t packet_b1 = *(uint8_t *)(untrusted + 1); |
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| 321 | struct drm_gem_cma_object *fbo; |
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| 322 | uint32_t buffer_type = packet_b0 & 0xf; |
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| 323 | uint32_t untrusted_address, offset, cpp; |
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| 324 | |||
| 325 | switch (buffer_type) { |
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| 326 | case VC4_LOADSTORE_TILE_BUFFER_NONE: |
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| 327 | return 0; |
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| 328 | case VC4_LOADSTORE_TILE_BUFFER_COLOR: |
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| 329 | if ((packet_b1 & VC4_LOADSTORE_TILE_BUFFER_MASK) == |
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| 330 | VC4_LOADSTORE_TILE_BUFFER_RGBA8888) { |
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| 331 | cpp = 4; |
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| 332 | } else { |
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| 333 | cpp = 2; |
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| 334 | } |
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| 335 | break; |
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| 336 | |||
| 337 | case VC4_LOADSTORE_TILE_BUFFER_Z: |
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| 338 | case VC4_LOADSTORE_TILE_BUFFER_ZS: |
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| 339 | cpp = 4; |
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| 340 | break; |
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| 341 | |||
| 342 | default: |
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| 343 | DRM_ERROR("Load/store type %d unsupported\n", buffer_type); |
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| 344 | return -EINVAL; |
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| 345 | } |
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| 346 | |||
| 347 | if (!vc4_use_handle(exec, 0, VC4_MODE_RENDER, &fbo)) |
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| 348 | return -EINVAL; |
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| 349 | |||
| 350 | untrusted_address = *(uint32_t *)(untrusted + 2); |
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| 351 | offset = untrusted_address & ~0xf; |
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| 352 | |||
| 353 | if (!check_tex_size(exec, fbo, offset, |
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| 354 | ((packet_b0 & |
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| 355 | VC4_LOADSTORE_TILE_BUFFER_FORMAT_MASK) >> |
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| 356 | VC4_LOADSTORE_TILE_BUFFER_FORMAT_SHIFT), |
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| 357 | exec->fb_width, exec->fb_height, cpp)) { |
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| 358 | return -EINVAL; |
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| 359 | } |
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| 360 | |||
| 361 | *(uint32_t *)(validated + 2) = (offset + fbo->paddr + |
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| 362 | (untrusted_address & 0xf)); |
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| 363 | |||
| 364 | return 0; |
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| 365 | } |
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| 366 | |||
| 367 | static int |
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| 368 | validate_indexed_prim_list(VALIDATE_ARGS) |
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| 369 | { |
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| 370 | struct drm_gem_cma_object *ib; |
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| 371 | uint32_t length = *(uint32_t *)(untrusted + 1); |
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| 372 | uint32_t offset = *(uint32_t *)(untrusted + 5); |
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| 373 | uint32_t max_index = *(uint32_t *)(untrusted + 9); |
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| 374 | uint32_t index_size = (*(uint8_t *)(untrusted + 0) >> 4) ? 2 : 1; |
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| 375 | struct vc4_shader_state *shader_state; |
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| 376 | |||
| 377 | if (exec->found_increment_semaphore_packet) { |
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| 378 | DRM_ERROR("Drawing after VC4_PACKET_INCREMENT_SEMAPHORE\n"); |
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| 379 | return -EINVAL; |
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| 380 | } |
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| 381 | |||
| 382 | /* Check overflow condition */ |
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| 383 | if (exec->shader_state_count == 0) { |
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| 384 | DRM_ERROR("shader state must precede primitives\n"); |
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| 385 | return -EINVAL; |
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| 386 | } |
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| 387 | shader_state = &exec->shader_state[exec->shader_state_count - 1]; |
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| 388 | |||
| 389 | if (max_index > shader_state->max_index) |
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| 390 | shader_state->max_index = max_index; |
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| 391 | |||
| 392 | if (!vc4_use_handle(exec, 0, VC4_MODE_RENDER, &ib)) |
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| 393 | return -EINVAL; |
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| 394 | |||
| 395 | if (offset > ib->base.size || |
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| 396 | (ib->base.size - offset) / index_size < length) { |
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| 397 | DRM_ERROR("IB access overflow (%d + %d*%d > %d)\n", |
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| 398 | offset, length, index_size, ib->base.size); |
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| 399 | return -EINVAL; |
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| 400 | } |
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| 401 | |||
| 402 | *(uint32_t *)(validated + 5) = ib->paddr + offset; |
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| 403 | |||
| 404 | return 0; |
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| 405 | } |
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| 406 | |||
| 407 | static int |
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| 408 | validate_gl_array_primitive(VALIDATE_ARGS) |
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| 409 | { |
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| 410 | uint32_t length = *(uint32_t *)(untrusted + 1); |
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| 411 | uint32_t base_index = *(uint32_t *)(untrusted + 5); |
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| 412 | uint32_t max_index; |
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| 413 | struct vc4_shader_state *shader_state; |
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| 414 | |||
| 415 | if (exec->found_increment_semaphore_packet) { |
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| 416 | DRM_ERROR("Drawing after VC4_PACKET_INCREMENT_SEMAPHORE\n"); |
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| 417 | return -EINVAL; |
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| 418 | } |
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| 419 | |||
| 420 | /* Check overflow condition */ |
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| 421 | if (exec->shader_state_count == 0) { |
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| 422 | DRM_ERROR("shader state must precede primitives\n"); |
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| 423 | return -EINVAL; |
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| 424 | } |
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| 425 | shader_state = &exec->shader_state[exec->shader_state_count - 1]; |
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| 426 | |||
| 427 | if (length + base_index < length) { |
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| 428 | DRM_ERROR("primitive vertex count overflow\n"); |
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| 429 | return -EINVAL; |
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| 430 | } |
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| 431 | max_index = length + base_index - 1; |
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| 432 | |||
| 433 | if (max_index > shader_state->max_index) |
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| 434 | shader_state->max_index = max_index; |
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| 435 | |||
| 436 | return 0; |
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| 437 | } |
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| 438 | |||
| 439 | static int |
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| 440 | validate_gl_shader_state(VALIDATE_ARGS) |
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| 441 | { |
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| 442 | uint32_t i = exec->shader_state_count++; |
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| 443 | |||
| 444 | if (i >= exec->shader_state_size) { |
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| 445 | DRM_ERROR("More requests for shader states than declared\n"); |
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| 446 | return -EINVAL; |
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| 447 | } |
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| 448 | |||
| 449 | exec->shader_state[i].packet = VC4_PACKET_GL_SHADER_STATE; |
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| 450 | exec->shader_state[i].addr = *(uint32_t *)untrusted; |
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| 451 | exec->shader_state[i].max_index = 0; |
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| 452 | |||
| 453 | if (exec->shader_state[i].addr & ~0xf) { |
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| 454 | DRM_ERROR("high bits set in GL shader rec reference\n"); |
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| 455 | return -EINVAL; |
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| 456 | } |
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| 457 | |||
| 458 | *(uint32_t *)validated = (exec->shader_rec_p + |
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| 459 | exec->shader_state[i].addr); |
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| 460 | |||
| 461 | exec->shader_rec_p += |
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| 462 | roundup(gl_shader_rec_size(exec->shader_state[i].addr), 16); |
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| 463 | |||
| 464 | return 0; |
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| 465 | } |
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| 466 | |||
| 467 | static int |
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| 468 | validate_nv_shader_state(VALIDATE_ARGS) |
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| 469 | { |
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| 470 | uint32_t i = exec->shader_state_count++; |
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| 471 | |||
| 472 | if (i >= exec->shader_state_size) { |
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| 473 | DRM_ERROR("More requests for shader states than declared\n"); |
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| 474 | return -EINVAL; |
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| 475 | } |
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| 476 | |||
| 477 | exec->shader_state[i].packet = VC4_PACKET_NV_SHADER_STATE; |
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| 478 | exec->shader_state[i].addr = *(uint32_t *)untrusted; |
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| 479 | |||
| 480 | if (exec->shader_state[i].addr & 15) { |
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| 481 | DRM_ERROR("NV shader state address 0x%08x misaligned\n", |
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| 482 | exec->shader_state[i].addr); |
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| 483 | return -EINVAL; |
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| 484 | } |
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| 485 | |||
| 486 | *(uint32_t *)validated = (exec->shader_state[i].addr + |
||
| 487 | exec->shader_rec_p); |
||
| 488 | |||
| 489 | return 0; |
||
| 490 | } |
||
| 491 | |||
| 492 | static int |
||
| 493 | validate_tile_binning_config(VALIDATE_ARGS) |
||
| 494 | { |
||
| 495 | struct drm_gem_cma_object *tile_allocation; |
||
| 496 | struct drm_gem_cma_object *tile_state_data_array; |
||
| 497 | uint8_t flags; |
||
| 498 | uint32_t tile_allocation_size; |
||
| 499 | |||
| 500 | if (!vc4_use_handle(exec, 0, VC4_MODE_TILE_ALLOC, &tile_allocation) || |
||
| 501 | !vc4_use_handle(exec, 1, VC4_MODE_TSDA, &tile_state_data_array)) |
||
| 502 | return -EINVAL; |
||
| 503 | |||
| 504 | if (exec->found_tile_binning_mode_config_packet) { |
||
| 505 | DRM_ERROR("Duplicate VC4_PACKET_TILE_BINNING_MODE_CONFIG\n"); |
||
| 506 | return -EINVAL; |
||
| 507 | } |
||
| 508 | exec->found_tile_binning_mode_config_packet = true; |
||
| 509 | |||
| 510 | exec->bin_tiles_x = *(uint8_t *)(untrusted + 12); |
||
| 511 | exec->bin_tiles_y = *(uint8_t *)(untrusted + 13); |
||
| 512 | flags = *(uint8_t *)(untrusted + 14); |
||
| 513 | |||
| 514 | if (exec->bin_tiles_x == 0 || |
||
| 515 | exec->bin_tiles_y == 0) { |
||
| 516 | DRM_ERROR("Tile binning config of %dx%d too small\n", |
||
| 517 | exec->bin_tiles_x, exec->bin_tiles_y); |
||
| 518 | return -EINVAL; |
||
| 519 | } |
||
| 520 | |||
| 521 | /* Our validation relies on the user not getting to set up their own |
||
| 522 | * tile state/tile allocation BO contents. |
||
| 523 | */ |
||
| 524 | if (!(flags & VC4_BIN_CONFIG_AUTO_INIT_TSDA)) { |
||
| 525 | DRM_ERROR("binning config missing " |
||
| 526 | "VC4_BIN_CONFIG_AUTO_INIT_TSDA\n"); |
||
| 527 | return -EINVAL; |
||
| 528 | } |
||
| 529 | |||
| 530 | if (flags & (VC4_BIN_CONFIG_DB_NON_MS | |
||
| 531 | VC4_BIN_CONFIG_TILE_BUFFER_64BIT | |
||
| 532 | VC4_BIN_CONFIG_MS_MODE_4X)) { |
||
| 533 | DRM_ERROR("unsupported bining config flags 0x%02x\n", flags); |
||
| 534 | return -EINVAL; |
||
| 535 | } |
||
| 536 | |||
| 537 | if (*(uint32_t *)(untrusted + 0) != 0) { |
||
| 538 | DRM_ERROR("tile allocation offset != 0 unsupported\n"); |
||
| 539 | return -EINVAL; |
||
| 540 | } |
||
| 541 | tile_allocation_size = *(uint32_t *)(untrusted + 4); |
||
| 542 | if (tile_allocation_size > tile_allocation->base.size) { |
||
| 543 | DRM_ERROR("tile allocation size %d > BO size %d\n", |
||
| 544 | tile_allocation_size, tile_allocation->base.size); |
||
| 545 | return -EINVAL; |
||
| 546 | } |
||
| 547 | *(uint32_t *)validated = tile_allocation->paddr; |
||
| 548 | exec->tile_alloc_bo = tile_allocation; |
||
| 549 | |||
| 550 | exec->tile_alloc_init_block_size = 1 << (5 + ((flags >> 5) & 3)); |
||
| 551 | if (exec->bin_tiles_x * exec->bin_tiles_y * |
||
| 552 | exec->tile_alloc_init_block_size > tile_allocation_size) { |
||
| 553 | DRM_ERROR("tile init exceeds tile alloc size (%d vs %d)\n", |
||
| 554 | exec->bin_tiles_x * exec->bin_tiles_y * |
||
| 555 | exec->tile_alloc_init_block_size, |
||
| 556 | tile_allocation_size); |
||
| 557 | return -EINVAL; |
||
| 558 | } |
||
| 559 | if (*(uint32_t *)(untrusted + 8) != 0) { |
||
| 560 | DRM_ERROR("TSDA offset != 0 unsupported\n"); |
||
| 561 | return -EINVAL; |
||
| 562 | } |
||
| 563 | if (exec->bin_tiles_x * exec->bin_tiles_y * 48 > |
||
| 564 | tile_state_data_array->base.size) { |
||
| 565 | DRM_ERROR("TSDA of %db too small for %dx%d bin config\n", |
||
| 566 | tile_state_data_array->base.size, |
||
| 567 | exec->bin_tiles_x, exec->bin_tiles_y); |
||
| 568 | } |
||
| 569 | *(uint32_t *)(validated + 8) = tile_state_data_array->paddr; |
||
| 570 | |||
| 571 | return 0; |
||
| 572 | } |
||
| 573 | |||
| 574 | static int |
||
| 575 | validate_tile_rendering_mode_config(VALIDATE_ARGS) |
||
| 576 | { |
||
| 577 | struct drm_gem_cma_object *fbo; |
||
| 578 | uint32_t flags, offset, cpp; |
||
| 579 | |||
| 580 | if (exec->found_tile_rendering_mode_config_packet) { |
||
| 581 | DRM_ERROR("Duplicate VC4_PACKET_TILE_RENDERING_MODE_CONFIG\n"); |
||
| 582 | return -EINVAL; |
||
| 583 | } |
||
| 584 | exec->found_tile_rendering_mode_config_packet = true; |
||
| 585 | |||
| 586 | if (!vc4_use_handle(exec, 0, VC4_MODE_RENDER, &fbo)) |
||
| 587 | return -EINVAL; |
||
| 588 | |||
| 589 | exec->fb_width = *(uint16_t *)(untrusted + 4); |
||
| 590 | exec->fb_height = *(uint16_t *)(untrusted + 6); |
||
| 591 | |||
| 592 | flags = *(uint16_t *)(untrusted + 8); |
||
| 593 | if ((flags & VC4_RENDER_CONFIG_FORMAT_MASK) == |
||
| 594 | VC4_RENDER_CONFIG_FORMAT_RGBA8888) { |
||
| 595 | cpp = 4; |
||
| 596 | } else { |
||
| 597 | cpp = 2; |
||
| 598 | } |
||
| 599 | |||
| 600 | offset = *(uint32_t *)untrusted; |
||
| 601 | if (!check_tex_size(exec, fbo, offset, |
||
| 602 | ((flags & |
||
| 603 | VC4_RENDER_CONFIG_MEMORY_FORMAT_MASK) >> |
||
| 604 | VC4_RENDER_CONFIG_MEMORY_FORMAT_SHIFT), |
||
| 605 | exec->fb_width, exec->fb_height, cpp)) { |
||
| 606 | return -EINVAL; |
||
| 607 | } |
||
| 608 | |||
| 609 | *(uint32_t *)validated = fbo->paddr + offset; |
||
| 610 | |||
| 611 | return 0; |
||
| 612 | } |
||
| 613 | |||
| 614 | static int |
||
| 615 | validate_tile_coordinates(VALIDATE_ARGS) |
||
| 616 | { |
||
| 617 | uint8_t tile_x = *(uint8_t *)(untrusted + 0); |
||
| 618 | uint8_t tile_y = *(uint8_t *)(untrusted + 1); |
||
| 619 | |||
| 620 | if (tile_x * 64 >= exec->fb_width || tile_y * 64 >= exec->fb_height) { |
||
| 621 | DRM_ERROR("Tile coordinates %d,%d > render config %dx%d\n", |
||
| 622 | tile_x, tile_y, exec->fb_width, exec->fb_height); |
||
| 623 | return -EINVAL; |
||
| 624 | } |
||
| 625 | |||
| 626 | return 0; |
||
| 627 | } |
||
| 628 | |||
| 629 | static int |
||
| 630 | validate_gem_handles(VALIDATE_ARGS) |
||
| 631 | { |
||
| 632 | memcpy(exec->bo_index, untrusted, sizeof(exec->bo_index)); |
||
| 633 | return 0; |
||
| 634 | } |
||
| 635 | |||
| 636 | static const struct cmd_info { |
||
| 637 | bool bin; |
||
| 638 | bool render; |
||
| 639 | uint16_t len; |
||
| 640 | const char *name; |
||
| 641 | int (*func)(struct vc4_exec_info *exec, void *validated, |
||
| 642 | void *untrusted); |
||
| 643 | } cmd_info[] = { |
||
| 644 | [VC4_PACKET_HALT] = { 1, 1, 1, "halt", NULL }, |
||
| 645 | [VC4_PACKET_NOP] = { 1, 1, 1, "nop", NULL }, |
||
| 646 | [VC4_PACKET_FLUSH] = { 1, 1, 1, "flush", NULL }, |
||
| 647 | [VC4_PACKET_FLUSH_ALL] = { 1, 0, 1, "flush all state", validate_flush_all }, |
||
| 648 | [VC4_PACKET_START_TILE_BINNING] = { 1, 0, 1, "start tile binning", validate_start_tile_binning }, |
||
| 649 | [VC4_PACKET_INCREMENT_SEMAPHORE] = { 1, 0, 1, "increment semaphore", validate_increment_semaphore }, |
||
| 650 | [VC4_PACKET_WAIT_ON_SEMAPHORE] = { 0, 1, 1, "wait on semaphore", validate_wait_on_semaphore }, |
||
| 651 | /* BRANCH_TO_SUB_LIST is actually supported in the binner as well, but |
||
| 652 | * we only use it from the render CL in order to jump into the tile |
||
| 653 | * allocation BO. |
||
| 654 | */ |
||
| 655 | [VC4_PACKET_BRANCH_TO_SUB_LIST] = { 0, 1, 5, "branch to sublist", validate_branch_to_sublist }, |
||
| 656 | [VC4_PACKET_STORE_MS_TILE_BUFFER] = { 0, 1, 1, "store MS resolved tile color buffer", NULL }, |
||
| 657 | [VC4_PACKET_STORE_MS_TILE_BUFFER_AND_EOF] = { 0, 1, 1, "store MS resolved tile color buffer and EOF", NULL }, |
||
| 658 | |||
| 659 | [VC4_PACKET_STORE_TILE_BUFFER_GENERAL] = { 0, 1, 7, "Store Tile Buffer General", validate_loadstore_tile_buffer_general }, |
||
| 660 | [VC4_PACKET_LOAD_TILE_BUFFER_GENERAL] = { 0, 1, 7, "Load Tile Buffer General", validate_loadstore_tile_buffer_general }, |
||
| 661 | |||
| 662 | [VC4_PACKET_GL_INDEXED_PRIMITIVE] = { 1, 1, 14, "Indexed Primitive List", validate_indexed_prim_list }, |
||
| 663 | |||
| 664 | [VC4_PACKET_GL_ARRAY_PRIMITIVE] = { 1, 1, 10, "Vertex Array Primitives", validate_gl_array_primitive }, |
||
| 665 | |||
| 666 | /* This is only used by clipped primitives (packets 48 and 49), which |
||
| 667 | * we don't support parsing yet. |
||
| 668 | */ |
||
| 669 | [VC4_PACKET_PRIMITIVE_LIST_FORMAT] = { 1, 1, 2, "primitive list format", NULL }, |
||
| 670 | |||
| 671 | [VC4_PACKET_GL_SHADER_STATE] = { 1, 1, 5, "GL Shader State", validate_gl_shader_state }, |
||
| 672 | [VC4_PACKET_NV_SHADER_STATE] = { 1, 1, 5, "NV Shader State", validate_nv_shader_state }, |
||
| 673 | |||
| 674 | [VC4_PACKET_CONFIGURATION_BITS] = { 1, 1, 4, "configuration bits", NULL }, |
||
| 675 | [VC4_PACKET_FLAT_SHADE_FLAGS] = { 1, 1, 5, "flat shade flags", NULL }, |
||
| 676 | [VC4_PACKET_POINT_SIZE] = { 1, 1, 5, "point size", NULL }, |
||
| 677 | [VC4_PACKET_LINE_WIDTH] = { 1, 1, 5, "line width", NULL }, |
||
| 678 | [VC4_PACKET_RHT_X_BOUNDARY] = { 1, 1, 3, "RHT X boundary", NULL }, |
||
| 679 | [VC4_PACKET_DEPTH_OFFSET] = { 1, 1, 5, "Depth Offset", NULL }, |
||
| 680 | [VC4_PACKET_CLIP_WINDOW] = { 1, 1, 9, "Clip Window", NULL }, |
||
| 681 | [VC4_PACKET_VIEWPORT_OFFSET] = { 1, 1, 5, "Viewport Offset", NULL }, |
||
| 682 | [VC4_PACKET_CLIPPER_XY_SCALING] = { 1, 1, 9, "Clipper XY Scaling", NULL }, |
||
| 683 | /* Note: The docs say this was also 105, but it was 106 in the |
||
| 684 | * initial userland code drop. |
||
| 685 | */ |
||
| 686 | [VC4_PACKET_CLIPPER_Z_SCALING] = { 1, 1, 9, "Clipper Z Scale and Offset", NULL }, |
||
| 687 | |||
| 688 | [VC4_PACKET_TILE_BINNING_MODE_CONFIG] = { 1, 0, 16, "tile binning configuration", validate_tile_binning_config }, |
||
| 689 | |||
| 690 | [VC4_PACKET_TILE_RENDERING_MODE_CONFIG] = { 0, 1, 11, "tile rendering mode configuration", validate_tile_rendering_mode_config}, |
||
| 691 | |||
| 692 | [VC4_PACKET_CLEAR_COLORS] = { 0, 1, 14, "Clear Colors", NULL }, |
||
| 693 | |||
| 694 | [VC4_PACKET_TILE_COORDINATES] = { 0, 1, 3, "Tile Coordinates", validate_tile_coordinates }, |
||
| 695 | |||
| 696 | [VC4_PACKET_GEM_HANDLES] = { 1, 1, 9, "GEM handles", validate_gem_handles }, |
||
| 697 | }; |
||
| 698 | |||
| 699 | int |
||
| 700 | vc4_validate_cl(struct drm_device *dev, |
||
| 701 | void *validated, |
||
| 702 | void *unvalidated, |
||
| 703 | uint32_t len, |
||
| 704 | bool is_bin, |
||
| 705 | bool has_bin, |
||
| 706 | struct vc4_exec_info *exec) |
||
| 707 | { |
||
| 708 | uint32_t dst_offset = 0; |
||
| 709 | uint32_t src_offset = 0; |
||
| 710 | |||
| 711 | while (src_offset < len) { |
||
| 712 | void *dst_pkt = validated + dst_offset; |
||
| 713 | void *src_pkt = unvalidated + src_offset; |
||
| 714 | u8 cmd = *(uint8_t *)src_pkt; |
||
| 715 | const struct cmd_info *info; |
||
| 716 | |||
| 717 | if (cmd > ARRAY_SIZE(cmd_info)) { |
||
| 718 | DRM_ERROR("0x%08x: packet %d out of bounds\n", |
||
| 719 | src_offset, cmd); |
||
| 720 | return -EINVAL; |
||
| 721 | } |
||
| 722 | |||
| 723 | info = &cmd_info[cmd]; |
||
| 724 | if (!info->name) { |
||
| 725 | DRM_ERROR("0x%08x: packet %d invalid\n", |
||
| 726 | src_offset, cmd); |
||
| 727 | return -EINVAL; |
||
| 728 | } |
||
| 729 | |||
| 730 | #if 0 |
||
| 731 | DRM_INFO("0x%08x: packet %d (%s) size %d processing...\n", |
||
| 732 | src_offset, cmd, info->name, info->len); |
||
| 733 | #endif |
||
| 734 | |||
| 735 | if ((is_bin && !info->bin) || |
||
| 736 | (!is_bin && !info->render)) { |
||
| 737 | DRM_ERROR("0x%08x: packet %d (%s) invalid for %s\n", |
||
| 738 | src_offset, cmd, info->name, |
||
| 739 | is_bin ? "binner" : "render"); |
||
| 740 | return -EINVAL; |
||
| 741 | } |
||
| 742 | |||
| 743 | if (src_offset + info->len > len) { |
||
| 744 | DRM_ERROR("0x%08x: packet %d (%s) length 0x%08x " |
||
| 745 | "exceeds bounds (0x%08x)\n", |
||
| 746 | src_offset, cmd, info->name, info->len, |
||
| 747 | src_offset + len); |
||
| 748 | return -EINVAL; |
||
| 749 | } |
||
| 750 | |||
| 751 | if (cmd != VC4_PACKET_GEM_HANDLES) |
||
| 752 | memcpy(dst_pkt, src_pkt, info->len); |
||
| 753 | |||
| 754 | if (info->func && info->func(exec, |
||
| 755 | dst_pkt + 1, |
||
| 756 | src_pkt + 1)) { |
||
| 757 | DRM_ERROR("0x%08x: packet %d (%s) failed to " |
||
| 758 | "validate\n", |
||
| 759 | src_offset, cmd, info->name); |
||
| 760 | return -EINVAL; |
||
| 761 | } |
||
| 762 | |||
| 763 | src_offset += info->len; |
||
| 764 | /* GEM handle loading doesn't produce HW packets. */ |
||
| 765 | if (cmd != VC4_PACKET_GEM_HANDLES) |
||
| 766 | dst_offset += info->len; |
||
| 767 | |||
| 768 | /* When the CL hits halt, it'll stop reading anything else. */ |
||
| 769 | if (cmd == VC4_PACKET_HALT) |
||
| 770 | break; |
||
| 771 | } |
||
| 772 | |||
| 773 | if (is_bin) { |
||
| 774 | exec->ct0ea = exec->ct0ca + dst_offset; |
||
| 775 | |||
| 776 | if (has_bin && !exec->found_start_tile_binning_packet) { |
||
| 777 | DRM_ERROR("Bin CL missing VC4_PACKET_START_TILE_BINNING\n"); |
||
| 778 | return -EINVAL; |
||
| 779 | } |
||
| 780 | } else { |
||
| 781 | if (!exec->found_tile_rendering_mode_config_packet) { |
||
| 782 | DRM_ERROR("Render CL missing VC4_PACKET_TILE_RENDERING_MODE_CONFIG\n"); |
||
| 783 | return -EINVAL; |
||
| 784 | } |
||
| 785 | |||
| 786 | /* Make sure that they actually consumed the semaphore |
||
| 787 | * increment from the bin CL. Otherwise a later submit would |
||
| 788 | * have render execute immediately. |
||
| 789 | */ |
||
| 790 | if (exec->found_wait_on_semaphore_packet != has_bin) { |
||
| 791 | DRM_ERROR("Render CL %s VC4_PACKET_WAIT_ON_SEMAPHORE\n", |
||
| 792 | exec->found_wait_on_semaphore_packet ? |
||
| 793 | "has" : "missing"); |
||
| 794 | return -EINVAL; |
||
| 795 | } |
||
| 796 | exec->ct1ea = exec->ct1ca + dst_offset; |
||
| 797 | } |
||
| 798 | |||
| 799 | return 0; |
||
| 800 | } |
||
| 801 | |||
| 802 | static bool |
||
| 803 | reloc_tex(struct vc4_exec_info *exec, |
||
| 804 | void *uniform_data_u, |
||
| 805 | struct vc4_texture_sample_info *sample, |
||
| 806 | uint32_t texture_handle_index) |
||
| 807 | |||
| 808 | { |
||
| 809 | struct drm_gem_cma_object *tex; |
||
| 810 | uint32_t p0 = *(uint32_t *)(uniform_data_u + sample->p_offset[0]); |
||
| 811 | uint32_t p1 = *(uint32_t *)(uniform_data_u + sample->p_offset[1]); |
||
| 812 | uint32_t p2 = (sample->p_offset[2] != ~0 ? |
||
| 813 | *(uint32_t *)(uniform_data_u + sample->p_offset[2]) : 0); |
||
| 814 | uint32_t p3 = (sample->p_offset[3] != ~0 ? |
||
| 815 | *(uint32_t *)(uniform_data_u + sample->p_offset[3]) : 0); |
||
| 816 | uint32_t *validated_p0 = exec->uniforms_v + sample->p_offset[0]; |
||
| 817 | uint32_t offset = p0 & ~0xfff; |
||
| 818 | uint32_t miplevels = (p0 & 15); |
||
| 819 | uint32_t width = (p1 >> 8) & 2047; |
||
| 820 | uint32_t height = (p1 >> 20) & 2047; |
||
| 821 | uint32_t cpp, tiling_format, utile_w, utile_h; |
||
| 822 | uint32_t i; |
||
| 823 | uint32_t cube_map_stride = 0; |
||
| 824 | enum vc4_texture_data_type type; |
||
| 825 | |||
| 826 | if (!vc4_use_bo(exec, texture_handle_index, VC4_MODE_RENDER, &tex)) |
||
| 827 | return false; |
||
| 828 | |||
| 829 | if (sample->is_direct) { |
||
| 830 | uint32_t remaining_size = tex->base.size - p0; |
||
| 831 | if (p0 > tex->base.size - 4) { |
||
| 832 | DRM_ERROR("UBO offset greater than UBO size\n"); |
||
| 833 | return false; |
||
| 834 | } |
||
| 835 | if (p1 > remaining_size - 4) { |
||
| 836 | DRM_ERROR("UBO clamp would allow reads outside of UBO\n"); |
||
| 837 | return false; |
||
| 838 | } |
||
| 839 | *validated_p0 = tex->paddr + p0; |
||
| 840 | return true; |
||
| 841 | } |
||
| 842 | |||
| 843 | if (width == 0) |
||
| 844 | width = 2048; |
||
| 845 | if (height == 0) |
||
| 846 | height = 2048; |
||
| 847 | |||
| 848 | if (p0 & (1 << 9)) { |
||
| 849 | if ((p2 & (3 << 30)) == (1 << 30)) |
||
| 850 | cube_map_stride = p2 & 0x3ffff000; |
||
| 851 | if ((p3 & (3 << 30)) == (1 << 30)) { |
||
| 852 | if (cube_map_stride) { |
||
| 853 | DRM_ERROR("Cube map stride set twice\n"); |
||
| 854 | return false; |
||
| 855 | } |
||
| 856 | |||
| 857 | cube_map_stride = p3 & 0x3ffff000; |
||
| 858 | } |
||
| 859 | if (!cube_map_stride) { |
||
| 860 | DRM_ERROR("Cube map stride not set\n"); |
||
| 861 | return false; |
||
| 862 | } |
||
| 863 | } |
||
| 864 | |||
| 865 | type = ((p0 >> 4) & 15) | ((p1 >> 31) << 4); |
||
| 866 | |||
| 867 | switch (type) { |
||
| 868 | case VC4_TEXTURE_TYPE_RGBA8888: |
||
| 869 | case VC4_TEXTURE_TYPE_RGBX8888: |
||
| 870 | case VC4_TEXTURE_TYPE_RGBA32R: |
||
| 871 | cpp = 4; |
||
| 872 | break; |
||
| 873 | case VC4_TEXTURE_TYPE_RGBA4444: |
||
| 874 | case VC4_TEXTURE_TYPE_RGBA5551: |
||
| 875 | case VC4_TEXTURE_TYPE_RGB565: |
||
| 876 | case VC4_TEXTURE_TYPE_LUMALPHA: |
||
| 877 | case VC4_TEXTURE_TYPE_S16F: |
||
| 878 | case VC4_TEXTURE_TYPE_S16: |
||
| 879 | cpp = 2; |
||
| 880 | break; |
||
| 881 | case VC4_TEXTURE_TYPE_LUMINANCE: |
||
| 882 | case VC4_TEXTURE_TYPE_ALPHA: |
||
| 883 | case VC4_TEXTURE_TYPE_S8: |
||
| 884 | cpp = 1; |
||
| 885 | break; |
||
| 886 | case VC4_TEXTURE_TYPE_ETC1: |
||
| 887 | case VC4_TEXTURE_TYPE_BW1: |
||
| 888 | case VC4_TEXTURE_TYPE_A4: |
||
| 889 | case VC4_TEXTURE_TYPE_A1: |
||
| 890 | case VC4_TEXTURE_TYPE_RGBA64: |
||
| 891 | case VC4_TEXTURE_TYPE_YUV422R: |
||
| 892 | default: |
||
| 893 | DRM_ERROR("Texture format %d unsupported\n", type); |
||
| 894 | return false; |
||
| 895 | } |
||
| 896 | utile_w = utile_width(cpp); |
||
| 897 | utile_h = utile_height(cpp); |
||
| 898 | |||
| 899 | if (type == VC4_TEXTURE_TYPE_RGBA32R) { |
||
| 900 | tiling_format = VC4_TILING_FORMAT_LINEAR; |
||
| 901 | } else { |
||
| 902 | if (size_is_lt(width, height, cpp)) |
||
| 903 | tiling_format = VC4_TILING_FORMAT_LT; |
||
| 904 | else |
||
| 905 | tiling_format = VC4_TILING_FORMAT_T; |
||
| 906 | } |
||
| 907 | |||
| 908 | if (!check_tex_size(exec, tex, offset + cube_map_stride * 5, |
||
| 909 | tiling_format, width, height, cpp)) { |
||
| 910 | return false; |
||
| 911 | } |
||
| 912 | |||
| 913 | /* The mipmap levels are stored before the base of the texture. Make |
||
| 914 | * sure there is actually space in the BO. |
||
| 915 | */ |
||
| 916 | for (i = 1; i <= miplevels; i++) { |
||
| 917 | uint32_t level_width = max(width >> i, 1u); |
||
| 918 | uint32_t level_height = max(height >> i, 1u); |
||
| 919 | uint32_t aligned_width, aligned_height; |
||
| 920 | uint32_t level_size; |
||
| 921 | |||
| 922 | /* Once the levels get small enough, they drop from T to LT. */ |
||
| 923 | if (tiling_format == VC4_TILING_FORMAT_T && |
||
| 924 | size_is_lt(level_width, level_height, cpp)) { |
||
| 925 | tiling_format = VC4_TILING_FORMAT_LT; |
||
| 926 | } |
||
| 927 | |||
| 928 | switch (tiling_format) { |
||
| 929 | case VC4_TILING_FORMAT_T: |
||
| 930 | aligned_width = roundup(level_width, utile_w * 8); |
||
| 931 | aligned_height = roundup(level_height, utile_h * 8); |
||
| 932 | break; |
||
| 933 | case VC4_TILING_FORMAT_LT: |
||
| 934 | aligned_width = roundup(level_width, utile_w); |
||
| 935 | aligned_height = roundup(level_height, utile_h); |
||
| 936 | break; |
||
| 937 | default: |
||
| 938 | aligned_width = roundup(level_width, utile_w); |
||
| 939 | aligned_height = level_height; |
||
| 940 | break; |
||
| 941 | } |
||
| 942 | |||
| 943 | level_size = aligned_width * cpp * aligned_height; |
||
| 944 | |||
| 945 | if (offset < level_size) { |
||
| 946 | DRM_ERROR("Level %d (%dx%d -> %dx%d) size %db " |
||
| 947 | "overflowed buffer bounds (offset %d)\n", |
||
| 948 | i, level_width, level_height, |
||
| 949 | aligned_width, aligned_height, |
||
| 950 | level_size, offset); |
||
| 951 | return false; |
||
| 952 | } |
||
| 953 | |||
| 954 | offset -= level_size; |
||
| 955 | } |
||
| 956 | |||
| 957 | *validated_p0 = tex->paddr + p0; |
||
| 958 | |||
| 959 | return true; |
||
| 960 | } |
||
| 961 | |||
| 962 | static int |
||
| 963 | validate_shader_rec(struct drm_device *dev, |
||
| 964 | struct vc4_exec_info *exec, |
||
| 965 | struct vc4_shader_state *state) |
||
| 966 | { |
||
| 967 | uint32_t *src_handles; |
||
| 968 | void *pkt_u, *pkt_v; |
||
| 969 | enum shader_rec_reloc_type { |
||
| 970 | RELOC_CODE, |
||
| 971 | RELOC_VBO, |
||
| 972 | }; |
||
| 973 | struct shader_rec_reloc { |
||
| 974 | enum shader_rec_reloc_type type; |
||
| 975 | uint32_t offset; |
||
| 976 | }; |
||
| 977 | static const struct shader_rec_reloc gl_relocs[] = { |
||
| 978 | { RELOC_CODE, 4 }, /* fs */ |
||
| 979 | { RELOC_CODE, 16 }, /* vs */ |
||
| 980 | { RELOC_CODE, 28 }, /* cs */ |
||
| 981 | }; |
||
| 982 | static const struct shader_rec_reloc nv_relocs[] = { |
||
| 983 | { RELOC_CODE, 4 }, /* fs */ |
||
| 984 | { RELOC_VBO, 12 } |
||
| 985 | }; |
||
| 986 | const struct shader_rec_reloc *relocs; |
||
| 987 | struct drm_gem_cma_object *bo[ARRAY_SIZE(gl_relocs) + 8]; |
||
| 988 | uint32_t nr_attributes = 0, nr_fixed_relocs, nr_relocs, packet_size; |
||
| 989 | int i; |
||
| 990 | struct vc4_validated_shader_info *validated_shader = NULL; |
||
| 991 | |||
| 992 | if (state->packet == VC4_PACKET_NV_SHADER_STATE) { |
||
| 993 | relocs = nv_relocs; |
||
| 994 | nr_fixed_relocs = ARRAY_SIZE(nv_relocs); |
||
| 995 | |||
| 996 | packet_size = 16; |
||
| 997 | } else { |
||
| 998 | relocs = gl_relocs; |
||
| 999 | nr_fixed_relocs = ARRAY_SIZE(gl_relocs); |
||
| 1000 | |||
| 1001 | nr_attributes = state->addr & 0x7; |
||
| 1002 | if (nr_attributes == 0) |
||
| 1003 | nr_attributes = 8; |
||
| 1004 | packet_size = gl_shader_rec_size(state->addr); |
||
| 1005 | } |
||
| 1006 | nr_relocs = nr_fixed_relocs + nr_attributes; |
||
| 1007 | |||
| 1008 | if (nr_relocs * 4 > exec->shader_rec_size) { |
||
| 1009 | DRM_ERROR("overflowed shader recs reading %d handles " |
||
| 1010 | "from %d bytes left\n", |
||
| 1011 | nr_relocs, exec->shader_rec_size); |
||
| 1012 | return -EINVAL; |
||
| 1013 | } |
||
| 1014 | src_handles = exec->shader_rec_u; |
||
| 1015 | exec->shader_rec_u += nr_relocs * 4; |
||
| 1016 | exec->shader_rec_size -= nr_relocs * 4; |
||
| 1017 | |||
| 1018 | if (packet_size > exec->shader_rec_size) { |
||
| 1019 | DRM_ERROR("overflowed shader recs copying %db packet " |
||
| 1020 | "from %d bytes left\n", |
||
| 1021 | packet_size, exec->shader_rec_size); |
||
| 1022 | return -EINVAL; |
||
| 1023 | } |
||
| 1024 | pkt_u = exec->shader_rec_u; |
||
| 1025 | pkt_v = exec->shader_rec_v; |
||
| 1026 | memcpy(pkt_v, pkt_u, packet_size); |
||
| 1027 | exec->shader_rec_u += packet_size; |
||
| 1028 | /* Shader recs have to be aligned to 16 bytes (due to the attribute |
||
| 1029 | * flags being in the low bytes), so round the next validated shader |
||
| 1030 | * rec address up. This should be safe, since we've got so many |
||
| 1031 | * relocations in a shader rec packet. |
||
| 1032 | */ |
||
| 1033 | BUG_ON(roundup(packet_size, 16) - packet_size > nr_relocs * 4); |
||
| 1034 | exec->shader_rec_v += roundup(packet_size, 16); |
||
| 1035 | exec->shader_rec_size -= packet_size; |
||
| 1036 | |||
| 1037 | for (i = 0; i < nr_relocs; i++) { |
||
| 1038 | enum vc4_bo_mode mode; |
||
| 1039 | |||
| 1040 | if (i < nr_fixed_relocs && relocs[i].type == RELOC_CODE) |
||
| 1041 | mode = VC4_MODE_SHADER; |
||
| 1042 | else |
||
| 1043 | mode = VC4_MODE_RENDER; |
||
| 1044 | |||
| 1045 | if (!vc4_use_bo(exec, src_handles[i], mode, &bo[i])) { |
||
| 1046 | return false; |
||
| 1047 | } |
||
| 1048 | } |
||
| 1049 | |||
| 1050 | for (i = 0; i < nr_fixed_relocs; i++) { |
||
| 1051 | uint32_t o = relocs[i].offset; |
||
| 1052 | uint32_t src_offset = *(uint32_t *)(pkt_u + o); |
||
| 1053 | uint32_t *texture_handles_u; |
||
| 1054 | void *uniform_data_u; |
||
| 1055 | uint32_t tex; |
||
| 1056 | |||
| 1057 | *(uint32_t *)(pkt_v + o) = bo[i]->paddr + src_offset; |
||
| 1058 | |||
| 1059 | switch (relocs[i].type) { |
||
| 1060 | case RELOC_CODE: |
||
| 1061 | if (src_offset != 0) { |
||
| 1062 | DRM_ERROR("Shaders must be at offset 0 of " |
||
| 1063 | "the BO.\n"); |
||
| 1064 | goto fail; |
||
| 1065 | } |
||
| 1066 | |||
| 1067 | kfree(validated_shader); |
||
| 1068 | validated_shader = vc4_validate_shader(bo[i]); |
||
| 1069 | if (!validated_shader) |
||
| 1070 | goto fail; |
||
| 1071 | |||
| 1072 | if (validated_shader->uniforms_src_size > |
||
| 1073 | exec->uniforms_size) { |
||
| 1074 | DRM_ERROR("Uniforms src buffer overflow\n"); |
||
| 1075 | goto fail; |
||
| 1076 | } |
||
| 1077 | |||
| 1078 | texture_handles_u = exec->uniforms_u; |
||
| 1079 | uniform_data_u = (texture_handles_u + |
||
| 1080 | validated_shader->num_texture_samples); |
||
| 1081 | |||
| 1082 | memcpy(exec->uniforms_v, uniform_data_u, |
||
| 1083 | validated_shader->uniforms_size); |
||
| 1084 | |||
| 1085 | for (tex = 0; |
||
| 1086 | tex < validated_shader->num_texture_samples; |
||
| 1087 | tex++) { |
||
| 1088 | if (!reloc_tex(exec, |
||
| 1089 | uniform_data_u, |
||
| 1090 | &validated_shader->texture_samples[tex], |
||
| 1091 | texture_handles_u[tex])) { |
||
| 1092 | goto fail; |
||
| 1093 | } |
||
| 1094 | } |
||
| 1095 | |||
| 1096 | *(uint32_t *)(pkt_v + o + 4) = exec->uniforms_p; |
||
| 1097 | |||
| 1098 | exec->uniforms_u += validated_shader->uniforms_src_size; |
||
| 1099 | exec->uniforms_v += validated_shader->uniforms_size; |
||
| 1100 | exec->uniforms_p += validated_shader->uniforms_size; |
||
| 1101 | |||
| 1102 | break; |
||
| 1103 | |||
| 1104 | case RELOC_VBO: |
||
| 1105 | break; |
||
| 1106 | } |
||
| 1107 | } |
||
| 1108 | |||
| 1109 | for (i = 0; i < nr_attributes; i++) { |
||
| 1110 | struct drm_gem_cma_object *vbo = bo[nr_fixed_relocs + i]; |
||
| 1111 | uint32_t o = 36 + i * 8; |
||
| 1112 | uint32_t offset = *(uint32_t *)(pkt_u + o + 0); |
||
| 1113 | uint32_t attr_size = *(uint8_t *)(pkt_u + o + 4) + 1; |
||
| 1114 | uint32_t stride = *(uint8_t *)(pkt_u + o + 5); |
||
| 1115 | uint32_t max_index; |
||
| 1116 | |||
| 1117 | if (state->addr & 0x8) |
||
| 1118 | stride |= (*(uint32_t *)(pkt_u + 100 + i * 4)) & ~0xff; |
||
| 1119 | |||
| 1120 | if (vbo->base.size < offset || |
||
| 1121 | vbo->base.size - offset < attr_size) { |
||
| 1122 | DRM_ERROR("BO offset overflow (%d + %d > %d)\n", |
||
| 1123 | offset, attr_size, vbo->base.size); |
||
| 1124 | return -EINVAL; |
||
| 1125 | } |
||
| 1126 | |||
| 1127 | if (stride != 0) { |
||
| 1128 | max_index = ((vbo->base.size - offset - attr_size) / |
||
| 1129 | stride); |
||
| 1130 | if (state->max_index > max_index) { |
||
| 1131 | DRM_ERROR("primitives use index %d out of supplied %d\n", |
||
| 1132 | state->max_index, max_index); |
||
| 1133 | return -EINVAL; |
||
| 1134 | } |
||
| 1135 | } |
||
| 1136 | |||
| 1137 | *(uint32_t *)(pkt_v + o) = vbo->paddr + offset; |
||
| 1138 | } |
||
| 1139 | |||
| 1140 | kfree(validated_shader); |
||
| 1141 | |||
| 1142 | return 0; |
||
| 1143 | |||
| 1144 | fail: |
||
| 1145 | kfree(validated_shader); |
||
| 1146 | return -EINVAL; |
||
| 1147 | } |
||
| 1148 | |||
| 1149 | int |
||
| 1150 | vc4_validate_shader_recs(struct drm_device *dev, |
||
| 1151 | struct vc4_exec_info *exec) |
||
| 1152 | { |
||
| 1153 | uint32_t i; |
||
| 1154 | int ret = 0; |
||
| 1155 | |||
| 1156 | for (i = 0; i < exec->shader_state_count; i++) { |
||
| 1157 | ret = validate_shader_rec(dev, exec, &exec->shader_state[i]); |
||
| 1158 | if (ret) |
||
| 1159 | return ret; |
||
| 1160 | } |
||
| 1161 | |||
| 1162 | return ret; |
||
| 1163 | } |