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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 5564 | serge | 1 | /* |
| 2 | * Southern Islands Register documentation |
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| 3 | * |
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| 4 | * Copyright (C) 2011 Advanced Micro Devices, Inc. |
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| 5 | * |
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| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 7 | * copy of this software and associated documentation files (the "Software"), |
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| 8 | * to deal in the Software without restriction, including without limitation |
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| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 11 | * Software is furnished to do so, subject to the following conditions: |
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| 12 | * |
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| 13 | * The above copyright notice and this permission notice shall be included |
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| 14 | * in all copies or substantial portions of the Software. |
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| 15 | * |
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| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
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| 17 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 19 | * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN |
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| 20 | * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
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| 21 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
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| 22 | */ |
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| 23 | |||
| 24 | #ifndef SID_H |
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| 25 | #define SID_H |
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| 26 | |||
| 27 | /* si values */ |
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| 28 | #define SI_CONFIG_REG_OFFSET 0x00008000 |
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| 29 | #define SI_CONFIG_REG_END 0x0000B000 |
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| 30 | #define SI_SH_REG_OFFSET 0x0000B000 |
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| 31 | #define SI_SH_REG_END 0x0000C000 |
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| 32 | #define SI_CONTEXT_REG_OFFSET 0x00028000 |
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| 33 | #define SI_CONTEXT_REG_END 0x00029000 |
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| 34 | #define CIK_UCONFIG_REG_OFFSET 0x00030000 |
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| 35 | #define CIK_UCONFIG_REG_END 0x00031000 |
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| 36 | |||
| 37 | #define EVENT_TYPE_CACHE_FLUSH 0x6 |
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| 38 | #define EVENT_TYPE_PS_PARTIAL_FLUSH 0x10 |
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| 39 | #define EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT 0x14 |
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| 40 | #define EVENT_TYPE_ZPASS_DONE 0x15 |
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| 41 | #define EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT 0x16 |
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| 42 | #define EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH 0x1f |
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| 43 | #define EVENT_TYPE_SAMPLE_STREAMOUTSTATS 0x20 |
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| 44 | #define EVENT_TYPE(x) ((x) << 0) |
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| 45 | #define EVENT_INDEX(x) ((x) << 8) |
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| 46 | /* 0 - any non-TS event |
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| 47 | * 1 - ZPASS_DONE |
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| 48 | * 2 - SAMPLE_PIPELINESTAT |
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| 49 | * 3 - SAMPLE_STREAMOUTSTAT* |
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| 50 | * 4 - *S_PARTIAL_FLUSH |
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| 51 | * 5 - TS events |
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| 52 | */ |
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| 53 | #define EVENT_WRITE_INV_L2 0x100000 |
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| 54 | |||
| 55 | |||
| 56 | #define PREDICATION_OP_CLEAR 0x0 |
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| 57 | #define PREDICATION_OP_ZPASS 0x1 |
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| 58 | #define PREDICATION_OP_PRIMCOUNT 0x2 |
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| 59 | |||
| 60 | #define PRED_OP(x) ((x) << 16) |
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| 61 | |||
| 62 | #define PREDICATION_CONTINUE (1 << 31) |
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| 63 | |||
| 64 | #define PREDICATION_HINT_WAIT (0 << 12) |
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| 65 | #define PREDICATION_HINT_NOWAIT_DRAW (1 << 12) |
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| 66 | |||
| 67 | #define PREDICATION_DRAW_NOT_VISIBLE (0 << 8) |
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| 68 | #define PREDICATION_DRAW_VISIBLE (1 << 8) |
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| 69 | |||
| 70 | #define R600_TEXEL_PITCH_ALIGNMENT_MASK 0x7 |
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| 71 | |||
| 72 | #define PKT3_NOP 0x10 |
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| 73 | #define PKT3_SET_BASE 0x11 |
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| 74 | #define PKT3_CLEAR_STATE 0x12 |
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| 75 | #define PKT3_INDEX_BUFFER_SIZE 0x13 |
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| 76 | #define PKT3_DISPATCH_DIRECT 0x15 |
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| 77 | #define PKT3_DISPATCH_INDIRECT 0x16 |
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| 78 | #define PKT3_OCCLUSION_QUERY 0x1F /* new for CIK */ |
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| 79 | #define PKT3_SET_PREDICATION 0x20 |
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| 80 | #define PKT3_COND_EXEC 0x22 |
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| 81 | #define PKT3_PRED_EXEC 0x23 |
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| 82 | #define PKT3_DRAW_INDIRECT 0x24 |
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| 83 | #define PKT3_DRAW_INDEX_INDIRECT 0x25 |
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| 84 | #define PKT3_INDEX_BASE 0x26 |
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| 85 | #define PKT3_DRAW_INDEX_2 0x27 |
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| 86 | #define PKT3_CONTEXT_CONTROL 0x28 |
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| 87 | #define PKT3_INDEX_TYPE 0x2A |
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| 88 | #define PKT3_DRAW_INDIRECT_MULTI 0x2C |
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| 89 | #define PKT3_DRAW_INDEX_AUTO 0x2D |
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| 90 | #define PKT3_DRAW_INDEX_IMMD 0x2E /* not on CIK */ |
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| 91 | #define PKT3_NUM_INSTANCES 0x2F |
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| 92 | #define PKT3_DRAW_INDEX_MULTI_AUTO 0x30 |
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| 93 | #define PKT3_INDIRECT_BUFFER 0x32 |
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| 94 | #define PKT3_STRMOUT_BUFFER_UPDATE 0x34 |
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| 95 | #define PKT3_DRAW_INDEX_OFFSET_2 0x35 |
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| 96 | #define PKT3_DRAW_PREAMBLE 0x36 /* new on CIK, required on GFX7.2 and later */ |
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| 97 | #define PKT3_WRITE_DATA 0x37 |
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| 98 | #define PKT3_WRITE_DATA_DST_SEL(x) ((x) << 8) |
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| 99 | #define PKT3_WRITE_DATA_DST_SEL_REG 0 |
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| 100 | #define PKT3_WRITE_DATA_DST_SEL_MEM_SYNC 1 |
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| 101 | #define PKT3_WRITE_DATA_DST_SEL_TC_L2 2 |
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| 102 | #define PKT3_WRITE_DATA_DST_SEL_GDS 3 |
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| 103 | #define PKT3_WRITE_DATA_DST_SEL_RESERVED_4 4 |
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| 104 | #define PKT3_WRITE_DATA_DST_SEL_MEM_ASYNC 5 |
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| 105 | #define PKT3_WR_ONE_ADDR (1 << 16) |
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| 106 | #define PKT3_WRITE_DATA_WR_CONFIRM (1 << 20) |
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| 107 | #define PKT3_WRITE_DATA_ENGINE_SEL(x) ((x) << 30) |
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| 108 | #define PKT3_WRITE_DATA_ENGINE_SEL_ME 0 |
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| 109 | #define PKT3_WRITE_DATA_ENGINE_SEL_PFP 1 |
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| 110 | #define PKT3_WRITE_DATA_ENGINE_SEL_CE 2 |
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| 111 | #define PKT3_DRAW_INDEX_INDIRECT_MULTI 0x38 |
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| 112 | #define PKT3_MEM_SEMAPHORE 0x39 |
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| 113 | #define PKT3_MPEG_INDEX 0x3A /* not on CIK */ |
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| 114 | #define PKT3_WAIT_REG_MEM 0x3C |
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| 115 | #define WAIT_REG_MEM_EQUAL 3 |
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| 116 | #define PKT3_MEM_WRITE 0x3D /* not on CIK */ |
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| 117 | #define PKT3_COPY_DATA 0x40 |
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| 118 | #define COPY_DATA_SRC_SEL(x) ((x) & 0xf) |
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| 119 | #define COPY_DATA_REG 0 |
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| 120 | #define COPY_DATA_MEM 1 |
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| 121 | #define COPY_DATA_DST_SEL(x) (((x) & 0xf) << 8) |
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| 122 | #define COPY_DATA_WR_CONFIRM (1 << 20) |
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| 123 | #define PKT3_SURFACE_SYNC 0x43 /* deprecated on CIK, use ACQUIRE_MEM */ |
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| 124 | #define PKT3_ME_INITIALIZE 0x44 /* not on CIK */ |
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| 125 | #define PKT3_COND_WRITE 0x45 |
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| 126 | #define PKT3_EVENT_WRITE 0x46 |
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| 127 | #define PKT3_EVENT_WRITE_EOP 0x47 |
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| 128 | #define PKT3_EVENT_WRITE_EOS 0x48 |
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| 129 | #define PKT3_ONE_REG_WRITE 0x57 /* not on CIK */ |
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| 130 | #define PKT3_ACQUIRE_MEM 0x58 /* new for CIK */ |
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| 131 | #define PKT3_SET_CONFIG_REG 0x68 |
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| 132 | #define PKT3_SET_CONTEXT_REG 0x69 |
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| 133 | #define PKT3_SET_SH_REG 0x76 |
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| 134 | #define PKT3_SET_SH_REG_OFFSET 0x77 |
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| 135 | #define PKT3_SET_UCONFIG_REG 0x79 /* new for CIK */ |
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| 136 | |||
| 137 | #define PKT_TYPE_S(x) (((x) & 0x3) << 30) |
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| 138 | #define PKT_TYPE_G(x) (((x) >> 30) & 0x3) |
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| 139 | #define PKT_TYPE_C 0x3FFFFFFF |
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| 140 | #define PKT_COUNT_S(x) (((x) & 0x3FFF) << 16) |
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| 141 | #define PKT_COUNT_G(x) (((x) >> 16) & 0x3FFF) |
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| 142 | #define PKT_COUNT_C 0xC000FFFF |
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| 143 | #define PKT0_BASE_INDEX_S(x) (((x) & 0xFFFF) << 0) |
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| 144 | #define PKT0_BASE_INDEX_G(x) (((x) >> 0) & 0xFFFF) |
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| 145 | #define PKT0_BASE_INDEX_C 0xFFFF0000 |
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| 146 | #define PKT3_IT_OPCODE_S(x) (((x) & 0xFF) << 8) |
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| 147 | #define PKT3_IT_OPCODE_G(x) (((x) >> 8) & 0xFF) |
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| 148 | #define PKT3_IT_OPCODE_C 0xFFFF00FF |
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| 149 | #define PKT3_PREDICATE(x) (((x) >> 0) & 0x1) |
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| 150 | #define PKT3_SHADER_TYPE_S(x) (((x) & 0x1) << 1) |
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| 151 | #define PKT0(index, count) (PKT_TYPE_S(0) | PKT0_BASE_INDEX_S(index) | PKT_COUNT_S(count)) |
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| 152 | #define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate)) |
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| 153 | |||
| 154 | #define PKT3_CP_DMA 0x41 |
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| 155 | /* 1. header |
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| 156 | * 2. SRC_ADDR_LO [31:0] or DATA [31:0] |
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| 157 | * 3. CP_SYNC [31] | SRC_SEL [30:29] | ENGINE [27] | DST_SEL [21:20] | SRC_ADDR_HI [15:0] |
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| 158 | * 4. DST_ADDR_LO [31:0] |
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| 159 | * 5. DST_ADDR_HI [15:0] |
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| 160 | * 6. COMMAND [29:22] | BYTE_COUNT [20:0] |
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| 161 | */ |
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| 162 | #define PKT3_CP_DMA_CP_SYNC (1 << 31) |
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| 163 | #define PKT3_CP_DMA_SRC_SEL(x) ((x) << 29) |
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| 164 | /* 0 - SRC_ADDR |
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| 165 | * 1 - GDS (program SAS to 1 as well) |
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| 166 | * 2 - DATA |
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| 167 | * 3 - SRC_ADDR using TC L2 (DMA_DATA only) |
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| 168 | */ |
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| 169 | #define PKT3_CP_DMA_DST_SEL(x) ((x) << 20) |
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| 170 | /* 0 - DST_ADDR |
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| 171 | * 1 - GDS (program DAS to 1 as well) |
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| 172 | * 3 - DST_ADDR using TC L2 (DMA_DATA only) |
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| 173 | */ |
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| 174 | /* COMMAND */ |
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| 175 | #define PKT3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 23) |
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| 176 | /* 0 - none |
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| 177 | * 1 - 8 in 16 |
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| 178 | * 2 - 8 in 32 |
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| 179 | * 3 - 8 in 64 |
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| 180 | */ |
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| 181 | #define PKT3_CP_DMA_CMD_DST_SWAP(x) ((x) << 24) |
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| 182 | /* 0 - none |
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| 183 | * 1 - 8 in 16 |
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| 184 | * 2 - 8 in 32 |
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| 185 | * 3 - 8 in 64 |
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| 186 | */ |
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| 187 | #define PKT3_CP_DMA_CMD_SAS (1 << 26) |
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| 188 | /* 0 - memory |
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| 189 | * 1 - register |
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| 190 | */ |
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| 191 | #define PKT3_CP_DMA_CMD_DAS (1 << 27) |
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| 192 | /* 0 - memory |
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| 193 | * 1 - register |
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| 194 | */ |
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| 195 | #define PKT3_CP_DMA_CMD_SAIC (1 << 28) |
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| 196 | #define PKT3_CP_DMA_CMD_DAIC (1 << 29) |
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| 197 | #define PKT3_CP_DMA_CMD_RAW_WAIT (1 << 30) |
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| 198 | |||
| 199 | #define PKT3_DMA_DATA 0x50 /* new for CIK */ |
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| 200 | /* 1. header |
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| 201 | * 2. CP_SYNC [31] | SRC_SEL [30:29] | DST_SEL [21:20] | ENGINE [0] |
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| 202 | * 2. SRC_ADDR_LO [31:0] or DATA [31:0] |
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| 203 | * 3. SRC_ADDR_HI [31:0] |
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| 204 | * 4. DST_ADDR_LO [31:0] |
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| 205 | * 5. DST_ADDR_HI [31:0] |
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| 206 | * 6. COMMAND [29:22] | BYTE_COUNT [20:0] |
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| 207 | */ |
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| 208 | |||
| 209 | #define GRBM_GFX_INDEX 0x802C |
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| 210 | #define INSTANCE_INDEX(x) ((x) << 0) |
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| 211 | #define SH_INDEX(x) ((x) << 8) |
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| 212 | #define SE_INDEX(x) ((x) << 16) |
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| 213 | #define SH_BROADCAST_WRITES (1 << 29) |
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| 214 | #define INSTANCE_BROADCAST_WRITES (1 << 30) |
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| 215 | #define SE_BROADCAST_WRITES (1 << 31) |
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| 216 | #define R_0084FC_CP_STRMOUT_CNTL 0x0084FC |
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| 217 | #define S_0084FC_OFFSET_UPDATE_DONE(x) (((x) & 0x1) << 0) |
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| 218 | #define R_0085F0_CP_COHER_CNTL 0x0085F0 |
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| 219 | #define S_0085F0_DEST_BASE_0_ENA(x) (((x) & 0x1) << 0) |
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| 220 | #define G_0085F0_DEST_BASE_0_ENA(x) (((x) >> 0) & 0x1) |
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| 221 | #define C_0085F0_DEST_BASE_0_ENA 0xFFFFFFFE |
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| 222 | #define S_0085F0_DEST_BASE_1_ENA(x) (((x) & 0x1) << 1) |
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| 223 | #define G_0085F0_DEST_BASE_1_ENA(x) (((x) >> 1) & 0x1) |
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| 224 | #define C_0085F0_DEST_BASE_1_ENA 0xFFFFFFFD |
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| 225 | #define S_0085F0_CB0_DEST_BASE_ENA_SHIFT 6 |
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| 226 | #define S_0085F0_CB0_DEST_BASE_ENA(x) (((x) & 0x1) << 6) |
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| 227 | #define G_0085F0_CB0_DEST_BASE_ENA(x) (((x) >> 6) & 0x1) |
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| 228 | #define C_0085F0_CB0_DEST_BASE_ENA 0xFFFFFFBF |
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| 229 | #define S_0085F0_CB1_DEST_BASE_ENA(x) (((x) & 0x1) << 7) |
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| 230 | #define G_0085F0_CB1_DEST_BASE_ENA(x) (((x) >> 7) & 0x1) |
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| 231 | #define C_0085F0_CB1_DEST_BASE_ENA 0xFFFFFF7F |
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| 232 | #define S_0085F0_CB2_DEST_BASE_ENA(x) (((x) & 0x1) << 8) |
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| 233 | #define G_0085F0_CB2_DEST_BASE_ENA(x) (((x) >> 8) & 0x1) |
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| 234 | #define C_0085F0_CB2_DEST_BASE_ENA 0xFFFFFEFF |
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| 235 | #define S_0085F0_CB3_DEST_BASE_ENA(x) (((x) & 0x1) << 9) |
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| 236 | #define G_0085F0_CB3_DEST_BASE_ENA(x) (((x) >> 9) & 0x1) |
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| 237 | #define C_0085F0_CB3_DEST_BASE_ENA 0xFFFFFDFF |
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| 238 | #define S_0085F0_CB4_DEST_BASE_ENA(x) (((x) & 0x1) << 10) |
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| 239 | #define G_0085F0_CB4_DEST_BASE_ENA(x) (((x) >> 10) & 0x1) |
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| 240 | #define C_0085F0_CB4_DEST_BASE_ENA 0xFFFFFBFF |
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| 241 | #define S_0085F0_CB5_DEST_BASE_ENA(x) (((x) & 0x1) << 11) |
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| 242 | #define G_0085F0_CB5_DEST_BASE_ENA(x) (((x) >> 11) & 0x1) |
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| 243 | #define C_0085F0_CB5_DEST_BASE_ENA 0xFFFFF7FF |
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| 244 | #define S_0085F0_CB6_DEST_BASE_ENA(x) (((x) & 0x1) << 12) |
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| 245 | #define G_0085F0_CB6_DEST_BASE_ENA(x) (((x) >> 12) & 0x1) |
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| 246 | #define C_0085F0_CB6_DEST_BASE_ENA 0xFFFFEFFF |
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| 247 | #define S_0085F0_CB7_DEST_BASE_ENA(x) (((x) & 0x1) << 13) |
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| 248 | #define G_0085F0_CB7_DEST_BASE_ENA(x) (((x) >> 13) & 0x1) |
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| 249 | #define C_0085F0_CB7_DEST_BASE_ENA 0xFFFFDFFF |
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| 250 | #define S_0085F0_DB_DEST_BASE_ENA(x) (((x) & 0x1) << 14) |
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| 251 | #define G_0085F0_DB_DEST_BASE_ENA(x) (((x) >> 14) & 0x1) |
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| 252 | #define C_0085F0_DB_DEST_BASE_ENA 0xFFFFBFFF |
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| 253 | #define S_0085F0_DEST_BASE_2_ENA(x) (((x) & 0x1) << 19) |
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| 254 | #define G_0085F0_DEST_BASE_2_ENA(x) (((x) >> 19) & 0x1) |
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| 255 | #define C_0085F0_DEST_BASE_2_ENA 0xFFF7FFFF |
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| 256 | #define S_0085F0_DEST_BASE_3_ENA(x) (((x) & 0x1) << 21) |
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| 257 | #define G_0085F0_DEST_BASE_3_ENA(x) (((x) >> 21) & 0x1) |
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| 258 | #define C_0085F0_DEST_BASE_3_ENA 0xFFDFFFFF |
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| 259 | #define S_0085F0_TCL1_ACTION_ENA(x) (((x) & 0x1) << 22) |
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| 260 | #define G_0085F0_TCL1_ACTION_ENA(x) (((x) >> 22) & 0x1) |
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| 261 | #define C_0085F0_TCL1_ACTION_ENA 0xFFBFFFFF |
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| 262 | #define S_0085F0_TC_ACTION_ENA(x) (((x) & 0x1) << 23) |
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| 263 | #define G_0085F0_TC_ACTION_ENA(x) (((x) >> 23) & 0x1) |
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| 264 | #define C_0085F0_TC_ACTION_ENA 0xFF7FFFFF |
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| 265 | #define S_0085F0_CB_ACTION_ENA(x) (((x) & 0x1) << 25) |
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| 266 | #define G_0085F0_CB_ACTION_ENA(x) (((x) >> 25) & 0x1) |
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| 267 | #define C_0085F0_CB_ACTION_ENA 0xFDFFFFFF |
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| 268 | #define S_0085F0_DB_ACTION_ENA(x) (((x) & 0x1) << 26) |
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| 269 | #define G_0085F0_DB_ACTION_ENA(x) (((x) >> 26) & 0x1) |
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| 270 | #define C_0085F0_DB_ACTION_ENA 0xFBFFFFFF |
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| 271 | #define S_0085F0_SH_KCACHE_ACTION_ENA(x) (((x) & 0x1) << 27) |
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| 272 | #define G_0085F0_SH_KCACHE_ACTION_ENA(x) (((x) >> 27) & 0x1) |
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| 273 | #define C_0085F0_SH_KCACHE_ACTION_ENA 0xF7FFFFFF |
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| 274 | #define S_0085F0_SH_ICACHE_ACTION_ENA(x) (((x) & 0x1) << 29) |
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| 275 | #define G_0085F0_SH_ICACHE_ACTION_ENA(x) (((x) >> 29) & 0x1) |
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| 276 | #define C_0085F0_SH_ICACHE_ACTION_ENA 0xDFFFFFFF |
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| 277 | #define R_0085F4_CP_COHER_SIZE 0x0085F4 |
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| 278 | #define R_0085F8_CP_COHER_BASE 0x0085F8 |
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| 279 | |||
| 280 | /* CIK */ |
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| 281 | #define R_0301E4_CP_COHER_BASE_HI 0x0301E4 |
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| 282 | #define S_0301E4_COHER_BASE_HI_256B(x) (((x) & 0xFF) << 0) |
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| 283 | #define G_0301E4_COHER_BASE_HI_256B(x) (((x) >> 0) & 0xFF) |
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| 284 | #define C_0301E4_COHER_BASE_HI_256B 0xFFFFFF00 |
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| 285 | #define R_0301F0_CP_COHER_CNTL 0x0301F0 |
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| 286 | #define S_0301F0_DEST_BASE_0_ENA(x) (((x) & 0x1) << 0) |
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| 287 | #define G_0301F0_DEST_BASE_0_ENA(x) (((x) >> 0) & 0x1) |
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| 288 | #define C_0301F0_DEST_BASE_0_ENA 0xFFFFFFFE |
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| 289 | #define S_0301F0_DEST_BASE_1_ENA(x) (((x) & 0x1) << 1) |
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| 290 | #define G_0301F0_DEST_BASE_1_ENA(x) (((x) >> 1) & 0x1) |
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| 291 | #define C_0301F0_DEST_BASE_1_ENA 0xFFFFFFFD |
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| 292 | #define S_0301F0_CB0_DEST_BASE_ENA(x) (((x) & 0x1) << 6) |
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| 293 | #define G_0301F0_CB0_DEST_BASE_ENA(x) (((x) >> 6) & 0x1) |
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| 294 | #define C_0301F0_CB0_DEST_BASE_ENA 0xFFFFFFBF |
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| 295 | #define S_0301F0_CB1_DEST_BASE_ENA(x) (((x) & 0x1) << 7) |
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| 296 | #define G_0301F0_CB1_DEST_BASE_ENA(x) (((x) >> 7) & 0x1) |
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| 297 | #define C_0301F0_CB1_DEST_BASE_ENA 0xFFFFFF7F |
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| 298 | #define S_0301F0_CB2_DEST_BASE_ENA(x) (((x) & 0x1) << 8) |
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| 299 | #define G_0301F0_CB2_DEST_BASE_ENA(x) (((x) >> 8) & 0x1) |
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| 300 | #define C_0301F0_CB2_DEST_BASE_ENA 0xFFFFFEFF |
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| 301 | #define S_0301F0_CB3_DEST_BASE_ENA(x) (((x) & 0x1) << 9) |
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| 302 | #define G_0301F0_CB3_DEST_BASE_ENA(x) (((x) >> 9) & 0x1) |
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| 303 | #define C_0301F0_CB3_DEST_BASE_ENA 0xFFFFFDFF |
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| 304 | #define S_0301F0_CB4_DEST_BASE_ENA(x) (((x) & 0x1) << 10) |
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| 305 | #define G_0301F0_CB4_DEST_BASE_ENA(x) (((x) >> 10) & 0x1) |
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| 306 | #define C_0301F0_CB4_DEST_BASE_ENA 0xFFFFFBFF |
||
| 307 | #define S_0301F0_CB5_DEST_BASE_ENA(x) (((x) & 0x1) << 11) |
||
| 308 | #define G_0301F0_CB5_DEST_BASE_ENA(x) (((x) >> 11) & 0x1) |
||
| 309 | #define C_0301F0_CB5_DEST_BASE_ENA 0xFFFFF7FF |
||
| 310 | #define S_0301F0_CB6_DEST_BASE_ENA(x) (((x) & 0x1) << 12) |
||
| 311 | #define G_0301F0_CB6_DEST_BASE_ENA(x) (((x) >> 12) & 0x1) |
||
| 312 | #define C_0301F0_CB6_DEST_BASE_ENA 0xFFFFEFFF |
||
| 313 | #define S_0301F0_CB7_DEST_BASE_ENA(x) (((x) & 0x1) << 13) |
||
| 314 | #define G_0301F0_CB7_DEST_BASE_ENA(x) (((x) >> 13) & 0x1) |
||
| 315 | #define C_0301F0_CB7_DEST_BASE_ENA 0xFFFFDFFF |
||
| 316 | #define S_0301F0_DB_DEST_BASE_ENA(x) (((x) & 0x1) << 14) |
||
| 317 | #define G_0301F0_DB_DEST_BASE_ENA(x) (((x) >> 14) & 0x1) |
||
| 318 | #define C_0301F0_DB_DEST_BASE_ENA 0xFFFFBFFF |
||
| 319 | #define S_0301F0_TCL1_VOL_ACTION_ENA(x) (((x) & 0x1) << 15) |
||
| 320 | #define G_0301F0_TCL1_VOL_ACTION_ENA(x) (((x) >> 15) & 0x1) |
||
| 321 | #define C_0301F0_TCL1_VOL_ACTION_ENA 0xFFFF7FFF |
||
| 322 | #define S_0301F0_TC_VOL_ACTION_ENA(x) (((x) & 0x1) << 16) |
||
| 323 | #define G_0301F0_TC_VOL_ACTION_ENA(x) (((x) >> 16) & 0x1) |
||
| 324 | #define C_0301F0_TC_VOL_ACTION_ENA 0xFFFEFFFF |
||
| 325 | #define S_0301F0_TC_WB_ACTION_ENA(x) (((x) & 0x1) << 18) |
||
| 326 | #define G_0301F0_TC_WB_ACTION_ENA(x) (((x) >> 18) & 0x1) |
||
| 327 | #define C_0301F0_TC_WB_ACTION_ENA 0xFFFBFFFF |
||
| 328 | #define S_0301F0_DEST_BASE_2_ENA(x) (((x) & 0x1) << 19) |
||
| 329 | #define G_0301F0_DEST_BASE_2_ENA(x) (((x) >> 19) & 0x1) |
||
| 330 | #define C_0301F0_DEST_BASE_2_ENA 0xFFF7FFFF |
||
| 331 | #define S_0301F0_DEST_BASE_3_ENA(x) (((x) & 0x1) << 21) |
||
| 332 | #define G_0301F0_DEST_BASE_3_ENA(x) (((x) >> 21) & 0x1) |
||
| 333 | #define C_0301F0_DEST_BASE_3_ENA 0xFFDFFFFF |
||
| 334 | #define S_0301F0_TCL1_ACTION_ENA(x) (((x) & 0x1) << 22) |
||
| 335 | #define G_0301F0_TCL1_ACTION_ENA(x) (((x) >> 22) & 0x1) |
||
| 336 | #define C_0301F0_TCL1_ACTION_ENA 0xFFBFFFFF |
||
| 337 | #define S_0301F0_TC_ACTION_ENA(x) (((x) & 0x1) << 23) |
||
| 338 | #define G_0301F0_TC_ACTION_ENA(x) (((x) >> 23) & 0x1) |
||
| 339 | #define C_0301F0_TC_ACTION_ENA 0xFF7FFFFF |
||
| 340 | #define S_0301F0_CB_ACTION_ENA(x) (((x) & 0x1) << 25) |
||
| 341 | #define G_0301F0_CB_ACTION_ENA(x) (((x) >> 25) & 0x1) |
||
| 342 | #define C_0301F0_CB_ACTION_ENA 0xFDFFFFFF |
||
| 343 | #define S_0301F0_DB_ACTION_ENA(x) (((x) & 0x1) << 26) |
||
| 344 | #define G_0301F0_DB_ACTION_ENA(x) (((x) >> 26) & 0x1) |
||
| 345 | #define C_0301F0_DB_ACTION_ENA 0xFBFFFFFF |
||
| 346 | #define S_0301F0_SH_KCACHE_ACTION_ENA(x) (((x) & 0x1) << 27) |
||
| 347 | #define G_0301F0_SH_KCACHE_ACTION_ENA(x) (((x) >> 27) & 0x1) |
||
| 348 | #define C_0301F0_SH_KCACHE_ACTION_ENA 0xF7FFFFFF |
||
| 349 | #define S_0301F0_SH_KCACHE_VOL_ACTION_ENA(x) (((x) & 0x1) << 28) |
||
| 350 | #define G_0301F0_SH_KCACHE_VOL_ACTION_ENA(x) (((x) >> 28) & 0x1) |
||
| 351 | #define C_0301F0_SH_KCACHE_VOL_ACTION_ENA 0xEFFFFFFF |
||
| 352 | #define S_0301F0_SH_ICACHE_ACTION_ENA(x) (((x) & 0x1) << 29) |
||
| 353 | #define G_0301F0_SH_ICACHE_ACTION_ENA(x) (((x) >> 29) & 0x1) |
||
| 354 | #define C_0301F0_SH_ICACHE_ACTION_ENA 0xDFFFFFFF |
||
| 355 | #define R_0301F4_CP_COHER_SIZE 0x0301F4 |
||
| 356 | #define R_0301F8_CP_COHER_BASE 0x0301F8 |
||
| 357 | #define R_030230_CP_COHER_SIZE_HI 0x030230 |
||
| 358 | #define S_030230_COHER_SIZE_HI_256B(x) (((x) & 0xFF) << 0) |
||
| 359 | #define G_030230_COHER_SIZE_HI_256B(x) (((x) >> 0) & 0xFF) |
||
| 360 | #define C_030230_COHER_SIZE_HI_256B 0xFFFFFF00 |
||
| 361 | /* */ |
||
| 362 | #define R_0088B0_VGT_VTX_VECT_EJECT_REG 0x0088B0 |
||
| 363 | #define S_0088B0_PRIM_COUNT(x) (((x) & 0x3FF) << 0) |
||
| 364 | #define G_0088B0_PRIM_COUNT(x) (((x) >> 0) & 0x3FF) |
||
| 365 | #define C_0088B0_PRIM_COUNT 0xFFFFFC00 |
||
| 366 | #define R_0088C4_VGT_CACHE_INVALIDATION 0x0088C4 |
||
| 367 | #define S_0088C4_VS_NO_EXTRA_BUFFER(x) (((x) & 0x1) << 5) |
||
| 368 | #define G_0088C4_VS_NO_EXTRA_BUFFER(x) (((x) >> 5) & 0x1) |
||
| 369 | #define C_0088C4_VS_NO_EXTRA_BUFFER 0xFFFFFFDF |
||
| 370 | #define S_0088C4_STREAMOUT_FULL_FLUSH(x) (((x) & 0x1) << 13) |
||
| 371 | #define G_0088C4_STREAMOUT_FULL_FLUSH(x) (((x) >> 13) & 0x1) |
||
| 372 | #define C_0088C4_STREAMOUT_FULL_FLUSH 0xFFFFDFFF |
||
| 373 | #define S_0088C4_ES_LIMIT(x) (((x) & 0x1F) << 16) |
||
| 374 | #define G_0088C4_ES_LIMIT(x) (((x) >> 16) & 0x1F) |
||
| 375 | #define C_0088C4_ES_LIMIT 0xFFE0FFFF |
||
| 376 | #define R_0088C8_VGT_ESGS_RING_SIZE 0x0088C8 |
||
| 377 | #define R_0088CC_VGT_GSVS_RING_SIZE 0x0088CC |
||
| 378 | /* CIK */ |
||
| 379 | #define R_030900_VGT_ESGS_RING_SIZE 0x030900 |
||
| 380 | #define R_030904_VGT_GSVS_RING_SIZE 0x030904 |
||
| 381 | /* */ |
||
| 382 | #define R_0088D4_VGT_GS_VERTEX_REUSE 0x0088D4 |
||
| 383 | #define S_0088D4_VERT_REUSE(x) (((x) & 0x1F) << 0) |
||
| 384 | #define G_0088D4_VERT_REUSE(x) (((x) >> 0) & 0x1F) |
||
| 385 | #define C_0088D4_VERT_REUSE 0xFFFFFFE0 |
||
| 386 | #define R_008958_VGT_PRIMITIVE_TYPE 0x008958 |
||
| 387 | #define S_008958_PRIM_TYPE(x) (((x) & 0x3F) << 0) |
||
| 388 | #define G_008958_PRIM_TYPE(x) (((x) >> 0) & 0x3F) |
||
| 389 | #define C_008958_PRIM_TYPE 0xFFFFFFC0 |
||
| 390 | #define V_008958_DI_PT_NONE 0x00 |
||
| 391 | #define V_008958_DI_PT_POINTLIST 0x01 |
||
| 392 | #define V_008958_DI_PT_LINELIST 0x02 |
||
| 393 | #define V_008958_DI_PT_LINESTRIP 0x03 |
||
| 394 | #define V_008958_DI_PT_TRILIST 0x04 |
||
| 395 | #define V_008958_DI_PT_TRIFAN 0x05 |
||
| 396 | #define V_008958_DI_PT_TRISTRIP 0x06 |
||
| 397 | #define V_008958_DI_PT_UNUSED_0 0x07 |
||
| 398 | #define V_008958_DI_PT_UNUSED_1 0x08 |
||
| 399 | #define V_008958_DI_PT_PATCH 0x09 |
||
| 400 | #define V_008958_DI_PT_LINELIST_ADJ 0x0A |
||
| 401 | #define V_008958_DI_PT_LINESTRIP_ADJ 0x0B |
||
| 402 | #define V_008958_DI_PT_TRILIST_ADJ 0x0C |
||
| 403 | #define V_008958_DI_PT_TRISTRIP_ADJ 0x0D |
||
| 404 | #define V_008958_DI_PT_UNUSED_3 0x0E |
||
| 405 | #define V_008958_DI_PT_UNUSED_4 0x0F |
||
| 406 | #define V_008958_DI_PT_TRI_WITH_WFLAGS 0x10 |
||
| 407 | #define V_008958_DI_PT_RECTLIST 0x11 |
||
| 408 | #define V_008958_DI_PT_LINELOOP 0x12 |
||
| 409 | #define V_008958_DI_PT_QUADLIST 0x13 |
||
| 410 | #define V_008958_DI_PT_QUADSTRIP 0x14 |
||
| 411 | #define V_008958_DI_PT_POLYGON 0x15 |
||
| 412 | #define V_008958_DI_PT_2D_COPY_RECT_LIST_V0 0x16 |
||
| 413 | #define V_008958_DI_PT_2D_COPY_RECT_LIST_V1 0x17 |
||
| 414 | #define V_008958_DI_PT_2D_COPY_RECT_LIST_V2 0x18 |
||
| 415 | #define V_008958_DI_PT_2D_COPY_RECT_LIST_V3 0x19 |
||
| 416 | #define V_008958_DI_PT_2D_FILL_RECT_LIST 0x1A |
||
| 417 | #define V_008958_DI_PT_2D_LINE_STRIP 0x1B |
||
| 418 | #define V_008958_DI_PT_2D_TRI_STRIP 0x1C |
||
| 419 | #define R_00895C_VGT_INDEX_TYPE 0x00895C |
||
| 420 | #define S_00895C_INDEX_TYPE(x) (((x) & 0x03) << 0) |
||
| 421 | #define G_00895C_INDEX_TYPE(x) (((x) >> 0) & 0x03) |
||
| 422 | #define C_00895C_INDEX_TYPE 0xFFFFFFFC |
||
| 423 | #define V_00895C_DI_INDEX_SIZE_16_BIT 0x00 |
||
| 424 | #define V_00895C_DI_INDEX_SIZE_32_BIT 0x01 |
||
| 425 | #define R_008960_VGT_STRMOUT_BUFFER_FILLED_SIZE_0 0x008960 |
||
| 426 | #define R_008964_VGT_STRMOUT_BUFFER_FILLED_SIZE_1 0x008964 |
||
| 427 | #define R_008968_VGT_STRMOUT_BUFFER_FILLED_SIZE_2 0x008968 |
||
| 428 | #define R_00896C_VGT_STRMOUT_BUFFER_FILLED_SIZE_3 0x00896C |
||
| 429 | #define R_008970_VGT_NUM_INDICES 0x008970 |
||
| 430 | #define R_008974_VGT_NUM_INSTANCES 0x008974 |
||
| 431 | #define R_008988_VGT_TF_RING_SIZE 0x008988 |
||
| 432 | #define S_008988_SIZE(x) (((x) & 0xFFFF) << 0) |
||
| 433 | #define G_008988_SIZE(x) (((x) >> 0) & 0xFFFF) |
||
| 434 | #define C_008988_SIZE 0xFFFF0000 |
||
| 435 | #define R_0089B0_VGT_HS_OFFCHIP_PARAM 0x0089B0 |
||
| 436 | #define S_0089B0_OFFCHIP_BUFFERING(x) (((x) & 0x7F) << 0) |
||
| 437 | #define G_0089B0_OFFCHIP_BUFFERING(x) (((x) >> 0) & 0x7F) |
||
| 438 | #define C_0089B0_OFFCHIP_BUFFERING 0xFFFFFF80 |
||
| 439 | #define R_0089B8_VGT_TF_MEMORY_BASE 0x0089B8 |
||
| 440 | #define R_008A14_PA_CL_ENHANCE 0x008A14 |
||
| 441 | #define S_008A14_CLIP_VTX_REORDER_ENA(x) (((x) & 0x1) << 0) |
||
| 442 | #define G_008A14_CLIP_VTX_REORDER_ENA(x) (((x) >> 0) & 0x1) |
||
| 443 | #define C_008A14_CLIP_VTX_REORDER_ENA 0xFFFFFFFE |
||
| 444 | #define S_008A14_NUM_CLIP_SEQ(x) (((x) & 0x03) << 1) |
||
| 445 | #define G_008A14_NUM_CLIP_SEQ(x) (((x) >> 1) & 0x03) |
||
| 446 | #define C_008A14_NUM_CLIP_SEQ 0xFFFFFFF9 |
||
| 447 | #define S_008A14_CLIPPED_PRIM_SEQ_STALL(x) (((x) & 0x1) << 3) |
||
| 448 | #define G_008A14_CLIPPED_PRIM_SEQ_STALL(x) (((x) >> 3) & 0x1) |
||
| 449 | #define C_008A14_CLIPPED_PRIM_SEQ_STALL 0xFFFFFFF7 |
||
| 450 | #define S_008A14_VE_NAN_PROC_DISABLE(x) (((x) & 0x1) << 4) |
||
| 451 | #define G_008A14_VE_NAN_PROC_DISABLE(x) (((x) >> 4) & 0x1) |
||
| 452 | #define C_008A14_VE_NAN_PROC_DISABLE 0xFFFFFFEF |
||
| 453 | #define R_008A60_PA_SU_LINE_STIPPLE_VALUE 0x008A60 |
||
| 454 | #define S_008A60_LINE_STIPPLE_VALUE(x) (((x) & 0xFFFFFF) << 0) |
||
| 455 | #define G_008A60_LINE_STIPPLE_VALUE(x) (((x) >> 0) & 0xFFFFFF) |
||
| 456 | #define C_008A60_LINE_STIPPLE_VALUE 0xFF000000 |
||
| 457 | #define R_008B10_PA_SC_LINE_STIPPLE_STATE 0x008B10 |
||
| 458 | #define S_008B10_CURRENT_PTR(x) (((x) & 0x0F) << 0) |
||
| 459 | #define G_008B10_CURRENT_PTR(x) (((x) >> 0) & 0x0F) |
||
| 460 | #define C_008B10_CURRENT_PTR 0xFFFFFFF0 |
||
| 461 | #define S_008B10_CURRENT_COUNT(x) (((x) & 0xFF) << 8) |
||
| 462 | #define G_008B10_CURRENT_COUNT(x) (((x) >> 8) & 0xFF) |
||
| 463 | #define C_008B10_CURRENT_COUNT 0xFFFF00FF |
||
| 464 | /* CIK */ |
||
| 465 | #define R_030908_VGT_PRIMITIVE_TYPE 0x030908 |
||
| 466 | #define S_030908_PRIM_TYPE(x) (((x) & 0x3F) << 0) |
||
| 467 | #define G_030908_PRIM_TYPE(x) (((x) >> 0) & 0x3F) |
||
| 468 | #define C_030908_PRIM_TYPE 0xFFFFFFC0 |
||
| 469 | #define V_030908_DI_PT_NONE 0x00 |
||
| 470 | #define V_030908_DI_PT_POINTLIST 0x01 |
||
| 471 | #define V_030908_DI_PT_LINELIST 0x02 |
||
| 472 | #define V_030908_DI_PT_LINESTRIP 0x03 |
||
| 473 | #define V_030908_DI_PT_TRILIST 0x04 |
||
| 474 | #define V_030908_DI_PT_TRIFAN 0x05 |
||
| 475 | #define V_030908_DI_PT_TRISTRIP 0x06 |
||
| 476 | #define V_030908_DI_PT_PATCH 0x09 |
||
| 477 | #define V_030908_DI_PT_LINELIST_ADJ 0x0A |
||
| 478 | #define V_030908_DI_PT_LINESTRIP_ADJ 0x0B |
||
| 479 | #define V_030908_DI_PT_TRILIST_ADJ 0x0C |
||
| 480 | #define V_030908_DI_PT_TRISTRIP_ADJ 0x0D |
||
| 481 | #define V_030908_DI_PT_TRI_WITH_WFLAGS 0x10 |
||
| 482 | #define V_030908_DI_PT_RECTLIST 0x11 |
||
| 483 | #define V_030908_DI_PT_LINELOOP 0x12 |
||
| 484 | #define V_030908_DI_PT_QUADLIST 0x13 |
||
| 485 | #define V_030908_DI_PT_QUADSTRIP 0x14 |
||
| 486 | #define V_030908_DI_PT_POLYGON 0x15 |
||
| 487 | #define V_030908_DI_PT_2D_COPY_RECT_LIST_V0 0x16 |
||
| 488 | #define V_030908_DI_PT_2D_COPY_RECT_LIST_V1 0x17 |
||
| 489 | #define V_030908_DI_PT_2D_COPY_RECT_LIST_V2 0x18 |
||
| 490 | #define V_030908_DI_PT_2D_COPY_RECT_LIST_V3 0x19 |
||
| 491 | #define V_030908_DI_PT_2D_FILL_RECT_LIST 0x1A |
||
| 492 | #define V_030908_DI_PT_2D_LINE_STRIP 0x1B |
||
| 493 | #define V_030908_DI_PT_2D_TRI_STRIP 0x1C |
||
| 494 | #define R_03090C_VGT_INDEX_TYPE 0x03090C |
||
| 495 | #define S_03090C_INDEX_TYPE(x) (((x) & 0x03) << 0) |
||
| 496 | #define G_03090C_INDEX_TYPE(x) (((x) >> 0) & 0x03) |
||
| 497 | #define C_03090C_INDEX_TYPE 0xFFFFFFFC |
||
| 498 | #define V_03090C_DI_INDEX_SIZE_16_BIT 0x00 |
||
| 499 | #define V_03090C_DI_INDEX_SIZE_32_BIT 0x01 |
||
| 500 | #define R_030910_VGT_STRMOUT_BUFFER_FILLED_SIZE_0 0x030910 |
||
| 501 | #define R_030914_VGT_STRMOUT_BUFFER_FILLED_SIZE_1 0x030914 |
||
| 502 | #define R_030918_VGT_STRMOUT_BUFFER_FILLED_SIZE_2 0x030918 |
||
| 503 | #define R_03091C_VGT_STRMOUT_BUFFER_FILLED_SIZE_3 0x03091C |
||
| 504 | #define R_030930_VGT_NUM_INDICES 0x030930 |
||
| 505 | #define R_030934_VGT_NUM_INSTANCES 0x030934 |
||
| 506 | #define R_030938_VGT_TF_RING_SIZE 0x030938 |
||
| 507 | #define S_030938_SIZE(x) (((x) & 0xFFFF) << 0) |
||
| 508 | #define G_030938_SIZE(x) (((x) >> 0) & 0xFFFF) |
||
| 509 | #define C_030938_SIZE 0xFFFF0000 |
||
| 510 | #define R_03093C_VGT_HS_OFFCHIP_PARAM 0x03093C |
||
| 511 | #define S_03093C_OFFCHIP_BUFFERING(x) (((x) & 0x1FF) << 0) |
||
| 512 | #define G_03093C_OFFCHIP_BUFFERING(x) (((x) >> 0) & 0x1FF) |
||
| 513 | #define C_03093C_OFFCHIP_BUFFERING 0xFFFFFE00 |
||
| 514 | #define S_03093C_OFFCHIP_GRANULARITY(x) (((x) & 0x03) << 9) |
||
| 515 | #define G_03093C_OFFCHIP_GRANULARITY(x) (((x) >> 9) & 0x03) |
||
| 516 | #define C_03093C_OFFCHIP_GRANULARITY 0xFFFFF9FF |
||
| 517 | #define V_03093C_X_8K_DWORDS 0x00 |
||
| 518 | #define V_03093C_X_4K_DWORDS 0x01 |
||
| 519 | #define V_03093C_X_2K_DWORDS 0x02 |
||
| 520 | #define V_03093C_X_1K_DWORDS 0x03 |
||
| 521 | #define R_030940_VGT_TF_MEMORY_BASE 0x030940 |
||
| 522 | #define R_030A00_PA_SU_LINE_STIPPLE_VALUE 0x030A00 |
||
| 523 | #define S_030A00_LINE_STIPPLE_VALUE(x) (((x) & 0xFFFFFF) << 0) |
||
| 524 | #define G_030A00_LINE_STIPPLE_VALUE(x) (((x) >> 0) & 0xFFFFFF) |
||
| 525 | #define C_030A00_LINE_STIPPLE_VALUE 0xFF000000 |
||
| 526 | #define R_030A04_PA_SC_LINE_STIPPLE_STATE 0x030A04 |
||
| 527 | #define S_030A04_CURRENT_PTR(x) (((x) & 0x0F) << 0) |
||
| 528 | #define G_030A04_CURRENT_PTR(x) (((x) >> 0) & 0x0F) |
||
| 529 | #define C_030A04_CURRENT_PTR 0xFFFFFFF0 |
||
| 530 | #define S_030A04_CURRENT_COUNT(x) (((x) & 0xFF) << 8) |
||
| 531 | #define G_030A04_CURRENT_COUNT(x) (((x) >> 8) & 0xFF) |
||
| 532 | #define C_030A04_CURRENT_COUNT 0xFFFF00FF |
||
| 533 | /* */ |
||
| 534 | #define R_008BF0_PA_SC_ENHANCE 0x008BF0 |
||
| 535 | #define S_008BF0_ENABLE_PA_SC_OUT_OF_ORDER(x) (((x) & 0x1) << 0) |
||
| 536 | #define G_008BF0_ENABLE_PA_SC_OUT_OF_ORDER(x) (((x) >> 0) & 0x1) |
||
| 537 | #define C_008BF0_ENABLE_PA_SC_OUT_OF_ORDER 0xFFFFFFFE |
||
| 538 | #define S_008BF0_DISABLE_SC_DB_TILE_FIX(x) (((x) & 0x1) << 1) |
||
| 539 | #define G_008BF0_DISABLE_SC_DB_TILE_FIX(x) (((x) >> 1) & 0x1) |
||
| 540 | #define C_008BF0_DISABLE_SC_DB_TILE_FIX 0xFFFFFFFD |
||
| 541 | #define S_008BF0_DISABLE_AA_MASK_FULL_FIX(x) (((x) & 0x1) << 2) |
||
| 542 | #define G_008BF0_DISABLE_AA_MASK_FULL_FIX(x) (((x) >> 2) & 0x1) |
||
| 543 | #define C_008BF0_DISABLE_AA_MASK_FULL_FIX 0xFFFFFFFB |
||
| 544 | #define S_008BF0_ENABLE_1XMSAA_SAMPLE_LOCATIONS(x) (((x) & 0x1) << 3) |
||
| 545 | #define G_008BF0_ENABLE_1XMSAA_SAMPLE_LOCATIONS(x) (((x) >> 3) & 0x1) |
||
| 546 | #define C_008BF0_ENABLE_1XMSAA_SAMPLE_LOCATIONS 0xFFFFFFF7 |
||
| 547 | #define S_008BF0_ENABLE_1XMSAA_SAMPLE_LOC_CENTROID(x) (((x) & 0x1) << 4) |
||
| 548 | #define G_008BF0_ENABLE_1XMSAA_SAMPLE_LOC_CENTROID(x) (((x) >> 4) & 0x1) |
||
| 549 | #define C_008BF0_ENABLE_1XMSAA_SAMPLE_LOC_CENTROID 0xFFFFFFEF |
||
| 550 | #define S_008BF0_DISABLE_SCISSOR_FIX(x) (((x) & 0x1) << 5) |
||
| 551 | #define G_008BF0_DISABLE_SCISSOR_FIX(x) (((x) >> 5) & 0x1) |
||
| 552 | #define C_008BF0_DISABLE_SCISSOR_FIX 0xFFFFFFDF |
||
| 553 | #define S_008BF0_DISABLE_PW_BUBBLE_COLLAPSE(x) (((x) & 0x03) << 6) |
||
| 554 | #define G_008BF0_DISABLE_PW_BUBBLE_COLLAPSE(x) (((x) >> 6) & 0x03) |
||
| 555 | #define C_008BF0_DISABLE_PW_BUBBLE_COLLAPSE 0xFFFFFF3F |
||
| 556 | #define S_008BF0_SEND_UNLIT_STILES_TO_PACKER(x) (((x) & 0x1) << 8) |
||
| 557 | #define G_008BF0_SEND_UNLIT_STILES_TO_PACKER(x) (((x) >> 8) & 0x1) |
||
| 558 | #define C_008BF0_SEND_UNLIT_STILES_TO_PACKER 0xFFFFFEFF |
||
| 559 | #define S_008BF0_DISABLE_DUALGRAD_PERF_OPTIMIZATION(x) (((x) & 0x1) << 9) |
||
| 560 | #define G_008BF0_DISABLE_DUALGRAD_PERF_OPTIMIZATION(x) (((x) >> 9) & 0x1) |
||
| 561 | #define C_008BF0_DISABLE_DUALGRAD_PERF_OPTIMIZATION 0xFFFFFDFF |
||
| 562 | #define R_008C08_SQC_CACHES 0x008C08 |
||
| 563 | #define S_008C08_INST_INVALIDATE(x) (((x) & 0x1) << 0) |
||
| 564 | #define G_008C08_INST_INVALIDATE(x) (((x) >> 0) & 0x1) |
||
| 565 | #define C_008C08_INST_INVALIDATE 0xFFFFFFFE |
||
| 566 | #define S_008C08_DATA_INVALIDATE(x) (((x) & 0x1) << 1) |
||
| 567 | #define G_008C08_DATA_INVALIDATE(x) (((x) >> 1) & 0x1) |
||
| 568 | #define C_008C08_DATA_INVALIDATE 0xFFFFFFFD |
||
| 569 | /* CIK */ |
||
| 570 | #define R_030D20_SQC_CACHES 0x030D20 |
||
| 571 | #define S_030D20_INST_INVALIDATE(x) (((x) & 0x1) << 0) |
||
| 572 | #define G_030D20_INST_INVALIDATE(x) (((x) >> 0) & 0x1) |
||
| 573 | #define C_030D20_INST_INVALIDATE 0xFFFFFFFE |
||
| 574 | #define S_030D20_DATA_INVALIDATE(x) (((x) & 0x1) << 1) |
||
| 575 | #define G_030D20_DATA_INVALIDATE(x) (((x) >> 1) & 0x1) |
||
| 576 | #define C_030D20_DATA_INVALIDATE 0xFFFFFFFD |
||
| 577 | #define S_030D20_INVALIDATE_VOLATILE(x) (((x) & 0x1) << 2) |
||
| 578 | #define G_030D20_INVALIDATE_VOLATILE(x) (((x) >> 2) & 0x1) |
||
| 579 | #define C_030D20_INVALIDATE_VOLATILE 0xFFFFFFFB |
||
| 580 | /* */ |
||
| 581 | #define R_008C0C_SQ_RANDOM_WAVE_PRI 0x008C0C |
||
| 582 | #define S_008C0C_RET(x) (((x) & 0x7F) << 0) |
||
| 583 | #define G_008C0C_RET(x) (((x) >> 0) & 0x7F) |
||
| 584 | #define C_008C0C_RET 0xFFFFFF80 |
||
| 585 | #define S_008C0C_RUI(x) (((x) & 0x07) << 7) |
||
| 586 | #define G_008C0C_RUI(x) (((x) >> 7) & 0x07) |
||
| 587 | #define C_008C0C_RUI 0xFFFFFC7F |
||
| 588 | #define S_008C0C_RNG(x) (((x) & 0x7FF) << 10) |
||
| 589 | #define G_008C0C_RNG(x) (((x) >> 10) & 0x7FF) |
||
| 590 | #define C_008C0C_RNG 0xFFE003FF |
||
| 591 | #if 0 |
||
| 592 | /* CIK */ |
||
| 593 | #define R_008DFC_SQ_FLAT_1 0x008DFC |
||
| 594 | #define S_008DFC_ADDR(x) (((x) & 0xFF) << 0) |
||
| 595 | #define G_008DFC_ADDR(x) (((x) >> 0) & 0xFF) |
||
| 596 | #define C_008DFC_ADDR 0xFFFFFF00 |
||
| 597 | #define V_008DFC_SQ_VGPR 0x00 |
||
| 598 | #define S_008DFC_DATA(x) (((x) & 0xFF) << 8) |
||
| 599 | #define G_008DFC_DATA(x) (((x) >> 8) & 0xFF) |
||
| 600 | #define C_008DFC_DATA 0xFFFF00FF |
||
| 601 | #define V_008DFC_SQ_VGPR 0x00 |
||
| 602 | #define S_008DFC_TFE(x) (((x) & 0x1) << 23) |
||
| 603 | #define G_008DFC_TFE(x) (((x) >> 23) & 0x1) |
||
| 604 | #define C_008DFC_TFE 0xFF7FFFFF |
||
| 605 | #define S_008DFC_VDST(x) (((x) & 0xFF) << 24) |
||
| 606 | #define G_008DFC_VDST(x) (((x) >> 24) & 0xFF) |
||
| 607 | #define C_008DFC_VDST 0x00FFFFFF |
||
| 608 | #define V_008DFC_SQ_VGPR 0x00 |
||
| 609 | /* */ |
||
| 610 | #define R_008DFC_SQ_INST 0x008DFC |
||
| 611 | #define R_008DFC_SQ_VOP1 0x008DFC |
||
| 612 | #define S_008DFC_SRC0(x) (((x) & 0x1FF) << 0) |
||
| 613 | #define G_008DFC_SRC0(x) (((x) >> 0) & 0x1FF) |
||
| 614 | #define C_008DFC_SRC0 0xFFFFFE00 |
||
| 615 | #define V_008DFC_SQ_SGPR 0x00 |
||
| 616 | /* CIK */ |
||
| 617 | #define V_008DFC_SQ_FLAT_SCRATCH_LO 0x68 |
||
| 618 | #define V_008DFC_SQ_FLAT_SCRATCH_HI 0x69 |
||
| 619 | /* */ |
||
| 620 | #define V_008DFC_SQ_VCC_LO 0x6A |
||
| 621 | #define V_008DFC_SQ_VCC_HI 0x6B |
||
| 622 | #define V_008DFC_SQ_TBA_LO 0x6C |
||
| 623 | #define V_008DFC_SQ_TBA_HI 0x6D |
||
| 624 | #define V_008DFC_SQ_TMA_LO 0x6E |
||
| 625 | #define V_008DFC_SQ_TMA_HI 0x6F |
||
| 626 | #define V_008DFC_SQ_TTMP0 0x70 |
||
| 627 | #define V_008DFC_SQ_TTMP1 0x71 |
||
| 628 | #define V_008DFC_SQ_TTMP2 0x72 |
||
| 629 | #define V_008DFC_SQ_TTMP3 0x73 |
||
| 630 | #define V_008DFC_SQ_TTMP4 0x74 |
||
| 631 | #define V_008DFC_SQ_TTMP5 0x75 |
||
| 632 | #define V_008DFC_SQ_TTMP6 0x76 |
||
| 633 | #define V_008DFC_SQ_TTMP7 0x77 |
||
| 634 | #define V_008DFC_SQ_TTMP8 0x78 |
||
| 635 | #define V_008DFC_SQ_TTMP9 0x79 |
||
| 636 | #define V_008DFC_SQ_TTMP10 0x7A |
||
| 637 | #define V_008DFC_SQ_TTMP11 0x7B |
||
| 638 | #define V_008DFC_SQ_M0 0x7C |
||
| 639 | #define V_008DFC_SQ_EXEC_LO 0x7E |
||
| 640 | #define V_008DFC_SQ_EXEC_HI 0x7F |
||
| 641 | #define V_008DFC_SQ_SRC_0 0x80 |
||
| 642 | #define V_008DFC_SQ_SRC_1_INT 0x81 |
||
| 643 | #define V_008DFC_SQ_SRC_2_INT 0x82 |
||
| 644 | #define V_008DFC_SQ_SRC_3_INT 0x83 |
||
| 645 | #define V_008DFC_SQ_SRC_4_INT 0x84 |
||
| 646 | #define V_008DFC_SQ_SRC_5_INT 0x85 |
||
| 647 | #define V_008DFC_SQ_SRC_6_INT 0x86 |
||
| 648 | #define V_008DFC_SQ_SRC_7_INT 0x87 |
||
| 649 | #define V_008DFC_SQ_SRC_8_INT 0x88 |
||
| 650 | #define V_008DFC_SQ_SRC_9_INT 0x89 |
||
| 651 | #define V_008DFC_SQ_SRC_10_INT 0x8A |
||
| 652 | #define V_008DFC_SQ_SRC_11_INT 0x8B |
||
| 653 | #define V_008DFC_SQ_SRC_12_INT 0x8C |
||
| 654 | #define V_008DFC_SQ_SRC_13_INT 0x8D |
||
| 655 | #define V_008DFC_SQ_SRC_14_INT 0x8E |
||
| 656 | #define V_008DFC_SQ_SRC_15_INT 0x8F |
||
| 657 | #define V_008DFC_SQ_SRC_16_INT 0x90 |
||
| 658 | #define V_008DFC_SQ_SRC_17_INT 0x91 |
||
| 659 | #define V_008DFC_SQ_SRC_18_INT 0x92 |
||
| 660 | #define V_008DFC_SQ_SRC_19_INT 0x93 |
||
| 661 | #define V_008DFC_SQ_SRC_20_INT 0x94 |
||
| 662 | #define V_008DFC_SQ_SRC_21_INT 0x95 |
||
| 663 | #define V_008DFC_SQ_SRC_22_INT 0x96 |
||
| 664 | #define V_008DFC_SQ_SRC_23_INT 0x97 |
||
| 665 | #define V_008DFC_SQ_SRC_24_INT 0x98 |
||
| 666 | #define V_008DFC_SQ_SRC_25_INT 0x99 |
||
| 667 | #define V_008DFC_SQ_SRC_26_INT 0x9A |
||
| 668 | #define V_008DFC_SQ_SRC_27_INT 0x9B |
||
| 669 | #define V_008DFC_SQ_SRC_28_INT 0x9C |
||
| 670 | #define V_008DFC_SQ_SRC_29_INT 0x9D |
||
| 671 | #define V_008DFC_SQ_SRC_30_INT 0x9E |
||
| 672 | #define V_008DFC_SQ_SRC_31_INT 0x9F |
||
| 673 | #define V_008DFC_SQ_SRC_32_INT 0xA0 |
||
| 674 | #define V_008DFC_SQ_SRC_33_INT 0xA1 |
||
| 675 | #define V_008DFC_SQ_SRC_34_INT 0xA2 |
||
| 676 | #define V_008DFC_SQ_SRC_35_INT 0xA3 |
||
| 677 | #define V_008DFC_SQ_SRC_36_INT 0xA4 |
||
| 678 | #define V_008DFC_SQ_SRC_37_INT 0xA5 |
||
| 679 | #define V_008DFC_SQ_SRC_38_INT 0xA6 |
||
| 680 | #define V_008DFC_SQ_SRC_39_INT 0xA7 |
||
| 681 | #define V_008DFC_SQ_SRC_40_INT 0xA8 |
||
| 682 | #define V_008DFC_SQ_SRC_41_INT 0xA9 |
||
| 683 | #define V_008DFC_SQ_SRC_42_INT 0xAA |
||
| 684 | #define V_008DFC_SQ_SRC_43_INT 0xAB |
||
| 685 | #define V_008DFC_SQ_SRC_44_INT 0xAC |
||
| 686 | #define V_008DFC_SQ_SRC_45_INT 0xAD |
||
| 687 | #define V_008DFC_SQ_SRC_46_INT 0xAE |
||
| 688 | #define V_008DFC_SQ_SRC_47_INT 0xAF |
||
| 689 | #define V_008DFC_SQ_SRC_48_INT 0xB0 |
||
| 690 | #define V_008DFC_SQ_SRC_49_INT 0xB1 |
||
| 691 | #define V_008DFC_SQ_SRC_50_INT 0xB2 |
||
| 692 | #define V_008DFC_SQ_SRC_51_INT 0xB3 |
||
| 693 | #define V_008DFC_SQ_SRC_52_INT 0xB4 |
||
| 694 | #define V_008DFC_SQ_SRC_53_INT 0xB5 |
||
| 695 | #define V_008DFC_SQ_SRC_54_INT 0xB6 |
||
| 696 | #define V_008DFC_SQ_SRC_55_INT 0xB7 |
||
| 697 | #define V_008DFC_SQ_SRC_56_INT 0xB8 |
||
| 698 | #define V_008DFC_SQ_SRC_57_INT 0xB9 |
||
| 699 | #define V_008DFC_SQ_SRC_58_INT 0xBA |
||
| 700 | #define V_008DFC_SQ_SRC_59_INT 0xBB |
||
| 701 | #define V_008DFC_SQ_SRC_60_INT 0xBC |
||
| 702 | #define V_008DFC_SQ_SRC_61_INT 0xBD |
||
| 703 | #define V_008DFC_SQ_SRC_62_INT 0xBE |
||
| 704 | #define V_008DFC_SQ_SRC_63_INT 0xBF |
||
| 705 | #define V_008DFC_SQ_SRC_64_INT 0xC0 |
||
| 706 | #define V_008DFC_SQ_SRC_M_1_INT 0xC1 |
||
| 707 | #define V_008DFC_SQ_SRC_M_2_INT 0xC2 |
||
| 708 | #define V_008DFC_SQ_SRC_M_3_INT 0xC3 |
||
| 709 | #define V_008DFC_SQ_SRC_M_4_INT 0xC4 |
||
| 710 | #define V_008DFC_SQ_SRC_M_5_INT 0xC5 |
||
| 711 | #define V_008DFC_SQ_SRC_M_6_INT 0xC6 |
||
| 712 | #define V_008DFC_SQ_SRC_M_7_INT 0xC7 |
||
| 713 | #define V_008DFC_SQ_SRC_M_8_INT 0xC8 |
||
| 714 | #define V_008DFC_SQ_SRC_M_9_INT 0xC9 |
||
| 715 | #define V_008DFC_SQ_SRC_M_10_INT 0xCA |
||
| 716 | #define V_008DFC_SQ_SRC_M_11_INT 0xCB |
||
| 717 | #define V_008DFC_SQ_SRC_M_12_INT 0xCC |
||
| 718 | #define V_008DFC_SQ_SRC_M_13_INT 0xCD |
||
| 719 | #define V_008DFC_SQ_SRC_M_14_INT 0xCE |
||
| 720 | #define V_008DFC_SQ_SRC_M_15_INT 0xCF |
||
| 721 | #define V_008DFC_SQ_SRC_M_16_INT 0xD0 |
||
| 722 | #define V_008DFC_SQ_SRC_0_5 0xF0 |
||
| 723 | #define V_008DFC_SQ_SRC_M_0_5 0xF1 |
||
| 724 | #define V_008DFC_SQ_SRC_1 0xF2 |
||
| 725 | #define V_008DFC_SQ_SRC_M_1 0xF3 |
||
| 726 | #define V_008DFC_SQ_SRC_2 0xF4 |
||
| 727 | #define V_008DFC_SQ_SRC_M_2 0xF5 |
||
| 728 | #define V_008DFC_SQ_SRC_4 0xF6 |
||
| 729 | #define V_008DFC_SQ_SRC_M_4 0xF7 |
||
| 730 | #define V_008DFC_SQ_SRC_VCCZ 0xFB |
||
| 731 | #define V_008DFC_SQ_SRC_EXECZ 0xFC |
||
| 732 | #define V_008DFC_SQ_SRC_SCC 0xFD |
||
| 733 | #define V_008DFC_SQ_SRC_LDS_DIRECT 0xFE |
||
| 734 | #define V_008DFC_SQ_SRC_VGPR 0x100 |
||
| 735 | #define S_008DFC_OP(x) (((x) & 0xFF) << 9) |
||
| 736 | #define G_008DFC_OP(x) (((x) >> 9) & 0xFF) |
||
| 737 | #define C_008DFC_OP 0xFFFE01FF |
||
| 738 | #define V_008DFC_SQ_V_NOP 0x00 |
||
| 739 | #define V_008DFC_SQ_V_MOV_B32 0x01 |
||
| 740 | #define V_008DFC_SQ_V_READFIRSTLANE_B32 0x02 |
||
| 741 | #define V_008DFC_SQ_V_CVT_I32_F64 0x03 |
||
| 742 | #define V_008DFC_SQ_V_CVT_F64_I32 0x04 |
||
| 743 | #define V_008DFC_SQ_V_CVT_F32_I32 0x05 |
||
| 744 | #define V_008DFC_SQ_V_CVT_F32_U32 0x06 |
||
| 745 | #define V_008DFC_SQ_V_CVT_U32_F32 0x07 |
||
| 746 | #define V_008DFC_SQ_V_CVT_I32_F32 0x08 |
||
| 747 | #define V_008DFC_SQ_V_MOV_FED_B32 0x09 |
||
| 748 | #define V_008DFC_SQ_V_CVT_F16_F32 0x0A |
||
| 749 | #define V_008DFC_SQ_V_CVT_F32_F16 0x0B |
||
| 750 | #define V_008DFC_SQ_V_CVT_RPI_I32_F32 0x0C |
||
| 751 | #define V_008DFC_SQ_V_CVT_FLR_I32_F32 0x0D |
||
| 752 | #define V_008DFC_SQ_V_CVT_OFF_F32_I4 0x0E |
||
| 753 | #define V_008DFC_SQ_V_CVT_F32_F64 0x0F |
||
| 754 | #define V_008DFC_SQ_V_CVT_F64_F32 0x10 |
||
| 755 | #define V_008DFC_SQ_V_CVT_F32_UBYTE0 0x11 |
||
| 756 | #define V_008DFC_SQ_V_CVT_F32_UBYTE1 0x12 |
||
| 757 | #define V_008DFC_SQ_V_CVT_F32_UBYTE2 0x13 |
||
| 758 | #define V_008DFC_SQ_V_CVT_F32_UBYTE3 0x14 |
||
| 759 | #define V_008DFC_SQ_V_CVT_U32_F64 0x15 |
||
| 760 | #define V_008DFC_SQ_V_CVT_F64_U32 0x16 |
||
| 761 | /* CIK */ |
||
| 762 | #define V_008DFC_SQ_V_TRUNC_F64 0x17 |
||
| 763 | #define V_008DFC_SQ_V_CEIL_F64 0x18 |
||
| 764 | #define V_008DFC_SQ_V_RNDNE_F64 0x19 |
||
| 765 | #define V_008DFC_SQ_V_FLOOR_F64 0x1A |
||
| 766 | /* */ |
||
| 767 | #define V_008DFC_SQ_V_FRACT_F32 0x20 |
||
| 768 | #define V_008DFC_SQ_V_TRUNC_F32 0x21 |
||
| 769 | #define V_008DFC_SQ_V_CEIL_F32 0x22 |
||
| 770 | #define V_008DFC_SQ_V_RNDNE_F32 0x23 |
||
| 771 | #define V_008DFC_SQ_V_FLOOR_F32 0x24 |
||
| 772 | #define V_008DFC_SQ_V_EXP_F32 0x25 |
||
| 773 | #define V_008DFC_SQ_V_LOG_CLAMP_F32 0x26 |
||
| 774 | #define V_008DFC_SQ_V_LOG_F32 0x27 |
||
| 775 | #define V_008DFC_SQ_V_RCP_CLAMP_F32 0x28 |
||
| 776 | #define V_008DFC_SQ_V_RCP_LEGACY_F32 0x29 |
||
| 777 | #define V_008DFC_SQ_V_RCP_F32 0x2A |
||
| 778 | #define V_008DFC_SQ_V_RCP_IFLAG_F32 0x2B |
||
| 779 | #define V_008DFC_SQ_V_RSQ_CLAMP_F32 0x2C |
||
| 780 | #define V_008DFC_SQ_V_RSQ_LEGACY_F32 0x2D |
||
| 781 | #define V_008DFC_SQ_V_RSQ_F32 0x2E |
||
| 782 | #define V_008DFC_SQ_V_RCP_F64 0x2F |
||
| 783 | #define V_008DFC_SQ_V_RCP_CLAMP_F64 0x30 |
||
| 784 | #define V_008DFC_SQ_V_RSQ_F64 0x31 |
||
| 785 | #define V_008DFC_SQ_V_RSQ_CLAMP_F64 0x32 |
||
| 786 | #define V_008DFC_SQ_V_SQRT_F32 0x33 |
||
| 787 | #define V_008DFC_SQ_V_SQRT_F64 0x34 |
||
| 788 | #define V_008DFC_SQ_V_SIN_F32 0x35 |
||
| 789 | #define V_008DFC_SQ_V_COS_F32 0x36 |
||
| 790 | #define V_008DFC_SQ_V_NOT_B32 0x37 |
||
| 791 | #define V_008DFC_SQ_V_BFREV_B32 0x38 |
||
| 792 | #define V_008DFC_SQ_V_FFBH_U32 0x39 |
||
| 793 | #define V_008DFC_SQ_V_FFBL_B32 0x3A |
||
| 794 | #define V_008DFC_SQ_V_FFBH_I32 0x3B |
||
| 795 | #define V_008DFC_SQ_V_FREXP_EXP_I32_F64 0x3C |
||
| 796 | #define V_008DFC_SQ_V_FREXP_MANT_F64 0x3D |
||
| 797 | #define V_008DFC_SQ_V_FRACT_F64 0x3E |
||
| 798 | #define V_008DFC_SQ_V_FREXP_EXP_I32_F32 0x3F |
||
| 799 | #define V_008DFC_SQ_V_FREXP_MANT_F32 0x40 |
||
| 800 | #define V_008DFC_SQ_V_CLREXCP 0x41 |
||
| 801 | #define V_008DFC_SQ_V_MOVRELD_B32 0x42 |
||
| 802 | #define V_008DFC_SQ_V_MOVRELS_B32 0x43 |
||
| 803 | #define V_008DFC_SQ_V_MOVRELSD_B32 0x44 |
||
| 804 | /* CIK */ |
||
| 805 | #define V_008DFC_SQ_V_LOG_LEGACY_F32 0x45 |
||
| 806 | #define V_008DFC_SQ_V_EXP_LEGACY_F32 0x46 |
||
| 807 | /* */ |
||
| 808 | #define S_008DFC_VDST(x) (((x) & 0xFF) << 17) |
||
| 809 | #define G_008DFC_VDST(x) (((x) >> 17) & 0xFF) |
||
| 810 | #define C_008DFC_VDST 0xFE01FFFF |
||
| 811 | #define V_008DFC_SQ_VGPR 0x00 |
||
| 812 | #define S_008DFC_ENCODING(x) (((x) & 0x7F) << 25) |
||
| 813 | #define G_008DFC_ENCODING(x) (((x) >> 25) & 0x7F) |
||
| 814 | #define C_008DFC_ENCODING 0x01FFFFFF |
||
| 815 | #define V_008DFC_SQ_ENC_VOP1_FIELD 0x3F |
||
| 816 | #define R_008DFC_SQ_MIMG_1 0x008DFC |
||
| 817 | #define S_008DFC_VADDR(x) (((x) & 0xFF) << 0) |
||
| 818 | #define G_008DFC_VADDR(x) (((x) >> 0) & 0xFF) |
||
| 819 | #define C_008DFC_VADDR 0xFFFFFF00 |
||
| 820 | #define V_008DFC_SQ_VGPR 0x00 |
||
| 821 | #define S_008DFC_VDATA(x) (((x) & 0xFF) << 8) |
||
| 822 | #define G_008DFC_VDATA(x) (((x) >> 8) & 0xFF) |
||
| 823 | #define C_008DFC_VDATA 0xFFFF00FF |
||
| 824 | #define V_008DFC_SQ_VGPR 0x00 |
||
| 825 | #define S_008DFC_SRSRC(x) (((x) & 0x1F) << 16) |
||
| 826 | #define G_008DFC_SRSRC(x) (((x) >> 16) & 0x1F) |
||
| 827 | #define C_008DFC_SRSRC 0xFFE0FFFF |
||
| 828 | #define S_008DFC_SSAMP(x) (((x) & 0x1F) << 21) |
||
| 829 | #define G_008DFC_SSAMP(x) (((x) >> 21) & 0x1F) |
||
| 830 | #define C_008DFC_SSAMP 0xFC1FFFFF |
||
| 831 | #define R_008DFC_SQ_VOP3_1 0x008DFC |
||
| 832 | #define S_008DFC_SRC0(x) (((x) & 0x1FF) << 0) |
||
| 833 | #define G_008DFC_SRC0(x) (((x) >> 0) & 0x1FF) |
||
| 834 | #define C_008DFC_SRC0 0xFFFFFE00 |
||
| 835 | #define V_008DFC_SQ_SGPR 0x00 |
||
| 836 | /* CIK */ |
||
| 837 | #define V_008DFC_SQ_FLAT_SCRATCH_LO 0x68 |
||
| 838 | #define V_008DFC_SQ_FLAT_SCRATCH_HI 0x69 |
||
| 839 | /* */ |
||
| 840 | #define V_008DFC_SQ_VCC_LO 0x6A |
||
| 841 | #define V_008DFC_SQ_VCC_HI 0x6B |
||
| 842 | #define V_008DFC_SQ_TBA_LO 0x6C |
||
| 843 | #define V_008DFC_SQ_TBA_HI 0x6D |
||
| 844 | #define V_008DFC_SQ_TMA_LO 0x6E |
||
| 845 | #define V_008DFC_SQ_TMA_HI 0x6F |
||
| 846 | #define V_008DFC_SQ_TTMP0 0x70 |
||
| 847 | #define V_008DFC_SQ_TTMP1 0x71 |
||
| 848 | #define V_008DFC_SQ_TTMP2 0x72 |
||
| 849 | #define V_008DFC_SQ_TTMP3 0x73 |
||
| 850 | #define V_008DFC_SQ_TTMP4 0x74 |
||
| 851 | #define V_008DFC_SQ_TTMP5 0x75 |
||
| 852 | #define V_008DFC_SQ_TTMP6 0x76 |
||
| 853 | #define V_008DFC_SQ_TTMP7 0x77 |
||
| 854 | #define V_008DFC_SQ_TTMP8 0x78 |
||
| 855 | #define V_008DFC_SQ_TTMP9 0x79 |
||
| 856 | #define V_008DFC_SQ_TTMP10 0x7A |
||
| 857 | #define V_008DFC_SQ_TTMP11 0x7B |
||
| 858 | #define V_008DFC_SQ_M0 0x7C |
||
| 859 | #define V_008DFC_SQ_EXEC_LO 0x7E |
||
| 860 | #define V_008DFC_SQ_EXEC_HI 0x7F |
||
| 861 | #define V_008DFC_SQ_SRC_0 0x80 |
||
| 862 | #define V_008DFC_SQ_SRC_1_INT 0x81 |
||
| 863 | #define V_008DFC_SQ_SRC_2_INT 0x82 |
||
| 864 | #define V_008DFC_SQ_SRC_3_INT 0x83 |
||
| 865 | #define V_008DFC_SQ_SRC_4_INT 0x84 |
||
| 866 | #define V_008DFC_SQ_SRC_5_INT 0x85 |
||
| 867 | #define V_008DFC_SQ_SRC_6_INT 0x86 |
||
| 868 | #define V_008DFC_SQ_SRC_7_INT 0x87 |
||
| 869 | #define V_008DFC_SQ_SRC_8_INT 0x88 |
||
| 870 | #define V_008DFC_SQ_SRC_9_INT 0x89 |
||
| 871 | #define V_008DFC_SQ_SRC_10_INT 0x8A |
||
| 872 | #define V_008DFC_SQ_SRC_11_INT 0x8B |
||
| 873 | #define V_008DFC_SQ_SRC_12_INT 0x8C |
||
| 874 | #define V_008DFC_SQ_SRC_13_INT 0x8D |
||
| 875 | #define V_008DFC_SQ_SRC_14_INT 0x8E |
||
| 876 | #define V_008DFC_SQ_SRC_15_INT 0x8F |
||
| 877 | #define V_008DFC_SQ_SRC_16_INT 0x90 |
||
| 878 | #define V_008DFC_SQ_SRC_17_INT 0x91 |
||
| 879 | #define V_008DFC_SQ_SRC_18_INT 0x92 |
||
| 880 | #define V_008DFC_SQ_SRC_19_INT 0x93 |
||
| 881 | #define V_008DFC_SQ_SRC_20_INT 0x94 |
||
| 882 | #define V_008DFC_SQ_SRC_21_INT 0x95 |
||
| 883 | #define V_008DFC_SQ_SRC_22_INT 0x96 |
||
| 884 | #define V_008DFC_SQ_SRC_23_INT 0x97 |
||
| 885 | #define V_008DFC_SQ_SRC_24_INT 0x98 |
||
| 886 | #define V_008DFC_SQ_SRC_25_INT 0x99 |
||
| 887 | #define V_008DFC_SQ_SRC_26_INT 0x9A |
||
| 888 | #define V_008DFC_SQ_SRC_27_INT 0x9B |
||
| 889 | #define V_008DFC_SQ_SRC_28_INT 0x9C |
||
| 890 | #define V_008DFC_SQ_SRC_29_INT 0x9D |
||
| 891 | #define V_008DFC_SQ_SRC_30_INT 0x9E |
||
| 892 | #define V_008DFC_SQ_SRC_31_INT 0x9F |
||
| 893 | #define V_008DFC_SQ_SRC_32_INT 0xA0 |
||
| 894 | #define V_008DFC_SQ_SRC_33_INT 0xA1 |
||
| 895 | #define V_008DFC_SQ_SRC_34_INT 0xA2 |
||
| 896 | #define V_008DFC_SQ_SRC_35_INT 0xA3 |
||
| 897 | #define V_008DFC_SQ_SRC_36_INT 0xA4 |
||
| 898 | #define V_008DFC_SQ_SRC_37_INT 0xA5 |
||
| 899 | #define V_008DFC_SQ_SRC_38_INT 0xA6 |
||
| 900 | #define V_008DFC_SQ_SRC_39_INT 0xA7 |
||
| 901 | #define V_008DFC_SQ_SRC_40_INT 0xA8 |
||
| 902 | #define V_008DFC_SQ_SRC_41_INT 0xA9 |
||
| 903 | #define V_008DFC_SQ_SRC_42_INT 0xAA |
||
| 904 | #define V_008DFC_SQ_SRC_43_INT 0xAB |
||
| 905 | #define V_008DFC_SQ_SRC_44_INT 0xAC |
||
| 906 | #define V_008DFC_SQ_SRC_45_INT 0xAD |
||
| 907 | #define V_008DFC_SQ_SRC_46_INT 0xAE |
||
| 908 | #define V_008DFC_SQ_SRC_47_INT 0xAF |
||
| 909 | #define V_008DFC_SQ_SRC_48_INT 0xB0 |
||
| 910 | #define V_008DFC_SQ_SRC_49_INT 0xB1 |
||
| 911 | #define V_008DFC_SQ_SRC_50_INT 0xB2 |
||
| 912 | #define V_008DFC_SQ_SRC_51_INT 0xB3 |
||
| 913 | #define V_008DFC_SQ_SRC_52_INT 0xB4 |
||
| 914 | #define V_008DFC_SQ_SRC_53_INT 0xB5 |
||
| 915 | #define V_008DFC_SQ_SRC_54_INT 0xB6 |
||
| 916 | #define V_008DFC_SQ_SRC_55_INT 0xB7 |
||
| 917 | #define V_008DFC_SQ_SRC_56_INT 0xB8 |
||
| 918 | #define V_008DFC_SQ_SRC_57_INT 0xB9 |
||
| 919 | #define V_008DFC_SQ_SRC_58_INT 0xBA |
||
| 920 | #define V_008DFC_SQ_SRC_59_INT 0xBB |
||
| 921 | #define V_008DFC_SQ_SRC_60_INT 0xBC |
||
| 922 | #define V_008DFC_SQ_SRC_61_INT 0xBD |
||
| 923 | #define V_008DFC_SQ_SRC_62_INT 0xBE |
||
| 924 | #define V_008DFC_SQ_SRC_63_INT 0xBF |
||
| 925 | #define V_008DFC_SQ_SRC_64_INT 0xC0 |
||
| 926 | #define V_008DFC_SQ_SRC_M_1_INT 0xC1 |
||
| 927 | #define V_008DFC_SQ_SRC_M_2_INT 0xC2 |
||
| 928 | #define V_008DFC_SQ_SRC_M_3_INT 0xC3 |
||
| 929 | #define V_008DFC_SQ_SRC_M_4_INT 0xC4 |
||
| 930 | #define V_008DFC_SQ_SRC_M_5_INT 0xC5 |
||
| 931 | #define V_008DFC_SQ_SRC_M_6_INT 0xC6 |
||
| 932 | #define V_008DFC_SQ_SRC_M_7_INT 0xC7 |
||
| 933 | #define V_008DFC_SQ_SRC_M_8_INT 0xC8 |
||
| 934 | #define V_008DFC_SQ_SRC_M_9_INT 0xC9 |
||
| 935 | #define V_008DFC_SQ_SRC_M_10_INT 0xCA |
||
| 936 | #define V_008DFC_SQ_SRC_M_11_INT 0xCB |
||
| 937 | #define V_008DFC_SQ_SRC_M_12_INT 0xCC |
||
| 938 | #define V_008DFC_SQ_SRC_M_13_INT 0xCD |
||
| 939 | #define V_008DFC_SQ_SRC_M_14_INT 0xCE |
||
| 940 | #define V_008DFC_SQ_SRC_M_15_INT 0xCF |
||
| 941 | #define V_008DFC_SQ_SRC_M_16_INT 0xD0 |
||
| 942 | #define V_008DFC_SQ_SRC_0_5 0xF0 |
||
| 943 | #define V_008DFC_SQ_SRC_M_0_5 0xF1 |
||
| 944 | #define V_008DFC_SQ_SRC_1 0xF2 |
||
| 945 | #define V_008DFC_SQ_SRC_M_1 0xF3 |
||
| 946 | #define V_008DFC_SQ_SRC_2 0xF4 |
||
| 947 | #define V_008DFC_SQ_SRC_M_2 0xF5 |
||
| 948 | #define V_008DFC_SQ_SRC_4 0xF6 |
||
| 949 | #define V_008DFC_SQ_SRC_M_4 0xF7 |
||
| 950 | #define V_008DFC_SQ_SRC_VCCZ 0xFB |
||
| 951 | #define V_008DFC_SQ_SRC_EXECZ 0xFC |
||
| 952 | #define V_008DFC_SQ_SRC_SCC 0xFD |
||
| 953 | #define V_008DFC_SQ_SRC_LDS_DIRECT 0xFE |
||
| 954 | #define V_008DFC_SQ_SRC_VGPR 0x100 |
||
| 955 | #define S_008DFC_SRC1(x) (((x) & 0x1FF) << 9) |
||
| 956 | #define G_008DFC_SRC1(x) (((x) >> 9) & 0x1FF) |
||
| 957 | #define C_008DFC_SRC1 0xFFFC01FF |
||
| 958 | #define V_008DFC_SQ_SGPR 0x00 |
||
| 959 | /* CIK */ |
||
| 960 | #define V_008DFC_SQ_FLAT_SCRATCH_LO 0x68 |
||
| 961 | #define V_008DFC_SQ_FLAT_SCRATCH_HI 0x69 |
||
| 962 | /* */ |
||
| 963 | #define V_008DFC_SQ_VCC_LO 0x6A |
||
| 964 | #define V_008DFC_SQ_VCC_HI 0x6B |
||
| 965 | #define V_008DFC_SQ_TBA_LO 0x6C |
||
| 966 | #define V_008DFC_SQ_TBA_HI 0x6D |
||
| 967 | #define V_008DFC_SQ_TMA_LO 0x6E |
||
| 968 | #define V_008DFC_SQ_TMA_HI 0x6F |
||
| 969 | #define V_008DFC_SQ_TTMP0 0x70 |
||
| 970 | #define V_008DFC_SQ_TTMP1 0x71 |
||
| 971 | #define V_008DFC_SQ_TTMP2 0x72 |
||
| 972 | #define V_008DFC_SQ_TTMP3 0x73 |
||
| 973 | #define V_008DFC_SQ_TTMP4 0x74 |
||
| 974 | #define V_008DFC_SQ_TTMP5 0x75 |
||
| 975 | #define V_008DFC_SQ_TTMP6 0x76 |
||
| 976 | #define V_008DFC_SQ_TTMP7 0x77 |
||
| 977 | #define V_008DFC_SQ_TTMP8 0x78 |
||
| 978 | #define V_008DFC_SQ_TTMP9 0x79 |
||
| 979 | #define V_008DFC_SQ_TTMP10 0x7A |
||
| 980 | #define V_008DFC_SQ_TTMP11 0x7B |
||
| 981 | #define V_008DFC_SQ_M0 0x7C |
||
| 982 | #define V_008DFC_SQ_EXEC_LO 0x7E |
||
| 983 | #define V_008DFC_SQ_EXEC_HI 0x7F |
||
| 984 | #define V_008DFC_SQ_SRC_0 0x80 |
||
| 985 | #define V_008DFC_SQ_SRC_1_INT 0x81 |
||
| 986 | #define V_008DFC_SQ_SRC_2_INT 0x82 |
||
| 987 | #define V_008DFC_SQ_SRC_3_INT 0x83 |
||
| 988 | #define V_008DFC_SQ_SRC_4_INT 0x84 |
||
| 989 | #define V_008DFC_SQ_SRC_5_INT 0x85 |
||
| 990 | #define V_008DFC_SQ_SRC_6_INT 0x86 |
||
| 991 | #define V_008DFC_SQ_SRC_7_INT 0x87 |
||
| 992 | #define V_008DFC_SQ_SRC_8_INT 0x88 |
||
| 993 | #define V_008DFC_SQ_SRC_9_INT 0x89 |
||
| 994 | #define V_008DFC_SQ_SRC_10_INT 0x8A |
||
| 995 | #define V_008DFC_SQ_SRC_11_INT 0x8B |
||
| 996 | #define V_008DFC_SQ_SRC_12_INT 0x8C |
||
| 997 | #define V_008DFC_SQ_SRC_13_INT 0x8D |
||
| 998 | #define V_008DFC_SQ_SRC_14_INT 0x8E |
||
| 999 | #define V_008DFC_SQ_SRC_15_INT 0x8F |
||
| 1000 | #define V_008DFC_SQ_SRC_16_INT 0x90 |
||
| 1001 | #define V_008DFC_SQ_SRC_17_INT 0x91 |
||
| 1002 | #define V_008DFC_SQ_SRC_18_INT 0x92 |
||
| 1003 | #define V_008DFC_SQ_SRC_19_INT 0x93 |
||
| 1004 | #define V_008DFC_SQ_SRC_20_INT 0x94 |
||
| 1005 | #define V_008DFC_SQ_SRC_21_INT 0x95 |
||
| 1006 | #define V_008DFC_SQ_SRC_22_INT 0x96 |
||
| 1007 | #define V_008DFC_SQ_SRC_23_INT 0x97 |
||
| 1008 | #define V_008DFC_SQ_SRC_24_INT 0x98 |
||
| 1009 | #define V_008DFC_SQ_SRC_25_INT 0x99 |
||
| 1010 | #define V_008DFC_SQ_SRC_26_INT 0x9A |
||
| 1011 | #define V_008DFC_SQ_SRC_27_INT 0x9B |
||
| 1012 | #define V_008DFC_SQ_SRC_28_INT 0x9C |
||
| 1013 | #define V_008DFC_SQ_SRC_29_INT 0x9D |
||
| 1014 | #define V_008DFC_SQ_SRC_30_INT 0x9E |
||
| 1015 | #define V_008DFC_SQ_SRC_31_INT 0x9F |
||
| 1016 | #define V_008DFC_SQ_SRC_32_INT 0xA0 |
||
| 1017 | #define V_008DFC_SQ_SRC_33_INT 0xA1 |
||
| 1018 | #define V_008DFC_SQ_SRC_34_INT 0xA2 |
||
| 1019 | #define V_008DFC_SQ_SRC_35_INT 0xA3 |
||
| 1020 | #define V_008DFC_SQ_SRC_36_INT 0xA4 |
||
| 1021 | #define V_008DFC_SQ_SRC_37_INT 0xA5 |
||
| 1022 | #define V_008DFC_SQ_SRC_38_INT 0xA6 |
||
| 1023 | #define V_008DFC_SQ_SRC_39_INT 0xA7 |
||
| 1024 | #define V_008DFC_SQ_SRC_40_INT 0xA8 |
||
| 1025 | #define V_008DFC_SQ_SRC_41_INT 0xA9 |
||
| 1026 | #define V_008DFC_SQ_SRC_42_INT 0xAA |
||
| 1027 | #define V_008DFC_SQ_SRC_43_INT 0xAB |
||
| 1028 | #define V_008DFC_SQ_SRC_44_INT 0xAC |
||
| 1029 | #define V_008DFC_SQ_SRC_45_INT 0xAD |
||
| 1030 | #define V_008DFC_SQ_SRC_46_INT 0xAE |
||
| 1031 | #define V_008DFC_SQ_SRC_47_INT 0xAF |
||
| 1032 | #define V_008DFC_SQ_SRC_48_INT 0xB0 |
||
| 1033 | #define V_008DFC_SQ_SRC_49_INT 0xB1 |
||
| 1034 | #define V_008DFC_SQ_SRC_50_INT 0xB2 |
||
| 1035 | #define V_008DFC_SQ_SRC_51_INT 0xB3 |
||
| 1036 | #define V_008DFC_SQ_SRC_52_INT 0xB4 |
||
| 1037 | #define V_008DFC_SQ_SRC_53_INT 0xB5 |
||
| 1038 | #define V_008DFC_SQ_SRC_54_INT 0xB6 |
||
| 1039 | #define V_008DFC_SQ_SRC_55_INT 0xB7 |
||
| 1040 | #define V_008DFC_SQ_SRC_56_INT 0xB8 |
||
| 1041 | #define V_008DFC_SQ_SRC_57_INT 0xB9 |
||
| 1042 | #define V_008DFC_SQ_SRC_58_INT 0xBA |
||
| 1043 | #define V_008DFC_SQ_SRC_59_INT 0xBB |
||
| 1044 | #define V_008DFC_SQ_SRC_60_INT 0xBC |
||
| 1045 | #define V_008DFC_SQ_SRC_61_INT 0xBD |
||
| 1046 | #define V_008DFC_SQ_SRC_62_INT 0xBE |
||
| 1047 | #define V_008DFC_SQ_SRC_63_INT 0xBF |
||
| 1048 | #define V_008DFC_SQ_SRC_64_INT 0xC0 |
||
| 1049 | #define V_008DFC_SQ_SRC_M_1_INT 0xC1 |
||
| 1050 | #define V_008DFC_SQ_SRC_M_2_INT 0xC2 |
||
| 1051 | #define V_008DFC_SQ_SRC_M_3_INT 0xC3 |
||
| 1052 | #define V_008DFC_SQ_SRC_M_4_INT 0xC4 |
||
| 1053 | #define V_008DFC_SQ_SRC_M_5_INT 0xC5 |
||
| 1054 | #define V_008DFC_SQ_SRC_M_6_INT 0xC6 |
||
| 1055 | #define V_008DFC_SQ_SRC_M_7_INT 0xC7 |
||
| 1056 | #define V_008DFC_SQ_SRC_M_8_INT 0xC8 |
||
| 1057 | #define V_008DFC_SQ_SRC_M_9_INT 0xC9 |
||
| 1058 | #define V_008DFC_SQ_SRC_M_10_INT 0xCA |
||
| 1059 | #define V_008DFC_SQ_SRC_M_11_INT 0xCB |
||
| 1060 | #define V_008DFC_SQ_SRC_M_12_INT 0xCC |
||
| 1061 | #define V_008DFC_SQ_SRC_M_13_INT 0xCD |
||
| 1062 | #define V_008DFC_SQ_SRC_M_14_INT 0xCE |
||
| 1063 | #define V_008DFC_SQ_SRC_M_15_INT 0xCF |
||
| 1064 | #define V_008DFC_SQ_SRC_M_16_INT 0xD0 |
||
| 1065 | #define V_008DFC_SQ_SRC_0_5 0xF0 |
||
| 1066 | #define V_008DFC_SQ_SRC_M_0_5 0xF1 |
||
| 1067 | #define V_008DFC_SQ_SRC_1 0xF2 |
||
| 1068 | #define V_008DFC_SQ_SRC_M_1 0xF3 |
||
| 1069 | #define V_008DFC_SQ_SRC_2 0xF4 |
||
| 1070 | #define V_008DFC_SQ_SRC_M_2 0xF5 |
||
| 1071 | #define V_008DFC_SQ_SRC_4 0xF6 |
||
| 1072 | #define V_008DFC_SQ_SRC_M_4 0xF7 |
||
| 1073 | #define V_008DFC_SQ_SRC_VCCZ 0xFB |
||
| 1074 | #define V_008DFC_SQ_SRC_EXECZ 0xFC |
||
| 1075 | #define V_008DFC_SQ_SRC_SCC 0xFD |
||
| 1076 | #define V_008DFC_SQ_SRC_LDS_DIRECT 0xFE |
||
| 1077 | #define V_008DFC_SQ_SRC_VGPR 0x100 |
||
| 1078 | #define S_008DFC_SRC2(x) (((x) & 0x1FF) << 18) |
||
| 1079 | #define G_008DFC_SRC2(x) (((x) >> 18) & 0x1FF) |
||
| 1080 | #define C_008DFC_SRC2 0xF803FFFF |
||
| 1081 | #define V_008DFC_SQ_SGPR 0x00 |
||
| 1082 | /* CIK */ |
||
| 1083 | #define V_008DFC_SQ_FLAT_SCRATCH_LO 0x68 |
||
| 1084 | #define V_008DFC_SQ_FLAT_SCRATCH_HI 0x69 |
||
| 1085 | /* */ |
||
| 1086 | #define V_008DFC_SQ_VCC_LO 0x6A |
||
| 1087 | #define V_008DFC_SQ_VCC_HI 0x6B |
||
| 1088 | #define V_008DFC_SQ_TBA_LO 0x6C |
||
| 1089 | #define V_008DFC_SQ_TBA_HI 0x6D |
||
| 1090 | #define V_008DFC_SQ_TMA_LO 0x6E |
||
| 1091 | #define V_008DFC_SQ_TMA_HI 0x6F |
||
| 1092 | #define V_008DFC_SQ_TTMP0 0x70 |
||
| 1093 | #define V_008DFC_SQ_TTMP1 0x71 |
||
| 1094 | #define V_008DFC_SQ_TTMP2 0x72 |
||
| 1095 | #define V_008DFC_SQ_TTMP3 0x73 |
||
| 1096 | #define V_008DFC_SQ_TTMP4 0x74 |
||
| 1097 | #define V_008DFC_SQ_TTMP5 0x75 |
||
| 1098 | #define V_008DFC_SQ_TTMP6 0x76 |
||
| 1099 | #define V_008DFC_SQ_TTMP7 0x77 |
||
| 1100 | #define V_008DFC_SQ_TTMP8 0x78 |
||
| 1101 | #define V_008DFC_SQ_TTMP9 0x79 |
||
| 1102 | #define V_008DFC_SQ_TTMP10 0x7A |
||
| 1103 | #define V_008DFC_SQ_TTMP11 0x7B |
||
| 1104 | #define V_008DFC_SQ_M0 0x7C |
||
| 1105 | #define V_008DFC_SQ_EXEC_LO 0x7E |
||
| 1106 | #define V_008DFC_SQ_EXEC_HI 0x7F |
||
| 1107 | #define V_008DFC_SQ_SRC_0 0x80 |
||
| 1108 | #define V_008DFC_SQ_SRC_1_INT 0x81 |
||
| 1109 | #define V_008DFC_SQ_SRC_2_INT 0x82 |
||
| 1110 | #define V_008DFC_SQ_SRC_3_INT 0x83 |
||
| 1111 | #define V_008DFC_SQ_SRC_4_INT 0x84 |
||
| 1112 | #define V_008DFC_SQ_SRC_5_INT 0x85 |
||
| 1113 | #define V_008DFC_SQ_SRC_6_INT 0x86 |
||
| 1114 | #define V_008DFC_SQ_SRC_7_INT 0x87 |
||
| 1115 | #define V_008DFC_SQ_SRC_8_INT 0x88 |
||
| 1116 | #define V_008DFC_SQ_SRC_9_INT 0x89 |
||
| 1117 | #define V_008DFC_SQ_SRC_10_INT 0x8A |
||
| 1118 | #define V_008DFC_SQ_SRC_11_INT 0x8B |
||
| 1119 | #define V_008DFC_SQ_SRC_12_INT 0x8C |
||
| 1120 | #define V_008DFC_SQ_SRC_13_INT 0x8D |
||
| 1121 | #define V_008DFC_SQ_SRC_14_INT 0x8E |
||
| 1122 | #define V_008DFC_SQ_SRC_15_INT 0x8F |
||
| 1123 | #define V_008DFC_SQ_SRC_16_INT 0x90 |
||
| 1124 | #define V_008DFC_SQ_SRC_17_INT 0x91 |
||
| 1125 | #define V_008DFC_SQ_SRC_18_INT 0x92 |
||
| 1126 | #define V_008DFC_SQ_SRC_19_INT 0x93 |
||
| 1127 | #define V_008DFC_SQ_SRC_20_INT 0x94 |
||
| 1128 | #define V_008DFC_SQ_SRC_21_INT 0x95 |
||
| 1129 | #define V_008DFC_SQ_SRC_22_INT 0x96 |
||
| 1130 | #define V_008DFC_SQ_SRC_23_INT 0x97 |
||
| 1131 | #define V_008DFC_SQ_SRC_24_INT 0x98 |
||
| 1132 | #define V_008DFC_SQ_SRC_25_INT 0x99 |
||
| 1133 | #define V_008DFC_SQ_SRC_26_INT 0x9A |
||
| 1134 | #define V_008DFC_SQ_SRC_27_INT 0x9B |
||
| 1135 | #define V_008DFC_SQ_SRC_28_INT 0x9C |
||
| 1136 | #define V_008DFC_SQ_SRC_29_INT 0x9D |
||
| 1137 | #define V_008DFC_SQ_SRC_30_INT 0x9E |
||
| 1138 | #define V_008DFC_SQ_SRC_31_INT 0x9F |
||
| 1139 | #define V_008DFC_SQ_SRC_32_INT 0xA0 |
||
| 1140 | #define V_008DFC_SQ_SRC_33_INT 0xA1 |
||
| 1141 | #define V_008DFC_SQ_SRC_34_INT 0xA2 |
||
| 1142 | #define V_008DFC_SQ_SRC_35_INT 0xA3 |
||
| 1143 | #define V_008DFC_SQ_SRC_36_INT 0xA4 |
||
| 1144 | #define V_008DFC_SQ_SRC_37_INT 0xA5 |
||
| 1145 | #define V_008DFC_SQ_SRC_38_INT 0xA6 |
||
| 1146 | #define V_008DFC_SQ_SRC_39_INT 0xA7 |
||
| 1147 | #define V_008DFC_SQ_SRC_40_INT 0xA8 |
||
| 1148 | #define V_008DFC_SQ_SRC_41_INT 0xA9 |
||
| 1149 | #define V_008DFC_SQ_SRC_42_INT 0xAA |
||
| 1150 | #define V_008DFC_SQ_SRC_43_INT 0xAB |
||
| 1151 | #define V_008DFC_SQ_SRC_44_INT 0xAC |
||
| 1152 | #define V_008DFC_SQ_SRC_45_INT 0xAD |
||
| 1153 | #define V_008DFC_SQ_SRC_46_INT 0xAE |
||
| 1154 | #define V_008DFC_SQ_SRC_47_INT 0xAF |
||
| 1155 | #define V_008DFC_SQ_SRC_48_INT 0xB0 |
||
| 1156 | #define V_008DFC_SQ_SRC_49_INT 0xB1 |
||
| 1157 | #define V_008DFC_SQ_SRC_50_INT 0xB2 |
||
| 1158 | #define V_008DFC_SQ_SRC_51_INT 0xB3 |
||
| 1159 | #define V_008DFC_SQ_SRC_52_INT 0xB4 |
||
| 1160 | #define V_008DFC_SQ_SRC_53_INT 0xB5 |
||
| 1161 | #define V_008DFC_SQ_SRC_54_INT 0xB6 |
||
| 1162 | #define V_008DFC_SQ_SRC_55_INT 0xB7 |
||
| 1163 | #define V_008DFC_SQ_SRC_56_INT 0xB8 |
||
| 1164 | #define V_008DFC_SQ_SRC_57_INT 0xB9 |
||
| 1165 | #define V_008DFC_SQ_SRC_58_INT 0xBA |
||
| 1166 | #define V_008DFC_SQ_SRC_59_INT 0xBB |
||
| 1167 | #define V_008DFC_SQ_SRC_60_INT 0xBC |
||
| 1168 | #define V_008DFC_SQ_SRC_61_INT 0xBD |
||
| 1169 | #define V_008DFC_SQ_SRC_62_INT 0xBE |
||
| 1170 | #define V_008DFC_SQ_SRC_63_INT 0xBF |
||
| 1171 | #define V_008DFC_SQ_SRC_64_INT 0xC0 |
||
| 1172 | #define V_008DFC_SQ_SRC_M_1_INT 0xC1 |
||
| 1173 | #define V_008DFC_SQ_SRC_M_2_INT 0xC2 |
||
| 1174 | #define V_008DFC_SQ_SRC_M_3_INT 0xC3 |
||
| 1175 | #define V_008DFC_SQ_SRC_M_4_INT 0xC4 |
||
| 1176 | #define V_008DFC_SQ_SRC_M_5_INT 0xC5 |
||
| 1177 | #define V_008DFC_SQ_SRC_M_6_INT 0xC6 |
||
| 1178 | #define V_008DFC_SQ_SRC_M_7_INT 0xC7 |
||
| 1179 | #define V_008DFC_SQ_SRC_M_8_INT 0xC8 |
||
| 1180 | #define V_008DFC_SQ_SRC_M_9_INT 0xC9 |
||
| 1181 | #define V_008DFC_SQ_SRC_M_10_INT 0xCA |
||
| 1182 | #define V_008DFC_SQ_SRC_M_11_INT 0xCB |
||
| 1183 | #define V_008DFC_SQ_SRC_M_12_INT 0xCC |
||
| 1184 | #define V_008DFC_SQ_SRC_M_13_INT 0xCD |
||
| 1185 | #define V_008DFC_SQ_SRC_M_14_INT 0xCE |
||
| 1186 | #define V_008DFC_SQ_SRC_M_15_INT 0xCF |
||
| 1187 | #define V_008DFC_SQ_SRC_M_16_INT 0xD0 |
||
| 1188 | #define V_008DFC_SQ_SRC_0_5 0xF0 |
||
| 1189 | #define V_008DFC_SQ_SRC_M_0_5 0xF1 |
||
| 1190 | #define V_008DFC_SQ_SRC_1 0xF2 |
||
| 1191 | #define V_008DFC_SQ_SRC_M_1 0xF3 |
||
| 1192 | #define V_008DFC_SQ_SRC_2 0xF4 |
||
| 1193 | #define V_008DFC_SQ_SRC_M_2 0xF5 |
||
| 1194 | #define V_008DFC_SQ_SRC_4 0xF6 |
||
| 1195 | #define V_008DFC_SQ_SRC_M_4 0xF7 |
||
| 1196 | #define V_008DFC_SQ_SRC_VCCZ 0xFB |
||
| 1197 | #define V_008DFC_SQ_SRC_EXECZ 0xFC |
||
| 1198 | #define V_008DFC_SQ_SRC_SCC 0xFD |
||
| 1199 | #define V_008DFC_SQ_SRC_LDS_DIRECT 0xFE |
||
| 1200 | #define V_008DFC_SQ_SRC_VGPR 0x100 |
||
| 1201 | #define S_008DFC_OMOD(x) (((x) & 0x03) << 27) |
||
| 1202 | #define G_008DFC_OMOD(x) (((x) >> 27) & 0x03) |
||
| 1203 | #define C_008DFC_OMOD 0xE7FFFFFF |
||
| 1204 | #define V_008DFC_SQ_OMOD_OFF 0x00 |
||
| 1205 | #define V_008DFC_SQ_OMOD_M2 0x01 |
||
| 1206 | #define V_008DFC_SQ_OMOD_M4 0x02 |
||
| 1207 | #define V_008DFC_SQ_OMOD_D2 0x03 |
||
| 1208 | #define S_008DFC_NEG(x) (((x) & 0x07) << 29) |
||
| 1209 | #define G_008DFC_NEG(x) (((x) >> 29) & 0x07) |
||
| 1210 | #define C_008DFC_NEG 0x1FFFFFFF |
||
| 1211 | #define R_008DFC_SQ_MUBUF_1 0x008DFC |
||
| 1212 | #define S_008DFC_VADDR(x) (((x) & 0xFF) << 0) |
||
| 1213 | #define G_008DFC_VADDR(x) (((x) >> 0) & 0xFF) |
||
| 1214 | #define C_008DFC_VADDR 0xFFFFFF00 |
||
| 1215 | #define V_008DFC_SQ_VGPR 0x00 |
||
| 1216 | #define S_008DFC_VDATA(x) (((x) & 0xFF) << 8) |
||
| 1217 | #define G_008DFC_VDATA(x) (((x) >> 8) & 0xFF) |
||
| 1218 | #define C_008DFC_VDATA 0xFFFF00FF |
||
| 1219 | #define V_008DFC_SQ_VGPR 0x00 |
||
| 1220 | #define S_008DFC_SRSRC(x) (((x) & 0x1F) << 16) |
||
| 1221 | #define G_008DFC_SRSRC(x) (((x) >> 16) & 0x1F) |
||
| 1222 | #define C_008DFC_SRSRC 0xFFE0FFFF |
||
| 1223 | #define S_008DFC_SLC(x) (((x) & 0x1) << 22) |
||
| 1224 | #define G_008DFC_SLC(x) (((x) >> 22) & 0x1) |
||
| 1225 | #define C_008DFC_SLC 0xFFBFFFFF |
||
| 1226 | #define S_008DFC_TFE(x) (((x) & 0x1) << 23) |
||
| 1227 | #define G_008DFC_TFE(x) (((x) >> 23) & 0x1) |
||
| 1228 | #define C_008DFC_TFE 0xFF7FFFFF |
||
| 1229 | #define S_008DFC_SOFFSET(x) (((x) & 0xFF) << 24) |
||
| 1230 | #define G_008DFC_SOFFSET(x) (((x) >> 24) & 0xFF) |
||
| 1231 | #define C_008DFC_SOFFSET 0x00FFFFFF |
||
| 1232 | #define V_008DFC_SQ_SGPR 0x00 |
||
| 1233 | /* CIK */ |
||
| 1234 | #define V_008DFC_SQ_FLAT_SCRATCH_LO 0x68 |
||
| 1235 | #define V_008DFC_SQ_FLAT_SCRATCH_HI 0x69 |
||
| 1236 | /* */ |
||
| 1237 | #define V_008DFC_SQ_VCC_LO 0x6A |
||
| 1238 | #define V_008DFC_SQ_VCC_HI 0x6B |
||
| 1239 | #define V_008DFC_SQ_TBA_LO 0x6C |
||
| 1240 | #define V_008DFC_SQ_TBA_HI 0x6D |
||
| 1241 | #define V_008DFC_SQ_TMA_LO 0x6E |
||
| 1242 | #define V_008DFC_SQ_TMA_HI 0x6F |
||
| 1243 | #define V_008DFC_SQ_TTMP0 0x70 |
||
| 1244 | #define V_008DFC_SQ_TTMP1 0x71 |
||
| 1245 | #define V_008DFC_SQ_TTMP2 0x72 |
||
| 1246 | #define V_008DFC_SQ_TTMP3 0x73 |
||
| 1247 | #define V_008DFC_SQ_TTMP4 0x74 |
||
| 1248 | #define V_008DFC_SQ_TTMP5 0x75 |
||
| 1249 | #define V_008DFC_SQ_TTMP6 0x76 |
||
| 1250 | #define V_008DFC_SQ_TTMP7 0x77 |
||
| 1251 | #define V_008DFC_SQ_TTMP8 0x78 |
||
| 1252 | #define V_008DFC_SQ_TTMP9 0x79 |
||
| 1253 | #define V_008DFC_SQ_TTMP10 0x7A |
||
| 1254 | #define V_008DFC_SQ_TTMP11 0x7B |
||
| 1255 | #define V_008DFC_SQ_M0 0x7C |
||
| 1256 | #define V_008DFC_SQ_EXEC_LO 0x7E |
||
| 1257 | #define V_008DFC_SQ_EXEC_HI 0x7F |
||
| 1258 | #define V_008DFC_SQ_SRC_0 0x80 |
||
| 1259 | #define V_008DFC_SQ_SRC_1_INT 0x81 |
||
| 1260 | #define V_008DFC_SQ_SRC_2_INT 0x82 |
||
| 1261 | #define V_008DFC_SQ_SRC_3_INT 0x83 |
||
| 1262 | #define V_008DFC_SQ_SRC_4_INT 0x84 |
||
| 1263 | #define V_008DFC_SQ_SRC_5_INT 0x85 |
||
| 1264 | #define V_008DFC_SQ_SRC_6_INT 0x86 |
||
| 1265 | #define V_008DFC_SQ_SRC_7_INT 0x87 |
||
| 1266 | #define V_008DFC_SQ_SRC_8_INT 0x88 |
||
| 1267 | #define V_008DFC_SQ_SRC_9_INT 0x89 |
||
| 1268 | #define V_008DFC_SQ_SRC_10_INT 0x8A |
||
| 1269 | #define V_008DFC_SQ_SRC_11_INT 0x8B |
||
| 1270 | #define V_008DFC_SQ_SRC_12_INT 0x8C |
||
| 1271 | #define V_008DFC_SQ_SRC_13_INT 0x8D |
||
| 1272 | #define V_008DFC_SQ_SRC_14_INT 0x8E |
||
| 1273 | #define V_008DFC_SQ_SRC_15_INT 0x8F |
||
| 1274 | #define V_008DFC_SQ_SRC_16_INT 0x90 |
||
| 1275 | #define V_008DFC_SQ_SRC_17_INT 0x91 |
||
| 1276 | #define V_008DFC_SQ_SRC_18_INT 0x92 |
||
| 1277 | #define V_008DFC_SQ_SRC_19_INT 0x93 |
||
| 1278 | #define V_008DFC_SQ_SRC_20_INT 0x94 |
||
| 1279 | #define V_008DFC_SQ_SRC_21_INT 0x95 |
||
| 1280 | #define V_008DFC_SQ_SRC_22_INT 0x96 |
||
| 1281 | #define V_008DFC_SQ_SRC_23_INT 0x97 |
||
| 1282 | #define V_008DFC_SQ_SRC_24_INT 0x98 |
||
| 1283 | #define V_008DFC_SQ_SRC_25_INT 0x99 |
||
| 1284 | #define V_008DFC_SQ_SRC_26_INT 0x9A |
||
| 1285 | #define V_008DFC_SQ_SRC_27_INT 0x9B |
||
| 1286 | #define V_008DFC_SQ_SRC_28_INT 0x9C |
||
| 1287 | #define V_008DFC_SQ_SRC_29_INT 0x9D |
||
| 1288 | #define V_008DFC_SQ_SRC_30_INT 0x9E |
||
| 1289 | #define V_008DFC_SQ_SRC_31_INT 0x9F |
||
| 1290 | #define V_008DFC_SQ_SRC_32_INT 0xA0 |
||
| 1291 | #define V_008DFC_SQ_SRC_33_INT 0xA1 |
||
| 1292 | #define V_008DFC_SQ_SRC_34_INT 0xA2 |
||
| 1293 | #define V_008DFC_SQ_SRC_35_INT 0xA3 |
||
| 1294 | #define V_008DFC_SQ_SRC_36_INT 0xA4 |
||
| 1295 | #define V_008DFC_SQ_SRC_37_INT 0xA5 |
||
| 1296 | #define V_008DFC_SQ_SRC_38_INT 0xA6 |
||
| 1297 | #define V_008DFC_SQ_SRC_39_INT 0xA7 |
||
| 1298 | #define V_008DFC_SQ_SRC_40_INT 0xA8 |
||
| 1299 | #define V_008DFC_SQ_SRC_41_INT 0xA9 |
||
| 1300 | #define V_008DFC_SQ_SRC_42_INT 0xAA |
||
| 1301 | #define V_008DFC_SQ_SRC_43_INT 0xAB |
||
| 1302 | #define V_008DFC_SQ_SRC_44_INT 0xAC |
||
| 1303 | #define V_008DFC_SQ_SRC_45_INT 0xAD |
||
| 1304 | #define V_008DFC_SQ_SRC_46_INT 0xAE |
||
| 1305 | #define V_008DFC_SQ_SRC_47_INT 0xAF |
||
| 1306 | #define V_008DFC_SQ_SRC_48_INT 0xB0 |
||
| 1307 | #define V_008DFC_SQ_SRC_49_INT 0xB1 |
||
| 1308 | #define V_008DFC_SQ_SRC_50_INT 0xB2 |
||
| 1309 | #define V_008DFC_SQ_SRC_51_INT 0xB3 |
||
| 1310 | #define V_008DFC_SQ_SRC_52_INT 0xB4 |
||
| 1311 | #define V_008DFC_SQ_SRC_53_INT 0xB5 |
||
| 1312 | #define V_008DFC_SQ_SRC_54_INT 0xB6 |
||
| 1313 | #define V_008DFC_SQ_SRC_55_INT 0xB7 |
||
| 1314 | #define V_008DFC_SQ_SRC_56_INT 0xB8 |
||
| 1315 | #define V_008DFC_SQ_SRC_57_INT 0xB9 |
||
| 1316 | #define V_008DFC_SQ_SRC_58_INT 0xBA |
||
| 1317 | #define V_008DFC_SQ_SRC_59_INT 0xBB |
||
| 1318 | #define V_008DFC_SQ_SRC_60_INT 0xBC |
||
| 1319 | #define V_008DFC_SQ_SRC_61_INT 0xBD |
||
| 1320 | #define V_008DFC_SQ_SRC_62_INT 0xBE |
||
| 1321 | #define V_008DFC_SQ_SRC_63_INT 0xBF |
||
| 1322 | #define V_008DFC_SQ_SRC_64_INT 0xC0 |
||
| 1323 | #define V_008DFC_SQ_SRC_M_1_INT 0xC1 |
||
| 1324 | #define V_008DFC_SQ_SRC_M_2_INT 0xC2 |
||
| 1325 | #define V_008DFC_SQ_SRC_M_3_INT 0xC3 |
||
| 1326 | #define V_008DFC_SQ_SRC_M_4_INT 0xC4 |
||
| 1327 | #define V_008DFC_SQ_SRC_M_5_INT 0xC5 |
||
| 1328 | #define V_008DFC_SQ_SRC_M_6_INT 0xC6 |
||
| 1329 | #define V_008DFC_SQ_SRC_M_7_INT 0xC7 |
||
| 1330 | #define V_008DFC_SQ_SRC_M_8_INT 0xC8 |
||
| 1331 | #define V_008DFC_SQ_SRC_M_9_INT 0xC9 |
||
| 1332 | #define V_008DFC_SQ_SRC_M_10_INT 0xCA |
||
| 1333 | #define V_008DFC_SQ_SRC_M_11_INT 0xCB |
||
| 1334 | #define V_008DFC_SQ_SRC_M_12_INT 0xCC |
||
| 1335 | #define V_008DFC_SQ_SRC_M_13_INT 0xCD |
||
| 1336 | #define V_008DFC_SQ_SRC_M_14_INT 0xCE |
||
| 1337 | #define V_008DFC_SQ_SRC_M_15_INT 0xCF |
||
| 1338 | #define V_008DFC_SQ_SRC_M_16_INT 0xD0 |
||
| 1339 | #define V_008DFC_SQ_SRC_0_5 0xF0 |
||
| 1340 | #define V_008DFC_SQ_SRC_M_0_5 0xF1 |
||
| 1341 | #define V_008DFC_SQ_SRC_1 0xF2 |
||
| 1342 | #define V_008DFC_SQ_SRC_M_1 0xF3 |
||
| 1343 | #define V_008DFC_SQ_SRC_2 0xF4 |
||
| 1344 | #define V_008DFC_SQ_SRC_M_2 0xF5 |
||
| 1345 | #define V_008DFC_SQ_SRC_4 0xF6 |
||
| 1346 | #define V_008DFC_SQ_SRC_M_4 0xF7 |
||
| 1347 | #define V_008DFC_SQ_SRC_VCCZ 0xFB |
||
| 1348 | #define V_008DFC_SQ_SRC_EXECZ 0xFC |
||
| 1349 | #define V_008DFC_SQ_SRC_SCC 0xFD |
||
| 1350 | #define V_008DFC_SQ_SRC_LDS_DIRECT 0xFE |
||
| 1351 | #define R_008DFC_SQ_DS_0 0x008DFC |
||
| 1352 | #define S_008DFC_OFFSET0(x) (((x) & 0xFF) << 0) |
||
| 1353 | #define G_008DFC_OFFSET0(x) (((x) >> 0) & 0xFF) |
||
| 1354 | #define C_008DFC_OFFSET0 0xFFFFFF00 |
||
| 1355 | #define S_008DFC_OFFSET1(x) (((x) & 0xFF) << 8) |
||
| 1356 | #define G_008DFC_OFFSET1(x) (((x) >> 8) & 0xFF) |
||
| 1357 | #define C_008DFC_OFFSET1 0xFFFF00FF |
||
| 1358 | #define S_008DFC_GDS(x) (((x) & 0x1) << 17) |
||
| 1359 | #define G_008DFC_GDS(x) (((x) >> 17) & 0x1) |
||
| 1360 | #define C_008DFC_GDS 0xFFFDFFFF |
||
| 1361 | #define S_008DFC_OP(x) (((x) & 0xFF) << 18) |
||
| 1362 | #define G_008DFC_OP(x) (((x) >> 18) & 0xFF) |
||
| 1363 | #define C_008DFC_OP 0xFC03FFFF |
||
| 1364 | #define V_008DFC_SQ_DS_ADD_U32 0x00 |
||
| 1365 | #define V_008DFC_SQ_DS_SUB_U32 0x01 |
||
| 1366 | #define V_008DFC_SQ_DS_RSUB_U32 0x02 |
||
| 1367 | #define V_008DFC_SQ_DS_INC_U32 0x03 |
||
| 1368 | #define V_008DFC_SQ_DS_DEC_U32 0x04 |
||
| 1369 | #define V_008DFC_SQ_DS_MIN_I32 0x05 |
||
| 1370 | #define V_008DFC_SQ_DS_MAX_I32 0x06 |
||
| 1371 | #define V_008DFC_SQ_DS_MIN_U32 0x07 |
||
| 1372 | #define V_008DFC_SQ_DS_MAX_U32 0x08 |
||
| 1373 | #define V_008DFC_SQ_DS_AND_B32 0x09 |
||
| 1374 | #define V_008DFC_SQ_DS_OR_B32 0x0A |
||
| 1375 | #define V_008DFC_SQ_DS_XOR_B32 0x0B |
||
| 1376 | #define V_008DFC_SQ_DS_MSKOR_B32 0x0C |
||
| 1377 | #define V_008DFC_SQ_DS_WRITE_B32 0x0D |
||
| 1378 | #define V_008DFC_SQ_DS_WRITE2_B32 0x0E |
||
| 1379 | #define V_008DFC_SQ_DS_WRITE2ST64_B32 0x0F |
||
| 1380 | #define V_008DFC_SQ_DS_CMPST_B32 0x10 |
||
| 1381 | #define V_008DFC_SQ_DS_CMPST_F32 0x11 |
||
| 1382 | #define V_008DFC_SQ_DS_MIN_F32 0x12 |
||
| 1383 | #define V_008DFC_SQ_DS_MAX_F32 0x13 |
||
| 1384 | /* CIK */ |
||
| 1385 | #define V_008DFC_SQ_DS_NOP 0x14 |
||
| 1386 | /* */ |
||
| 1387 | #define V_008DFC_SQ_DS_GWS_INIT 0x19 |
||
| 1388 | #define V_008DFC_SQ_DS_GWS_SEMA_V 0x1A |
||
| 1389 | #define V_008DFC_SQ_DS_GWS_SEMA_BR 0x1B |
||
| 1390 | #define V_008DFC_SQ_DS_GWS_SEMA_P 0x1C |
||
| 1391 | #define V_008DFC_SQ_DS_GWS_BARRIER 0x1D |
||
| 1392 | #define V_008DFC_SQ_DS_WRITE_B8 0x1E |
||
| 1393 | #define V_008DFC_SQ_DS_WRITE_B16 0x1F |
||
| 1394 | #define V_008DFC_SQ_DS_ADD_RTN_U32 0x20 |
||
| 1395 | #define V_008DFC_SQ_DS_SUB_RTN_U32 0x21 |
||
| 1396 | #define V_008DFC_SQ_DS_RSUB_RTN_U32 0x22 |
||
| 1397 | #define V_008DFC_SQ_DS_INC_RTN_U32 0x23 |
||
| 1398 | #define V_008DFC_SQ_DS_DEC_RTN_U32 0x24 |
||
| 1399 | #define V_008DFC_SQ_DS_MIN_RTN_I32 0x25 |
||
| 1400 | #define V_008DFC_SQ_DS_MAX_RTN_I32 0x26 |
||
| 1401 | #define V_008DFC_SQ_DS_MIN_RTN_U32 0x27 |
||
| 1402 | #define V_008DFC_SQ_DS_MAX_RTN_U32 0x28 |
||
| 1403 | #define V_008DFC_SQ_DS_AND_RTN_B32 0x29 |
||
| 1404 | #define V_008DFC_SQ_DS_OR_RTN_B32 0x2A |
||
| 1405 | #define V_008DFC_SQ_DS_XOR_RTN_B32 0x2B |
||
| 1406 | #define V_008DFC_SQ_DS_MSKOR_RTN_B32 0x2C |
||
| 1407 | #define V_008DFC_SQ_DS_WRXCHG_RTN_B32 0x2D |
||
| 1408 | #define V_008DFC_SQ_DS_WRXCHG2_RTN_B32 0x2E |
||
| 1409 | #define V_008DFC_SQ_DS_WRXCHG2ST64_RTN_B32 0x2F |
||
| 1410 | #define V_008DFC_SQ_DS_CMPST_RTN_B32 0x30 |
||
| 1411 | #define V_008DFC_SQ_DS_CMPST_RTN_F32 0x31 |
||
| 1412 | #define V_008DFC_SQ_DS_MIN_RTN_F32 0x32 |
||
| 1413 | #define V_008DFC_SQ_DS_MAX_RTN_F32 0x33 |
||
| 1414 | #define V_008DFC_SQ_DS_SWIZZLE_B32 0x35 |
||
| 1415 | #define V_008DFC_SQ_DS_READ_B32 0x36 |
||
| 1416 | #define V_008DFC_SQ_DS_READ2_B32 0x37 |
||
| 1417 | #define V_008DFC_SQ_DS_READ2ST64_B32 0x38 |
||
| 1418 | #define V_008DFC_SQ_DS_READ_I8 0x39 |
||
| 1419 | #define V_008DFC_SQ_DS_READ_U8 0x3A |
||
| 1420 | #define V_008DFC_SQ_DS_READ_I16 0x3B |
||
| 1421 | #define V_008DFC_SQ_DS_READ_U16 0x3C |
||
| 1422 | #define V_008DFC_SQ_DS_CONSUME 0x3D |
||
| 1423 | #define V_008DFC_SQ_DS_APPEND 0x3E |
||
| 1424 | #define V_008DFC_SQ_DS_ORDERED_COUNT 0x3F |
||
| 1425 | #define V_008DFC_SQ_DS_ADD_U64 0x40 |
||
| 1426 | #define V_008DFC_SQ_DS_SUB_U64 0x41 |
||
| 1427 | #define V_008DFC_SQ_DS_RSUB_U64 0x42 |
||
| 1428 | #define V_008DFC_SQ_DS_INC_U64 0x43 |
||
| 1429 | #define V_008DFC_SQ_DS_DEC_U64 0x44 |
||
| 1430 | #define V_008DFC_SQ_DS_MIN_I64 0x45 |
||
| 1431 | #define V_008DFC_SQ_DS_MAX_I64 0x46 |
||
| 1432 | #define V_008DFC_SQ_DS_MIN_U64 0x47 |
||
| 1433 | #define V_008DFC_SQ_DS_MAX_U64 0x48 |
||
| 1434 | #define V_008DFC_SQ_DS_AND_B64 0x49 |
||
| 1435 | #define V_008DFC_SQ_DS_OR_B64 0x4A |
||
| 1436 | #define V_008DFC_SQ_DS_XOR_B64 0x4B |
||
| 1437 | #define V_008DFC_SQ_DS_MSKOR_B64 0x4C |
||
| 1438 | #define V_008DFC_SQ_DS_WRITE_B64 0x4D |
||
| 1439 | #define V_008DFC_SQ_DS_WRITE2_B64 0x4E |
||
| 1440 | #define V_008DFC_SQ_DS_WRITE2ST64_B64 0x4F |
||
| 1441 | #define V_008DFC_SQ_DS_CMPST_B64 0x50 |
||
| 1442 | #define V_008DFC_SQ_DS_CMPST_F64 0x51 |
||
| 1443 | #define V_008DFC_SQ_DS_MIN_F64 0x52 |
||
| 1444 | #define V_008DFC_SQ_DS_MAX_F64 0x53 |
||
| 1445 | #define V_008DFC_SQ_DS_ADD_RTN_U64 0x60 |
||
| 1446 | #define V_008DFC_SQ_DS_SUB_RTN_U64 0x61 |
||
| 1447 | #define V_008DFC_SQ_DS_RSUB_RTN_U64 0x62 |
||
| 1448 | #define V_008DFC_SQ_DS_INC_RTN_U64 0x63 |
||
| 1449 | #define V_008DFC_SQ_DS_DEC_RTN_U64 0x64 |
||
| 1450 | #define V_008DFC_SQ_DS_MIN_RTN_I64 0x65 |
||
| 1451 | #define V_008DFC_SQ_DS_MAX_RTN_I64 0x66 |
||
| 1452 | #define V_008DFC_SQ_DS_MIN_RTN_U64 0x67 |
||
| 1453 | #define V_008DFC_SQ_DS_MAX_RTN_U64 0x68 |
||
| 1454 | #define V_008DFC_SQ_DS_AND_RTN_B64 0x69 |
||
| 1455 | #define V_008DFC_SQ_DS_OR_RTN_B64 0x6A |
||
| 1456 | #define V_008DFC_SQ_DS_XOR_RTN_B64 0x6B |
||
| 1457 | #define V_008DFC_SQ_DS_MSKOR_RTN_B64 0x6C |
||
| 1458 | #define V_008DFC_SQ_DS_WRXCHG_RTN_B64 0x6D |
||
| 1459 | #define V_008DFC_SQ_DS_WRXCHG2_RTN_B64 0x6E |
||
| 1460 | #define V_008DFC_SQ_DS_WRXCHG2ST64_RTN_B64 0x6F |
||
| 1461 | #define V_008DFC_SQ_DS_CMPST_RTN_B64 0x70 |
||
| 1462 | #define V_008DFC_SQ_DS_CMPST_RTN_F64 0x71 |
||
| 1463 | #define V_008DFC_SQ_DS_MIN_RTN_F64 0x72 |
||
| 1464 | #define V_008DFC_SQ_DS_MAX_RTN_F64 0x73 |
||
| 1465 | #define V_008DFC_SQ_DS_READ_B64 0x76 |
||
| 1466 | #define V_008DFC_SQ_DS_READ2_B64 0x77 |
||
| 1467 | #define V_008DFC_SQ_DS_READ2ST64_B64 0x78 |
||
| 1468 | /* CIK */ |
||
| 1469 | #define V_008DFC_SQ_DS_CONDXCHG32_RTN_B64 0x7E |
||
| 1470 | /* */ |
||
| 1471 | #define V_008DFC_SQ_DS_ADD_SRC2_U32 0x80 |
||
| 1472 | #define V_008DFC_SQ_DS_SUB_SRC2_U32 0x81 |
||
| 1473 | #define V_008DFC_SQ_DS_RSUB_SRC2_U32 0x82 |
||
| 1474 | #define V_008DFC_SQ_DS_INC_SRC2_U32 0x83 |
||
| 1475 | #define V_008DFC_SQ_DS_DEC_SRC2_U32 0x84 |
||
| 1476 | #define V_008DFC_SQ_DS_MIN_SRC2_I32 0x85 |
||
| 1477 | #define V_008DFC_SQ_DS_MAX_SRC2_I32 0x86 |
||
| 1478 | #define V_008DFC_SQ_DS_MIN_SRC2_U32 0x87 |
||
| 1479 | #define V_008DFC_SQ_DS_MAX_SRC2_U32 0x88 |
||
| 1480 | #define V_008DFC_SQ_DS_AND_SRC2_B32 0x89 |
||
| 1481 | #define V_008DFC_SQ_DS_OR_SRC2_B32 0x8A |
||
| 1482 | #define V_008DFC_SQ_DS_XOR_SRC2_B32 0x8B |
||
| 1483 | #define V_008DFC_SQ_DS_WRITE_SRC2_B32 0x8D |
||
| 1484 | #define V_008DFC_SQ_DS_MIN_SRC2_F32 0x92 |
||
| 1485 | #define V_008DFC_SQ_DS_MAX_SRC2_F32 0x93 |
||
| 1486 | #define V_008DFC_SQ_DS_ADD_SRC2_U64 0xC0 |
||
| 1487 | #define V_008DFC_SQ_DS_SUB_SRC2_U64 0xC1 |
||
| 1488 | #define V_008DFC_SQ_DS_RSUB_SRC2_U64 0xC2 |
||
| 1489 | #define V_008DFC_SQ_DS_INC_SRC2_U64 0xC3 |
||
| 1490 | #define V_008DFC_SQ_DS_DEC_SRC2_U64 0xC4 |
||
| 1491 | #define V_008DFC_SQ_DS_MIN_SRC2_I64 0xC5 |
||
| 1492 | #define V_008DFC_SQ_DS_MAX_SRC2_I64 0xC6 |
||
| 1493 | #define V_008DFC_SQ_DS_MIN_SRC2_U64 0xC7 |
||
| 1494 | #define V_008DFC_SQ_DS_MAX_SRC2_U64 0xC8 |
||
| 1495 | #define V_008DFC_SQ_DS_AND_SRC2_B64 0xC9 |
||
| 1496 | #define V_008DFC_SQ_DS_OR_SRC2_B64 0xCA |
||
| 1497 | #define V_008DFC_SQ_DS_XOR_SRC2_B64 0xCB |
||
| 1498 | #define V_008DFC_SQ_DS_WRITE_SRC2_B64 0xCD |
||
| 1499 | #define V_008DFC_SQ_DS_MIN_SRC2_F64 0xD2 |
||
| 1500 | #define V_008DFC_SQ_DS_MAX_SRC2_F64 0xD3 |
||
| 1501 | /* CIK */ |
||
| 1502 | #define V_008DFC_SQ_DS_WRITE_B96 0xDE |
||
| 1503 | #define V_008DFC_SQ_DS_WRITE_B128 0xDF |
||
| 1504 | #define V_008DFC_SQ_DS_CONDXCHG32_RTN_B128 0xFD |
||
| 1505 | #define V_008DFC_SQ_DS_READ_B96 0xFE |
||
| 1506 | #define V_008DFC_SQ_DS_READ_B128 0xFF |
||
| 1507 | /* */ |
||
| 1508 | #define S_008DFC_ENCODING(x) (((x) & 0x3F) << 26) |
||
| 1509 | #define G_008DFC_ENCODING(x) (((x) >> 26) & 0x3F) |
||
| 1510 | #define C_008DFC_ENCODING 0x03FFFFFF |
||
| 1511 | #define V_008DFC_SQ_ENC_DS_FIELD 0x36 |
||
| 1512 | #define R_008DFC_SQ_SOPC 0x008DFC |
||
| 1513 | #define S_008DFC_SSRC0(x) (((x) & 0xFF) << 0) |
||
| 1514 | #define G_008DFC_SSRC0(x) (((x) >> 0) & 0xFF) |
||
| 1515 | #define C_008DFC_SSRC0 0xFFFFFF00 |
||
| 1516 | #define V_008DFC_SQ_SGPR 0x00 |
||
| 1517 | /* CIK */ |
||
| 1518 | #define V_008DFC_SQ_FLAT_SCRATCH_LO 0x68 |
||
| 1519 | #define V_008DFC_SQ_FLAT_SCRATCH_HI 0x69 |
||
| 1520 | /* */ |
||
| 1521 | #define V_008DFC_SQ_VCC_LO 0x6A |
||
| 1522 | #define V_008DFC_SQ_VCC_HI 0x6B |
||
| 1523 | #define V_008DFC_SQ_TBA_LO 0x6C |
||
| 1524 | #define V_008DFC_SQ_TBA_HI 0x6D |
||
| 1525 | #define V_008DFC_SQ_TMA_LO 0x6E |
||
| 1526 | #define V_008DFC_SQ_TMA_HI 0x6F |
||
| 1527 | #define V_008DFC_SQ_TTMP0 0x70 |
||
| 1528 | #define V_008DFC_SQ_TTMP1 0x71 |
||
| 1529 | #define V_008DFC_SQ_TTMP2 0x72 |
||
| 1530 | #define V_008DFC_SQ_TTMP3 0x73 |
||
| 1531 | #define V_008DFC_SQ_TTMP4 0x74 |
||
| 1532 | #define V_008DFC_SQ_TTMP5 0x75 |
||
| 1533 | #define V_008DFC_SQ_TTMP6 0x76 |
||
| 1534 | #define V_008DFC_SQ_TTMP7 0x77 |
||
| 1535 | #define V_008DFC_SQ_TTMP8 0x78 |
||
| 1536 | #define V_008DFC_SQ_TTMP9 0x79 |
||
| 1537 | #define V_008DFC_SQ_TTMP10 0x7A |
||
| 1538 | #define V_008DFC_SQ_TTMP11 0x7B |
||
| 1539 | #define V_008DFC_SQ_M0 0x7C |
||
| 1540 | #define V_008DFC_SQ_EXEC_LO 0x7E |
||
| 1541 | #define V_008DFC_SQ_EXEC_HI 0x7F |
||
| 1542 | #define V_008DFC_SQ_SRC_0 0x80 |
||
| 1543 | #define V_008DFC_SQ_SRC_1_INT 0x81 |
||
| 1544 | #define V_008DFC_SQ_SRC_2_INT 0x82 |
||
| 1545 | #define V_008DFC_SQ_SRC_3_INT 0x83 |
||
| 1546 | #define V_008DFC_SQ_SRC_4_INT 0x84 |
||
| 1547 | #define V_008DFC_SQ_SRC_5_INT 0x85 |
||
| 1548 | #define V_008DFC_SQ_SRC_6_INT 0x86 |
||
| 1549 | #define V_008DFC_SQ_SRC_7_INT 0x87 |
||
| 1550 | #define V_008DFC_SQ_SRC_8_INT 0x88 |
||
| 1551 | #define V_008DFC_SQ_SRC_9_INT 0x89 |
||
| 1552 | #define V_008DFC_SQ_SRC_10_INT 0x8A |
||
| 1553 | #define V_008DFC_SQ_SRC_11_INT 0x8B |
||
| 1554 | #define V_008DFC_SQ_SRC_12_INT 0x8C |
||
| 1555 | #define V_008DFC_SQ_SRC_13_INT 0x8D |
||
| 1556 | #define V_008DFC_SQ_SRC_14_INT 0x8E |
||
| 1557 | #define V_008DFC_SQ_SRC_15_INT 0x8F |
||
| 1558 | #define V_008DFC_SQ_SRC_16_INT 0x90 |
||
| 1559 | #define V_008DFC_SQ_SRC_17_INT 0x91 |
||
| 1560 | #define V_008DFC_SQ_SRC_18_INT 0x92 |
||
| 1561 | #define V_008DFC_SQ_SRC_19_INT 0x93 |
||
| 1562 | #define V_008DFC_SQ_SRC_20_INT 0x94 |
||
| 1563 | #define V_008DFC_SQ_SRC_21_INT 0x95 |
||
| 1564 | #define V_008DFC_SQ_SRC_22_INT 0x96 |
||
| 1565 | #define V_008DFC_SQ_SRC_23_INT 0x97 |
||
| 1566 | #define V_008DFC_SQ_SRC_24_INT 0x98 |
||
| 1567 | #define V_008DFC_SQ_SRC_25_INT 0x99 |
||
| 1568 | #define V_008DFC_SQ_SRC_26_INT 0x9A |
||
| 1569 | #define V_008DFC_SQ_SRC_27_INT 0x9B |
||
| 1570 | #define V_008DFC_SQ_SRC_28_INT 0x9C |
||
| 1571 | #define V_008DFC_SQ_SRC_29_INT 0x9D |
||
| 1572 | #define V_008DFC_SQ_SRC_30_INT 0x9E |
||
| 1573 | #define V_008DFC_SQ_SRC_31_INT 0x9F |
||
| 1574 | #define V_008DFC_SQ_SRC_32_INT 0xA0 |
||
| 1575 | #define V_008DFC_SQ_SRC_33_INT 0xA1 |
||
| 1576 | #define V_008DFC_SQ_SRC_34_INT 0xA2 |
||
| 1577 | #define V_008DFC_SQ_SRC_35_INT 0xA3 |
||
| 1578 | #define V_008DFC_SQ_SRC_36_INT 0xA4 |
||
| 1579 | #define V_008DFC_SQ_SRC_37_INT 0xA5 |
||
| 1580 | #define V_008DFC_SQ_SRC_38_INT 0xA6 |
||
| 1581 | #define V_008DFC_SQ_SRC_39_INT 0xA7 |
||
| 1582 | #define V_008DFC_SQ_SRC_40_INT 0xA8 |
||
| 1583 | #define V_008DFC_SQ_SRC_41_INT 0xA9 |
||
| 1584 | #define V_008DFC_SQ_SRC_42_INT 0xAA |
||
| 1585 | #define V_008DFC_SQ_SRC_43_INT 0xAB |
||
| 1586 | #define V_008DFC_SQ_SRC_44_INT 0xAC |
||
| 1587 | #define V_008DFC_SQ_SRC_45_INT 0xAD |
||
| 1588 | #define V_008DFC_SQ_SRC_46_INT 0xAE |
||
| 1589 | #define V_008DFC_SQ_SRC_47_INT 0xAF |
||
| 1590 | #define V_008DFC_SQ_SRC_48_INT 0xB0 |
||
| 1591 | #define V_008DFC_SQ_SRC_49_INT 0xB1 |
||
| 1592 | #define V_008DFC_SQ_SRC_50_INT 0xB2 |
||
| 1593 | #define V_008DFC_SQ_SRC_51_INT 0xB3 |
||
| 1594 | #define V_008DFC_SQ_SRC_52_INT 0xB4 |
||
| 1595 | #define V_008DFC_SQ_SRC_53_INT 0xB5 |
||
| 1596 | #define V_008DFC_SQ_SRC_54_INT 0xB6 |
||
| 1597 | #define V_008DFC_SQ_SRC_55_INT 0xB7 |
||
| 1598 | #define V_008DFC_SQ_SRC_56_INT 0xB8 |
||
| 1599 | #define V_008DFC_SQ_SRC_57_INT 0xB9 |
||
| 1600 | #define V_008DFC_SQ_SRC_58_INT 0xBA |
||
| 1601 | #define V_008DFC_SQ_SRC_59_INT 0xBB |
||
| 1602 | #define V_008DFC_SQ_SRC_60_INT 0xBC |
||
| 1603 | #define V_008DFC_SQ_SRC_61_INT 0xBD |
||
| 1604 | #define V_008DFC_SQ_SRC_62_INT 0xBE |
||
| 1605 | #define V_008DFC_SQ_SRC_63_INT 0xBF |
||
| 1606 | #define V_008DFC_SQ_SRC_64_INT 0xC0 |
||
| 1607 | #define V_008DFC_SQ_SRC_M_1_INT 0xC1 |
||
| 1608 | #define V_008DFC_SQ_SRC_M_2_INT 0xC2 |
||
| 1609 | #define V_008DFC_SQ_SRC_M_3_INT 0xC3 |
||
| 1610 | #define V_008DFC_SQ_SRC_M_4_INT 0xC4 |
||
| 1611 | #define V_008DFC_SQ_SRC_M_5_INT 0xC5 |
||
| 1612 | #define V_008DFC_SQ_SRC_M_6_INT 0xC6 |
||
| 1613 | #define V_008DFC_SQ_SRC_M_7_INT 0xC7 |
||
| 1614 | #define V_008DFC_SQ_SRC_M_8_INT 0xC8 |
||
| 1615 | #define V_008DFC_SQ_SRC_M_9_INT 0xC9 |
||
| 1616 | #define V_008DFC_SQ_SRC_M_10_INT 0xCA |
||
| 1617 | #define V_008DFC_SQ_SRC_M_11_INT 0xCB |
||
| 1618 | #define V_008DFC_SQ_SRC_M_12_INT 0xCC |
||
| 1619 | #define V_008DFC_SQ_SRC_M_13_INT 0xCD |
||
| 1620 | #define V_008DFC_SQ_SRC_M_14_INT 0xCE |
||
| 1621 | #define V_008DFC_SQ_SRC_M_15_INT 0xCF |
||
| 1622 | #define V_008DFC_SQ_SRC_M_16_INT 0xD0 |
||
| 1623 | #define V_008DFC_SQ_SRC_0_5 0xF0 |
||
| 1624 | #define V_008DFC_SQ_SRC_M_0_5 0xF1 |
||
| 1625 | #define V_008DFC_SQ_SRC_1 0xF2 |
||
| 1626 | #define V_008DFC_SQ_SRC_M_1 0xF3 |
||
| 1627 | #define V_008DFC_SQ_SRC_2 0xF4 |
||
| 1628 | #define V_008DFC_SQ_SRC_M_2 0xF5 |
||
| 1629 | #define V_008DFC_SQ_SRC_4 0xF6 |
||
| 1630 | #define V_008DFC_SQ_SRC_M_4 0xF7 |
||
| 1631 | #define V_008DFC_SQ_SRC_VCCZ 0xFB |
||
| 1632 | #define V_008DFC_SQ_SRC_EXECZ 0xFC |
||
| 1633 | #define V_008DFC_SQ_SRC_SCC 0xFD |
||
| 1634 | #define V_008DFC_SQ_SRC_LDS_DIRECT 0xFE |
||
| 1635 | #define S_008DFC_SSRC1(x) (((x) & 0xFF) << 8) |
||
| 1636 | #define G_008DFC_SSRC1(x) (((x) >> 8) & 0xFF) |
||
| 1637 | #define C_008DFC_SSRC1 0xFFFF00FF |
||
| 1638 | #define V_008DFC_SQ_SGPR 0x00 |
||
| 1639 | /* CIK */ |
||
| 1640 | #define V_008DFC_SQ_FLAT_SCRATCH_LO 0x68 |
||
| 1641 | #define V_008DFC_SQ_FLAT_SCRATCH_HI 0x69 |
||
| 1642 | /* */ |
||
| 1643 | #define V_008DFC_SQ_VCC_LO 0x6A |
||
| 1644 | #define V_008DFC_SQ_VCC_HI 0x6B |
||
| 1645 | #define V_008DFC_SQ_TBA_LO 0x6C |
||
| 1646 | #define V_008DFC_SQ_TBA_HI 0x6D |
||
| 1647 | #define V_008DFC_SQ_TMA_LO 0x6E |
||
| 1648 | #define V_008DFC_SQ_TMA_HI 0x6F |
||
| 1649 | #define V_008DFC_SQ_TTMP0 0x70 |
||
| 1650 | #define V_008DFC_SQ_TTMP1 0x71 |
||
| 1651 | #define V_008DFC_SQ_TTMP2 0x72 |
||
| 1652 | #define V_008DFC_SQ_TTMP3 0x73 |
||
| 1653 | #define V_008DFC_SQ_TTMP4 0x74 |
||
| 1654 | #define V_008DFC_SQ_TTMP5 0x75 |
||
| 1655 | #define V_008DFC_SQ_TTMP6 0x76 |
||
| 1656 | #define V_008DFC_SQ_TTMP7 0x77 |
||
| 1657 | #define V_008DFC_SQ_TTMP8 0x78 |
||
| 1658 | #define V_008DFC_SQ_TTMP9 0x79 |
||
| 1659 | #define V_008DFC_SQ_TTMP10 0x7A |
||
| 1660 | #define V_008DFC_SQ_TTMP11 0x7B |
||
| 1661 | #define V_008DFC_SQ_M0 0x7C |
||
| 1662 | #define V_008DFC_SQ_EXEC_LO 0x7E |
||
| 1663 | #define V_008DFC_SQ_EXEC_HI 0x7F |
||
| 1664 | #define V_008DFC_SQ_SRC_0 0x80 |
||
| 1665 | #define V_008DFC_SQ_SRC_1_INT 0x81 |
||
| 1666 | #define V_008DFC_SQ_SRC_2_INT 0x82 |
||
| 1667 | #define V_008DFC_SQ_SRC_3_INT 0x83 |
||
| 1668 | #define V_008DFC_SQ_SRC_4_INT 0x84 |
||
| 1669 | #define V_008DFC_SQ_SRC_5_INT 0x85 |
||
| 1670 | #define V_008DFC_SQ_SRC_6_INT 0x86 |
||
| 1671 | #define V_008DFC_SQ_SRC_7_INT 0x87 |
||
| 1672 | #define V_008DFC_SQ_SRC_8_INT 0x88 |
||
| 1673 | #define V_008DFC_SQ_SRC_9_INT 0x89 |
||
| 1674 | #define V_008DFC_SQ_SRC_10_INT 0x8A |
||
| 1675 | #define V_008DFC_SQ_SRC_11_INT 0x8B |
||
| 1676 | #define V_008DFC_SQ_SRC_12_INT 0x8C |
||
| 1677 | #define V_008DFC_SQ_SRC_13_INT 0x8D |
||
| 1678 | #define V_008DFC_SQ_SRC_14_INT 0x8E |
||
| 1679 | #define V_008DFC_SQ_SRC_15_INT 0x8F |
||
| 1680 | #define V_008DFC_SQ_SRC_16_INT 0x90 |
||
| 1681 | #define V_008DFC_SQ_SRC_17_INT 0x91 |
||
| 1682 | #define V_008DFC_SQ_SRC_18_INT 0x92 |
||
| 1683 | #define V_008DFC_SQ_SRC_19_INT 0x93 |
||
| 1684 | #define V_008DFC_SQ_SRC_20_INT 0x94 |
||
| 1685 | #define V_008DFC_SQ_SRC_21_INT 0x95 |
||
| 1686 | #define V_008DFC_SQ_SRC_22_INT 0x96 |
||
| 1687 | #define V_008DFC_SQ_SRC_23_INT 0x97 |
||
| 1688 | #define V_008DFC_SQ_SRC_24_INT 0x98 |
||
| 1689 | #define V_008DFC_SQ_SRC_25_INT 0x99 |
||
| 1690 | #define V_008DFC_SQ_SRC_26_INT 0x9A |
||
| 1691 | #define V_008DFC_SQ_SRC_27_INT 0x9B |
||
| 1692 | #define V_008DFC_SQ_SRC_28_INT 0x9C |
||
| 1693 | #define V_008DFC_SQ_SRC_29_INT 0x9D |
||
| 1694 | #define V_008DFC_SQ_SRC_30_INT 0x9E |
||
| 1695 | #define V_008DFC_SQ_SRC_31_INT 0x9F |
||
| 1696 | #define V_008DFC_SQ_SRC_32_INT 0xA0 |
||
| 1697 | #define V_008DFC_SQ_SRC_33_INT 0xA1 |
||
| 1698 | #define V_008DFC_SQ_SRC_34_INT 0xA2 |
||
| 1699 | #define V_008DFC_SQ_SRC_35_INT 0xA3 |
||
| 1700 | #define V_008DFC_SQ_SRC_36_INT 0xA4 |
||
| 1701 | #define V_008DFC_SQ_SRC_37_INT 0xA5 |
||
| 1702 | #define V_008DFC_SQ_SRC_38_INT 0xA6 |
||
| 1703 | #define V_008DFC_SQ_SRC_39_INT 0xA7 |
||
| 1704 | #define V_008DFC_SQ_SRC_40_INT 0xA8 |
||
| 1705 | #define V_008DFC_SQ_SRC_41_INT 0xA9 |
||
| 1706 | #define V_008DFC_SQ_SRC_42_INT 0xAA |
||
| 1707 | #define V_008DFC_SQ_SRC_43_INT 0xAB |
||
| 1708 | #define V_008DFC_SQ_SRC_44_INT 0xAC |
||
| 1709 | #define V_008DFC_SQ_SRC_45_INT 0xAD |
||
| 1710 | #define V_008DFC_SQ_SRC_46_INT 0xAE |
||
| 1711 | #define V_008DFC_SQ_SRC_47_INT 0xAF |
||
| 1712 | #define V_008DFC_SQ_SRC_48_INT 0xB0 |
||
| 1713 | #define V_008DFC_SQ_SRC_49_INT 0xB1 |
||
| 1714 | #define V_008DFC_SQ_SRC_50_INT 0xB2 |
||
| 1715 | #define V_008DFC_SQ_SRC_51_INT 0xB3 |
||
| 1716 | #define V_008DFC_SQ_SRC_52_INT 0xB4 |
||
| 1717 | #define V_008DFC_SQ_SRC_53_INT 0xB5 |
||
| 1718 | #define V_008DFC_SQ_SRC_54_INT 0xB6 |
||
| 1719 | #define V_008DFC_SQ_SRC_55_INT 0xB7 |
||
| 1720 | #define V_008DFC_SQ_SRC_56_INT 0xB8 |
||
| 1721 | #define V_008DFC_SQ_SRC_57_INT 0xB9 |
||
| 1722 | #define V_008DFC_SQ_SRC_58_INT 0xBA |
||
| 1723 | #define V_008DFC_SQ_SRC_59_INT 0xBB |
||
| 1724 | #define V_008DFC_SQ_SRC_60_INT 0xBC |
||
| 1725 | #define V_008DFC_SQ_SRC_61_INT 0xBD |
||
| 1726 | #define V_008DFC_SQ_SRC_62_INT 0xBE |
||
| 1727 | #define V_008DFC_SQ_SRC_63_INT 0xBF |
||
| 1728 | #define V_008DFC_SQ_SRC_64_INT 0xC0 |
||
| 1729 | #define V_008DFC_SQ_SRC_M_1_INT 0xC1 |
||
| 1730 | #define V_008DFC_SQ_SRC_M_2_INT 0xC2 |
||
| 1731 | #define V_008DFC_SQ_SRC_M_3_INT 0xC3 |
||
| 1732 | #define V_008DFC_SQ_SRC_M_4_INT 0xC4 |
||
| 1733 | #define V_008DFC_SQ_SRC_M_5_INT 0xC5 |
||
| 1734 | #define V_008DFC_SQ_SRC_M_6_INT 0xC6 |
||
| 1735 | #define V_008DFC_SQ_SRC_M_7_INT 0xC7 |
||
| 1736 | #define V_008DFC_SQ_SRC_M_8_INT 0xC8 |
||
| 1737 | #define V_008DFC_SQ_SRC_M_9_INT 0xC9 |
||
| 1738 | #define V_008DFC_SQ_SRC_M_10_INT 0xCA |
||
| 1739 | #define V_008DFC_SQ_SRC_M_11_INT 0xCB |
||
| 1740 | #define V_008DFC_SQ_SRC_M_12_INT 0xCC |
||
| 1741 | #define V_008DFC_SQ_SRC_M_13_INT 0xCD |
||
| 1742 | #define V_008DFC_SQ_SRC_M_14_INT 0xCE |
||
| 1743 | #define V_008DFC_SQ_SRC_M_15_INT 0xCF |
||
| 1744 | #define V_008DFC_SQ_SRC_M_16_INT 0xD0 |
||
| 1745 | #define V_008DFC_SQ_SRC_0_5 0xF0 |
||
| 1746 | #define V_008DFC_SQ_SRC_M_0_5 0xF1 |
||
| 1747 | #define V_008DFC_SQ_SRC_1 0xF2 |
||
| 1748 | #define V_008DFC_SQ_SRC_M_1 0xF3 |
||
| 1749 | #define V_008DFC_SQ_SRC_2 0xF4 |
||
| 1750 | #define V_008DFC_SQ_SRC_M_2 0xF5 |
||
| 1751 | #define V_008DFC_SQ_SRC_4 0xF6 |
||
| 1752 | #define V_008DFC_SQ_SRC_M_4 0xF7 |
||
| 1753 | #define V_008DFC_SQ_SRC_VCCZ 0xFB |
||
| 1754 | #define V_008DFC_SQ_SRC_EXECZ 0xFC |
||
| 1755 | #define V_008DFC_SQ_SRC_SCC 0xFD |
||
| 1756 | #define V_008DFC_SQ_SRC_LDS_DIRECT 0xFE |
||
| 1757 | #define S_008DFC_OP(x) (((x) & 0x7F) << 16) |
||
| 1758 | #define G_008DFC_OP(x) (((x) >> 16) & 0x7F) |
||
| 1759 | #define C_008DFC_OP 0xFF80FFFF |
||
| 1760 | #define V_008DFC_SQ_S_CMP_EQ_I32 0x00 |
||
| 1761 | #define V_008DFC_SQ_S_CMP_LG_I32 0x01 |
||
| 1762 | #define V_008DFC_SQ_S_CMP_GT_I32 0x02 |
||
| 1763 | #define V_008DFC_SQ_S_CMP_GE_I32 0x03 |
||
| 1764 | #define V_008DFC_SQ_S_CMP_LT_I32 0x04 |
||
| 1765 | #define V_008DFC_SQ_S_CMP_LE_I32 0x05 |
||
| 1766 | #define V_008DFC_SQ_S_CMP_EQ_U32 0x06 |
||
| 1767 | #define V_008DFC_SQ_S_CMP_LG_U32 0x07 |
||
| 1768 | #define V_008DFC_SQ_S_CMP_GT_U32 0x08 |
||
| 1769 | #define V_008DFC_SQ_S_CMP_GE_U32 0x09 |
||
| 1770 | #define V_008DFC_SQ_S_CMP_LT_U32 0x0A |
||
| 1771 | #define V_008DFC_SQ_S_CMP_LE_U32 0x0B |
||
| 1772 | #define V_008DFC_SQ_S_BITCMP0_B32 0x0C |
||
| 1773 | #define V_008DFC_SQ_S_BITCMP1_B32 0x0D |
||
| 1774 | #define V_008DFC_SQ_S_BITCMP0_B64 0x0E |
||
| 1775 | #define V_008DFC_SQ_S_BITCMP1_B64 0x0F |
||
| 1776 | #define V_008DFC_SQ_S_SETVSKIP 0x10 |
||
| 1777 | #define S_008DFC_ENCODING(x) (((x) & 0x1FF) << 23) |
||
| 1778 | #define G_008DFC_ENCODING(x) (((x) >> 23) & 0x1FF) |
||
| 1779 | #define C_008DFC_ENCODING 0x007FFFFF |
||
| 1780 | #define V_008DFC_SQ_ENC_SOPC_FIELD 0x17E |
||
| 1781 | #endif |
||
| 1782 | #define R_008DFC_SQ_EXP_0 0x008DFC |
||
| 1783 | #define S_008DFC_EN(x) (((x) & 0x0F) << 0) |
||
| 1784 | #define G_008DFC_EN(x) (((x) >> 0) & 0x0F) |
||
| 1785 | #define C_008DFC_EN 0xFFFFFFF0 |
||
| 1786 | #define S_008DFC_TGT(x) (((x) & 0x3F) << 4) |
||
| 1787 | #define G_008DFC_TGT(x) (((x) >> 4) & 0x3F) |
||
| 1788 | #define C_008DFC_TGT 0xFFFFFC0F |
||
| 1789 | #define V_008DFC_SQ_EXP_MRT 0x00 |
||
| 1790 | #define V_008DFC_SQ_EXP_MRTZ 0x08 |
||
| 1791 | #define V_008DFC_SQ_EXP_NULL 0x09 |
||
| 1792 | #define V_008DFC_SQ_EXP_POS 0x0C |
||
| 1793 | #define V_008DFC_SQ_EXP_PARAM 0x20 |
||
| 1794 | #define S_008DFC_COMPR(x) (((x) & 0x1) << 10) |
||
| 1795 | #define G_008DFC_COMPR(x) (((x) >> 10) & 0x1) |
||
| 1796 | #define C_008DFC_COMPR 0xFFFFFBFF |
||
| 1797 | #define S_008DFC_DONE(x) (((x) & 0x1) << 11) |
||
| 1798 | #define G_008DFC_DONE(x) (((x) >> 11) & 0x1) |
||
| 1799 | #define C_008DFC_DONE 0xFFFFF7FF |
||
| 1800 | #define S_008DFC_VM(x) (((x) & 0x1) << 12) |
||
| 1801 | #define G_008DFC_VM(x) (((x) >> 12) & 0x1) |
||
| 1802 | #define C_008DFC_VM 0xFFFFEFFF |
||
| 1803 | #define S_008DFC_ENCODING(x) (((x) & 0x3F) << 26) |
||
| 1804 | #define G_008DFC_ENCODING(x) (((x) >> 26) & 0x3F) |
||
| 1805 | #define C_008DFC_ENCODING 0x03FFFFFF |
||
| 1806 | #define V_008DFC_SQ_ENC_EXP_FIELD 0x3E |
||
| 1807 | #if 0 |
||
| 1808 | #define R_008DFC_SQ_MIMG_0 0x008DFC |
||
| 1809 | #define S_008DFC_DMASK(x) (((x) & 0x0F) << 8) |
||
| 1810 | #define G_008DFC_DMASK(x) (((x) >> 8) & 0x0F) |
||
| 1811 | #define C_008DFC_DMASK 0xFFFFF0FF |
||
| 1812 | #define S_008DFC_UNORM(x) (((x) & 0x1) << 12) |
||
| 1813 | #define G_008DFC_UNORM(x) (((x) >> 12) & 0x1) |
||
| 1814 | #define C_008DFC_UNORM 0xFFFFEFFF |
||
| 1815 | #define S_008DFC_GLC(x) (((x) & 0x1) << 13) |
||
| 1816 | #define G_008DFC_GLC(x) (((x) >> 13) & 0x1) |
||
| 1817 | #define C_008DFC_GLC 0xFFFFDFFF |
||
| 1818 | #define S_008DFC_DA(x) (((x) & 0x1) << 14) |
||
| 1819 | #define G_008DFC_DA(x) (((x) >> 14) & 0x1) |
||
| 1820 | #define C_008DFC_DA 0xFFFFBFFF |
||
| 1821 | #define S_008DFC_R128(x) (((x) & 0x1) << 15) |
||
| 1822 | #define G_008DFC_R128(x) (((x) >> 15) & 0x1) |
||
| 1823 | #define C_008DFC_R128 0xFFFF7FFF |
||
| 1824 | #define S_008DFC_TFE(x) (((x) & 0x1) << 16) |
||
| 1825 | #define G_008DFC_TFE(x) (((x) >> 16) & 0x1) |
||
| 1826 | #define C_008DFC_TFE 0xFFFEFFFF |
||
| 1827 | #define S_008DFC_LWE(x) (((x) & 0x1) << 17) |
||
| 1828 | #define G_008DFC_LWE(x) (((x) >> 17) & 0x1) |
||
| 1829 | #define C_008DFC_LWE 0xFFFDFFFF |
||
| 1830 | #define S_008DFC_OP(x) (((x) & 0x7F) << 18) |
||
| 1831 | #define G_008DFC_OP(x) (((x) >> 18) & 0x7F) |
||
| 1832 | #define C_008DFC_OP 0xFE03FFFF |
||
| 1833 | #define V_008DFC_SQ_IMAGE_LOAD 0x00 |
||
| 1834 | #define V_008DFC_SQ_IMAGE_LOAD_MIP 0x01 |
||
| 1835 | #define V_008DFC_SQ_IMAGE_LOAD_PCK 0x02 |
||
| 1836 | #define V_008DFC_SQ_IMAGE_LOAD_PCK_SGN 0x03 |
||
| 1837 | #define V_008DFC_SQ_IMAGE_LOAD_MIP_PCK 0x04 |
||
| 1838 | #define V_008DFC_SQ_IMAGE_LOAD_MIP_PCK_SGN 0x05 |
||
| 1839 | #define V_008DFC_SQ_IMAGE_STORE 0x08 |
||
| 1840 | #define V_008DFC_SQ_IMAGE_STORE_MIP 0x09 |
||
| 1841 | #define V_008DFC_SQ_IMAGE_STORE_PCK 0x0A |
||
| 1842 | #define V_008DFC_SQ_IMAGE_STORE_MIP_PCK 0x0B |
||
| 1843 | #define V_008DFC_SQ_IMAGE_GET_RESINFO 0x0E |
||
| 1844 | #define V_008DFC_SQ_IMAGE_ATOMIC_SWAP 0x0F |
||
| 1845 | #define V_008DFC_SQ_IMAGE_ATOMIC_CMPSWAP 0x10 |
||
| 1846 | #define V_008DFC_SQ_IMAGE_ATOMIC_ADD 0x11 |
||
| 1847 | #define V_008DFC_SQ_IMAGE_ATOMIC_SUB 0x12 |
||
| 1848 | #define V_008DFC_SQ_IMAGE_ATOMIC_RSUB 0x13 /* not on CIK */ |
||
| 1849 | #define V_008DFC_SQ_IMAGE_ATOMIC_SMIN 0x14 |
||
| 1850 | #define V_008DFC_SQ_IMAGE_ATOMIC_UMIN 0x15 |
||
| 1851 | #define V_008DFC_SQ_IMAGE_ATOMIC_SMAX 0x16 |
||
| 1852 | #define V_008DFC_SQ_IMAGE_ATOMIC_UMAX 0x17 |
||
| 1853 | #define V_008DFC_SQ_IMAGE_ATOMIC_AND 0x18 |
||
| 1854 | #define V_008DFC_SQ_IMAGE_ATOMIC_OR 0x19 |
||
| 1855 | #define V_008DFC_SQ_IMAGE_ATOMIC_XOR 0x1A |
||
| 1856 | #define V_008DFC_SQ_IMAGE_ATOMIC_INC 0x1B |
||
| 1857 | #define V_008DFC_SQ_IMAGE_ATOMIC_DEC 0x1C |
||
| 1858 | #define V_008DFC_SQ_IMAGE_ATOMIC_FCMPSWAP 0x1D |
||
| 1859 | #define V_008DFC_SQ_IMAGE_ATOMIC_FMIN 0x1E |
||
| 1860 | #define V_008DFC_SQ_IMAGE_ATOMIC_FMAX 0x1F |
||
| 1861 | #define V_008DFC_SQ_IMAGE_SAMPLE 0x20 |
||
| 1862 | #define V_008DFC_SQ_IMAGE_SAMPLE_CL 0x21 |
||
| 1863 | #define V_008DFC_SQ_IMAGE_SAMPLE_D 0x22 |
||
| 1864 | #define V_008DFC_SQ_IMAGE_SAMPLE_D_CL 0x23 |
||
| 1865 | #define V_008DFC_SQ_IMAGE_SAMPLE_L 0x24 |
||
| 1866 | #define V_008DFC_SQ_IMAGE_SAMPLE_B 0x25 |
||
| 1867 | #define V_008DFC_SQ_IMAGE_SAMPLE_B_CL 0x26 |
||
| 1868 | #define V_008DFC_SQ_IMAGE_SAMPLE_LZ 0x27 |
||
| 1869 | #define V_008DFC_SQ_IMAGE_SAMPLE_C 0x28 |
||
| 1870 | #define V_008DFC_SQ_IMAGE_SAMPLE_C_CL 0x29 |
||
| 1871 | #define V_008DFC_SQ_IMAGE_SAMPLE_C_D 0x2A |
||
| 1872 | #define V_008DFC_SQ_IMAGE_SAMPLE_C_D_CL 0x2B |
||
| 1873 | #define V_008DFC_SQ_IMAGE_SAMPLE_C_L 0x2C |
||
| 1874 | #define V_008DFC_SQ_IMAGE_SAMPLE_C_B 0x2D |
||
| 1875 | #define V_008DFC_SQ_IMAGE_SAMPLE_C_B_CL 0x2E |
||
| 1876 | #define V_008DFC_SQ_IMAGE_SAMPLE_C_LZ 0x2F |
||
| 1877 | #define V_008DFC_SQ_IMAGE_SAMPLE_O 0x30 |
||
| 1878 | #define V_008DFC_SQ_IMAGE_SAMPLE_CL_O 0x31 |
||
| 1879 | #define V_008DFC_SQ_IMAGE_SAMPLE_D_O 0x32 |
||
| 1880 | #define V_008DFC_SQ_IMAGE_SAMPLE_D_CL_O 0x33 |
||
| 1881 | #define V_008DFC_SQ_IMAGE_SAMPLE_L_O 0x34 |
||
| 1882 | #define V_008DFC_SQ_IMAGE_SAMPLE_B_O 0x35 |
||
| 1883 | #define V_008DFC_SQ_IMAGE_SAMPLE_B_CL_O 0x36 |
||
| 1884 | #define V_008DFC_SQ_IMAGE_SAMPLE_LZ_O 0x37 |
||
| 1885 | #define V_008DFC_SQ_IMAGE_SAMPLE_C_O 0x38 |
||
| 1886 | #define V_008DFC_SQ_IMAGE_SAMPLE_C_CL_O 0x39 |
||
| 1887 | #define V_008DFC_SQ_IMAGE_SAMPLE_C_D_O 0x3A |
||
| 1888 | #define V_008DFC_SQ_IMAGE_SAMPLE_C_D_CL_O 0x3B |
||
| 1889 | #define V_008DFC_SQ_IMAGE_SAMPLE_C_L_O 0x3C |
||
| 1890 | #define V_008DFC_SQ_IMAGE_SAMPLE_C_B_O 0x3D |
||
| 1891 | #define V_008DFC_SQ_IMAGE_SAMPLE_C_B_CL_O 0x3E |
||
| 1892 | #define V_008DFC_SQ_IMAGE_SAMPLE_C_LZ_O 0x3F |
||
| 1893 | #define V_008DFC_SQ_IMAGE_GATHER4 0x40 |
||
| 1894 | #define V_008DFC_SQ_IMAGE_GATHER4_CL 0x41 |
||
| 1895 | #define V_008DFC_SQ_IMAGE_GATHER4_L 0x44 |
||
| 1896 | #define V_008DFC_SQ_IMAGE_GATHER4_B 0x45 |
||
| 1897 | #define V_008DFC_SQ_IMAGE_GATHER4_B_CL 0x46 |
||
| 1898 | #define V_008DFC_SQ_IMAGE_GATHER4_LZ 0x47 |
||
| 1899 | #define V_008DFC_SQ_IMAGE_GATHER4_C 0x48 |
||
| 1900 | #define V_008DFC_SQ_IMAGE_GATHER4_C_CL 0x49 |
||
| 1901 | #define V_008DFC_SQ_IMAGE_GATHER4_C_L 0x4C |
||
| 1902 | #define V_008DFC_SQ_IMAGE_GATHER4_C_B 0x4D |
||
| 1903 | #define V_008DFC_SQ_IMAGE_GATHER4_C_B_CL 0x4E |
||
| 1904 | #define V_008DFC_SQ_IMAGE_GATHER4_C_LZ 0x4F |
||
| 1905 | #define V_008DFC_SQ_IMAGE_GATHER4_O 0x50 |
||
| 1906 | #define V_008DFC_SQ_IMAGE_GATHER4_CL_O 0x51 |
||
| 1907 | #define V_008DFC_SQ_IMAGE_GATHER4_L_O 0x54 |
||
| 1908 | #define V_008DFC_SQ_IMAGE_GATHER4_B_O 0x55 |
||
| 1909 | #define V_008DFC_SQ_IMAGE_GATHER4_B_CL_O 0x56 |
||
| 1910 | #define V_008DFC_SQ_IMAGE_GATHER4_LZ_O 0x57 |
||
| 1911 | #define V_008DFC_SQ_IMAGE_GATHER4_C_O 0x58 |
||
| 1912 | #define V_008DFC_SQ_IMAGE_GATHER4_C_CL_O 0x59 |
||
| 1913 | #define V_008DFC_SQ_IMAGE_GATHER4_C_L_O 0x5C |
||
| 1914 | #define V_008DFC_SQ_IMAGE_GATHER4_C_B_O 0x5D |
||
| 1915 | #define V_008DFC_SQ_IMAGE_GATHER4_C_B_CL_O 0x5E |
||
| 1916 | #define V_008DFC_SQ_IMAGE_GATHER4_C_LZ_O 0x5F |
||
| 1917 | #define V_008DFC_SQ_IMAGE_GET_LOD 0x60 |
||
| 1918 | #define V_008DFC_SQ_IMAGE_SAMPLE_CD 0x68 |
||
| 1919 | #define V_008DFC_SQ_IMAGE_SAMPLE_CD_CL 0x69 |
||
| 1920 | #define V_008DFC_SQ_IMAGE_SAMPLE_C_CD 0x6A |
||
| 1921 | #define V_008DFC_SQ_IMAGE_SAMPLE_C_CD_CL 0x6B |
||
| 1922 | #define V_008DFC_SQ_IMAGE_SAMPLE_CD_O 0x6C |
||
| 1923 | #define V_008DFC_SQ_IMAGE_SAMPLE_CD_CL_O 0x6D |
||
| 1924 | #define V_008DFC_SQ_IMAGE_SAMPLE_C_CD_O 0x6E |
||
| 1925 | #define V_008DFC_SQ_IMAGE_SAMPLE_C_CD_CL_O 0x6F |
||
| 1926 | #define S_008DFC_SLC(x) (((x) & 0x1) << 25) |
||
| 1927 | #define G_008DFC_SLC(x) (((x) >> 25) & 0x1) |
||
| 1928 | #define C_008DFC_SLC 0xFDFFFFFF |
||
| 1929 | #define S_008DFC_ENCODING(x) (((x) & 0x3F) << 26) |
||
| 1930 | #define G_008DFC_ENCODING(x) (((x) >> 26) & 0x3F) |
||
| 1931 | #define C_008DFC_ENCODING 0x03FFFFFF |
||
| 1932 | #define V_008DFC_SQ_ENC_MIMG_FIELD 0x3C |
||
| 1933 | #define R_008DFC_SQ_SOPP 0x008DFC |
||
| 1934 | #define S_008DFC_SIMM16(x) (((x) & 0xFFFF) << 0) |
||
| 1935 | #define G_008DFC_SIMM16(x) (((x) >> 0) & 0xFFFF) |
||
| 1936 | #define C_008DFC_SIMM16 0xFFFF0000 |
||
| 1937 | #define S_008DFC_OP(x) (((x) & 0x7F) << 16) |
||
| 1938 | #define G_008DFC_OP(x) (((x) >> 16) & 0x7F) |
||
| 1939 | #define C_008DFC_OP 0xFF80FFFF |
||
| 1940 | #define V_008DFC_SQ_S_NOP 0x00 |
||
| 1941 | #define V_008DFC_SQ_S_ENDPGM 0x01 |
||
| 1942 | #define V_008DFC_SQ_S_BRANCH 0x02 |
||
| 1943 | #define V_008DFC_SQ_S_CBRANCH_SCC0 0x04 |
||
| 1944 | #define V_008DFC_SQ_S_CBRANCH_SCC1 0x05 |
||
| 1945 | #define V_008DFC_SQ_S_CBRANCH_VCCZ 0x06 |
||
| 1946 | #define V_008DFC_SQ_S_CBRANCH_VCCNZ 0x07 |
||
| 1947 | #define V_008DFC_SQ_S_CBRANCH_EXECZ 0x08 |
||
| 1948 | #define V_008DFC_SQ_S_CBRANCH_EXECNZ 0x09 |
||
| 1949 | #define V_008DFC_SQ_S_BARRIER 0x0A |
||
| 1950 | /* CIK */ |
||
| 1951 | #define V_008DFC_SQ_S_SETKILL 0x0B |
||
| 1952 | /* */ |
||
| 1953 | #define V_008DFC_SQ_S_WAITCNT 0x0C |
||
| 1954 | #define V_008DFC_SQ_S_SETHALT 0x0D |
||
| 1955 | #define V_008DFC_SQ_S_SLEEP 0x0E |
||
| 1956 | #define V_008DFC_SQ_S_SETPRIO 0x0F |
||
| 1957 | #define V_008DFC_SQ_S_SENDMSG 0x10 |
||
| 1958 | #define V_008DFC_SQ_S_SENDMSGHALT 0x11 |
||
| 1959 | #define V_008DFC_SQ_S_TRAP 0x12 |
||
| 1960 | #define V_008DFC_SQ_S_ICACHE_INV 0x13 |
||
| 1961 | #define V_008DFC_SQ_S_INCPERFLEVEL 0x14 |
||
| 1962 | #define V_008DFC_SQ_S_DECPERFLEVEL 0x15 |
||
| 1963 | #define V_008DFC_SQ_S_TTRACEDATA 0x16 |
||
| 1964 | /* CIK */ |
||
| 1965 | #define V_008DFC_SQ_S_CBRANCH_CDBGSYS 0x17 |
||
| 1966 | #define V_008DFC_SQ_S_CBRANCH_CDBGUSER 0x18 |
||
| 1967 | #define V_008DFC_SQ_S_CBRANCH_CDBGSYS_OR_USER 0x19 |
||
| 1968 | #define V_008DFC_SQ_S_CBRANCH_CDBGSYS_AND_USER 0x1A |
||
| 1969 | /* */ |
||
| 1970 | #define S_008DFC_ENCODING(x) (((x) & 0x1FF) << 23) |
||
| 1971 | #define G_008DFC_ENCODING(x) (((x) >> 23) & 0x1FF) |
||
| 1972 | #define C_008DFC_ENCODING 0x007FFFFF |
||
| 1973 | #define V_008DFC_SQ_ENC_SOPP_FIELD 0x17F |
||
| 1974 | #define R_008DFC_SQ_VINTRP 0x008DFC |
||
| 1975 | #define S_008DFC_VSRC(x) (((x) & 0xFF) << 0) |
||
| 1976 | #define G_008DFC_VSRC(x) (((x) >> 0) & 0xFF) |
||
| 1977 | #define C_008DFC_VSRC 0xFFFFFF00 |
||
| 1978 | #define V_008DFC_SQ_VGPR 0x00 |
||
| 1979 | #define S_008DFC_ATTRCHAN(x) (((x) & 0x03) << 8) |
||
| 1980 | #define G_008DFC_ATTRCHAN(x) (((x) >> 8) & 0x03) |
||
| 1981 | #define C_008DFC_ATTRCHAN 0xFFFFFCFF |
||
| 1982 | #define V_008DFC_SQ_CHAN_X 0x00 |
||
| 1983 | #define V_008DFC_SQ_CHAN_Y 0x01 |
||
| 1984 | #define V_008DFC_SQ_CHAN_Z 0x02 |
||
| 1985 | #define V_008DFC_SQ_CHAN_W 0x03 |
||
| 1986 | #define S_008DFC_ATTR(x) (((x) & 0x3F) << 10) |
||
| 1987 | #define G_008DFC_ATTR(x) (((x) >> 10) & 0x3F) |
||
| 1988 | #define C_008DFC_ATTR 0xFFFF03FF |
||
| 1989 | #define V_008DFC_SQ_ATTR 0x00 |
||
| 1990 | #define S_008DFC_OP(x) (((x) & 0x03) << 16) |
||
| 1991 | #define G_008DFC_OP(x) (((x) >> 16) & 0x03) |
||
| 1992 | #define C_008DFC_OP 0xFFFCFFFF |
||
| 1993 | #define V_008DFC_SQ_V_INTERP_P1_F32 0x00 |
||
| 1994 | #define V_008DFC_SQ_V_INTERP_P2_F32 0x01 |
||
| 1995 | #define V_008DFC_SQ_V_INTERP_MOV_F32 0x02 |
||
| 1996 | #define S_008DFC_VDST(x) (((x) & 0xFF) << 18) |
||
| 1997 | #define G_008DFC_VDST(x) (((x) >> 18) & 0xFF) |
||
| 1998 | #define C_008DFC_VDST 0xFC03FFFF |
||
| 1999 | #define V_008DFC_SQ_VGPR 0x00 |
||
| 2000 | #define S_008DFC_ENCODING(x) (((x) & 0x3F) << 26) |
||
| 2001 | #define G_008DFC_ENCODING(x) (((x) >> 26) & 0x3F) |
||
| 2002 | #define C_008DFC_ENCODING 0x03FFFFFF |
||
| 2003 | #define V_008DFC_SQ_ENC_VINTRP_FIELD 0x32 |
||
| 2004 | #define R_008DFC_SQ_MTBUF_0 0x008DFC |
||
| 2005 | #define S_008DFC_OFFSET(x) (((x) & 0xFFF) << 0) |
||
| 2006 | #define G_008DFC_OFFSET(x) (((x) >> 0) & 0xFFF) |
||
| 2007 | #define C_008DFC_OFFSET 0xFFFFF000 |
||
| 2008 | #define S_008DFC_OFFEN(x) (((x) & 0x1) << 12) |
||
| 2009 | #define G_008DFC_OFFEN(x) (((x) >> 12) & 0x1) |
||
| 2010 | #define C_008DFC_OFFEN 0xFFFFEFFF |
||
| 2011 | #define S_008DFC_IDXEN(x) (((x) & 0x1) << 13) |
||
| 2012 | #define G_008DFC_IDXEN(x) (((x) >> 13) & 0x1) |
||
| 2013 | #define C_008DFC_IDXEN 0xFFFFDFFF |
||
| 2014 | #define S_008DFC_GLC(x) (((x) & 0x1) << 14) |
||
| 2015 | #define G_008DFC_GLC(x) (((x) >> 14) & 0x1) |
||
| 2016 | #define C_008DFC_GLC 0xFFFFBFFF |
||
| 2017 | #define S_008DFC_ADDR64(x) (((x) & 0x1) << 15) |
||
| 2018 | #define G_008DFC_ADDR64(x) (((x) >> 15) & 0x1) |
||
| 2019 | #define C_008DFC_ADDR64 0xFFFF7FFF |
||
| 2020 | #define S_008DFC_OP(x) (((x) & 0x07) << 16) |
||
| 2021 | #define G_008DFC_OP(x) (((x) >> 16) & 0x07) |
||
| 2022 | #define C_008DFC_OP 0xFFF8FFFF |
||
| 2023 | #define V_008DFC_SQ_TBUFFER_LOAD_FORMAT_X 0x00 |
||
| 2024 | #define V_008DFC_SQ_TBUFFER_LOAD_FORMAT_XY 0x01 |
||
| 2025 | #define V_008DFC_SQ_TBUFFER_LOAD_FORMAT_XYZ 0x02 |
||
| 2026 | #define V_008DFC_SQ_TBUFFER_LOAD_FORMAT_XYZW 0x03 |
||
| 2027 | #define V_008DFC_SQ_TBUFFER_STORE_FORMAT_X 0x04 |
||
| 2028 | #define V_008DFC_SQ_TBUFFER_STORE_FORMAT_XY 0x05 |
||
| 2029 | #define V_008DFC_SQ_TBUFFER_STORE_FORMAT_XYZ 0x06 |
||
| 2030 | #define V_008DFC_SQ_TBUFFER_STORE_FORMAT_XYZW 0x07 |
||
| 2031 | #define S_008DFC_DFMT(x) (((x) & 0x0F) << 19) |
||
| 2032 | #define G_008DFC_DFMT(x) (((x) >> 19) & 0x0F) |
||
| 2033 | #define C_008DFC_DFMT 0xFF87FFFF |
||
| 2034 | #define S_008DFC_NFMT(x) (((x) & 0x07) << 23) |
||
| 2035 | #define G_008DFC_NFMT(x) (((x) >> 23) & 0x07) |
||
| 2036 | #define C_008DFC_NFMT 0xFC7FFFFF |
||
| 2037 | #define S_008DFC_ENCODING(x) (((x) & 0x3F) << 26) |
||
| 2038 | #define G_008DFC_ENCODING(x) (((x) >> 26) & 0x3F) |
||
| 2039 | #define C_008DFC_ENCODING 0x03FFFFFF |
||
| 2040 | #define V_008DFC_SQ_ENC_MTBUF_FIELD 0x3A |
||
| 2041 | #define R_008DFC_SQ_SMRD 0x008DFC |
||
| 2042 | #define S_008DFC_OFFSET(x) (((x) & 0xFF) << 0) |
||
| 2043 | #define G_008DFC_OFFSET(x) (((x) >> 0) & 0xFF) |
||
| 2044 | #define C_008DFC_OFFSET 0xFFFFFF00 |
||
| 2045 | #define V_008DFC_SQ_SGPR 0x00 |
||
| 2046 | /* CIK */ |
||
| 2047 | #define V_008DFC_SQ_FLAT_SCRATCH_LO 0x68 |
||
| 2048 | #define V_008DFC_SQ_FLAT_SCRATCH_HI 0x69 |
||
| 2049 | /* */ |
||
| 2050 | #define V_008DFC_SQ_VCC_LO 0x6A |
||
| 2051 | #define V_008DFC_SQ_VCC_HI 0x6B |
||
| 2052 | #define V_008DFC_SQ_TBA_LO 0x6C |
||
| 2053 | #define V_008DFC_SQ_TBA_HI 0x6D |
||
| 2054 | #define V_008DFC_SQ_TMA_LO 0x6E |
||
| 2055 | #define V_008DFC_SQ_TMA_HI 0x6F |
||
| 2056 | #define V_008DFC_SQ_TTMP0 0x70 |
||
| 2057 | #define V_008DFC_SQ_TTMP1 0x71 |
||
| 2058 | #define V_008DFC_SQ_TTMP2 0x72 |
||
| 2059 | #define V_008DFC_SQ_TTMP3 0x73 |
||
| 2060 | #define V_008DFC_SQ_TTMP4 0x74 |
||
| 2061 | #define V_008DFC_SQ_TTMP5 0x75 |
||
| 2062 | #define V_008DFC_SQ_TTMP6 0x76 |
||
| 2063 | #define V_008DFC_SQ_TTMP7 0x77 |
||
| 2064 | #define V_008DFC_SQ_TTMP8 0x78 |
||
| 2065 | #define V_008DFC_SQ_TTMP9 0x79 |
||
| 2066 | #define V_008DFC_SQ_TTMP10 0x7A |
||
| 2067 | #define V_008DFC_SQ_TTMP11 0x7B |
||
| 2068 | /* CIK */ |
||
| 2069 | #define V_008DFC_SQ_SRC_LITERAL 0xFF |
||
| 2070 | /* */ |
||
| 2071 | #define S_008DFC_IMM(x) (((x) & 0x1) << 8) |
||
| 2072 | #define G_008DFC_IMM(x) (((x) >> 8) & 0x1) |
||
| 2073 | #define C_008DFC_IMM 0xFFFFFEFF |
||
| 2074 | #define S_008DFC_SBASE(x) (((x) & 0x3F) << 9) |
||
| 2075 | #define G_008DFC_SBASE(x) (((x) >> 9) & 0x3F) |
||
| 2076 | #define C_008DFC_SBASE 0xFFFF81FF |
||
| 2077 | #define S_008DFC_SDST(x) (((x) & 0x7F) << 15) |
||
| 2078 | #define G_008DFC_SDST(x) (((x) >> 15) & 0x7F) |
||
| 2079 | #define C_008DFC_SDST 0xFFC07FFF |
||
| 2080 | #define V_008DFC_SQ_SGPR 0x00 |
||
| 2081 | /* CIK */ |
||
| 2082 | #define V_008DFC_SQ_FLAT_SCRATCH_LO 0x68 |
||
| 2083 | #define V_008DFC_SQ_FLAT_SCRATCH_HI 0x69 |
||
| 2084 | /* */ |
||
| 2085 | #define V_008DFC_SQ_VCC_LO 0x6A |
||
| 2086 | #define V_008DFC_SQ_VCC_HI 0x6B |
||
| 2087 | #define V_008DFC_SQ_TBA_LO 0x6C |
||
| 2088 | #define V_008DFC_SQ_TBA_HI 0x6D |
||
| 2089 | #define V_008DFC_SQ_TMA_LO 0x6E |
||
| 2090 | #define V_008DFC_SQ_TMA_HI 0x6F |
||
| 2091 | #define V_008DFC_SQ_TTMP0 0x70 |
||
| 2092 | #define V_008DFC_SQ_TTMP1 0x71 |
||
| 2093 | #define V_008DFC_SQ_TTMP2 0x72 |
||
| 2094 | #define V_008DFC_SQ_TTMP3 0x73 |
||
| 2095 | #define V_008DFC_SQ_TTMP4 0x74 |
||
| 2096 | #define V_008DFC_SQ_TTMP5 0x75 |
||
| 2097 | #define V_008DFC_SQ_TTMP6 0x76 |
||
| 2098 | #define V_008DFC_SQ_TTMP7 0x77 |
||
| 2099 | #define V_008DFC_SQ_TTMP8 0x78 |
||
| 2100 | #define V_008DFC_SQ_TTMP9 0x79 |
||
| 2101 | #define V_008DFC_SQ_TTMP10 0x7A |
||
| 2102 | #define V_008DFC_SQ_TTMP11 0x7B |
||
| 2103 | #define V_008DFC_SQ_M0 0x7C |
||
| 2104 | #define V_008DFC_SQ_EXEC_LO 0x7E |
||
| 2105 | #define V_008DFC_SQ_EXEC_HI 0x7F |
||
| 2106 | #define S_008DFC_OP(x) (((x) & 0x1F) << 22) |
||
| 2107 | #define G_008DFC_OP(x) (((x) >> 22) & 0x1F) |
||
| 2108 | #define C_008DFC_OP 0xF83FFFFF |
||
| 2109 | #define V_008DFC_SQ_S_LOAD_DWORD 0x00 |
||
| 2110 | #define V_008DFC_SQ_S_LOAD_DWORDX2 0x01 |
||
| 2111 | #define V_008DFC_SQ_S_LOAD_DWORDX4 0x02 |
||
| 2112 | #define V_008DFC_SQ_S_LOAD_DWORDX8 0x03 |
||
| 2113 | #define V_008DFC_SQ_S_LOAD_DWORDX16 0x04 |
||
| 2114 | #define V_008DFC_SQ_S_BUFFER_LOAD_DWORD 0x08 |
||
| 2115 | #define V_008DFC_SQ_S_BUFFER_LOAD_DWORDX2 0x09 |
||
| 2116 | #define V_008DFC_SQ_S_BUFFER_LOAD_DWORDX4 0x0A |
||
| 2117 | #define V_008DFC_SQ_S_BUFFER_LOAD_DWORDX8 0x0B |
||
| 2118 | #define V_008DFC_SQ_S_BUFFER_LOAD_DWORDX16 0x0C |
||
| 2119 | /* CIK */ |
||
| 2120 | #define V_008DFC_SQ_S_DCACHE_INV_VOL 0x1D |
||
| 2121 | /* */ |
||
| 2122 | #define V_008DFC_SQ_S_MEMTIME 0x1E |
||
| 2123 | #define V_008DFC_SQ_S_DCACHE_INV 0x1F |
||
| 2124 | #define S_008DFC_ENCODING(x) (((x) & 0x1F) << 27) |
||
| 2125 | #define G_008DFC_ENCODING(x) (((x) >> 27) & 0x1F) |
||
| 2126 | #define C_008DFC_ENCODING 0x07FFFFFF |
||
| 2127 | #define V_008DFC_SQ_ENC_SMRD_FIELD 0x18 |
||
| 2128 | /* CIK */ |
||
| 2129 | #define R_008DFC_SQ_FLAT_0 0x008DFC |
||
| 2130 | #define S_008DFC_GLC(x) (((x) & 0x1) << 16) |
||
| 2131 | #define G_008DFC_GLC(x) (((x) >> 16) & 0x1) |
||
| 2132 | #define C_008DFC_GLC 0xFFFEFFFF |
||
| 2133 | #define S_008DFC_SLC(x) (((x) & 0x1) << 17) |
||
| 2134 | #define G_008DFC_SLC(x) (((x) >> 17) & 0x1) |
||
| 2135 | #define C_008DFC_SLC 0xFFFDFFFF |
||
| 2136 | #define S_008DFC_OP(x) (((x) & 0x7F) << 18) |
||
| 2137 | #define G_008DFC_OP(x) (((x) >> 18) & 0x7F) |
||
| 2138 | #define C_008DFC_OP 0xFE03FFFF |
||
| 2139 | #define V_008DFC_SQ_FLAT_LOAD_UBYTE 0x08 |
||
| 2140 | #define V_008DFC_SQ_FLAT_LOAD_SBYTE 0x09 |
||
| 2141 | #define V_008DFC_SQ_FLAT_LOAD_USHORT 0x0A |
||
| 2142 | #define V_008DFC_SQ_FLAT_LOAD_SSHORT 0x0B |
||
| 2143 | #define V_008DFC_SQ_FLAT_LOAD_DWORD 0x0C |
||
| 2144 | #define V_008DFC_SQ_FLAT_LOAD_DWORDX2 0x0D |
||
| 2145 | #define V_008DFC_SQ_FLAT_LOAD_DWORDX4 0x0E |
||
| 2146 | #define V_008DFC_SQ_FLAT_LOAD_DWORDX3 0x0F |
||
| 2147 | #define V_008DFC_SQ_FLAT_STORE_BYTE 0x18 |
||
| 2148 | #define V_008DFC_SQ_FLAT_STORE_SHORT 0x1A |
||
| 2149 | #define V_008DFC_SQ_FLAT_STORE_DWORD 0x1C |
||
| 2150 | #define V_008DFC_SQ_FLAT_STORE_DWORDX2 0x1D |
||
| 2151 | #define V_008DFC_SQ_FLAT_STORE_DWORDX4 0x1E |
||
| 2152 | #define V_008DFC_SQ_FLAT_STORE_DWORDX3 0x1F |
||
| 2153 | #define V_008DFC_SQ_FLAT_ATOMIC_SWAP 0x30 |
||
| 2154 | #define V_008DFC_SQ_FLAT_ATOMIC_CMPSWAP 0x31 |
||
| 2155 | #define V_008DFC_SQ_FLAT_ATOMIC_ADD 0x32 |
||
| 2156 | #define V_008DFC_SQ_FLAT_ATOMIC_SUB 0x33 |
||
| 2157 | #define V_008DFC_SQ_FLAT_ATOMIC_SMIN 0x35 |
||
| 2158 | #define V_008DFC_SQ_FLAT_ATOMIC_UMIN 0x36 |
||
| 2159 | #define V_008DFC_SQ_FLAT_ATOMIC_SMAX 0x37 |
||
| 2160 | #define V_008DFC_SQ_FLAT_ATOMIC_UMAX 0x38 |
||
| 2161 | #define V_008DFC_SQ_FLAT_ATOMIC_AND 0x39 |
||
| 2162 | #define V_008DFC_SQ_FLAT_ATOMIC_OR 0x3A |
||
| 2163 | #define V_008DFC_SQ_FLAT_ATOMIC_XOR 0x3B |
||
| 2164 | #define V_008DFC_SQ_FLAT_ATOMIC_INC 0x3C |
||
| 2165 | #define V_008DFC_SQ_FLAT_ATOMIC_DEC 0x3D |
||
| 2166 | #define V_008DFC_SQ_FLAT_ATOMIC_FCMPSWAP 0x3E |
||
| 2167 | #define V_008DFC_SQ_FLAT_ATOMIC_FMIN 0x3F |
||
| 2168 | #define V_008DFC_SQ_FLAT_ATOMIC_FMAX 0x40 |
||
| 2169 | #define V_008DFC_SQ_FLAT_ATOMIC_SWAP_X2 0x50 |
||
| 2170 | #define V_008DFC_SQ_FLAT_ATOMIC_CMPSWAP_X2 0x51 |
||
| 2171 | #define V_008DFC_SQ_FLAT_ATOMIC_ADD_X2 0x52 |
||
| 2172 | #define V_008DFC_SQ_FLAT_ATOMIC_SUB_X2 0x53 |
||
| 2173 | #define V_008DFC_SQ_FLAT_ATOMIC_SMIN_X2 0x55 |
||
| 2174 | #define V_008DFC_SQ_FLAT_ATOMIC_UMIN_X2 0x56 |
||
| 2175 | #define V_008DFC_SQ_FLAT_ATOMIC_SMAX_X2 0x57 |
||
| 2176 | #define V_008DFC_SQ_FLAT_ATOMIC_UMAX_X2 0x58 |
||
| 2177 | #define V_008DFC_SQ_FLAT_ATOMIC_AND_X2 0x59 |
||
| 2178 | #define V_008DFC_SQ_FLAT_ATOMIC_OR_X2 0x5A |
||
| 2179 | #define V_008DFC_SQ_FLAT_ATOMIC_XOR_X2 0x5B |
||
| 2180 | #define V_008DFC_SQ_FLAT_ATOMIC_INC_X2 0x5C |
||
| 2181 | #define V_008DFC_SQ_FLAT_ATOMIC_DEC_X2 0x5D |
||
| 2182 | #define V_008DFC_SQ_FLAT_ATOMIC_FCMPSWAP_X2 0x5E |
||
| 2183 | #define V_008DFC_SQ_FLAT_ATOMIC_FMIN_X2 0x5F |
||
| 2184 | #define V_008DFC_SQ_FLAT_ATOMIC_FMAX_X2 0x60 |
||
| 2185 | #define S_008DFC_ENCODING(x) (((x) & 0x3F) << 26) |
||
| 2186 | #define G_008DFC_ENCODING(x) (((x) >> 26) & 0x3F) |
||
| 2187 | #define C_008DFC_ENCODING 0x03FFFFFF |
||
| 2188 | #define V_008DFC_SQ_ENC_FLAT_FIELD 0x37 |
||
| 2189 | /* */ |
||
| 2190 | #define R_008DFC_SQ_EXP_1 0x008DFC |
||
| 2191 | #define S_008DFC_VSRC0(x) (((x) & 0xFF) << 0) |
||
| 2192 | #define G_008DFC_VSRC0(x) (((x) >> 0) & 0xFF) |
||
| 2193 | #define C_008DFC_VSRC0 0xFFFFFF00 |
||
| 2194 | #define V_008DFC_SQ_VGPR 0x00 |
||
| 2195 | #define S_008DFC_VSRC1(x) (((x) & 0xFF) << 8) |
||
| 2196 | #define G_008DFC_VSRC1(x) (((x) >> 8) & 0xFF) |
||
| 2197 | #define C_008DFC_VSRC1 0xFFFF00FF |
||
| 2198 | #define V_008DFC_SQ_VGPR 0x00 |
||
| 2199 | #define S_008DFC_VSRC2(x) (((x) & 0xFF) << 16) |
||
| 2200 | #define G_008DFC_VSRC2(x) (((x) >> 16) & 0xFF) |
||
| 2201 | #define C_008DFC_VSRC2 0xFF00FFFF |
||
| 2202 | #define V_008DFC_SQ_VGPR 0x00 |
||
| 2203 | #define S_008DFC_VSRC3(x) (((x) & 0xFF) << 24) |
||
| 2204 | #define G_008DFC_VSRC3(x) (((x) >> 24) & 0xFF) |
||
| 2205 | #define C_008DFC_VSRC3 0x00FFFFFF |
||
| 2206 | #define V_008DFC_SQ_VGPR 0x00 |
||
| 2207 | #define R_008DFC_SQ_DS_1 0x008DFC |
||
| 2208 | #define S_008DFC_ADDR(x) (((x) & 0xFF) << 0) |
||
| 2209 | #define G_008DFC_ADDR(x) (((x) >> 0) & 0xFF) |
||
| 2210 | #define C_008DFC_ADDR 0xFFFFFF00 |
||
| 2211 | #define V_008DFC_SQ_VGPR 0x00 |
||
| 2212 | #define S_008DFC_DATA0(x) (((x) & 0xFF) << 8) |
||
| 2213 | #define G_008DFC_DATA0(x) (((x) >> 8) & 0xFF) |
||
| 2214 | #define C_008DFC_DATA0 0xFFFF00FF |
||
| 2215 | #define V_008DFC_SQ_VGPR 0x00 |
||
| 2216 | #define S_008DFC_DATA1(x) (((x) & 0xFF) << 16) |
||
| 2217 | #define G_008DFC_DATA1(x) (((x) >> 16) & 0xFF) |
||
| 2218 | #define C_008DFC_DATA1 0xFF00FFFF |
||
| 2219 | #define V_008DFC_SQ_VGPR 0x00 |
||
| 2220 | #define S_008DFC_VDST(x) (((x) & 0xFF) << 24) |
||
| 2221 | #define G_008DFC_VDST(x) (((x) >> 24) & 0xFF) |
||
| 2222 | #define C_008DFC_VDST 0x00FFFFFF |
||
| 2223 | #define V_008DFC_SQ_VGPR 0x00 |
||
| 2224 | #define R_008DFC_SQ_VOPC 0x008DFC |
||
| 2225 | #define S_008DFC_SRC0(x) (((x) & 0x1FF) << 0) |
||
| 2226 | #define G_008DFC_SRC0(x) (((x) >> 0) & 0x1FF) |
||
| 2227 | #define C_008DFC_SRC0 0xFFFFFE00 |
||
| 2228 | #define V_008DFC_SQ_SGPR 0x00 |
||
| 2229 | #define V_008DFC_SQ_VCC_LO 0x6A |
||
| 2230 | #define V_008DFC_SQ_VCC_HI 0x6B |
||
| 2231 | #define V_008DFC_SQ_TBA_LO 0x6C |
||
| 2232 | #define V_008DFC_SQ_TBA_HI 0x6D |
||
| 2233 | #define V_008DFC_SQ_TMA_LO 0x6E |
||
| 2234 | #define V_008DFC_SQ_TMA_HI 0x6F |
||
| 2235 | #define V_008DFC_SQ_TTMP0 0x70 |
||
| 2236 | #define V_008DFC_SQ_TTMP1 0x71 |
||
| 2237 | #define V_008DFC_SQ_TTMP2 0x72 |
||
| 2238 | #define V_008DFC_SQ_TTMP3 0x73 |
||
| 2239 | #define V_008DFC_SQ_TTMP4 0x74 |
||
| 2240 | #define V_008DFC_SQ_TTMP5 0x75 |
||
| 2241 | #define V_008DFC_SQ_TTMP6 0x76 |
||
| 2242 | #define V_008DFC_SQ_TTMP7 0x77 |
||
| 2243 | #define V_008DFC_SQ_TTMP8 0x78 |
||
| 2244 | #define V_008DFC_SQ_TTMP9 0x79 |
||
| 2245 | #define V_008DFC_SQ_TTMP10 0x7A |
||
| 2246 | #define V_008DFC_SQ_TTMP11 0x7B |
||
| 2247 | #define V_008DFC_SQ_M0 0x7C |
||
| 2248 | #define V_008DFC_SQ_EXEC_LO 0x7E |
||
| 2249 | #define V_008DFC_SQ_EXEC_HI 0x7F |
||
| 2250 | #define V_008DFC_SQ_SRC_0 0x80 |
||
| 2251 | #define V_008DFC_SQ_SRC_1_INT 0x81 |
||
| 2252 | #define V_008DFC_SQ_SRC_2_INT 0x82 |
||
| 2253 | #define V_008DFC_SQ_SRC_3_INT 0x83 |
||
| 2254 | #define V_008DFC_SQ_SRC_4_INT 0x84 |
||
| 2255 | #define V_008DFC_SQ_SRC_5_INT 0x85 |
||
| 2256 | #define V_008DFC_SQ_SRC_6_INT 0x86 |
||
| 2257 | #define V_008DFC_SQ_SRC_7_INT 0x87 |
||
| 2258 | #define V_008DFC_SQ_SRC_8_INT 0x88 |
||
| 2259 | #define V_008DFC_SQ_SRC_9_INT 0x89 |
||
| 2260 | #define V_008DFC_SQ_SRC_10_INT 0x8A |
||
| 2261 | #define V_008DFC_SQ_SRC_11_INT 0x8B |
||
| 2262 | #define V_008DFC_SQ_SRC_12_INT 0x8C |
||
| 2263 | #define V_008DFC_SQ_SRC_13_INT 0x8D |
||
| 2264 | #define V_008DFC_SQ_SRC_14_INT 0x8E |
||
| 2265 | #define V_008DFC_SQ_SRC_15_INT 0x8F |
||
| 2266 | #define V_008DFC_SQ_SRC_16_INT 0x90 |
||
| 2267 | #define V_008DFC_SQ_SRC_17_INT 0x91 |
||
| 2268 | #define V_008DFC_SQ_SRC_18_INT 0x92 |
||
| 2269 | #define V_008DFC_SQ_SRC_19_INT 0x93 |
||
| 2270 | #define V_008DFC_SQ_SRC_20_INT 0x94 |
||
| 2271 | #define V_008DFC_SQ_SRC_21_INT 0x95 |
||
| 2272 | #define V_008DFC_SQ_SRC_22_INT 0x96 |
||
| 2273 | #define V_008DFC_SQ_SRC_23_INT 0x97 |
||
| 2274 | #define V_008DFC_SQ_SRC_24_INT 0x98 |
||
| 2275 | #define V_008DFC_SQ_SRC_25_INT 0x99 |
||
| 2276 | #define V_008DFC_SQ_SRC_26_INT 0x9A |
||
| 2277 | #define V_008DFC_SQ_SRC_27_INT 0x9B |
||
| 2278 | #define V_008DFC_SQ_SRC_28_INT 0x9C |
||
| 2279 | #define V_008DFC_SQ_SRC_29_INT 0x9D |
||
| 2280 | #define V_008DFC_SQ_SRC_30_INT 0x9E |
||
| 2281 | #define V_008DFC_SQ_SRC_31_INT 0x9F |
||
| 2282 | #define V_008DFC_SQ_SRC_32_INT 0xA0 |
||
| 2283 | #define V_008DFC_SQ_SRC_33_INT 0xA1 |
||
| 2284 | #define V_008DFC_SQ_SRC_34_INT 0xA2 |
||
| 2285 | #define V_008DFC_SQ_SRC_35_INT 0xA3 |
||
| 2286 | #define V_008DFC_SQ_SRC_36_INT 0xA4 |
||
| 2287 | #define V_008DFC_SQ_SRC_37_INT 0xA5 |
||
| 2288 | #define V_008DFC_SQ_SRC_38_INT 0xA6 |
||
| 2289 | #define V_008DFC_SQ_SRC_39_INT 0xA7 |
||
| 2290 | #define V_008DFC_SQ_SRC_40_INT 0xA8 |
||
| 2291 | #define V_008DFC_SQ_SRC_41_INT 0xA9 |
||
| 2292 | #define V_008DFC_SQ_SRC_42_INT 0xAA |
||
| 2293 | #define V_008DFC_SQ_SRC_43_INT 0xAB |
||
| 2294 | #define V_008DFC_SQ_SRC_44_INT 0xAC |
||
| 2295 | #define V_008DFC_SQ_SRC_45_INT 0xAD |
||
| 2296 | #define V_008DFC_SQ_SRC_46_INT 0xAE |
||
| 2297 | #define V_008DFC_SQ_SRC_47_INT 0xAF |
||
| 2298 | #define V_008DFC_SQ_SRC_48_INT 0xB0 |
||
| 2299 | #define V_008DFC_SQ_SRC_49_INT 0xB1 |
||
| 2300 | #define V_008DFC_SQ_SRC_50_INT 0xB2 |
||
| 2301 | #define V_008DFC_SQ_SRC_51_INT 0xB3 |
||
| 2302 | #define V_008DFC_SQ_SRC_52_INT 0xB4 |
||
| 2303 | #define V_008DFC_SQ_SRC_53_INT 0xB5 |
||
| 2304 | #define V_008DFC_SQ_SRC_54_INT 0xB6 |
||
| 2305 | #define V_008DFC_SQ_SRC_55_INT 0xB7 |
||
| 2306 | #define V_008DFC_SQ_SRC_56_INT 0xB8 |
||
| 2307 | #define V_008DFC_SQ_SRC_57_INT 0xB9 |
||
| 2308 | #define V_008DFC_SQ_SRC_58_INT 0xBA |
||
| 2309 | #define V_008DFC_SQ_SRC_59_INT 0xBB |
||
| 2310 | #define V_008DFC_SQ_SRC_60_INT 0xBC |
||
| 2311 | #define V_008DFC_SQ_SRC_61_INT 0xBD |
||
| 2312 | #define V_008DFC_SQ_SRC_62_INT 0xBE |
||
| 2313 | #define V_008DFC_SQ_SRC_63_INT 0xBF |
||
| 2314 | #define V_008DFC_SQ_SRC_64_INT 0xC0 |
||
| 2315 | #define V_008DFC_SQ_SRC_M_1_INT 0xC1 |
||
| 2316 | #define V_008DFC_SQ_SRC_M_2_INT 0xC2 |
||
| 2317 | #define V_008DFC_SQ_SRC_M_3_INT 0xC3 |
||
| 2318 | #define V_008DFC_SQ_SRC_M_4_INT 0xC4 |
||
| 2319 | #define V_008DFC_SQ_SRC_M_5_INT 0xC5 |
||
| 2320 | #define V_008DFC_SQ_SRC_M_6_INT 0xC6 |
||
| 2321 | #define V_008DFC_SQ_SRC_M_7_INT 0xC7 |
||
| 2322 | #define V_008DFC_SQ_SRC_M_8_INT 0xC8 |
||
| 2323 | #define V_008DFC_SQ_SRC_M_9_INT 0xC9 |
||
| 2324 | #define V_008DFC_SQ_SRC_M_10_INT 0xCA |
||
| 2325 | #define V_008DFC_SQ_SRC_M_11_INT 0xCB |
||
| 2326 | #define V_008DFC_SQ_SRC_M_12_INT 0xCC |
||
| 2327 | #define V_008DFC_SQ_SRC_M_13_INT 0xCD |
||
| 2328 | #define V_008DFC_SQ_SRC_M_14_INT 0xCE |
||
| 2329 | #define V_008DFC_SQ_SRC_M_15_INT 0xCF |
||
| 2330 | #define V_008DFC_SQ_SRC_M_16_INT 0xD0 |
||
| 2331 | #define V_008DFC_SQ_SRC_0_5 0xF0 |
||
| 2332 | #define V_008DFC_SQ_SRC_M_0_5 0xF1 |
||
| 2333 | #define V_008DFC_SQ_SRC_1 0xF2 |
||
| 2334 | #define V_008DFC_SQ_SRC_M_1 0xF3 |
||
| 2335 | #define V_008DFC_SQ_SRC_2 0xF4 |
||
| 2336 | #define V_008DFC_SQ_SRC_M_2 0xF5 |
||
| 2337 | #define V_008DFC_SQ_SRC_4 0xF6 |
||
| 2338 | #define V_008DFC_SQ_SRC_M_4 0xF7 |
||
| 2339 | #define V_008DFC_SQ_SRC_VCCZ 0xFB |
||
| 2340 | #define V_008DFC_SQ_SRC_EXECZ 0xFC |
||
| 2341 | #define V_008DFC_SQ_SRC_SCC 0xFD |
||
| 2342 | #define V_008DFC_SQ_SRC_LDS_DIRECT 0xFE |
||
| 2343 | #define V_008DFC_SQ_SRC_VGPR 0x100 |
||
| 2344 | #define S_008DFC_VSRC1(x) (((x) & 0xFF) << 9) |
||
| 2345 | #define G_008DFC_VSRC1(x) (((x) >> 9) & 0xFF) |
||
| 2346 | #define C_008DFC_VSRC1 0xFFFE01FF |
||
| 2347 | #define V_008DFC_SQ_VGPR 0x00 |
||
| 2348 | #define S_008DFC_OP(x) (((x) & 0xFF) << 17) |
||
| 2349 | #define G_008DFC_OP(x) (((x) >> 17) & 0xFF) |
||
| 2350 | #define C_008DFC_OP 0xFE01FFFF |
||
| 2351 | #define V_008DFC_SQ_V_CMP_F_F32 0x00 |
||
| 2352 | #define V_008DFC_SQ_V_CMP_LT_F32 0x01 |
||
| 2353 | #define V_008DFC_SQ_V_CMP_EQ_F32 0x02 |
||
| 2354 | #define V_008DFC_SQ_V_CMP_LE_F32 0x03 |
||
| 2355 | #define V_008DFC_SQ_V_CMP_GT_F32 0x04 |
||
| 2356 | #define V_008DFC_SQ_V_CMP_LG_F32 0x05 |
||
| 2357 | #define V_008DFC_SQ_V_CMP_GE_F32 0x06 |
||
| 2358 | #define V_008DFC_SQ_V_CMP_O_F32 0x07 |
||
| 2359 | #define V_008DFC_SQ_V_CMP_U_F32 0x08 |
||
| 2360 | #define V_008DFC_SQ_V_CMP_NGE_F32 0x09 |
||
| 2361 | #define V_008DFC_SQ_V_CMP_NLG_F32 0x0A |
||
| 2362 | #define V_008DFC_SQ_V_CMP_NGT_F32 0x0B |
||
| 2363 | #define V_008DFC_SQ_V_CMP_NLE_F32 0x0C |
||
| 2364 | #define V_008DFC_SQ_V_CMP_NEQ_F32 0x0D |
||
| 2365 | #define V_008DFC_SQ_V_CMP_NLT_F32 0x0E |
||
| 2366 | #define V_008DFC_SQ_V_CMP_TRU_F32 0x0F |
||
| 2367 | #define V_008DFC_SQ_V_CMPX_F_F32 0x10 |
||
| 2368 | #define V_008DFC_SQ_V_CMPX_LT_F32 0x11 |
||
| 2369 | #define V_008DFC_SQ_V_CMPX_EQ_F32 0x12 |
||
| 2370 | #define V_008DFC_SQ_V_CMPX_LE_F32 0x13 |
||
| 2371 | #define V_008DFC_SQ_V_CMPX_GT_F32 0x14 |
||
| 2372 | #define V_008DFC_SQ_V_CMPX_LG_F32 0x15 |
||
| 2373 | #define V_008DFC_SQ_V_CMPX_GE_F32 0x16 |
||
| 2374 | #define V_008DFC_SQ_V_CMPX_O_F32 0x17 |
||
| 2375 | #define V_008DFC_SQ_V_CMPX_U_F32 0x18 |
||
| 2376 | #define V_008DFC_SQ_V_CMPX_NGE_F32 0x19 |
||
| 2377 | #define V_008DFC_SQ_V_CMPX_NLG_F32 0x1A |
||
| 2378 | #define V_008DFC_SQ_V_CMPX_NGT_F32 0x1B |
||
| 2379 | #define V_008DFC_SQ_V_CMPX_NLE_F32 0x1C |
||
| 2380 | #define V_008DFC_SQ_V_CMPX_NEQ_F32 0x1D |
||
| 2381 | #define V_008DFC_SQ_V_CMPX_NLT_F32 0x1E |
||
| 2382 | #define V_008DFC_SQ_V_CMPX_TRU_F32 0x1F |
||
| 2383 | #define V_008DFC_SQ_V_CMP_F_F64 0x20 |
||
| 2384 | #define V_008DFC_SQ_V_CMP_LT_F64 0x21 |
||
| 2385 | #define V_008DFC_SQ_V_CMP_EQ_F64 0x22 |
||
| 2386 | #define V_008DFC_SQ_V_CMP_LE_F64 0x23 |
||
| 2387 | #define V_008DFC_SQ_V_CMP_GT_F64 0x24 |
||
| 2388 | #define V_008DFC_SQ_V_CMP_LG_F64 0x25 |
||
| 2389 | #define V_008DFC_SQ_V_CMP_GE_F64 0x26 |
||
| 2390 | #define V_008DFC_SQ_V_CMP_O_F64 0x27 |
||
| 2391 | #define V_008DFC_SQ_V_CMP_U_F64 0x28 |
||
| 2392 | #define V_008DFC_SQ_V_CMP_NGE_F64 0x29 |
||
| 2393 | #define V_008DFC_SQ_V_CMP_NLG_F64 0x2A |
||
| 2394 | #define V_008DFC_SQ_V_CMP_NGT_F64 0x2B |
||
| 2395 | #define V_008DFC_SQ_V_CMP_NLE_F64 0x2C |
||
| 2396 | #define V_008DFC_SQ_V_CMP_NEQ_F64 0x2D |
||
| 2397 | #define V_008DFC_SQ_V_CMP_NLT_F64 0x2E |
||
| 2398 | #define V_008DFC_SQ_V_CMP_TRU_F64 0x2F |
||
| 2399 | #define V_008DFC_SQ_V_CMPX_F_F64 0x30 |
||
| 2400 | #define V_008DFC_SQ_V_CMPX_LT_F64 0x31 |
||
| 2401 | #define V_008DFC_SQ_V_CMPX_EQ_F64 0x32 |
||
| 2402 | #define V_008DFC_SQ_V_CMPX_LE_F64 0x33 |
||
| 2403 | #define V_008DFC_SQ_V_CMPX_GT_F64 0x34 |
||
| 2404 | #define V_008DFC_SQ_V_CMPX_LG_F64 0x35 |
||
| 2405 | #define V_008DFC_SQ_V_CMPX_GE_F64 0x36 |
||
| 2406 | #define V_008DFC_SQ_V_CMPX_O_F64 0x37 |
||
| 2407 | #define V_008DFC_SQ_V_CMPX_U_F64 0x38 |
||
| 2408 | #define V_008DFC_SQ_V_CMPX_NGE_F64 0x39 |
||
| 2409 | #define V_008DFC_SQ_V_CMPX_NLG_F64 0x3A |
||
| 2410 | #define V_008DFC_SQ_V_CMPX_NGT_F64 0x3B |
||
| 2411 | #define V_008DFC_SQ_V_CMPX_NLE_F64 0x3C |
||
| 2412 | #define V_008DFC_SQ_V_CMPX_NEQ_F64 0x3D |
||
| 2413 | #define V_008DFC_SQ_V_CMPX_NLT_F64 0x3E |
||
| 2414 | #define V_008DFC_SQ_V_CMPX_TRU_F64 0x3F |
||
| 2415 | #define V_008DFC_SQ_V_CMPS_F_F32 0x40 |
||
| 2416 | #define V_008DFC_SQ_V_CMPS_LT_F32 0x41 |
||
| 2417 | #define V_008DFC_SQ_V_CMPS_EQ_F32 0x42 |
||
| 2418 | #define V_008DFC_SQ_V_CMPS_LE_F32 0x43 |
||
| 2419 | #define V_008DFC_SQ_V_CMPS_GT_F32 0x44 |
||
| 2420 | #define V_008DFC_SQ_V_CMPS_LG_F32 0x45 |
||
| 2421 | #define V_008DFC_SQ_V_CMPS_GE_F32 0x46 |
||
| 2422 | #define V_008DFC_SQ_V_CMPS_O_F32 0x47 |
||
| 2423 | #define V_008DFC_SQ_V_CMPS_U_F32 0x48 |
||
| 2424 | #define V_008DFC_SQ_V_CMPS_NGE_F32 0x49 |
||
| 2425 | #define V_008DFC_SQ_V_CMPS_NLG_F32 0x4A |
||
| 2426 | #define V_008DFC_SQ_V_CMPS_NGT_F32 0x4B |
||
| 2427 | #define V_008DFC_SQ_V_CMPS_NLE_F32 0x4C |
||
| 2428 | #define V_008DFC_SQ_V_CMPS_NEQ_F32 0x4D |
||
| 2429 | #define V_008DFC_SQ_V_CMPS_NLT_F32 0x4E |
||
| 2430 | #define V_008DFC_SQ_V_CMPS_TRU_F32 0x4F |
||
| 2431 | #define V_008DFC_SQ_V_CMPSX_F_F32 0x50 |
||
| 2432 | #define V_008DFC_SQ_V_CMPSX_LT_F32 0x51 |
||
| 2433 | #define V_008DFC_SQ_V_CMPSX_EQ_F32 0x52 |
||
| 2434 | #define V_008DFC_SQ_V_CMPSX_LE_F32 0x53 |
||
| 2435 | #define V_008DFC_SQ_V_CMPSX_GT_F32 0x54 |
||
| 2436 | #define V_008DFC_SQ_V_CMPSX_LG_F32 0x55 |
||
| 2437 | #define V_008DFC_SQ_V_CMPSX_GE_F32 0x56 |
||
| 2438 | #define V_008DFC_SQ_V_CMPSX_O_F32 0x57 |
||
| 2439 | #define V_008DFC_SQ_V_CMPSX_U_F32 0x58 |
||
| 2440 | #define V_008DFC_SQ_V_CMPSX_NGE_F32 0x59 |
||
| 2441 | #define V_008DFC_SQ_V_CMPSX_NLG_F32 0x5A |
||
| 2442 | #define V_008DFC_SQ_V_CMPSX_NGT_F32 0x5B |
||
| 2443 | #define V_008DFC_SQ_V_CMPSX_NLE_F32 0x5C |
||
| 2444 | #define V_008DFC_SQ_V_CMPSX_NEQ_F32 0x5D |
||
| 2445 | #define V_008DFC_SQ_V_CMPSX_NLT_F32 0x5E |
||
| 2446 | #define V_008DFC_SQ_V_CMPSX_TRU_F32 0x5F |
||
| 2447 | #define V_008DFC_SQ_V_CMPS_F_F64 0x60 |
||
| 2448 | #define V_008DFC_SQ_V_CMPS_LT_F64 0x61 |
||
| 2449 | #define V_008DFC_SQ_V_CMPS_EQ_F64 0x62 |
||
| 2450 | #define V_008DFC_SQ_V_CMPS_LE_F64 0x63 |
||
| 2451 | #define V_008DFC_SQ_V_CMPS_GT_F64 0x64 |
||
| 2452 | #define V_008DFC_SQ_V_CMPS_LG_F64 0x65 |
||
| 2453 | #define V_008DFC_SQ_V_CMPS_GE_F64 0x66 |
||
| 2454 | #define V_008DFC_SQ_V_CMPS_O_F64 0x67 |
||
| 2455 | #define V_008DFC_SQ_V_CMPS_U_F64 0x68 |
||
| 2456 | #define V_008DFC_SQ_V_CMPS_NGE_F64 0x69 |
||
| 2457 | #define V_008DFC_SQ_V_CMPS_NLG_F64 0x6A |
||
| 2458 | #define V_008DFC_SQ_V_CMPS_NGT_F64 0x6B |
||
| 2459 | #define V_008DFC_SQ_V_CMPS_NLE_F64 0x6C |
||
| 2460 | #define V_008DFC_SQ_V_CMPS_NEQ_F64 0x6D |
||
| 2461 | #define V_008DFC_SQ_V_CMPS_NLT_F64 0x6E |
||
| 2462 | #define V_008DFC_SQ_V_CMPS_TRU_F64 0x6F |
||
| 2463 | #define V_008DFC_SQ_V_CMPSX_F_F64 0x70 |
||
| 2464 | #define V_008DFC_SQ_V_CMPSX_LT_F64 0x71 |
||
| 2465 | #define V_008DFC_SQ_V_CMPSX_EQ_F64 0x72 |
||
| 2466 | #define V_008DFC_SQ_V_CMPSX_LE_F64 0x73 |
||
| 2467 | #define V_008DFC_SQ_V_CMPSX_GT_F64 0x74 |
||
| 2468 | #define V_008DFC_SQ_V_CMPSX_LG_F64 0x75 |
||
| 2469 | #define V_008DFC_SQ_V_CMPSX_GE_F64 0x76 |
||
| 2470 | #define V_008DFC_SQ_V_CMPSX_O_F64 0x77 |
||
| 2471 | #define V_008DFC_SQ_V_CMPSX_U_F64 0x78 |
||
| 2472 | #define V_008DFC_SQ_V_CMPSX_NGE_F64 0x79 |
||
| 2473 | #define V_008DFC_SQ_V_CMPSX_NLG_F64 0x7A |
||
| 2474 | #define V_008DFC_SQ_V_CMPSX_NGT_F64 0x7B |
||
| 2475 | #define V_008DFC_SQ_V_CMPSX_NLE_F64 0x7C |
||
| 2476 | #define V_008DFC_SQ_V_CMPSX_NEQ_F64 0x7D |
||
| 2477 | #define V_008DFC_SQ_V_CMPSX_NLT_F64 0x7E |
||
| 2478 | #define V_008DFC_SQ_V_CMPSX_TRU_F64 0x7F |
||
| 2479 | #define V_008DFC_SQ_V_CMP_F_I32 0x80 |
||
| 2480 | #define V_008DFC_SQ_V_CMP_LT_I32 0x81 |
||
| 2481 | #define V_008DFC_SQ_V_CMP_EQ_I32 0x82 |
||
| 2482 | #define V_008DFC_SQ_V_CMP_LE_I32 0x83 |
||
| 2483 | #define V_008DFC_SQ_V_CMP_GT_I32 0x84 |
||
| 2484 | #define V_008DFC_SQ_V_CMP_NE_I32 0x85 |
||
| 2485 | #define V_008DFC_SQ_V_CMP_GE_I32 0x86 |
||
| 2486 | #define V_008DFC_SQ_V_CMP_T_I32 0x87 |
||
| 2487 | #define V_008DFC_SQ_V_CMP_CLASS_F32 0x88 |
||
| 2488 | #define V_008DFC_SQ_V_CMPX_F_I32 0x90 |
||
| 2489 | #define V_008DFC_SQ_V_CMPX_LT_I32 0x91 |
||
| 2490 | #define V_008DFC_SQ_V_CMPX_EQ_I32 0x92 |
||
| 2491 | #define V_008DFC_SQ_V_CMPX_LE_I32 0x93 |
||
| 2492 | #define V_008DFC_SQ_V_CMPX_GT_I32 0x94 |
||
| 2493 | #define V_008DFC_SQ_V_CMPX_NE_I32 0x95 |
||
| 2494 | #define V_008DFC_SQ_V_CMPX_GE_I32 0x96 |
||
| 2495 | #define V_008DFC_SQ_V_CMPX_T_I32 0x97 |
||
| 2496 | #define V_008DFC_SQ_V_CMPX_CLASS_F32 0x98 |
||
| 2497 | #define V_008DFC_SQ_V_CMP_F_I64 0xA0 |
||
| 2498 | #define V_008DFC_SQ_V_CMP_LT_I64 0xA1 |
||
| 2499 | #define V_008DFC_SQ_V_CMP_EQ_I64 0xA2 |
||
| 2500 | #define V_008DFC_SQ_V_CMP_LE_I64 0xA3 |
||
| 2501 | #define V_008DFC_SQ_V_CMP_GT_I64 0xA4 |
||
| 2502 | #define V_008DFC_SQ_V_CMP_NE_I64 0xA5 |
||
| 2503 | #define V_008DFC_SQ_V_CMP_GE_I64 0xA6 |
||
| 2504 | #define V_008DFC_SQ_V_CMP_T_I64 0xA7 |
||
| 2505 | #define V_008DFC_SQ_V_CMP_CLASS_F64 0xA8 |
||
| 2506 | #define V_008DFC_SQ_V_CMPX_F_I64 0xB0 |
||
| 2507 | #define V_008DFC_SQ_V_CMPX_LT_I64 0xB1 |
||
| 2508 | #define V_008DFC_SQ_V_CMPX_EQ_I64 0xB2 |
||
| 2509 | #define V_008DFC_SQ_V_CMPX_LE_I64 0xB3 |
||
| 2510 | #define V_008DFC_SQ_V_CMPX_GT_I64 0xB4 |
||
| 2511 | #define V_008DFC_SQ_V_CMPX_NE_I64 0xB5 |
||
| 2512 | #define V_008DFC_SQ_V_CMPX_GE_I64 0xB6 |
||
| 2513 | #define V_008DFC_SQ_V_CMPX_T_I64 0xB7 |
||
| 2514 | #define V_008DFC_SQ_V_CMPX_CLASS_F64 0xB8 |
||
| 2515 | #define V_008DFC_SQ_V_CMP_F_U32 0xC0 |
||
| 2516 | #define V_008DFC_SQ_V_CMP_LT_U32 0xC1 |
||
| 2517 | #define V_008DFC_SQ_V_CMP_EQ_U32 0xC2 |
||
| 2518 | #define V_008DFC_SQ_V_CMP_LE_U32 0xC3 |
||
| 2519 | #define V_008DFC_SQ_V_CMP_GT_U32 0xC4 |
||
| 2520 | #define V_008DFC_SQ_V_CMP_NE_U32 0xC5 |
||
| 2521 | #define V_008DFC_SQ_V_CMP_GE_U32 0xC6 |
||
| 2522 | #define V_008DFC_SQ_V_CMP_T_U32 0xC7 |
||
| 2523 | #define V_008DFC_SQ_V_CMPX_F_U32 0xD0 |
||
| 2524 | #define V_008DFC_SQ_V_CMPX_LT_U32 0xD1 |
||
| 2525 | #define V_008DFC_SQ_V_CMPX_EQ_U32 0xD2 |
||
| 2526 | #define V_008DFC_SQ_V_CMPX_LE_U32 0xD3 |
||
| 2527 | #define V_008DFC_SQ_V_CMPX_GT_U32 0xD4 |
||
| 2528 | #define V_008DFC_SQ_V_CMPX_NE_U32 0xD5 |
||
| 2529 | #define V_008DFC_SQ_V_CMPX_GE_U32 0xD6 |
||
| 2530 | #define V_008DFC_SQ_V_CMPX_T_U32 0xD7 |
||
| 2531 | #define V_008DFC_SQ_V_CMP_F_U64 0xE0 |
||
| 2532 | #define V_008DFC_SQ_V_CMP_LT_U64 0xE1 |
||
| 2533 | #define V_008DFC_SQ_V_CMP_EQ_U64 0xE2 |
||
| 2534 | #define V_008DFC_SQ_V_CMP_LE_U64 0xE3 |
||
| 2535 | #define V_008DFC_SQ_V_CMP_GT_U64 0xE4 |
||
| 2536 | #define V_008DFC_SQ_V_CMP_NE_U64 0xE5 |
||
| 2537 | #define V_008DFC_SQ_V_CMP_GE_U64 0xE6 |
||
| 2538 | #define V_008DFC_SQ_V_CMP_T_U64 0xE7 |
||
| 2539 | #define V_008DFC_SQ_V_CMPX_F_U64 0xF0 |
||
| 2540 | #define V_008DFC_SQ_V_CMPX_LT_U64 0xF1 |
||
| 2541 | #define V_008DFC_SQ_V_CMPX_EQ_U64 0xF2 |
||
| 2542 | #define V_008DFC_SQ_V_CMPX_LE_U64 0xF3 |
||
| 2543 | #define V_008DFC_SQ_V_CMPX_GT_U64 0xF4 |
||
| 2544 | #define V_008DFC_SQ_V_CMPX_NE_U64 0xF5 |
||
| 2545 | #define V_008DFC_SQ_V_CMPX_GE_U64 0xF6 |
||
| 2546 | #define V_008DFC_SQ_V_CMPX_T_U64 0xF7 |
||
| 2547 | #define S_008DFC_ENCODING(x) (((x) & 0x7F) << 25) |
||
| 2548 | #define G_008DFC_ENCODING(x) (((x) >> 25) & 0x7F) |
||
| 2549 | #define C_008DFC_ENCODING 0x01FFFFFF |
||
| 2550 | #define V_008DFC_SQ_ENC_VOPC_FIELD 0x3E |
||
| 2551 | #define R_008DFC_SQ_SOP1 0x008DFC |
||
| 2552 | #define S_008DFC_SSRC0(x) (((x) & 0xFF) << 0) |
||
| 2553 | #define G_008DFC_SSRC0(x) (((x) >> 0) & 0xFF) |
||
| 2554 | #define C_008DFC_SSRC0 0xFFFFFF00 |
||
| 2555 | #define V_008DFC_SQ_SGPR 0x00 |
||
| 2556 | /* CIK */ |
||
| 2557 | #define V_008DFC_SQ_FLAT_SCRATCH_LO 0x68 |
||
| 2558 | #define V_008DFC_SQ_FLAT_SCRATCH_HI 0x69 |
||
| 2559 | /* */ |
||
| 2560 | #define V_008DFC_SQ_VCC_LO 0x6A |
||
| 2561 | #define V_008DFC_SQ_VCC_HI 0x6B |
||
| 2562 | #define V_008DFC_SQ_TBA_LO 0x6C |
||
| 2563 | #define V_008DFC_SQ_TBA_HI 0x6D |
||
| 2564 | #define V_008DFC_SQ_TMA_LO 0x6E |
||
| 2565 | #define V_008DFC_SQ_TMA_HI 0x6F |
||
| 2566 | #define V_008DFC_SQ_TTMP0 0x70 |
||
| 2567 | #define V_008DFC_SQ_TTMP1 0x71 |
||
| 2568 | #define V_008DFC_SQ_TTMP2 0x72 |
||
| 2569 | #define V_008DFC_SQ_TTMP3 0x73 |
||
| 2570 | #define V_008DFC_SQ_TTMP4 0x74 |
||
| 2571 | #define V_008DFC_SQ_TTMP5 0x75 |
||
| 2572 | #define V_008DFC_SQ_TTMP6 0x76 |
||
| 2573 | #define V_008DFC_SQ_TTMP7 0x77 |
||
| 2574 | #define V_008DFC_SQ_TTMP8 0x78 |
||
| 2575 | #define V_008DFC_SQ_TTMP9 0x79 |
||
| 2576 | #define V_008DFC_SQ_TTMP10 0x7A |
||
| 2577 | #define V_008DFC_SQ_TTMP11 0x7B |
||
| 2578 | #define V_008DFC_SQ_M0 0x7C |
||
| 2579 | #define V_008DFC_SQ_EXEC_LO 0x7E |
||
| 2580 | #define V_008DFC_SQ_EXEC_HI 0x7F |
||
| 2581 | #define V_008DFC_SQ_SRC_0 0x80 |
||
| 2582 | #define V_008DFC_SQ_SRC_1_INT 0x81 |
||
| 2583 | #define V_008DFC_SQ_SRC_2_INT 0x82 |
||
| 2584 | #define V_008DFC_SQ_SRC_3_INT 0x83 |
||
| 2585 | #define V_008DFC_SQ_SRC_4_INT 0x84 |
||
| 2586 | #define V_008DFC_SQ_SRC_5_INT 0x85 |
||
| 2587 | #define V_008DFC_SQ_SRC_6_INT 0x86 |
||
| 2588 | #define V_008DFC_SQ_SRC_7_INT 0x87 |
||
| 2589 | #define V_008DFC_SQ_SRC_8_INT 0x88 |
||
| 2590 | #define V_008DFC_SQ_SRC_9_INT 0x89 |
||
| 2591 | #define V_008DFC_SQ_SRC_10_INT 0x8A |
||
| 2592 | #define V_008DFC_SQ_SRC_11_INT 0x8B |
||
| 2593 | #define V_008DFC_SQ_SRC_12_INT 0x8C |
||
| 2594 | #define V_008DFC_SQ_SRC_13_INT 0x8D |
||
| 2595 | #define V_008DFC_SQ_SRC_14_INT 0x8E |
||
| 2596 | #define V_008DFC_SQ_SRC_15_INT 0x8F |
||
| 2597 | #define V_008DFC_SQ_SRC_16_INT 0x90 |
||
| 2598 | #define V_008DFC_SQ_SRC_17_INT 0x91 |
||
| 2599 | #define V_008DFC_SQ_SRC_18_INT 0x92 |
||
| 2600 | #define V_008DFC_SQ_SRC_19_INT 0x93 |
||
| 2601 | #define V_008DFC_SQ_SRC_20_INT 0x94 |
||
| 2602 | #define V_008DFC_SQ_SRC_21_INT 0x95 |
||
| 2603 | #define V_008DFC_SQ_SRC_22_INT 0x96 |
||
| 2604 | #define V_008DFC_SQ_SRC_23_INT 0x97 |
||
| 2605 | #define V_008DFC_SQ_SRC_24_INT 0x98 |
||
| 2606 | #define V_008DFC_SQ_SRC_25_INT 0x99 |
||
| 2607 | #define V_008DFC_SQ_SRC_26_INT 0x9A |
||
| 2608 | #define V_008DFC_SQ_SRC_27_INT 0x9B |
||
| 2609 | #define V_008DFC_SQ_SRC_28_INT 0x9C |
||
| 2610 | #define V_008DFC_SQ_SRC_29_INT 0x9D |
||
| 2611 | #define V_008DFC_SQ_SRC_30_INT 0x9E |
||
| 2612 | #define V_008DFC_SQ_SRC_31_INT 0x9F |
||
| 2613 | #define V_008DFC_SQ_SRC_32_INT 0xA0 |
||
| 2614 | #define V_008DFC_SQ_SRC_33_INT 0xA1 |
||
| 2615 | #define V_008DFC_SQ_SRC_34_INT 0xA2 |
||
| 2616 | #define V_008DFC_SQ_SRC_35_INT 0xA3 |
||
| 2617 | #define V_008DFC_SQ_SRC_36_INT 0xA4 |
||
| 2618 | #define V_008DFC_SQ_SRC_37_INT 0xA5 |
||
| 2619 | #define V_008DFC_SQ_SRC_38_INT 0xA6 |
||
| 2620 | #define V_008DFC_SQ_SRC_39_INT 0xA7 |
||
| 2621 | #define V_008DFC_SQ_SRC_40_INT 0xA8 |
||
| 2622 | #define V_008DFC_SQ_SRC_41_INT 0xA9 |
||
| 2623 | #define V_008DFC_SQ_SRC_42_INT 0xAA |
||
| 2624 | #define V_008DFC_SQ_SRC_43_INT 0xAB |
||
| 2625 | #define V_008DFC_SQ_SRC_44_INT 0xAC |
||
| 2626 | #define V_008DFC_SQ_SRC_45_INT 0xAD |
||
| 2627 | #define V_008DFC_SQ_SRC_46_INT 0xAE |
||
| 2628 | #define V_008DFC_SQ_SRC_47_INT 0xAF |
||
| 2629 | #define V_008DFC_SQ_SRC_48_INT 0xB0 |
||
| 2630 | #define V_008DFC_SQ_SRC_49_INT 0xB1 |
||
| 2631 | #define V_008DFC_SQ_SRC_50_INT 0xB2 |
||
| 2632 | #define V_008DFC_SQ_SRC_51_INT 0xB3 |
||
| 2633 | #define V_008DFC_SQ_SRC_52_INT 0xB4 |
||
| 2634 | #define V_008DFC_SQ_SRC_53_INT 0xB5 |
||
| 2635 | #define V_008DFC_SQ_SRC_54_INT 0xB6 |
||
| 2636 | #define V_008DFC_SQ_SRC_55_INT 0xB7 |
||
| 2637 | #define V_008DFC_SQ_SRC_56_INT 0xB8 |
||
| 2638 | #define V_008DFC_SQ_SRC_57_INT 0xB9 |
||
| 2639 | #define V_008DFC_SQ_SRC_58_INT 0xBA |
||
| 2640 | #define V_008DFC_SQ_SRC_59_INT 0xBB |
||
| 2641 | #define V_008DFC_SQ_SRC_60_INT 0xBC |
||
| 2642 | #define V_008DFC_SQ_SRC_61_INT 0xBD |
||
| 2643 | #define V_008DFC_SQ_SRC_62_INT 0xBE |
||
| 2644 | #define V_008DFC_SQ_SRC_63_INT 0xBF |
||
| 2645 | #define V_008DFC_SQ_SRC_64_INT 0xC0 |
||
| 2646 | #define V_008DFC_SQ_SRC_M_1_INT 0xC1 |
||
| 2647 | #define V_008DFC_SQ_SRC_M_2_INT 0xC2 |
||
| 2648 | #define V_008DFC_SQ_SRC_M_3_INT 0xC3 |
||
| 2649 | #define V_008DFC_SQ_SRC_M_4_INT 0xC4 |
||
| 2650 | #define V_008DFC_SQ_SRC_M_5_INT 0xC5 |
||
| 2651 | #define V_008DFC_SQ_SRC_M_6_INT 0xC6 |
||
| 2652 | #define V_008DFC_SQ_SRC_M_7_INT 0xC7 |
||
| 2653 | #define V_008DFC_SQ_SRC_M_8_INT 0xC8 |
||
| 2654 | #define V_008DFC_SQ_SRC_M_9_INT 0xC9 |
||
| 2655 | #define V_008DFC_SQ_SRC_M_10_INT 0xCA |
||
| 2656 | #define V_008DFC_SQ_SRC_M_11_INT 0xCB |
||
| 2657 | #define V_008DFC_SQ_SRC_M_12_INT 0xCC |
||
| 2658 | #define V_008DFC_SQ_SRC_M_13_INT 0xCD |
||
| 2659 | #define V_008DFC_SQ_SRC_M_14_INT 0xCE |
||
| 2660 | #define V_008DFC_SQ_SRC_M_15_INT 0xCF |
||
| 2661 | #define V_008DFC_SQ_SRC_M_16_INT 0xD0 |
||
| 2662 | #define V_008DFC_SQ_SRC_0_5 0xF0 |
||
| 2663 | #define V_008DFC_SQ_SRC_M_0_5 0xF1 |
||
| 2664 | #define V_008DFC_SQ_SRC_1 0xF2 |
||
| 2665 | #define V_008DFC_SQ_SRC_M_1 0xF3 |
||
| 2666 | #define V_008DFC_SQ_SRC_2 0xF4 |
||
| 2667 | #define V_008DFC_SQ_SRC_M_2 0xF5 |
||
| 2668 | #define V_008DFC_SQ_SRC_4 0xF6 |
||
| 2669 | #define V_008DFC_SQ_SRC_M_4 0xF7 |
||
| 2670 | #define V_008DFC_SQ_SRC_VCCZ 0xFB |
||
| 2671 | #define V_008DFC_SQ_SRC_EXECZ 0xFC |
||
| 2672 | #define V_008DFC_SQ_SRC_SCC 0xFD |
||
| 2673 | #define V_008DFC_SQ_SRC_LDS_DIRECT 0xFE |
||
| 2674 | #define S_008DFC_OP(x) (((x) & 0xFF) << 8) |
||
| 2675 | #define G_008DFC_OP(x) (((x) >> 8) & 0xFF) |
||
| 2676 | #define C_008DFC_OP 0xFFFF00FF |
||
| 2677 | #define V_008DFC_SQ_S_MOV_B32 0x03 |
||
| 2678 | #define V_008DFC_SQ_S_MOV_B64 0x04 |
||
| 2679 | #define V_008DFC_SQ_S_CMOV_B32 0x05 |
||
| 2680 | #define V_008DFC_SQ_S_CMOV_B64 0x06 |
||
| 2681 | #define V_008DFC_SQ_S_NOT_B32 0x07 |
||
| 2682 | #define V_008DFC_SQ_S_NOT_B64 0x08 |
||
| 2683 | #define V_008DFC_SQ_S_WQM_B32 0x09 |
||
| 2684 | #define V_008DFC_SQ_S_WQM_B64 0x0A |
||
| 2685 | #define V_008DFC_SQ_S_BREV_B32 0x0B |
||
| 2686 | #define V_008DFC_SQ_S_BREV_B64 0x0C |
||
| 2687 | #define V_008DFC_SQ_S_BCNT0_I32_B32 0x0D |
||
| 2688 | #define V_008DFC_SQ_S_BCNT0_I32_B64 0x0E |
||
| 2689 | #define V_008DFC_SQ_S_BCNT1_I32_B32 0x0F |
||
| 2690 | #define V_008DFC_SQ_S_BCNT1_I32_B64 0x10 |
||
| 2691 | #define V_008DFC_SQ_S_FF0_I32_B32 0x11 |
||
| 2692 | #define V_008DFC_SQ_S_FF0_I32_B64 0x12 |
||
| 2693 | #define V_008DFC_SQ_S_FF1_I32_B32 0x13 |
||
| 2694 | #define V_008DFC_SQ_S_FF1_I32_B64 0x14 |
||
| 2695 | #define V_008DFC_SQ_S_FLBIT_I32_B32 0x15 |
||
| 2696 | #define V_008DFC_SQ_S_FLBIT_I32_B64 0x16 |
||
| 2697 | #define V_008DFC_SQ_S_FLBIT_I32 0x17 |
||
| 2698 | #define V_008DFC_SQ_S_FLBIT_I32_I64 0x18 |
||
| 2699 | #define V_008DFC_SQ_S_SEXT_I32_I8 0x19 |
||
| 2700 | #define V_008DFC_SQ_S_SEXT_I32_I16 0x1A |
||
| 2701 | #define V_008DFC_SQ_S_BITSET0_B32 0x1B |
||
| 2702 | #define V_008DFC_SQ_S_BITSET0_B64 0x1C |
||
| 2703 | #define V_008DFC_SQ_S_BITSET1_B32 0x1D |
||
| 2704 | #define V_008DFC_SQ_S_BITSET1_B64 0x1E |
||
| 2705 | #define V_008DFC_SQ_S_GETPC_B64 0x1F |
||
| 2706 | #define V_008DFC_SQ_S_SETPC_B64 0x20 |
||
| 2707 | #define V_008DFC_SQ_S_SWAPPC_B64 0x21 |
||
| 2708 | #define V_008DFC_SQ_S_RFE_B64 0x22 |
||
| 2709 | #define V_008DFC_SQ_S_AND_SAVEEXEC_B64 0x24 |
||
| 2710 | #define V_008DFC_SQ_S_OR_SAVEEXEC_B64 0x25 |
||
| 2711 | #define V_008DFC_SQ_S_XOR_SAVEEXEC_B64 0x26 |
||
| 2712 | #define V_008DFC_SQ_S_ANDN2_SAVEEXEC_B64 0x27 |
||
| 2713 | #define V_008DFC_SQ_S_ORN2_SAVEEXEC_B64 0x28 |
||
| 2714 | #define V_008DFC_SQ_S_NAND_SAVEEXEC_B64 0x29 |
||
| 2715 | #define V_008DFC_SQ_S_NOR_SAVEEXEC_B64 0x2A |
||
| 2716 | #define V_008DFC_SQ_S_XNOR_SAVEEXEC_B64 0x2B |
||
| 2717 | #define V_008DFC_SQ_S_QUADMASK_B32 0x2C |
||
| 2718 | #define V_008DFC_SQ_S_QUADMASK_B64 0x2D |
||
| 2719 | #define V_008DFC_SQ_S_MOVRELS_B32 0x2E |
||
| 2720 | #define V_008DFC_SQ_S_MOVRELS_B64 0x2F |
||
| 2721 | #define V_008DFC_SQ_S_MOVRELD_B32 0x30 |
||
| 2722 | #define V_008DFC_SQ_S_MOVRELD_B64 0x31 |
||
| 2723 | #define V_008DFC_SQ_S_CBRANCH_JOIN 0x32 |
||
| 2724 | #define V_008DFC_SQ_S_MOV_REGRD_B32 0x33 |
||
| 2725 | #define V_008DFC_SQ_S_ABS_I32 0x34 |
||
| 2726 | #define V_008DFC_SQ_S_MOV_FED_B32 0x35 |
||
| 2727 | #define S_008DFC_SDST(x) (((x) & 0x7F) << 16) |
||
| 2728 | #define G_008DFC_SDST(x) (((x) >> 16) & 0x7F) |
||
| 2729 | #define C_008DFC_SDST 0xFF80FFFF |
||
| 2730 | #define V_008DFC_SQ_SGPR 0x00 |
||
| 2731 | /* CIK */ |
||
| 2732 | #define V_008DFC_SQ_FLAT_SCRATCH_LO 0x68 |
||
| 2733 | #define V_008DFC_SQ_FLAT_SCRATCH_HI 0x69 |
||
| 2734 | /* */ |
||
| 2735 | #define V_008DFC_SQ_VCC_LO 0x6A |
||
| 2736 | #define V_008DFC_SQ_VCC_HI 0x6B |
||
| 2737 | #define V_008DFC_SQ_TBA_LO 0x6C |
||
| 2738 | #define V_008DFC_SQ_TBA_HI 0x6D |
||
| 2739 | #define V_008DFC_SQ_TMA_LO 0x6E |
||
| 2740 | #define V_008DFC_SQ_TMA_HI 0x6F |
||
| 2741 | #define V_008DFC_SQ_TTMP0 0x70 |
||
| 2742 | #define V_008DFC_SQ_TTMP1 0x71 |
||
| 2743 | #define V_008DFC_SQ_TTMP2 0x72 |
||
| 2744 | #define V_008DFC_SQ_TTMP3 0x73 |
||
| 2745 | #define V_008DFC_SQ_TTMP4 0x74 |
||
| 2746 | #define V_008DFC_SQ_TTMP5 0x75 |
||
| 2747 | #define V_008DFC_SQ_TTMP6 0x76 |
||
| 2748 | #define V_008DFC_SQ_TTMP7 0x77 |
||
| 2749 | #define V_008DFC_SQ_TTMP8 0x78 |
||
| 2750 | #define V_008DFC_SQ_TTMP9 0x79 |
||
| 2751 | #define V_008DFC_SQ_TTMP10 0x7A |
||
| 2752 | #define V_008DFC_SQ_TTMP11 0x7B |
||
| 2753 | #define V_008DFC_SQ_M0 0x7C |
||
| 2754 | #define V_008DFC_SQ_EXEC_LO 0x7E |
||
| 2755 | #define V_008DFC_SQ_EXEC_HI 0x7F |
||
| 2756 | #define S_008DFC_ENCODING(x) (((x) & 0x1FF) << 23) |
||
| 2757 | #define G_008DFC_ENCODING(x) (((x) >> 23) & 0x1FF) |
||
| 2758 | #define C_008DFC_ENCODING 0x007FFFFF |
||
| 2759 | #define V_008DFC_SQ_ENC_SOP1_FIELD 0x17D |
||
| 2760 | #define R_008DFC_SQ_MTBUF_1 0x008DFC |
||
| 2761 | #define S_008DFC_VADDR(x) (((x) & 0xFF) << 0) |
||
| 2762 | #define G_008DFC_VADDR(x) (((x) >> 0) & 0xFF) |
||
| 2763 | #define C_008DFC_VADDR 0xFFFFFF00 |
||
| 2764 | #define V_008DFC_SQ_VGPR 0x00 |
||
| 2765 | #define S_008DFC_VDATA(x) (((x) & 0xFF) << 8) |
||
| 2766 | #define G_008DFC_VDATA(x) (((x) >> 8) & 0xFF) |
||
| 2767 | #define C_008DFC_VDATA 0xFFFF00FF |
||
| 2768 | #define V_008DFC_SQ_VGPR 0x00 |
||
| 2769 | #define S_008DFC_SRSRC(x) (((x) & 0x1F) << 16) |
||
| 2770 | #define G_008DFC_SRSRC(x) (((x) >> 16) & 0x1F) |
||
| 2771 | #define C_008DFC_SRSRC 0xFFE0FFFF |
||
| 2772 | #define S_008DFC_SLC(x) (((x) & 0x1) << 22) |
||
| 2773 | #define G_008DFC_SLC(x) (((x) >> 22) & 0x1) |
||
| 2774 | #define C_008DFC_SLC 0xFFBFFFFF |
||
| 2775 | #define S_008DFC_TFE(x) (((x) & 0x1) << 23) |
||
| 2776 | #define G_008DFC_TFE(x) (((x) >> 23) & 0x1) |
||
| 2777 | #define C_008DFC_TFE 0xFF7FFFFF |
||
| 2778 | #define S_008DFC_SOFFSET(x) (((x) & 0xFF) << 24) |
||
| 2779 | #define G_008DFC_SOFFSET(x) (((x) >> 24) & 0xFF) |
||
| 2780 | #define C_008DFC_SOFFSET 0x00FFFFFF |
||
| 2781 | #define V_008DFC_SQ_SGPR 0x00 |
||
| 2782 | /* CIK */ |
||
| 2783 | #define V_008DFC_SQ_FLAT_SCRATCH_LO 0x68 |
||
| 2784 | #define V_008DFC_SQ_FLAT_SCRATCH_HI 0x69 |
||
| 2785 | /* */ |
||
| 2786 | #define V_008DFC_SQ_VCC_LO 0x6A |
||
| 2787 | #define V_008DFC_SQ_VCC_HI 0x6B |
||
| 2788 | #define V_008DFC_SQ_TBA_LO 0x6C |
||
| 2789 | #define V_008DFC_SQ_TBA_HI 0x6D |
||
| 2790 | #define V_008DFC_SQ_TMA_LO 0x6E |
||
| 2791 | #define V_008DFC_SQ_TMA_HI 0x6F |
||
| 2792 | #define V_008DFC_SQ_TTMP0 0x70 |
||
| 2793 | #define V_008DFC_SQ_TTMP1 0x71 |
||
| 2794 | #define V_008DFC_SQ_TTMP2 0x72 |
||
| 2795 | #define V_008DFC_SQ_TTMP3 0x73 |
||
| 2796 | #define V_008DFC_SQ_TTMP4 0x74 |
||
| 2797 | #define V_008DFC_SQ_TTMP5 0x75 |
||
| 2798 | #define V_008DFC_SQ_TTMP6 0x76 |
||
| 2799 | #define V_008DFC_SQ_TTMP7 0x77 |
||
| 2800 | #define V_008DFC_SQ_TTMP8 0x78 |
||
| 2801 | #define V_008DFC_SQ_TTMP9 0x79 |
||
| 2802 | #define V_008DFC_SQ_TTMP10 0x7A |
||
| 2803 | #define V_008DFC_SQ_TTMP11 0x7B |
||
| 2804 | #define V_008DFC_SQ_M0 0x7C |
||
| 2805 | #define V_008DFC_SQ_EXEC_LO 0x7E |
||
| 2806 | #define V_008DFC_SQ_EXEC_HI 0x7F |
||
| 2807 | #define V_008DFC_SQ_SRC_0 0x80 |
||
| 2808 | #define V_008DFC_SQ_SRC_1_INT 0x81 |
||
| 2809 | #define V_008DFC_SQ_SRC_2_INT 0x82 |
||
| 2810 | #define V_008DFC_SQ_SRC_3_INT 0x83 |
||
| 2811 | #define V_008DFC_SQ_SRC_4_INT 0x84 |
||
| 2812 | #define V_008DFC_SQ_SRC_5_INT 0x85 |
||
| 2813 | #define V_008DFC_SQ_SRC_6_INT 0x86 |
||
| 2814 | #define V_008DFC_SQ_SRC_7_INT 0x87 |
||
| 2815 | #define V_008DFC_SQ_SRC_8_INT 0x88 |
||
| 2816 | #define V_008DFC_SQ_SRC_9_INT 0x89 |
||
| 2817 | #define V_008DFC_SQ_SRC_10_INT 0x8A |
||
| 2818 | #define V_008DFC_SQ_SRC_11_INT 0x8B |
||
| 2819 | #define V_008DFC_SQ_SRC_12_INT 0x8C |
||
| 2820 | #define V_008DFC_SQ_SRC_13_INT 0x8D |
||
| 2821 | #define V_008DFC_SQ_SRC_14_INT 0x8E |
||
| 2822 | #define V_008DFC_SQ_SRC_15_INT 0x8F |
||
| 2823 | #define V_008DFC_SQ_SRC_16_INT 0x90 |
||
| 2824 | #define V_008DFC_SQ_SRC_17_INT 0x91 |
||
| 2825 | #define V_008DFC_SQ_SRC_18_INT 0x92 |
||
| 2826 | #define V_008DFC_SQ_SRC_19_INT 0x93 |
||
| 2827 | #define V_008DFC_SQ_SRC_20_INT 0x94 |
||
| 2828 | #define V_008DFC_SQ_SRC_21_INT 0x95 |
||
| 2829 | #define V_008DFC_SQ_SRC_22_INT 0x96 |
||
| 2830 | #define V_008DFC_SQ_SRC_23_INT 0x97 |
||
| 2831 | #define V_008DFC_SQ_SRC_24_INT 0x98 |
||
| 2832 | #define V_008DFC_SQ_SRC_25_INT 0x99 |
||
| 2833 | #define V_008DFC_SQ_SRC_26_INT 0x9A |
||
| 2834 | #define V_008DFC_SQ_SRC_27_INT 0x9B |
||
| 2835 | #define V_008DFC_SQ_SRC_28_INT 0x9C |
||
| 2836 | #define V_008DFC_SQ_SRC_29_INT 0x9D |
||
| 2837 | #define V_008DFC_SQ_SRC_30_INT 0x9E |
||
| 2838 | #define V_008DFC_SQ_SRC_31_INT 0x9F |
||
| 2839 | #define V_008DFC_SQ_SRC_32_INT 0xA0 |
||
| 2840 | #define V_008DFC_SQ_SRC_33_INT 0xA1 |
||
| 2841 | #define V_008DFC_SQ_SRC_34_INT 0xA2 |
||
| 2842 | #define V_008DFC_SQ_SRC_35_INT 0xA3 |
||
| 2843 | #define V_008DFC_SQ_SRC_36_INT 0xA4 |
||
| 2844 | #define V_008DFC_SQ_SRC_37_INT 0xA5 |
||
| 2845 | #define V_008DFC_SQ_SRC_38_INT 0xA6 |
||
| 2846 | #define V_008DFC_SQ_SRC_39_INT 0xA7 |
||
| 2847 | #define V_008DFC_SQ_SRC_40_INT 0xA8 |
||
| 2848 | #define V_008DFC_SQ_SRC_41_INT 0xA9 |
||
| 2849 | #define V_008DFC_SQ_SRC_42_INT 0xAA |
||
| 2850 | #define V_008DFC_SQ_SRC_43_INT 0xAB |
||
| 2851 | #define V_008DFC_SQ_SRC_44_INT 0xAC |
||
| 2852 | #define V_008DFC_SQ_SRC_45_INT 0xAD |
||
| 2853 | #define V_008DFC_SQ_SRC_46_INT 0xAE |
||
| 2854 | #define V_008DFC_SQ_SRC_47_INT 0xAF |
||
| 2855 | #define V_008DFC_SQ_SRC_48_INT 0xB0 |
||
| 2856 | #define V_008DFC_SQ_SRC_49_INT 0xB1 |
||
| 2857 | #define V_008DFC_SQ_SRC_50_INT 0xB2 |
||
| 2858 | #define V_008DFC_SQ_SRC_51_INT 0xB3 |
||
| 2859 | #define V_008DFC_SQ_SRC_52_INT 0xB4 |
||
| 2860 | #define V_008DFC_SQ_SRC_53_INT 0xB5 |
||
| 2861 | #define V_008DFC_SQ_SRC_54_INT 0xB6 |
||
| 2862 | #define V_008DFC_SQ_SRC_55_INT 0xB7 |
||
| 2863 | #define V_008DFC_SQ_SRC_56_INT 0xB8 |
||
| 2864 | #define V_008DFC_SQ_SRC_57_INT 0xB9 |
||
| 2865 | #define V_008DFC_SQ_SRC_58_INT 0xBA |
||
| 2866 | #define V_008DFC_SQ_SRC_59_INT 0xBB |
||
| 2867 | #define V_008DFC_SQ_SRC_60_INT 0xBC |
||
| 2868 | #define V_008DFC_SQ_SRC_61_INT 0xBD |
||
| 2869 | #define V_008DFC_SQ_SRC_62_INT 0xBE |
||
| 2870 | #define V_008DFC_SQ_SRC_63_INT 0xBF |
||
| 2871 | #define V_008DFC_SQ_SRC_64_INT 0xC0 |
||
| 2872 | #define V_008DFC_SQ_SRC_M_1_INT 0xC1 |
||
| 2873 | #define V_008DFC_SQ_SRC_M_2_INT 0xC2 |
||
| 2874 | #define V_008DFC_SQ_SRC_M_3_INT 0xC3 |
||
| 2875 | #define V_008DFC_SQ_SRC_M_4_INT 0xC4 |
||
| 2876 | #define V_008DFC_SQ_SRC_M_5_INT 0xC5 |
||
| 2877 | #define V_008DFC_SQ_SRC_M_6_INT 0xC6 |
||
| 2878 | #define V_008DFC_SQ_SRC_M_7_INT 0xC7 |
||
| 2879 | #define V_008DFC_SQ_SRC_M_8_INT 0xC8 |
||
| 2880 | #define V_008DFC_SQ_SRC_M_9_INT 0xC9 |
||
| 2881 | #define V_008DFC_SQ_SRC_M_10_INT 0xCA |
||
| 2882 | #define V_008DFC_SQ_SRC_M_11_INT 0xCB |
||
| 2883 | #define V_008DFC_SQ_SRC_M_12_INT 0xCC |
||
| 2884 | #define V_008DFC_SQ_SRC_M_13_INT 0xCD |
||
| 2885 | #define V_008DFC_SQ_SRC_M_14_INT 0xCE |
||
| 2886 | #define V_008DFC_SQ_SRC_M_15_INT 0xCF |
||
| 2887 | #define V_008DFC_SQ_SRC_M_16_INT 0xD0 |
||
| 2888 | #define V_008DFC_SQ_SRC_0_5 0xF0 |
||
| 2889 | #define V_008DFC_SQ_SRC_M_0_5 0xF1 |
||
| 2890 | #define V_008DFC_SQ_SRC_1 0xF2 |
||
| 2891 | #define V_008DFC_SQ_SRC_M_1 0xF3 |
||
| 2892 | #define V_008DFC_SQ_SRC_2 0xF4 |
||
| 2893 | #define V_008DFC_SQ_SRC_M_2 0xF5 |
||
| 2894 | #define V_008DFC_SQ_SRC_4 0xF6 |
||
| 2895 | #define V_008DFC_SQ_SRC_M_4 0xF7 |
||
| 2896 | #define V_008DFC_SQ_SRC_VCCZ 0xFB |
||
| 2897 | #define V_008DFC_SQ_SRC_EXECZ 0xFC |
||
| 2898 | #define V_008DFC_SQ_SRC_SCC 0xFD |
||
| 2899 | #define V_008DFC_SQ_SRC_LDS_DIRECT 0xFE |
||
| 2900 | #define R_008DFC_SQ_SOP2 0x008DFC |
||
| 2901 | #define S_008DFC_SSRC0(x) (((x) & 0xFF) << 0) |
||
| 2902 | #define G_008DFC_SSRC0(x) (((x) >> 0) & 0xFF) |
||
| 2903 | #define C_008DFC_SSRC0 0xFFFFFF00 |
||
| 2904 | #define V_008DFC_SQ_SGPR 0x00 |
||
| 2905 | /* CIK */ |
||
| 2906 | #define V_008DFC_SQ_FLAT_SCRATCH_LO 0x68 |
||
| 2907 | #define V_008DFC_SQ_FLAT_SCRATCH_HI 0x69 |
||
| 2908 | /* */ |
||
| 2909 | #define V_008DFC_SQ_VCC_LO 0x6A |
||
| 2910 | #define V_008DFC_SQ_VCC_HI 0x6B |
||
| 2911 | #define V_008DFC_SQ_TBA_LO 0x6C |
||
| 2912 | #define V_008DFC_SQ_TBA_HI 0x6D |
||
| 2913 | #define V_008DFC_SQ_TMA_LO 0x6E |
||
| 2914 | #define V_008DFC_SQ_TMA_HI 0x6F |
||
| 2915 | #define V_008DFC_SQ_TTMP0 0x70 |
||
| 2916 | #define V_008DFC_SQ_TTMP1 0x71 |
||
| 2917 | #define V_008DFC_SQ_TTMP2 0x72 |
||
| 2918 | #define V_008DFC_SQ_TTMP3 0x73 |
||
| 2919 | #define V_008DFC_SQ_TTMP4 0x74 |
||
| 2920 | #define V_008DFC_SQ_TTMP5 0x75 |
||
| 2921 | #define V_008DFC_SQ_TTMP6 0x76 |
||
| 2922 | #define V_008DFC_SQ_TTMP7 0x77 |
||
| 2923 | #define V_008DFC_SQ_TTMP8 0x78 |
||
| 2924 | #define V_008DFC_SQ_TTMP9 0x79 |
||
| 2925 | #define V_008DFC_SQ_TTMP10 0x7A |
||
| 2926 | #define V_008DFC_SQ_TTMP11 0x7B |
||
| 2927 | #define V_008DFC_SQ_M0 0x7C |
||
| 2928 | #define V_008DFC_SQ_EXEC_LO 0x7E |
||
| 2929 | #define V_008DFC_SQ_EXEC_HI 0x7F |
||
| 2930 | #define V_008DFC_SQ_SRC_0 0x80 |
||
| 2931 | #define V_008DFC_SQ_SRC_1_INT 0x81 |
||
| 2932 | #define V_008DFC_SQ_SRC_2_INT 0x82 |
||
| 2933 | #define V_008DFC_SQ_SRC_3_INT 0x83 |
||
| 2934 | #define V_008DFC_SQ_SRC_4_INT 0x84 |
||
| 2935 | #define V_008DFC_SQ_SRC_5_INT 0x85 |
||
| 2936 | #define V_008DFC_SQ_SRC_6_INT 0x86 |
||
| 2937 | #define V_008DFC_SQ_SRC_7_INT 0x87 |
||
| 2938 | #define V_008DFC_SQ_SRC_8_INT 0x88 |
||
| 2939 | #define V_008DFC_SQ_SRC_9_INT 0x89 |
||
| 2940 | #define V_008DFC_SQ_SRC_10_INT 0x8A |
||
| 2941 | #define V_008DFC_SQ_SRC_11_INT 0x8B |
||
| 2942 | #define V_008DFC_SQ_SRC_12_INT 0x8C |
||
| 2943 | #define V_008DFC_SQ_SRC_13_INT 0x8D |
||
| 2944 | #define V_008DFC_SQ_SRC_14_INT 0x8E |
||
| 2945 | #define V_008DFC_SQ_SRC_15_INT 0x8F |
||
| 2946 | #define V_008DFC_SQ_SRC_16_INT 0x90 |
||
| 2947 | #define V_008DFC_SQ_SRC_17_INT 0x91 |
||
| 2948 | #define V_008DFC_SQ_SRC_18_INT 0x92 |
||
| 2949 | #define V_008DFC_SQ_SRC_19_INT 0x93 |
||
| 2950 | #define V_008DFC_SQ_SRC_20_INT 0x94 |
||
| 2951 | #define V_008DFC_SQ_SRC_21_INT 0x95 |
||
| 2952 | #define V_008DFC_SQ_SRC_22_INT 0x96 |
||
| 2953 | #define V_008DFC_SQ_SRC_23_INT 0x97 |
||
| 2954 | #define V_008DFC_SQ_SRC_24_INT 0x98 |
||
| 2955 | #define V_008DFC_SQ_SRC_25_INT 0x99 |
||
| 2956 | #define V_008DFC_SQ_SRC_26_INT 0x9A |
||
| 2957 | #define V_008DFC_SQ_SRC_27_INT 0x9B |
||
| 2958 | #define V_008DFC_SQ_SRC_28_INT 0x9C |
||
| 2959 | #define V_008DFC_SQ_SRC_29_INT 0x9D |
||
| 2960 | #define V_008DFC_SQ_SRC_30_INT 0x9E |
||
| 2961 | #define V_008DFC_SQ_SRC_31_INT 0x9F |
||
| 2962 | #define V_008DFC_SQ_SRC_32_INT 0xA0 |
||
| 2963 | #define V_008DFC_SQ_SRC_33_INT 0xA1 |
||
| 2964 | #define V_008DFC_SQ_SRC_34_INT 0xA2 |
||
| 2965 | #define V_008DFC_SQ_SRC_35_INT 0xA3 |
||
| 2966 | #define V_008DFC_SQ_SRC_36_INT 0xA4 |
||
| 2967 | #define V_008DFC_SQ_SRC_37_INT 0xA5 |
||
| 2968 | #define V_008DFC_SQ_SRC_38_INT 0xA6 |
||
| 2969 | #define V_008DFC_SQ_SRC_39_INT 0xA7 |
||
| 2970 | #define V_008DFC_SQ_SRC_40_INT 0xA8 |
||
| 2971 | #define V_008DFC_SQ_SRC_41_INT 0xA9 |
||
| 2972 | #define V_008DFC_SQ_SRC_42_INT 0xAA |
||
| 2973 | #define V_008DFC_SQ_SRC_43_INT 0xAB |
||
| 2974 | #define V_008DFC_SQ_SRC_44_INT 0xAC |
||
| 2975 | #define V_008DFC_SQ_SRC_45_INT 0xAD |
||
| 2976 | #define V_008DFC_SQ_SRC_46_INT 0xAE |
||
| 2977 | #define V_008DFC_SQ_SRC_47_INT 0xAF |
||
| 2978 | #define V_008DFC_SQ_SRC_48_INT 0xB0 |
||
| 2979 | #define V_008DFC_SQ_SRC_49_INT 0xB1 |
||
| 2980 | #define V_008DFC_SQ_SRC_50_INT 0xB2 |
||
| 2981 | #define V_008DFC_SQ_SRC_51_INT 0xB3 |
||
| 2982 | #define V_008DFC_SQ_SRC_52_INT 0xB4 |
||
| 2983 | #define V_008DFC_SQ_SRC_53_INT 0xB5 |
||
| 2984 | #define V_008DFC_SQ_SRC_54_INT 0xB6 |
||
| 2985 | #define V_008DFC_SQ_SRC_55_INT 0xB7 |
||
| 2986 | #define V_008DFC_SQ_SRC_56_INT 0xB8 |
||
| 2987 | #define V_008DFC_SQ_SRC_57_INT 0xB9 |
||
| 2988 | #define V_008DFC_SQ_SRC_58_INT 0xBA |
||
| 2989 | #define V_008DFC_SQ_SRC_59_INT 0xBB |
||
| 2990 | #define V_008DFC_SQ_SRC_60_INT 0xBC |
||
| 2991 | #define V_008DFC_SQ_SRC_61_INT 0xBD |
||
| 2992 | #define V_008DFC_SQ_SRC_62_INT 0xBE |
||
| 2993 | #define V_008DFC_SQ_SRC_63_INT 0xBF |
||
| 2994 | #define V_008DFC_SQ_SRC_64_INT 0xC0 |
||
| 2995 | #define V_008DFC_SQ_SRC_M_1_INT 0xC1 |
||
| 2996 | #define V_008DFC_SQ_SRC_M_2_INT 0xC2 |
||
| 2997 | #define V_008DFC_SQ_SRC_M_3_INT 0xC3 |
||
| 2998 | #define V_008DFC_SQ_SRC_M_4_INT 0xC4 |
||
| 2999 | #define V_008DFC_SQ_SRC_M_5_INT 0xC5 |
||
| 3000 | #define V_008DFC_SQ_SRC_M_6_INT 0xC6 |
||
| 3001 | #define V_008DFC_SQ_SRC_M_7_INT 0xC7 |
||
| 3002 | #define V_008DFC_SQ_SRC_M_8_INT 0xC8 |
||
| 3003 | #define V_008DFC_SQ_SRC_M_9_INT 0xC9 |
||
| 3004 | #define V_008DFC_SQ_SRC_M_10_INT 0xCA |
||
| 3005 | #define V_008DFC_SQ_SRC_M_11_INT 0xCB |
||
| 3006 | #define V_008DFC_SQ_SRC_M_12_INT 0xCC |
||
| 3007 | #define V_008DFC_SQ_SRC_M_13_INT 0xCD |
||
| 3008 | #define V_008DFC_SQ_SRC_M_14_INT 0xCE |
||
| 3009 | #define V_008DFC_SQ_SRC_M_15_INT 0xCF |
||
| 3010 | #define V_008DFC_SQ_SRC_M_16_INT 0xD0 |
||
| 3011 | #define V_008DFC_SQ_SRC_0_5 0xF0 |
||
| 3012 | #define V_008DFC_SQ_SRC_M_0_5 0xF1 |
||
| 3013 | #define V_008DFC_SQ_SRC_1 0xF2 |
||
| 3014 | #define V_008DFC_SQ_SRC_M_1 0xF3 |
||
| 3015 | #define V_008DFC_SQ_SRC_2 0xF4 |
||
| 3016 | #define V_008DFC_SQ_SRC_M_2 0xF5 |
||
| 3017 | #define V_008DFC_SQ_SRC_4 0xF6 |
||
| 3018 | #define V_008DFC_SQ_SRC_M_4 0xF7 |
||
| 3019 | #define V_008DFC_SQ_SRC_VCCZ 0xFB |
||
| 3020 | #define V_008DFC_SQ_SRC_EXECZ 0xFC |
||
| 3021 | #define V_008DFC_SQ_SRC_SCC 0xFD |
||
| 3022 | #define V_008DFC_SQ_SRC_LDS_DIRECT 0xFE |
||
| 3023 | #define S_008DFC_SSRC1(x) (((x) & 0xFF) << 8) |
||
| 3024 | #define G_008DFC_SSRC1(x) (((x) >> 8) & 0xFF) |
||
| 3025 | #define C_008DFC_SSRC1 0xFFFF00FF |
||
| 3026 | #define V_008DFC_SQ_SGPR 0x00 |
||
| 3027 | /* CIK */ |
||
| 3028 | #define V_008DFC_SQ_FLAT_SCRATCH_LO 0x68 |
||
| 3029 | #define V_008DFC_SQ_FLAT_SCRATCH_HI 0x69 |
||
| 3030 | /* */ |
||
| 3031 | #define V_008DFC_SQ_VCC_LO 0x6A |
||
| 3032 | #define V_008DFC_SQ_VCC_HI 0x6B |
||
| 3033 | #define V_008DFC_SQ_TBA_LO 0x6C |
||
| 3034 | #define V_008DFC_SQ_TBA_HI 0x6D |
||
| 3035 | #define V_008DFC_SQ_TMA_LO 0x6E |
||
| 3036 | #define V_008DFC_SQ_TMA_HI 0x6F |
||
| 3037 | #define V_008DFC_SQ_TTMP0 0x70 |
||
| 3038 | #define V_008DFC_SQ_TTMP1 0x71 |
||
| 3039 | #define V_008DFC_SQ_TTMP2 0x72 |
||
| 3040 | #define V_008DFC_SQ_TTMP3 0x73 |
||
| 3041 | #define V_008DFC_SQ_TTMP4 0x74 |
||
| 3042 | #define V_008DFC_SQ_TTMP5 0x75 |
||
| 3043 | #define V_008DFC_SQ_TTMP6 0x76 |
||
| 3044 | #define V_008DFC_SQ_TTMP7 0x77 |
||
| 3045 | #define V_008DFC_SQ_TTMP8 0x78 |
||
| 3046 | #define V_008DFC_SQ_TTMP9 0x79 |
||
| 3047 | #define V_008DFC_SQ_TTMP10 0x7A |
||
| 3048 | #define V_008DFC_SQ_TTMP11 0x7B |
||
| 3049 | #define V_008DFC_SQ_M0 0x7C |
||
| 3050 | #define V_008DFC_SQ_EXEC_LO 0x7E |
||
| 3051 | #define V_008DFC_SQ_EXEC_HI 0x7F |
||
| 3052 | #define V_008DFC_SQ_SRC_0 0x80 |
||
| 3053 | #define V_008DFC_SQ_SRC_1_INT 0x81 |
||
| 3054 | #define V_008DFC_SQ_SRC_2_INT 0x82 |
||
| 3055 | #define V_008DFC_SQ_SRC_3_INT 0x83 |
||
| 3056 | #define V_008DFC_SQ_SRC_4_INT 0x84 |
||
| 3057 | #define V_008DFC_SQ_SRC_5_INT 0x85 |
||
| 3058 | #define V_008DFC_SQ_SRC_6_INT 0x86 |
||
| 3059 | #define V_008DFC_SQ_SRC_7_INT 0x87 |
||
| 3060 | #define V_008DFC_SQ_SRC_8_INT 0x88 |
||
| 3061 | #define V_008DFC_SQ_SRC_9_INT 0x89 |
||
| 3062 | #define V_008DFC_SQ_SRC_10_INT 0x8A |
||
| 3063 | #define V_008DFC_SQ_SRC_11_INT 0x8B |
||
| 3064 | #define V_008DFC_SQ_SRC_12_INT 0x8C |
||
| 3065 | #define V_008DFC_SQ_SRC_13_INT 0x8D |
||
| 3066 | #define V_008DFC_SQ_SRC_14_INT 0x8E |
||
| 3067 | #define V_008DFC_SQ_SRC_15_INT 0x8F |
||
| 3068 | #define V_008DFC_SQ_SRC_16_INT 0x90 |
||
| 3069 | #define V_008DFC_SQ_SRC_17_INT 0x91 |
||
| 3070 | #define V_008DFC_SQ_SRC_18_INT 0x92 |
||
| 3071 | #define V_008DFC_SQ_SRC_19_INT 0x93 |
||
| 3072 | #define V_008DFC_SQ_SRC_20_INT 0x94 |
||
| 3073 | #define V_008DFC_SQ_SRC_21_INT 0x95 |
||
| 3074 | #define V_008DFC_SQ_SRC_22_INT 0x96 |
||
| 3075 | #define V_008DFC_SQ_SRC_23_INT 0x97 |
||
| 3076 | #define V_008DFC_SQ_SRC_24_INT 0x98 |
||
| 3077 | #define V_008DFC_SQ_SRC_25_INT 0x99 |
||
| 3078 | #define V_008DFC_SQ_SRC_26_INT 0x9A |
||
| 3079 | #define V_008DFC_SQ_SRC_27_INT 0x9B |
||
| 3080 | #define V_008DFC_SQ_SRC_28_INT 0x9C |
||
| 3081 | #define V_008DFC_SQ_SRC_29_INT 0x9D |
||
| 3082 | #define V_008DFC_SQ_SRC_30_INT 0x9E |
||
| 3083 | #define V_008DFC_SQ_SRC_31_INT 0x9F |
||
| 3084 | #define V_008DFC_SQ_SRC_32_INT 0xA0 |
||
| 3085 | #define V_008DFC_SQ_SRC_33_INT 0xA1 |
||
| 3086 | #define V_008DFC_SQ_SRC_34_INT 0xA2 |
||
| 3087 | #define V_008DFC_SQ_SRC_35_INT 0xA3 |
||
| 3088 | #define V_008DFC_SQ_SRC_36_INT 0xA4 |
||
| 3089 | #define V_008DFC_SQ_SRC_37_INT 0xA5 |
||
| 3090 | #define V_008DFC_SQ_SRC_38_INT 0xA6 |
||
| 3091 | #define V_008DFC_SQ_SRC_39_INT 0xA7 |
||
| 3092 | #define V_008DFC_SQ_SRC_40_INT 0xA8 |
||
| 3093 | #define V_008DFC_SQ_SRC_41_INT 0xA9 |
||
| 3094 | #define V_008DFC_SQ_SRC_42_INT 0xAA |
||
| 3095 | #define V_008DFC_SQ_SRC_43_INT 0xAB |
||
| 3096 | #define V_008DFC_SQ_SRC_44_INT 0xAC |
||
| 3097 | #define V_008DFC_SQ_SRC_45_INT 0xAD |
||
| 3098 | #define V_008DFC_SQ_SRC_46_INT 0xAE |
||
| 3099 | #define V_008DFC_SQ_SRC_47_INT 0xAF |
||
| 3100 | #define V_008DFC_SQ_SRC_48_INT 0xB0 |
||
| 3101 | #define V_008DFC_SQ_SRC_49_INT 0xB1 |
||
| 3102 | #define V_008DFC_SQ_SRC_50_INT 0xB2 |
||
| 3103 | #define V_008DFC_SQ_SRC_51_INT 0xB3 |
||
| 3104 | #define V_008DFC_SQ_SRC_52_INT 0xB4 |
||
| 3105 | #define V_008DFC_SQ_SRC_53_INT 0xB5 |
||
| 3106 | #define V_008DFC_SQ_SRC_54_INT 0xB6 |
||
| 3107 | #define V_008DFC_SQ_SRC_55_INT 0xB7 |
||
| 3108 | #define V_008DFC_SQ_SRC_56_INT 0xB8 |
||
| 3109 | #define V_008DFC_SQ_SRC_57_INT 0xB9 |
||
| 3110 | #define V_008DFC_SQ_SRC_58_INT 0xBA |
||
| 3111 | #define V_008DFC_SQ_SRC_59_INT 0xBB |
||
| 3112 | #define V_008DFC_SQ_SRC_60_INT 0xBC |
||
| 3113 | #define V_008DFC_SQ_SRC_61_INT 0xBD |
||
| 3114 | #define V_008DFC_SQ_SRC_62_INT 0xBE |
||
| 3115 | #define V_008DFC_SQ_SRC_63_INT 0xBF |
||
| 3116 | #define V_008DFC_SQ_SRC_64_INT 0xC0 |
||
| 3117 | #define V_008DFC_SQ_SRC_M_1_INT 0xC1 |
||
| 3118 | #define V_008DFC_SQ_SRC_M_2_INT 0xC2 |
||
| 3119 | #define V_008DFC_SQ_SRC_M_3_INT 0xC3 |
||
| 3120 | #define V_008DFC_SQ_SRC_M_4_INT 0xC4 |
||
| 3121 | #define V_008DFC_SQ_SRC_M_5_INT 0xC5 |
||
| 3122 | #define V_008DFC_SQ_SRC_M_6_INT 0xC6 |
||
| 3123 | #define V_008DFC_SQ_SRC_M_7_INT 0xC7 |
||
| 3124 | #define V_008DFC_SQ_SRC_M_8_INT 0xC8 |
||
| 3125 | #define V_008DFC_SQ_SRC_M_9_INT 0xC9 |
||
| 3126 | #define V_008DFC_SQ_SRC_M_10_INT 0xCA |
||
| 3127 | #define V_008DFC_SQ_SRC_M_11_INT 0xCB |
||
| 3128 | #define V_008DFC_SQ_SRC_M_12_INT 0xCC |
||
| 3129 | #define V_008DFC_SQ_SRC_M_13_INT 0xCD |
||
| 3130 | #define V_008DFC_SQ_SRC_M_14_INT 0xCE |
||
| 3131 | #define V_008DFC_SQ_SRC_M_15_INT 0xCF |
||
| 3132 | #define V_008DFC_SQ_SRC_M_16_INT 0xD0 |
||
| 3133 | #define V_008DFC_SQ_SRC_0_5 0xF0 |
||
| 3134 | #define V_008DFC_SQ_SRC_M_0_5 0xF1 |
||
| 3135 | #define V_008DFC_SQ_SRC_1 0xF2 |
||
| 3136 | #define V_008DFC_SQ_SRC_M_1 0xF3 |
||
| 3137 | #define V_008DFC_SQ_SRC_2 0xF4 |
||
| 3138 | #define V_008DFC_SQ_SRC_M_2 0xF5 |
||
| 3139 | #define V_008DFC_SQ_SRC_4 0xF6 |
||
| 3140 | #define V_008DFC_SQ_SRC_M_4 0xF7 |
||
| 3141 | #define V_008DFC_SQ_SRC_VCCZ 0xFB |
||
| 3142 | #define V_008DFC_SQ_SRC_EXECZ 0xFC |
||
| 3143 | #define V_008DFC_SQ_SRC_SCC 0xFD |
||
| 3144 | #define V_008DFC_SQ_SRC_LDS_DIRECT 0xFE |
||
| 3145 | #define S_008DFC_SDST(x) (((x) & 0x7F) << 16) |
||
| 3146 | #define G_008DFC_SDST(x) (((x) >> 16) & 0x7F) |
||
| 3147 | #define C_008DFC_SDST 0xFF80FFFF |
||
| 3148 | #define V_008DFC_SQ_SGPR 0x00 |
||
| 3149 | /* CIK */ |
||
| 3150 | #define V_008DFC_SQ_FLAT_SCRATCH_LO 0x68 |
||
| 3151 | #define V_008DFC_SQ_FLAT_SCRATCH_HI 0x69 |
||
| 3152 | /* */ |
||
| 3153 | #define V_008DFC_SQ_VCC_LO 0x6A |
||
| 3154 | #define V_008DFC_SQ_VCC_HI 0x6B |
||
| 3155 | #define V_008DFC_SQ_TBA_LO 0x6C |
||
| 3156 | #define V_008DFC_SQ_TBA_HI 0x6D |
||
| 3157 | #define V_008DFC_SQ_TMA_LO 0x6E |
||
| 3158 | #define V_008DFC_SQ_TMA_HI 0x6F |
||
| 3159 | #define V_008DFC_SQ_TTMP0 0x70 |
||
| 3160 | #define V_008DFC_SQ_TTMP1 0x71 |
||
| 3161 | #define V_008DFC_SQ_TTMP2 0x72 |
||
| 3162 | #define V_008DFC_SQ_TTMP3 0x73 |
||
| 3163 | #define V_008DFC_SQ_TTMP4 0x74 |
||
| 3164 | #define V_008DFC_SQ_TTMP5 0x75 |
||
| 3165 | #define V_008DFC_SQ_TTMP6 0x76 |
||
| 3166 | #define V_008DFC_SQ_TTMP7 0x77 |
||
| 3167 | #define V_008DFC_SQ_TTMP8 0x78 |
||
| 3168 | #define V_008DFC_SQ_TTMP9 0x79 |
||
| 3169 | #define V_008DFC_SQ_TTMP10 0x7A |
||
| 3170 | #define V_008DFC_SQ_TTMP11 0x7B |
||
| 3171 | #define V_008DFC_SQ_M0 0x7C |
||
| 3172 | #define V_008DFC_SQ_EXEC_LO 0x7E |
||
| 3173 | #define V_008DFC_SQ_EXEC_HI 0x7F |
||
| 3174 | #define S_008DFC_OP(x) (((x) & 0x7F) << 23) |
||
| 3175 | #define G_008DFC_OP(x) (((x) >> 23) & 0x7F) |
||
| 3176 | #define C_008DFC_OP 0xC07FFFFF |
||
| 3177 | #define V_008DFC_SQ_S_ADD_U32 0x00 |
||
| 3178 | #define V_008DFC_SQ_S_SUB_U32 0x01 |
||
| 3179 | #define V_008DFC_SQ_S_ADD_I32 0x02 |
||
| 3180 | #define V_008DFC_SQ_S_SUB_I32 0x03 |
||
| 3181 | #define V_008DFC_SQ_S_ADDC_U32 0x04 |
||
| 3182 | #define V_008DFC_SQ_S_SUBB_U32 0x05 |
||
| 3183 | #define V_008DFC_SQ_S_MIN_I32 0x06 |
||
| 3184 | #define V_008DFC_SQ_S_MIN_U32 0x07 |
||
| 3185 | #define V_008DFC_SQ_S_MAX_I32 0x08 |
||
| 3186 | #define V_008DFC_SQ_S_MAX_U32 0x09 |
||
| 3187 | #define V_008DFC_SQ_S_CSELECT_B32 0x0A |
||
| 3188 | #define V_008DFC_SQ_S_CSELECT_B64 0x0B |
||
| 3189 | #define V_008DFC_SQ_S_AND_B32 0x0E |
||
| 3190 | #define V_008DFC_SQ_S_AND_B64 0x0F |
||
| 3191 | #define V_008DFC_SQ_S_OR_B32 0x10 |
||
| 3192 | #define V_008DFC_SQ_S_OR_B64 0x11 |
||
| 3193 | #define V_008DFC_SQ_S_XOR_B32 0x12 |
||
| 3194 | #define V_008DFC_SQ_S_XOR_B64 0x13 |
||
| 3195 | #define V_008DFC_SQ_S_ANDN2_B32 0x14 |
||
| 3196 | #define V_008DFC_SQ_S_ANDN2_B64 0x15 |
||
| 3197 | #define V_008DFC_SQ_S_ORN2_B32 0x16 |
||
| 3198 | #define V_008DFC_SQ_S_ORN2_B64 0x17 |
||
| 3199 | #define V_008DFC_SQ_S_NAND_B32 0x18 |
||
| 3200 | #define V_008DFC_SQ_S_NAND_B64 0x19 |
||
| 3201 | #define V_008DFC_SQ_S_NOR_B32 0x1A |
||
| 3202 | #define V_008DFC_SQ_S_NOR_B64 0x1B |
||
| 3203 | #define V_008DFC_SQ_S_XNOR_B32 0x1C |
||
| 3204 | #define V_008DFC_SQ_S_XNOR_B64 0x1D |
||
| 3205 | #define V_008DFC_SQ_S_LSHL_B32 0x1E |
||
| 3206 | #define V_008DFC_SQ_S_LSHL_B64 0x1F |
||
| 3207 | #define V_008DFC_SQ_S_LSHR_B32 0x20 |
||
| 3208 | #define V_008DFC_SQ_S_LSHR_B64 0x21 |
||
| 3209 | #define V_008DFC_SQ_S_ASHR_I32 0x22 |
||
| 3210 | #define V_008DFC_SQ_S_ASHR_I64 0x23 |
||
| 3211 | #define V_008DFC_SQ_S_BFM_B32 0x24 |
||
| 3212 | #define V_008DFC_SQ_S_BFM_B64 0x25 |
||
| 3213 | #define V_008DFC_SQ_S_MUL_I32 0x26 |
||
| 3214 | #define V_008DFC_SQ_S_BFE_U32 0x27 |
||
| 3215 | #define V_008DFC_SQ_S_BFE_I32 0x28 |
||
| 3216 | #define V_008DFC_SQ_S_BFE_U64 0x29 |
||
| 3217 | #define V_008DFC_SQ_S_BFE_I64 0x2A |
||
| 3218 | #define V_008DFC_SQ_S_CBRANCH_G_FORK 0x2B |
||
| 3219 | #define V_008DFC_SQ_S_ABSDIFF_I32 0x2C |
||
| 3220 | #define S_008DFC_ENCODING(x) (((x) & 0x03) << 30) |
||
| 3221 | #define G_008DFC_ENCODING(x) (((x) >> 30) & 0x03) |
||
| 3222 | #define C_008DFC_ENCODING 0x3FFFFFFF |
||
| 3223 | #define V_008DFC_SQ_ENC_SOP2_FIELD 0x02 |
||
| 3224 | #define R_008DFC_SQ_SOPK 0x008DFC |
||
| 3225 | #define S_008DFC_SIMM16(x) (((x) & 0xFFFF) << 0) |
||
| 3226 | #define G_008DFC_SIMM16(x) (((x) >> 0) & 0xFFFF) |
||
| 3227 | #define C_008DFC_SIMM16 0xFFFF0000 |
||
| 3228 | #define S_008DFC_SDST(x) (((x) & 0x7F) << 16) |
||
| 3229 | #define G_008DFC_SDST(x) (((x) >> 16) & 0x7F) |
||
| 3230 | #define C_008DFC_SDST 0xFF80FFFF |
||
| 3231 | #define V_008DFC_SQ_SGPR 0x00 |
||
| 3232 | /* CIK */ |
||
| 3233 | #define V_008DFC_SQ_FLAT_SCRATCH_LO 0x68 |
||
| 3234 | #define V_008DFC_SQ_FLAT_SCRATCH_HI 0x69 |
||
| 3235 | /* */ |
||
| 3236 | #define V_008DFC_SQ_VCC_LO 0x6A |
||
| 3237 | #define V_008DFC_SQ_VCC_HI 0x6B |
||
| 3238 | #define V_008DFC_SQ_TBA_LO 0x6C |
||
| 3239 | #define V_008DFC_SQ_TBA_HI 0x6D |
||
| 3240 | #define V_008DFC_SQ_TMA_LO 0x6E |
||
| 3241 | #define V_008DFC_SQ_TMA_HI 0x6F |
||
| 3242 | #define V_008DFC_SQ_TTMP0 0x70 |
||
| 3243 | #define V_008DFC_SQ_TTMP1 0x71 |
||
| 3244 | #define V_008DFC_SQ_TTMP2 0x72 |
||
| 3245 | #define V_008DFC_SQ_TTMP3 0x73 |
||
| 3246 | #define V_008DFC_SQ_TTMP4 0x74 |
||
| 3247 | #define V_008DFC_SQ_TTMP5 0x75 |
||
| 3248 | #define V_008DFC_SQ_TTMP6 0x76 |
||
| 3249 | #define V_008DFC_SQ_TTMP7 0x77 |
||
| 3250 | #define V_008DFC_SQ_TTMP8 0x78 |
||
| 3251 | #define V_008DFC_SQ_TTMP9 0x79 |
||
| 3252 | #define V_008DFC_SQ_TTMP10 0x7A |
||
| 3253 | #define V_008DFC_SQ_TTMP11 0x7B |
||
| 3254 | #define V_008DFC_SQ_M0 0x7C |
||
| 3255 | #define V_008DFC_SQ_EXEC_LO 0x7E |
||
| 3256 | #define V_008DFC_SQ_EXEC_HI 0x7F |
||
| 3257 | #define S_008DFC_OP(x) (((x) & 0x1F) << 23) |
||
| 3258 | #define G_008DFC_OP(x) (((x) >> 23) & 0x1F) |
||
| 3259 | #define C_008DFC_OP 0xF07FFFFF |
||
| 3260 | #define V_008DFC_SQ_S_MOVK_I32 0x00 |
||
| 3261 | #define V_008DFC_SQ_S_CMOVK_I32 0x02 |
||
| 3262 | #define V_008DFC_SQ_S_CMPK_EQ_I32 0x03 |
||
| 3263 | #define V_008DFC_SQ_S_CMPK_LG_I32 0x04 |
||
| 3264 | #define V_008DFC_SQ_S_CMPK_GT_I32 0x05 |
||
| 3265 | #define V_008DFC_SQ_S_CMPK_GE_I32 0x06 |
||
| 3266 | #define V_008DFC_SQ_S_CMPK_LT_I32 0x07 |
||
| 3267 | #define V_008DFC_SQ_S_CMPK_LE_I32 0x08 |
||
| 3268 | #define V_008DFC_SQ_S_CMPK_EQ_U32 0x09 |
||
| 3269 | #define V_008DFC_SQ_S_CMPK_LG_U32 0x0A |
||
| 3270 | #define V_008DFC_SQ_S_CMPK_GT_U32 0x0B |
||
| 3271 | #define V_008DFC_SQ_S_CMPK_GE_U32 0x0C |
||
| 3272 | #define V_008DFC_SQ_S_CMPK_LT_U32 0x0D |
||
| 3273 | #define V_008DFC_SQ_S_CMPK_LE_U32 0x0E |
||
| 3274 | #define V_008DFC_SQ_S_ADDK_I32 0x0F |
||
| 3275 | #define V_008DFC_SQ_S_MULK_I32 0x10 |
||
| 3276 | #define V_008DFC_SQ_S_CBRANCH_I_FORK 0x11 |
||
| 3277 | #define V_008DFC_SQ_S_GETREG_B32 0x12 |
||
| 3278 | #define V_008DFC_SQ_S_SETREG_B32 0x13 |
||
| 3279 | #define V_008DFC_SQ_S_GETREG_REGRD_B32 0x14 |
||
| 3280 | #define V_008DFC_SQ_S_SETREG_IMM32_B32 0x15 |
||
| 3281 | #define S_008DFC_ENCODING(x) (((x) & 0x0F) << 28) |
||
| 3282 | #define G_008DFC_ENCODING(x) (((x) >> 28) & 0x0F) |
||
| 3283 | #define C_008DFC_ENCODING 0x0FFFFFFF |
||
| 3284 | #define V_008DFC_SQ_ENC_SOPK_FIELD 0x0B |
||
| 3285 | #define R_008DFC_SQ_VOP3_0 0x008DFC |
||
| 3286 | #define S_008DFC_VDST(x) (((x) & 0xFF) << 0) |
||
| 3287 | #define G_008DFC_VDST(x) (((x) >> 0) & 0xFF) |
||
| 3288 | #define C_008DFC_VDST 0xFFFFFF00 |
||
| 3289 | #define V_008DFC_SQ_VGPR 0x00 |
||
| 3290 | #define S_008DFC_ABS(x) (((x) & 0x07) << 8) |
||
| 3291 | #define G_008DFC_ABS(x) (((x) >> 8) & 0x07) |
||
| 3292 | #define C_008DFC_ABS 0xFFFFF8FF |
||
| 3293 | #define S_008DFC_CLAMP(x) (((x) & 0x1) << 11) |
||
| 3294 | #define G_008DFC_CLAMP(x) (((x) >> 11) & 0x1) |
||
| 3295 | #define C_008DFC_CLAMP 0xFFFFF7FF |
||
| 3296 | #define S_008DFC_OP(x) (((x) & 0x1FF) << 17) |
||
| 3297 | #define G_008DFC_OP(x) (((x) >> 17) & 0x1FF) |
||
| 3298 | #define C_008DFC_OP 0xFC01FFFF |
||
| 3299 | #define V_008DFC_SQ_V_OPC_OFFSET 0x00 |
||
| 3300 | #define V_008DFC_SQ_V_OP2_OFFSET 0x100 |
||
| 3301 | #define V_008DFC_SQ_V_MAD_LEGACY_F32 0x140 |
||
| 3302 | #define V_008DFC_SQ_V_MAD_F32 0x141 |
||
| 3303 | #define V_008DFC_SQ_V_MAD_I32_I24 0x142 |
||
| 3304 | #define V_008DFC_SQ_V_MAD_U32_U24 0x143 |
||
| 3305 | #define V_008DFC_SQ_V_CUBEID_F32 0x144 |
||
| 3306 | #define V_008DFC_SQ_V_CUBESC_F32 0x145 |
||
| 3307 | #define V_008DFC_SQ_V_CUBETC_F32 0x146 |
||
| 3308 | #define V_008DFC_SQ_V_CUBEMA_F32 0x147 |
||
| 3309 | #define V_008DFC_SQ_V_BFE_U32 0x148 |
||
| 3310 | #define V_008DFC_SQ_V_BFE_I32 0x149 |
||
| 3311 | #define V_008DFC_SQ_V_BFI_B32 0x14A |
||
| 3312 | #define V_008DFC_SQ_V_FMA_F32 0x14B |
||
| 3313 | #define V_008DFC_SQ_V_FMA_F64 0x14C |
||
| 3314 | #define V_008DFC_SQ_V_LERP_U8 0x14D |
||
| 3315 | #define V_008DFC_SQ_V_ALIGNBIT_B32 0x14E |
||
| 3316 | #define V_008DFC_SQ_V_ALIGNBYTE_B32 0x14F |
||
| 3317 | #define V_008DFC_SQ_V_MULLIT_F32 0x150 |
||
| 3318 | #define V_008DFC_SQ_V_MIN3_F32 0x151 |
||
| 3319 | #define V_008DFC_SQ_V_MIN3_I32 0x152 |
||
| 3320 | #define V_008DFC_SQ_V_MIN3_U32 0x153 |
||
| 3321 | #define V_008DFC_SQ_V_MAX3_F32 0x154 |
||
| 3322 | #define V_008DFC_SQ_V_MAX3_I32 0x155 |
||
| 3323 | #define V_008DFC_SQ_V_MAX3_U32 0x156 |
||
| 3324 | #define V_008DFC_SQ_V_MED3_F32 0x157 |
||
| 3325 | #define V_008DFC_SQ_V_MED3_I32 0x158 |
||
| 3326 | #define V_008DFC_SQ_V_MED3_U32 0x159 |
||
| 3327 | #define V_008DFC_SQ_V_SAD_U8 0x15A |
||
| 3328 | #define V_008DFC_SQ_V_SAD_HI_U8 0x15B |
||
| 3329 | #define V_008DFC_SQ_V_SAD_U16 0x15C |
||
| 3330 | #define V_008DFC_SQ_V_SAD_U32 0x15D |
||
| 3331 | #define V_008DFC_SQ_V_CVT_PK_U8_F32 0x15E |
||
| 3332 | #define V_008DFC_SQ_V_DIV_FIXUP_F32 0x15F |
||
| 3333 | #define V_008DFC_SQ_V_DIV_FIXUP_F64 0x160 |
||
| 3334 | #define V_008DFC_SQ_V_LSHL_B64 0x161 |
||
| 3335 | #define V_008DFC_SQ_V_LSHR_B64 0x162 |
||
| 3336 | #define V_008DFC_SQ_V_ASHR_I64 0x163 |
||
| 3337 | #define V_008DFC_SQ_V_ADD_F64 0x164 |
||
| 3338 | #define V_008DFC_SQ_V_MUL_F64 0x165 |
||
| 3339 | #define V_008DFC_SQ_V_MIN_F64 0x166 |
||
| 3340 | #define V_008DFC_SQ_V_MAX_F64 0x167 |
||
| 3341 | #define V_008DFC_SQ_V_LDEXP_F64 0x168 |
||
| 3342 | #define V_008DFC_SQ_V_MUL_LO_U32 0x169 |
||
| 3343 | #define V_008DFC_SQ_V_MUL_HI_U32 0x16A |
||
| 3344 | #define V_008DFC_SQ_V_MUL_LO_I32 0x16B |
||
| 3345 | #define V_008DFC_SQ_V_MUL_HI_I32 0x16C |
||
| 3346 | #define V_008DFC_SQ_V_DIV_SCALE_F32 0x16D |
||
| 3347 | #define V_008DFC_SQ_V_DIV_SCALE_F64 0x16E |
||
| 3348 | #define V_008DFC_SQ_V_DIV_FMAS_F32 0x16F |
||
| 3349 | #define V_008DFC_SQ_V_DIV_FMAS_F64 0x170 |
||
| 3350 | #define V_008DFC_SQ_V_MSAD_U8 0x171 |
||
| 3351 | #define V_008DFC_SQ_V_QSAD_U8 0x172 |
||
| 3352 | #define V_008DFC_SQ_V_MQSAD_U8 0x173 |
||
| 3353 | #define V_008DFC_SQ_V_TRIG_PREOP_F64 0x174 |
||
| 3354 | /* CIK */ |
||
| 3355 | #define V_008DFC_SQ_V_MQSAD_U32_U8 0x175 |
||
| 3356 | #define V_008DFC_SQ_V_MAD_U64_U32 0x176 |
||
| 3357 | #define V_008DFC_SQ_V_MAD_I64_I32 0x177 |
||
| 3358 | /* */ |
||
| 3359 | #define V_008DFC_SQ_V_OP1_OFFSET 0x180 |
||
| 3360 | #define S_008DFC_ENCODING(x) (((x) & 0x3F) << 26) |
||
| 3361 | #define G_008DFC_ENCODING(x) (((x) >> 26) & 0x3F) |
||
| 3362 | #define C_008DFC_ENCODING 0x03FFFFFF |
||
| 3363 | #define V_008DFC_SQ_ENC_VOP3_FIELD 0x34 |
||
| 3364 | #define R_008DFC_SQ_VOP2 0x008DFC |
||
| 3365 | #define S_008DFC_SRC0(x) (((x) & 0x1FF) << 0) |
||
| 3366 | #define G_008DFC_SRC0(x) (((x) >> 0) & 0x1FF) |
||
| 3367 | #define C_008DFC_SRC0 0xFFFFFE00 |
||
| 3368 | #define V_008DFC_SQ_SGPR 0x00 |
||
| 3369 | /* CIK */ |
||
| 3370 | #define V_008DFC_SQ_FLAT_SCRATCH_LO 0x68 |
||
| 3371 | #define V_008DFC_SQ_FLAT_SCRATCH_HI 0x69 |
||
| 3372 | /* */ |
||
| 3373 | #define V_008DFC_SQ_VCC_LO 0x6A |
||
| 3374 | #define V_008DFC_SQ_VCC_HI 0x6B |
||
| 3375 | #define V_008DFC_SQ_TBA_LO 0x6C |
||
| 3376 | #define V_008DFC_SQ_TBA_HI 0x6D |
||
| 3377 | #define V_008DFC_SQ_TMA_LO 0x6E |
||
| 3378 | #define V_008DFC_SQ_TMA_HI 0x6F |
||
| 3379 | #define V_008DFC_SQ_TTMP0 0x70 |
||
| 3380 | #define V_008DFC_SQ_TTMP1 0x71 |
||
| 3381 | #define V_008DFC_SQ_TTMP2 0x72 |
||
| 3382 | #define V_008DFC_SQ_TTMP3 0x73 |
||
| 3383 | #define V_008DFC_SQ_TTMP4 0x74 |
||
| 3384 | #define V_008DFC_SQ_TTMP5 0x75 |
||
| 3385 | #define V_008DFC_SQ_TTMP6 0x76 |
||
| 3386 | #define V_008DFC_SQ_TTMP7 0x77 |
||
| 3387 | #define V_008DFC_SQ_TTMP8 0x78 |
||
| 3388 | #define V_008DFC_SQ_TTMP9 0x79 |
||
| 3389 | #define V_008DFC_SQ_TTMP10 0x7A |
||
| 3390 | #define V_008DFC_SQ_TTMP11 0x7B |
||
| 3391 | #define V_008DFC_SQ_M0 0x7C |
||
| 3392 | #define V_008DFC_SQ_EXEC_LO 0x7E |
||
| 3393 | #define V_008DFC_SQ_EXEC_HI 0x7F |
||
| 3394 | #define V_008DFC_SQ_SRC_0 0x80 |
||
| 3395 | #define V_008DFC_SQ_SRC_1_INT 0x81 |
||
| 3396 | #define V_008DFC_SQ_SRC_2_INT 0x82 |
||
| 3397 | #define V_008DFC_SQ_SRC_3_INT 0x83 |
||
| 3398 | #define V_008DFC_SQ_SRC_4_INT 0x84 |
||
| 3399 | #define V_008DFC_SQ_SRC_5_INT 0x85 |
||
| 3400 | #define V_008DFC_SQ_SRC_6_INT 0x86 |
||
| 3401 | #define V_008DFC_SQ_SRC_7_INT 0x87 |
||
| 3402 | #define V_008DFC_SQ_SRC_8_INT 0x88 |
||
| 3403 | #define V_008DFC_SQ_SRC_9_INT 0x89 |
||
| 3404 | #define V_008DFC_SQ_SRC_10_INT 0x8A |
||
| 3405 | #define V_008DFC_SQ_SRC_11_INT 0x8B |
||
| 3406 | #define V_008DFC_SQ_SRC_12_INT 0x8C |
||
| 3407 | #define V_008DFC_SQ_SRC_13_INT 0x8D |
||
| 3408 | #define V_008DFC_SQ_SRC_14_INT 0x8E |
||
| 3409 | #define V_008DFC_SQ_SRC_15_INT 0x8F |
||
| 3410 | #define V_008DFC_SQ_SRC_16_INT 0x90 |
||
| 3411 | #define V_008DFC_SQ_SRC_17_INT 0x91 |
||
| 3412 | #define V_008DFC_SQ_SRC_18_INT 0x92 |
||
| 3413 | #define V_008DFC_SQ_SRC_19_INT 0x93 |
||
| 3414 | #define V_008DFC_SQ_SRC_20_INT 0x94 |
||
| 3415 | #define V_008DFC_SQ_SRC_21_INT 0x95 |
||
| 3416 | #define V_008DFC_SQ_SRC_22_INT 0x96 |
||
| 3417 | #define V_008DFC_SQ_SRC_23_INT 0x97 |
||
| 3418 | #define V_008DFC_SQ_SRC_24_INT 0x98 |
||
| 3419 | #define V_008DFC_SQ_SRC_25_INT 0x99 |
||
| 3420 | #define V_008DFC_SQ_SRC_26_INT 0x9A |
||
| 3421 | #define V_008DFC_SQ_SRC_27_INT 0x9B |
||
| 3422 | #define V_008DFC_SQ_SRC_28_INT 0x9C |
||
| 3423 | #define V_008DFC_SQ_SRC_29_INT 0x9D |
||
| 3424 | #define V_008DFC_SQ_SRC_30_INT 0x9E |
||
| 3425 | #define V_008DFC_SQ_SRC_31_INT 0x9F |
||
| 3426 | #define V_008DFC_SQ_SRC_32_INT 0xA0 |
||
| 3427 | #define V_008DFC_SQ_SRC_33_INT 0xA1 |
||
| 3428 | #define V_008DFC_SQ_SRC_34_INT 0xA2 |
||
| 3429 | #define V_008DFC_SQ_SRC_35_INT 0xA3 |
||
| 3430 | #define V_008DFC_SQ_SRC_36_INT 0xA4 |
||
| 3431 | #define V_008DFC_SQ_SRC_37_INT 0xA5 |
||
| 3432 | #define V_008DFC_SQ_SRC_38_INT 0xA6 |
||
| 3433 | #define V_008DFC_SQ_SRC_39_INT 0xA7 |
||
| 3434 | #define V_008DFC_SQ_SRC_40_INT 0xA8 |
||
| 3435 | #define V_008DFC_SQ_SRC_41_INT 0xA9 |
||
| 3436 | #define V_008DFC_SQ_SRC_42_INT 0xAA |
||
| 3437 | #define V_008DFC_SQ_SRC_43_INT 0xAB |
||
| 3438 | #define V_008DFC_SQ_SRC_44_INT 0xAC |
||
| 3439 | #define V_008DFC_SQ_SRC_45_INT 0xAD |
||
| 3440 | #define V_008DFC_SQ_SRC_46_INT 0xAE |
||
| 3441 | #define V_008DFC_SQ_SRC_47_INT 0xAF |
||
| 3442 | #define V_008DFC_SQ_SRC_48_INT 0xB0 |
||
| 3443 | #define V_008DFC_SQ_SRC_49_INT 0xB1 |
||
| 3444 | #define V_008DFC_SQ_SRC_50_INT 0xB2 |
||
| 3445 | #define V_008DFC_SQ_SRC_51_INT 0xB3 |
||
| 3446 | #define V_008DFC_SQ_SRC_52_INT 0xB4 |
||
| 3447 | #define V_008DFC_SQ_SRC_53_INT 0xB5 |
||
| 3448 | #define V_008DFC_SQ_SRC_54_INT 0xB6 |
||
| 3449 | #define V_008DFC_SQ_SRC_55_INT 0xB7 |
||
| 3450 | #define V_008DFC_SQ_SRC_56_INT 0xB8 |
||
| 3451 | #define V_008DFC_SQ_SRC_57_INT 0xB9 |
||
| 3452 | #define V_008DFC_SQ_SRC_58_INT 0xBA |
||
| 3453 | #define V_008DFC_SQ_SRC_59_INT 0xBB |
||
| 3454 | #define V_008DFC_SQ_SRC_60_INT 0xBC |
||
| 3455 | #define V_008DFC_SQ_SRC_61_INT 0xBD |
||
| 3456 | #define V_008DFC_SQ_SRC_62_INT 0xBE |
||
| 3457 | #define V_008DFC_SQ_SRC_63_INT 0xBF |
||
| 3458 | #define V_008DFC_SQ_SRC_64_INT 0xC0 |
||
| 3459 | #define V_008DFC_SQ_SRC_M_1_INT 0xC1 |
||
| 3460 | #define V_008DFC_SQ_SRC_M_2_INT 0xC2 |
||
| 3461 | #define V_008DFC_SQ_SRC_M_3_INT 0xC3 |
||
| 3462 | #define V_008DFC_SQ_SRC_M_4_INT 0xC4 |
||
| 3463 | #define V_008DFC_SQ_SRC_M_5_INT 0xC5 |
||
| 3464 | #define V_008DFC_SQ_SRC_M_6_INT 0xC6 |
||
| 3465 | #define V_008DFC_SQ_SRC_M_7_INT 0xC7 |
||
| 3466 | #define V_008DFC_SQ_SRC_M_8_INT 0xC8 |
||
| 3467 | #define V_008DFC_SQ_SRC_M_9_INT 0xC9 |
||
| 3468 | #define V_008DFC_SQ_SRC_M_10_INT 0xCA |
||
| 3469 | #define V_008DFC_SQ_SRC_M_11_INT 0xCB |
||
| 3470 | #define V_008DFC_SQ_SRC_M_12_INT 0xCC |
||
| 3471 | #define V_008DFC_SQ_SRC_M_13_INT 0xCD |
||
| 3472 | #define V_008DFC_SQ_SRC_M_14_INT 0xCE |
||
| 3473 | #define V_008DFC_SQ_SRC_M_15_INT 0xCF |
||
| 3474 | #define V_008DFC_SQ_SRC_M_16_INT 0xD0 |
||
| 3475 | #define V_008DFC_SQ_SRC_0_5 0xF0 |
||
| 3476 | #define V_008DFC_SQ_SRC_M_0_5 0xF1 |
||
| 3477 | #define V_008DFC_SQ_SRC_1 0xF2 |
||
| 3478 | #define V_008DFC_SQ_SRC_M_1 0xF3 |
||
| 3479 | #define V_008DFC_SQ_SRC_2 0xF4 |
||
| 3480 | #define V_008DFC_SQ_SRC_M_2 0xF5 |
||
| 3481 | #define V_008DFC_SQ_SRC_4 0xF6 |
||
| 3482 | #define V_008DFC_SQ_SRC_M_4 0xF7 |
||
| 3483 | #define V_008DFC_SQ_SRC_VCCZ 0xFB |
||
| 3484 | #define V_008DFC_SQ_SRC_EXECZ 0xFC |
||
| 3485 | #define V_008DFC_SQ_SRC_SCC 0xFD |
||
| 3486 | #define V_008DFC_SQ_SRC_LDS_DIRECT 0xFE |
||
| 3487 | #define V_008DFC_SQ_SRC_VGPR 0x100 |
||
| 3488 | #define S_008DFC_VSRC1(x) (((x) & 0xFF) << 9) |
||
| 3489 | #define G_008DFC_VSRC1(x) (((x) >> 9) & 0xFF) |
||
| 3490 | #define C_008DFC_VSRC1 0xFFFE01FF |
||
| 3491 | #define V_008DFC_SQ_VGPR 0x00 |
||
| 3492 | #define S_008DFC_VDST(x) (((x) & 0xFF) << 17) |
||
| 3493 | #define G_008DFC_VDST(x) (((x) >> 17) & 0xFF) |
||
| 3494 | #define C_008DFC_VDST 0xFE01FFFF |
||
| 3495 | #define V_008DFC_SQ_VGPR 0x00 |
||
| 3496 | #define S_008DFC_OP(x) (((x) & 0x3F) << 25) |
||
| 3497 | #define G_008DFC_OP(x) (((x) >> 25) & 0x3F) |
||
| 3498 | #define C_008DFC_OP 0x81FFFFFF |
||
| 3499 | #define V_008DFC_SQ_V_CNDMASK_B32 0x00 |
||
| 3500 | #define V_008DFC_SQ_V_READLANE_B32 0x01 |
||
| 3501 | #define V_008DFC_SQ_V_WRITELANE_B32 0x02 |
||
| 3502 | #define V_008DFC_SQ_V_ADD_F32 0x03 |
||
| 3503 | #define V_008DFC_SQ_V_SUB_F32 0x04 |
||
| 3504 | #define V_008DFC_SQ_V_SUBREV_F32 0x05 |
||
| 3505 | #define V_008DFC_SQ_V_MAC_LEGACY_F32 0x06 |
||
| 3506 | #define V_008DFC_SQ_V_MUL_LEGACY_F32 0x07 |
||
| 3507 | #define V_008DFC_SQ_V_MUL_F32 0x08 |
||
| 3508 | #define V_008DFC_SQ_V_MUL_I32_I24 0x09 |
||
| 3509 | #define V_008DFC_SQ_V_MUL_HI_I32_I24 0x0A |
||
| 3510 | #define V_008DFC_SQ_V_MUL_U32_U24 0x0B |
||
| 3511 | #define V_008DFC_SQ_V_MUL_HI_U32_U24 0x0C |
||
| 3512 | #define V_008DFC_SQ_V_MIN_LEGACY_F32 0x0D |
||
| 3513 | #define V_008DFC_SQ_V_MAX_LEGACY_F32 0x0E |
||
| 3514 | #define V_008DFC_SQ_V_MIN_F32 0x0F |
||
| 3515 | #define V_008DFC_SQ_V_MAX_F32 0x10 |
||
| 3516 | #define V_008DFC_SQ_V_MIN_I32 0x11 |
||
| 3517 | #define V_008DFC_SQ_V_MAX_I32 0x12 |
||
| 3518 | #define V_008DFC_SQ_V_MIN_U32 0x13 |
||
| 3519 | #define V_008DFC_SQ_V_MAX_U32 0x14 |
||
| 3520 | #define V_008DFC_SQ_V_LSHR_B32 0x15 |
||
| 3521 | #define V_008DFC_SQ_V_LSHRREV_B32 0x16 |
||
| 3522 | #define V_008DFC_SQ_V_ASHR_I32 0x17 |
||
| 3523 | #define V_008DFC_SQ_V_ASHRREV_I32 0x18 |
||
| 3524 | #define V_008DFC_SQ_V_LSHL_B32 0x19 |
||
| 3525 | #define V_008DFC_SQ_V_LSHLREV_B32 0x1A |
||
| 3526 | #define V_008DFC_SQ_V_AND_B32 0x1B |
||
| 3527 | #define V_008DFC_SQ_V_OR_B32 0x1C |
||
| 3528 | #define V_008DFC_SQ_V_XOR_B32 0x1D |
||
| 3529 | #define V_008DFC_SQ_V_BFM_B32 0x1E |
||
| 3530 | #define V_008DFC_SQ_V_MAC_F32 0x1F |
||
| 3531 | #define V_008DFC_SQ_V_MADMK_F32 0x20 |
||
| 3532 | #define V_008DFC_SQ_V_MADAK_F32 0x21 |
||
| 3533 | #define V_008DFC_SQ_V_BCNT_U32_B32 0x22 |
||
| 3534 | #define V_008DFC_SQ_V_MBCNT_LO_U32_B32 0x23 |
||
| 3535 | #define V_008DFC_SQ_V_MBCNT_HI_U32_B32 0x24 |
||
| 3536 | #define V_008DFC_SQ_V_ADD_I32 0x25 |
||
| 3537 | #define V_008DFC_SQ_V_SUB_I32 0x26 |
||
| 3538 | #define V_008DFC_SQ_V_SUBREV_I32 0x27 |
||
| 3539 | #define V_008DFC_SQ_V_ADDC_U32 0x28 |
||
| 3540 | #define V_008DFC_SQ_V_SUBB_U32 0x29 |
||
| 3541 | #define V_008DFC_SQ_V_SUBBREV_U32 0x2A |
||
| 3542 | #define V_008DFC_SQ_V_LDEXP_F32 0x2B |
||
| 3543 | #define V_008DFC_SQ_V_CVT_PKACCUM_U8_F32 0x2C |
||
| 3544 | #define V_008DFC_SQ_V_CVT_PKNORM_I16_F32 0x2D |
||
| 3545 | #define V_008DFC_SQ_V_CVT_PKNORM_U16_F32 0x2E |
||
| 3546 | #define V_008DFC_SQ_V_CVT_PKRTZ_F16_F32 0x2F |
||
| 3547 | #define V_008DFC_SQ_V_CVT_PK_U16_U32 0x30 |
||
| 3548 | #define V_008DFC_SQ_V_CVT_PK_I16_I32 0x31 |
||
| 3549 | #define S_008DFC_ENCODING(x) (((x) & 0x1) << 31) |
||
| 3550 | #define G_008DFC_ENCODING(x) (((x) >> 31) & 0x1) |
||
| 3551 | #define C_008DFC_ENCODING 0x7FFFFFFF |
||
| 3552 | #define R_008DFC_SQ_VOP3_0_SDST_ENC 0x008DFC |
||
| 3553 | #define S_008DFC_VDST(x) (((x) & 0xFF) << 0) |
||
| 3554 | #define G_008DFC_VDST(x) (((x) >> 0) & 0xFF) |
||
| 3555 | #define C_008DFC_VDST 0xFFFFFF00 |
||
| 3556 | #define V_008DFC_SQ_VGPR 0x00 |
||
| 3557 | #define S_008DFC_SDST(x) (((x) & 0x7F) << 8) |
||
| 3558 | #define G_008DFC_SDST(x) (((x) >> 8) & 0x7F) |
||
| 3559 | #define C_008DFC_SDST 0xFFFF80FF |
||
| 3560 | #define V_008DFC_SQ_SGPR 0x00 |
||
| 3561 | /* CIK */ |
||
| 3562 | #define V_008DFC_SQ_FLAT_SCRATCH_LO 0x68 |
||
| 3563 | #define V_008DFC_SQ_FLAT_SCRATCH_HI 0x69 |
||
| 3564 | /* */ |
||
| 3565 | #define V_008DFC_SQ_VCC_LO 0x6A |
||
| 3566 | #define V_008DFC_SQ_VCC_HI 0x6B |
||
| 3567 | #define V_008DFC_SQ_TBA_LO 0x6C |
||
| 3568 | #define V_008DFC_SQ_TBA_HI 0x6D |
||
| 3569 | #define V_008DFC_SQ_TMA_LO 0x6E |
||
| 3570 | #define V_008DFC_SQ_TMA_HI 0x6F |
||
| 3571 | #define V_008DFC_SQ_TTMP0 0x70 |
||
| 3572 | #define V_008DFC_SQ_TTMP1 0x71 |
||
| 3573 | #define V_008DFC_SQ_TTMP2 0x72 |
||
| 3574 | #define V_008DFC_SQ_TTMP3 0x73 |
||
| 3575 | #define V_008DFC_SQ_TTMP4 0x74 |
||
| 3576 | #define V_008DFC_SQ_TTMP5 0x75 |
||
| 3577 | #define V_008DFC_SQ_TTMP6 0x76 |
||
| 3578 | #define V_008DFC_SQ_TTMP7 0x77 |
||
| 3579 | #define V_008DFC_SQ_TTMP8 0x78 |
||
| 3580 | #define V_008DFC_SQ_TTMP9 0x79 |
||
| 3581 | #define V_008DFC_SQ_TTMP10 0x7A |
||
| 3582 | #define V_008DFC_SQ_TTMP11 0x7B |
||
| 3583 | #define S_008DFC_OP(x) (((x) & 0x1FF) << 17) |
||
| 3584 | #define G_008DFC_OP(x) (((x) >> 17) & 0x1FF) |
||
| 3585 | #define C_008DFC_OP 0xFC01FFFF |
||
| 3586 | #define V_008DFC_SQ_V_OPC_OFFSET 0x00 |
||
| 3587 | #define V_008DFC_SQ_V_OP2_OFFSET 0x100 |
||
| 3588 | #define V_008DFC_SQ_V_MAD_LEGACY_F32 0x140 |
||
| 3589 | #define V_008DFC_SQ_V_MAD_F32 0x141 |
||
| 3590 | #define V_008DFC_SQ_V_MAD_I32_I24 0x142 |
||
| 3591 | #define V_008DFC_SQ_V_MAD_U32_U24 0x143 |
||
| 3592 | #define V_008DFC_SQ_V_CUBEID_F32 0x144 |
||
| 3593 | #define V_008DFC_SQ_V_CUBESC_F32 0x145 |
||
| 3594 | #define V_008DFC_SQ_V_CUBETC_F32 0x146 |
||
| 3595 | #define V_008DFC_SQ_V_CUBEMA_F32 0x147 |
||
| 3596 | #define V_008DFC_SQ_V_BFE_U32 0x148 |
||
| 3597 | #define V_008DFC_SQ_V_BFE_I32 0x149 |
||
| 3598 | #define V_008DFC_SQ_V_BFI_B32 0x14A |
||
| 3599 | #define V_008DFC_SQ_V_FMA_F32 0x14B |
||
| 3600 | #define V_008DFC_SQ_V_FMA_F64 0x14C |
||
| 3601 | #define V_008DFC_SQ_V_LERP_U8 0x14D |
||
| 3602 | #define V_008DFC_SQ_V_ALIGNBIT_B32 0x14E |
||
| 3603 | #define V_008DFC_SQ_V_ALIGNBYTE_B32 0x14F |
||
| 3604 | #define V_008DFC_SQ_V_MULLIT_F32 0x150 |
||
| 3605 | #define V_008DFC_SQ_V_MIN3_F32 0x151 |
||
| 3606 | #define V_008DFC_SQ_V_MIN3_I32 0x152 |
||
| 3607 | #define V_008DFC_SQ_V_MIN3_U32 0x153 |
||
| 3608 | #define V_008DFC_SQ_V_MAX3_F32 0x154 |
||
| 3609 | #define V_008DFC_SQ_V_MAX3_I32 0x155 |
||
| 3610 | #define V_008DFC_SQ_V_MAX3_U32 0x156 |
||
| 3611 | #define V_008DFC_SQ_V_MED3_F32 0x157 |
||
| 3612 | #define V_008DFC_SQ_V_MED3_I32 0x158 |
||
| 3613 | #define V_008DFC_SQ_V_MED3_U32 0x159 |
||
| 3614 | #define V_008DFC_SQ_V_SAD_U8 0x15A |
||
| 3615 | #define V_008DFC_SQ_V_SAD_HI_U8 0x15B |
||
| 3616 | #define V_008DFC_SQ_V_SAD_U16 0x15C |
||
| 3617 | #define V_008DFC_SQ_V_SAD_U32 0x15D |
||
| 3618 | #define V_008DFC_SQ_V_CVT_PK_U8_F32 0x15E |
||
| 3619 | #define V_008DFC_SQ_V_DIV_FIXUP_F32 0x15F |
||
| 3620 | #define V_008DFC_SQ_V_DIV_FIXUP_F64 0x160 |
||
| 3621 | #define V_008DFC_SQ_V_LSHL_B64 0x161 |
||
| 3622 | #define V_008DFC_SQ_V_LSHR_B64 0x162 |
||
| 3623 | #define V_008DFC_SQ_V_ASHR_I64 0x163 |
||
| 3624 | #define V_008DFC_SQ_V_ADD_F64 0x164 |
||
| 3625 | #define V_008DFC_SQ_V_MUL_F64 0x165 |
||
| 3626 | #define V_008DFC_SQ_V_MIN_F64 0x166 |
||
| 3627 | #define V_008DFC_SQ_V_MAX_F64 0x167 |
||
| 3628 | #define V_008DFC_SQ_V_LDEXP_F64 0x168 |
||
| 3629 | #define V_008DFC_SQ_V_MUL_LO_U32 0x169 |
||
| 3630 | #define V_008DFC_SQ_V_MUL_HI_U32 0x16A |
||
| 3631 | #define V_008DFC_SQ_V_MUL_LO_I32 0x16B |
||
| 3632 | #define V_008DFC_SQ_V_MUL_HI_I32 0x16C |
||
| 3633 | #define V_008DFC_SQ_V_DIV_SCALE_F32 0x16D |
||
| 3634 | #define V_008DFC_SQ_V_DIV_SCALE_F64 0x16E |
||
| 3635 | #define V_008DFC_SQ_V_DIV_FMAS_F32 0x16F |
||
| 3636 | #define V_008DFC_SQ_V_DIV_FMAS_F64 0x170 |
||
| 3637 | #define V_008DFC_SQ_V_MSAD_U8 0x171 |
||
| 3638 | #define V_008DFC_SQ_V_QSAD_U8 0x172 |
||
| 3639 | #define V_008DFC_SQ_V_MQSAD_U8 0x173 |
||
| 3640 | #define V_008DFC_SQ_V_TRIG_PREOP_F64 0x174 |
||
| 3641 | /* CIK */ |
||
| 3642 | #define V_008DFC_SQ_V_MQSAD_U32_U8 0x175 |
||
| 3643 | #define V_008DFC_SQ_V_MAD_U64_U32 0x176 |
||
| 3644 | #define V_008DFC_SQ_V_MAD_I64_I32 0x177 |
||
| 3645 | /* */ |
||
| 3646 | #define V_008DFC_SQ_V_OP1_OFFSET 0x180 |
||
| 3647 | #define S_008DFC_ENCODING(x) (((x) & 0x3F) << 26) |
||
| 3648 | #define G_008DFC_ENCODING(x) (((x) >> 26) & 0x3F) |
||
| 3649 | #define C_008DFC_ENCODING 0x03FFFFFF |
||
| 3650 | #define V_008DFC_SQ_ENC_VOP3_FIELD 0x34 |
||
| 3651 | #define R_008DFC_SQ_MUBUF_0 0x008DFC |
||
| 3652 | #define S_008DFC_OFFSET(x) (((x) & 0xFFF) << 0) |
||
| 3653 | #define G_008DFC_OFFSET(x) (((x) >> 0) & 0xFFF) |
||
| 3654 | #define C_008DFC_OFFSET 0xFFFFF000 |
||
| 3655 | #define S_008DFC_OFFEN(x) (((x) & 0x1) << 12) |
||
| 3656 | #define G_008DFC_OFFEN(x) (((x) >> 12) & 0x1) |
||
| 3657 | #define C_008DFC_OFFEN 0xFFFFEFFF |
||
| 3658 | #define S_008DFC_IDXEN(x) (((x) & 0x1) << 13) |
||
| 3659 | #define G_008DFC_IDXEN(x) (((x) >> 13) & 0x1) |
||
| 3660 | #define C_008DFC_IDXEN 0xFFFFDFFF |
||
| 3661 | #define S_008DFC_GLC(x) (((x) & 0x1) << 14) |
||
| 3662 | #define G_008DFC_GLC(x) (((x) >> 14) & 0x1) |
||
| 3663 | #define C_008DFC_GLC 0xFFFFBFFF |
||
| 3664 | #define S_008DFC_ADDR64(x) (((x) & 0x1) << 15) |
||
| 3665 | #define G_008DFC_ADDR64(x) (((x) >> 15) & 0x1) |
||
| 3666 | #define C_008DFC_ADDR64 0xFFFF7FFF |
||
| 3667 | #define S_008DFC_LDS(x) (((x) & 0x1) << 16) |
||
| 3668 | #define G_008DFC_LDS(x) (((x) >> 16) & 0x1) |
||
| 3669 | #define C_008DFC_LDS 0xFFFEFFFF |
||
| 3670 | #define S_008DFC_OP(x) (((x) & 0x7F) << 18) |
||
| 3671 | #define G_008DFC_OP(x) (((x) >> 18) & 0x7F) |
||
| 3672 | #define C_008DFC_OP 0xFE03FFFF |
||
| 3673 | #define V_008DFC_SQ_BUFFER_LOAD_FORMAT_X 0x00 |
||
| 3674 | #define V_008DFC_SQ_BUFFER_LOAD_FORMAT_XY 0x01 |
||
| 3675 | #define V_008DFC_SQ_BUFFER_LOAD_FORMAT_XYZ 0x02 |
||
| 3676 | #define V_008DFC_SQ_BUFFER_LOAD_FORMAT_XYZW 0x03 |
||
| 3677 | #define V_008DFC_SQ_BUFFER_STORE_FORMAT_X 0x04 |
||
| 3678 | #define V_008DFC_SQ_BUFFER_STORE_FORMAT_XY 0x05 |
||
| 3679 | #define V_008DFC_SQ_BUFFER_STORE_FORMAT_XYZ 0x06 |
||
| 3680 | #define V_008DFC_SQ_BUFFER_STORE_FORMAT_XYZW 0x07 |
||
| 3681 | #define V_008DFC_SQ_BUFFER_LOAD_UBYTE 0x08 |
||
| 3682 | #define V_008DFC_SQ_BUFFER_LOAD_SBYTE 0x09 |
||
| 3683 | #define V_008DFC_SQ_BUFFER_LOAD_USHORT 0x0A |
||
| 3684 | #define V_008DFC_SQ_BUFFER_LOAD_SSHORT 0x0B |
||
| 3685 | #define V_008DFC_SQ_BUFFER_LOAD_DWORD 0x0C |
||
| 3686 | #define V_008DFC_SQ_BUFFER_LOAD_DWORDX2 0x0D |
||
| 3687 | #define V_008DFC_SQ_BUFFER_LOAD_DWORDX4 0x0E |
||
| 3688 | /* CIK */ |
||
| 3689 | #define V_008DFC_SQ_BUFFER_LOAD_DWORDX3 0x0F |
||
| 3690 | /* */ |
||
| 3691 | #define V_008DFC_SQ_BUFFER_STORE_BYTE 0x18 |
||
| 3692 | #define V_008DFC_SQ_BUFFER_STORE_SHORT 0x1A |
||
| 3693 | #define V_008DFC_SQ_BUFFER_STORE_DWORD 0x1C |
||
| 3694 | #define V_008DFC_SQ_BUFFER_STORE_DWORDX2 0x1D |
||
| 3695 | #define V_008DFC_SQ_BUFFER_STORE_DWORDX4 0x1E |
||
| 3696 | /* CIK */ |
||
| 3697 | #define V_008DFC_SQ_BUFFER_STORE_DWORDX3 0x1F |
||
| 3698 | /* */ |
||
| 3699 | #define V_008DFC_SQ_BUFFER_ATOMIC_SWAP 0x30 |
||
| 3700 | #define V_008DFC_SQ_BUFFER_ATOMIC_CMPSWAP 0x31 |
||
| 3701 | #define V_008DFC_SQ_BUFFER_ATOMIC_ADD 0x32 |
||
| 3702 | #define V_008DFC_SQ_BUFFER_ATOMIC_SUB 0x33 |
||
| 3703 | #define V_008DFC_SQ_BUFFER_ATOMIC_RSUB 0x34 /* not on CIK */ |
||
| 3704 | #define V_008DFC_SQ_BUFFER_ATOMIC_SMIN 0x35 |
||
| 3705 | #define V_008DFC_SQ_BUFFER_ATOMIC_UMIN 0x36 |
||
| 3706 | #define V_008DFC_SQ_BUFFER_ATOMIC_SMAX 0x37 |
||
| 3707 | #define V_008DFC_SQ_BUFFER_ATOMIC_UMAX 0x38 |
||
| 3708 | #define V_008DFC_SQ_BUFFER_ATOMIC_AND 0x39 |
||
| 3709 | #define V_008DFC_SQ_BUFFER_ATOMIC_OR 0x3A |
||
| 3710 | #define V_008DFC_SQ_BUFFER_ATOMIC_XOR 0x3B |
||
| 3711 | #define V_008DFC_SQ_BUFFER_ATOMIC_INC 0x3C |
||
| 3712 | #define V_008DFC_SQ_BUFFER_ATOMIC_DEC 0x3D |
||
| 3713 | #define V_008DFC_SQ_BUFFER_ATOMIC_FCMPSWAP 0x3E |
||
| 3714 | #define V_008DFC_SQ_BUFFER_ATOMIC_FMIN 0x3F |
||
| 3715 | #define V_008DFC_SQ_BUFFER_ATOMIC_FMAX 0x40 |
||
| 3716 | #define V_008DFC_SQ_BUFFER_ATOMIC_SWAP_X2 0x50 |
||
| 3717 | #define V_008DFC_SQ_BUFFER_ATOMIC_CMPSWAP_X2 0x51 |
||
| 3718 | #define V_008DFC_SQ_BUFFER_ATOMIC_ADD_X2 0x52 |
||
| 3719 | #define V_008DFC_SQ_BUFFER_ATOMIC_SUB_X2 0x53 |
||
| 3720 | #define V_008DFC_SQ_BUFFER_ATOMIC_RSUB_X2 0x54 /* not on CIK */ |
||
| 3721 | #define V_008DFC_SQ_BUFFER_ATOMIC_SMIN_X2 0x55 |
||
| 3722 | #define V_008DFC_SQ_BUFFER_ATOMIC_UMIN_X2 0x56 |
||
| 3723 | #define V_008DFC_SQ_BUFFER_ATOMIC_SMAX_X2 0x57 |
||
| 3724 | #define V_008DFC_SQ_BUFFER_ATOMIC_UMAX_X2 0x58 |
||
| 3725 | #define V_008DFC_SQ_BUFFER_ATOMIC_AND_X2 0x59 |
||
| 3726 | #define V_008DFC_SQ_BUFFER_ATOMIC_OR_X2 0x5A |
||
| 3727 | #define V_008DFC_SQ_BUFFER_ATOMIC_XOR_X2 0x5B |
||
| 3728 | #define V_008DFC_SQ_BUFFER_ATOMIC_INC_X2 0x5C |
||
| 3729 | #define V_008DFC_SQ_BUFFER_ATOMIC_DEC_X2 0x5D |
||
| 3730 | #define V_008DFC_SQ_BUFFER_ATOMIC_FCMPSWAP_X2 0x5E |
||
| 3731 | #define V_008DFC_SQ_BUFFER_ATOMIC_FMIN_X2 0x5F |
||
| 3732 | #define V_008DFC_SQ_BUFFER_ATOMIC_FMAX_X2 0x60 |
||
| 3733 | #define V_008DFC_SQ_BUFFER_WBINVL1_SC 0x70 |
||
| 3734 | /* CIK */ |
||
| 3735 | #define V_008DFC_SQ_BUFFER_WBINVL1_VOL 0x70 |
||
| 3736 | /* */ |
||
| 3737 | #define V_008DFC_SQ_BUFFER_WBINVL1 0x71 |
||
| 3738 | #define S_008DFC_ENCODING(x) (((x) & 0x3F) << 26) |
||
| 3739 | #define G_008DFC_ENCODING(x) (((x) >> 26) & 0x3F) |
||
| 3740 | #define C_008DFC_ENCODING 0x03FFFFFF |
||
| 3741 | #define V_008DFC_SQ_ENC_MUBUF_FIELD 0x38 |
||
| 3742 | #endif |
||
| 3743 | #define R_008F00_SQ_BUF_RSRC_WORD0 0x008F00 |
||
| 3744 | #define R_008F04_SQ_BUF_RSRC_WORD1 0x008F04 |
||
| 3745 | #define S_008F04_BASE_ADDRESS_HI(x) (((x) & 0xFFFF) << 0) |
||
| 3746 | #define G_008F04_BASE_ADDRESS_HI(x) (((x) >> 0) & 0xFFFF) |
||
| 3747 | #define C_008F04_BASE_ADDRESS_HI 0xFFFF0000 |
||
| 3748 | #define S_008F04_STRIDE(x) (((x) & 0x3FFF) << 16) |
||
| 3749 | #define G_008F04_STRIDE(x) (((x) >> 16) & 0x3FFF) |
||
| 3750 | #define C_008F04_STRIDE 0xC000FFFF |
||
| 3751 | #define S_008F04_CACHE_SWIZZLE(x) (((x) & 0x1) << 30) |
||
| 3752 | #define G_008F04_CACHE_SWIZZLE(x) (((x) >> 30) & 0x1) |
||
| 3753 | #define C_008F04_CACHE_SWIZZLE 0xBFFFFFFF |
||
| 3754 | #define S_008F04_SWIZZLE_ENABLE(x) (((x) & 0x1) << 31) |
||
| 3755 | #define G_008F04_SWIZZLE_ENABLE(x) (((x) >> 31) & 0x1) |
||
| 3756 | #define C_008F04_SWIZZLE_ENABLE 0x7FFFFFFF |
||
| 3757 | #define R_008F08_SQ_BUF_RSRC_WORD2 0x008F08 |
||
| 3758 | #define R_008F0C_SQ_BUF_RSRC_WORD3 0x008F0C |
||
| 3759 | #define S_008F0C_DST_SEL_X(x) (((x) & 0x07) << 0) |
||
| 3760 | #define G_008F0C_DST_SEL_X(x) (((x) >> 0) & 0x07) |
||
| 3761 | #define C_008F0C_DST_SEL_X 0xFFFFFFF8 |
||
| 3762 | #define V_008F0C_SQ_SEL_0 0x00 |
||
| 3763 | #define V_008F0C_SQ_SEL_1 0x01 |
||
| 3764 | #define V_008F0C_SQ_SEL_RESERVED_0 0x02 |
||
| 3765 | #define V_008F0C_SQ_SEL_RESERVED_1 0x03 |
||
| 3766 | #define V_008F0C_SQ_SEL_X 0x04 |
||
| 3767 | #define V_008F0C_SQ_SEL_Y 0x05 |
||
| 3768 | #define V_008F0C_SQ_SEL_Z 0x06 |
||
| 3769 | #define V_008F0C_SQ_SEL_W 0x07 |
||
| 3770 | #define S_008F0C_DST_SEL_Y(x) (((x) & 0x07) << 3) |
||
| 3771 | #define G_008F0C_DST_SEL_Y(x) (((x) >> 3) & 0x07) |
||
| 3772 | #define C_008F0C_DST_SEL_Y 0xFFFFFFC7 |
||
| 3773 | #define V_008F0C_SQ_SEL_0 0x00 |
||
| 3774 | #define V_008F0C_SQ_SEL_1 0x01 |
||
| 3775 | #define V_008F0C_SQ_SEL_RESERVED_0 0x02 |
||
| 3776 | #define V_008F0C_SQ_SEL_RESERVED_1 0x03 |
||
| 3777 | #define V_008F0C_SQ_SEL_X 0x04 |
||
| 3778 | #define V_008F0C_SQ_SEL_Y 0x05 |
||
| 3779 | #define V_008F0C_SQ_SEL_Z 0x06 |
||
| 3780 | #define V_008F0C_SQ_SEL_W 0x07 |
||
| 3781 | #define S_008F0C_DST_SEL_Z(x) (((x) & 0x07) << 6) |
||
| 3782 | #define G_008F0C_DST_SEL_Z(x) (((x) >> 6) & 0x07) |
||
| 3783 | #define C_008F0C_DST_SEL_Z 0xFFFFFE3F |
||
| 3784 | #define V_008F0C_SQ_SEL_0 0x00 |
||
| 3785 | #define V_008F0C_SQ_SEL_1 0x01 |
||
| 3786 | #define V_008F0C_SQ_SEL_RESERVED_0 0x02 |
||
| 3787 | #define V_008F0C_SQ_SEL_RESERVED_1 0x03 |
||
| 3788 | #define V_008F0C_SQ_SEL_X 0x04 |
||
| 3789 | #define V_008F0C_SQ_SEL_Y 0x05 |
||
| 3790 | #define V_008F0C_SQ_SEL_Z 0x06 |
||
| 3791 | #define V_008F0C_SQ_SEL_W 0x07 |
||
| 3792 | #define S_008F0C_DST_SEL_W(x) (((x) & 0x07) << 9) |
||
| 3793 | #define G_008F0C_DST_SEL_W(x) (((x) >> 9) & 0x07) |
||
| 3794 | #define C_008F0C_DST_SEL_W 0xFFFFF1FF |
||
| 3795 | #define V_008F0C_SQ_SEL_0 0x00 |
||
| 3796 | #define V_008F0C_SQ_SEL_1 0x01 |
||
| 3797 | #define V_008F0C_SQ_SEL_RESERVED_0 0x02 |
||
| 3798 | #define V_008F0C_SQ_SEL_RESERVED_1 0x03 |
||
| 3799 | #define V_008F0C_SQ_SEL_X 0x04 |
||
| 3800 | #define V_008F0C_SQ_SEL_Y 0x05 |
||
| 3801 | #define V_008F0C_SQ_SEL_Z 0x06 |
||
| 3802 | #define V_008F0C_SQ_SEL_W 0x07 |
||
| 3803 | #define S_008F0C_NUM_FORMAT(x) (((x) & 0x07) << 12) |
||
| 3804 | #define G_008F0C_NUM_FORMAT(x) (((x) >> 12) & 0x07) |
||
| 3805 | #define C_008F0C_NUM_FORMAT 0xFFFF8FFF |
||
| 3806 | #define V_008F0C_BUF_NUM_FORMAT_UNORM 0x00 |
||
| 3807 | #define V_008F0C_BUF_NUM_FORMAT_SNORM 0x01 |
||
| 3808 | #define V_008F0C_BUF_NUM_FORMAT_USCALED 0x02 |
||
| 3809 | #define V_008F0C_BUF_NUM_FORMAT_SSCALED 0x03 |
||
| 3810 | #define V_008F0C_BUF_NUM_FORMAT_UINT 0x04 |
||
| 3811 | #define V_008F0C_BUF_NUM_FORMAT_SINT 0x05 |
||
| 3812 | #define V_008F0C_BUF_NUM_FORMAT_SNORM_OGL 0x06 |
||
| 3813 | #define V_008F0C_BUF_NUM_FORMAT_FLOAT 0x07 |
||
| 3814 | #define S_008F0C_DATA_FORMAT(x) (((x) & 0x0F) << 15) |
||
| 3815 | #define G_008F0C_DATA_FORMAT(x) (((x) >> 15) & 0x0F) |
||
| 3816 | #define C_008F0C_DATA_FORMAT 0xFFF87FFF |
||
| 3817 | #define V_008F0C_BUF_DATA_FORMAT_INVALID 0x00 |
||
| 3818 | #define V_008F0C_BUF_DATA_FORMAT_8 0x01 |
||
| 3819 | #define V_008F0C_BUF_DATA_FORMAT_16 0x02 |
||
| 3820 | #define V_008F0C_BUF_DATA_FORMAT_8_8 0x03 |
||
| 3821 | #define V_008F0C_BUF_DATA_FORMAT_32 0x04 |
||
| 3822 | #define V_008F0C_BUF_DATA_FORMAT_16_16 0x05 |
||
| 3823 | #define V_008F0C_BUF_DATA_FORMAT_10_11_11 0x06 |
||
| 3824 | #define V_008F0C_BUF_DATA_FORMAT_11_11_10 0x07 |
||
| 3825 | #define V_008F0C_BUF_DATA_FORMAT_10_10_10_2 0x08 |
||
| 3826 | #define V_008F0C_BUF_DATA_FORMAT_2_10_10_10 0x09 |
||
| 3827 | #define V_008F0C_BUF_DATA_FORMAT_8_8_8_8 0x0A |
||
| 3828 | #define V_008F0C_BUF_DATA_FORMAT_32_32 0x0B |
||
| 3829 | #define V_008F0C_BUF_DATA_FORMAT_16_16_16_16 0x0C |
||
| 3830 | #define V_008F0C_BUF_DATA_FORMAT_32_32_32 0x0D |
||
| 3831 | #define V_008F0C_BUF_DATA_FORMAT_32_32_32_32 0x0E |
||
| 3832 | #define V_008F0C_BUF_DATA_FORMAT_RESERVED_15 0x0F |
||
| 3833 | #define S_008F0C_ELEMENT_SIZE(x) (((x) & 0x03) << 19) |
||
| 3834 | #define G_008F0C_ELEMENT_SIZE(x) (((x) >> 19) & 0x03) |
||
| 3835 | #define C_008F0C_ELEMENT_SIZE 0xFFE7FFFF |
||
| 3836 | #define S_008F0C_INDEX_STRIDE(x) (((x) & 0x03) << 21) |
||
| 3837 | #define G_008F0C_INDEX_STRIDE(x) (((x) >> 21) & 0x03) |
||
| 3838 | #define C_008F0C_INDEX_STRIDE 0xFF9FFFFF |
||
| 3839 | #define S_008F0C_ADD_TID_ENABLE(x) (((x) & 0x1) << 23) |
||
| 3840 | #define G_008F0C_ADD_TID_ENABLE(x) (((x) >> 23) & 0x1) |
||
| 3841 | #define C_008F0C_ADD_TID_ENABLE 0xFF7FFFFF |
||
| 3842 | /* CIK */ |
||
| 3843 | #define S_008F0C_ATC(x) (((x) & 0x1) << 24) |
||
| 3844 | #define G_008F0C_ATC(x) (((x) >> 24) & 0x1) |
||
| 3845 | #define C_008F0C_ATC 0xFEFFFFFF |
||
| 3846 | /* */ |
||
| 3847 | #define S_008F0C_HASH_ENABLE(x) (((x) & 0x1) << 25) |
||
| 3848 | #define G_008F0C_HASH_ENABLE(x) (((x) >> 25) & 0x1) |
||
| 3849 | #define C_008F0C_HASH_ENABLE 0xFDFFFFFF |
||
| 3850 | #define S_008F0C_HEAP(x) (((x) & 0x1) << 26) |
||
| 3851 | #define G_008F0C_HEAP(x) (((x) >> 26) & 0x1) |
||
| 3852 | #define C_008F0C_HEAP 0xFBFFFFFF |
||
| 3853 | /* CIK */ |
||
| 3854 | #define S_008F0C_MTYPE(x) (((x) & 0x07) << 27) |
||
| 3855 | #define G_008F0C_MTYPE(x) (((x) >> 27) & 0x07) |
||
| 3856 | #define C_008F0C_MTYPE 0xC7FFFFFF |
||
| 3857 | /* */ |
||
| 3858 | #define S_008F0C_TYPE(x) (((x) & 0x03) << 30) |
||
| 3859 | #define G_008F0C_TYPE(x) (((x) >> 30) & 0x03) |
||
| 3860 | #define C_008F0C_TYPE 0x3FFFFFFF |
||
| 3861 | #define V_008F0C_SQ_RSRC_BUF 0x00 |
||
| 3862 | #define V_008F0C_SQ_RSRC_BUF_RSVD_1 0x01 |
||
| 3863 | #define V_008F0C_SQ_RSRC_BUF_RSVD_2 0x02 |
||
| 3864 | #define V_008F0C_SQ_RSRC_BUF_RSVD_3 0x03 |
||
| 3865 | #define R_008F10_SQ_IMG_RSRC_WORD0 0x008F10 |
||
| 3866 | #define R_008F14_SQ_IMG_RSRC_WORD1 0x008F14 |
||
| 3867 | #define S_008F14_BASE_ADDRESS_HI(x) (((x) & 0xFF) << 0) |
||
| 3868 | #define G_008F14_BASE_ADDRESS_HI(x) (((x) >> 0) & 0xFF) |
||
| 3869 | #define C_008F14_BASE_ADDRESS_HI 0xFFFFFF00 |
||
| 3870 | #define S_008F14_MIN_LOD(x) (((x) & 0xFFF) << 8) |
||
| 3871 | #define G_008F14_MIN_LOD(x) (((x) >> 8) & 0xFFF) |
||
| 3872 | #define C_008F14_MIN_LOD 0xFFF000FF |
||
| 3873 | #define S_008F14_DATA_FORMAT(x) (((x) & 0x3F) << 20) |
||
| 3874 | #define G_008F14_DATA_FORMAT(x) (((x) >> 20) & 0x3F) |
||
| 3875 | #define C_008F14_DATA_FORMAT 0xFC0FFFFF |
||
| 3876 | #define V_008F14_IMG_DATA_FORMAT_INVALID 0x00 |
||
| 3877 | #define V_008F14_IMG_DATA_FORMAT_8 0x01 |
||
| 3878 | #define V_008F14_IMG_DATA_FORMAT_16 0x02 |
||
| 3879 | #define V_008F14_IMG_DATA_FORMAT_8_8 0x03 |
||
| 3880 | #define V_008F14_IMG_DATA_FORMAT_32 0x04 |
||
| 3881 | #define V_008F14_IMG_DATA_FORMAT_16_16 0x05 |
||
| 3882 | #define V_008F14_IMG_DATA_FORMAT_10_11_11 0x06 |
||
| 3883 | #define V_008F14_IMG_DATA_FORMAT_11_11_10 0x07 |
||
| 3884 | #define V_008F14_IMG_DATA_FORMAT_10_10_10_2 0x08 |
||
| 3885 | #define V_008F14_IMG_DATA_FORMAT_2_10_10_10 0x09 |
||
| 3886 | #define V_008F14_IMG_DATA_FORMAT_8_8_8_8 0x0A |
||
| 3887 | #define V_008F14_IMG_DATA_FORMAT_32_32 0x0B |
||
| 3888 | #define V_008F14_IMG_DATA_FORMAT_16_16_16_16 0x0C |
||
| 3889 | #define V_008F14_IMG_DATA_FORMAT_32_32_32 0x0D |
||
| 3890 | #define V_008F14_IMG_DATA_FORMAT_32_32_32_32 0x0E |
||
| 3891 | #define V_008F14_IMG_DATA_FORMAT_RESERVED_15 0x0F |
||
| 3892 | #define V_008F14_IMG_DATA_FORMAT_5_6_5 0x10 |
||
| 3893 | #define V_008F14_IMG_DATA_FORMAT_1_5_5_5 0x11 |
||
| 3894 | #define V_008F14_IMG_DATA_FORMAT_5_5_5_1 0x12 |
||
| 3895 | #define V_008F14_IMG_DATA_FORMAT_4_4_4_4 0x13 |
||
| 3896 | #define V_008F14_IMG_DATA_FORMAT_8_24 0x14 |
||
| 3897 | #define V_008F14_IMG_DATA_FORMAT_24_8 0x15 |
||
| 3898 | #define V_008F14_IMG_DATA_FORMAT_X24_8_32 0x16 |
||
| 3899 | #define V_008F14_IMG_DATA_FORMAT_RESERVED_23 0x17 |
||
| 3900 | #define V_008F14_IMG_DATA_FORMAT_RESERVED_24 0x18 |
||
| 3901 | #define V_008F14_IMG_DATA_FORMAT_RESERVED_25 0x19 |
||
| 3902 | #define V_008F14_IMG_DATA_FORMAT_RESERVED_26 0x1A |
||
| 3903 | #define V_008F14_IMG_DATA_FORMAT_RESERVED_27 0x1B |
||
| 3904 | #define V_008F14_IMG_DATA_FORMAT_RESERVED_28 0x1C |
||
| 3905 | #define V_008F14_IMG_DATA_FORMAT_RESERVED_29 0x1D |
||
| 3906 | #define V_008F14_IMG_DATA_FORMAT_RESERVED_30 0x1E |
||
| 3907 | #define V_008F14_IMG_DATA_FORMAT_RESERVED_31 0x1F |
||
| 3908 | #define V_008F14_IMG_DATA_FORMAT_GB_GR 0x20 |
||
| 3909 | #define V_008F14_IMG_DATA_FORMAT_BG_RG 0x21 |
||
| 3910 | #define V_008F14_IMG_DATA_FORMAT_5_9_9_9 0x22 |
||
| 3911 | #define V_008F14_IMG_DATA_FORMAT_BC1 0x23 |
||
| 3912 | #define V_008F14_IMG_DATA_FORMAT_BC2 0x24 |
||
| 3913 | #define V_008F14_IMG_DATA_FORMAT_BC3 0x25 |
||
| 3914 | #define V_008F14_IMG_DATA_FORMAT_BC4 0x26 |
||
| 3915 | #define V_008F14_IMG_DATA_FORMAT_BC5 0x27 |
||
| 3916 | #define V_008F14_IMG_DATA_FORMAT_BC6 0x28 |
||
| 3917 | #define V_008F14_IMG_DATA_FORMAT_BC7 0x29 |
||
| 3918 | #define V_008F14_IMG_DATA_FORMAT_RESERVED_42 0x2A |
||
| 3919 | #define V_008F14_IMG_DATA_FORMAT_RESERVED_43 0x2B |
||
| 3920 | #define V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F1 0x2C |
||
| 3921 | #define V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F1 0x2D |
||
| 3922 | #define V_008F14_IMG_DATA_FORMAT_FMASK8_S8_F1 0x2E |
||
| 3923 | #define V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2 0x2F |
||
| 3924 | #define V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F2 0x30 |
||
| 3925 | #define V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4 0x31 |
||
| 3926 | #define V_008F14_IMG_DATA_FORMAT_FMASK16_S16_F1 0x32 |
||
| 3927 | #define V_008F14_IMG_DATA_FORMAT_FMASK16_S8_F2 0x33 |
||
| 3928 | #define V_008F14_IMG_DATA_FORMAT_FMASK32_S16_F2 0x34 |
||
| 3929 | #define V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F4 0x35 |
||
| 3930 | #define V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8 0x36 |
||
| 3931 | #define V_008F14_IMG_DATA_FORMAT_FMASK64_S16_F4 0x37 |
||
| 3932 | #define V_008F14_IMG_DATA_FORMAT_FMASK64_S16_F8 0x38 |
||
| 3933 | #define V_008F14_IMG_DATA_FORMAT_4_4 0x39 |
||
| 3934 | #define V_008F14_IMG_DATA_FORMAT_6_5_5 0x3A |
||
| 3935 | #define V_008F14_IMG_DATA_FORMAT_1 0x3B |
||
| 3936 | #define V_008F14_IMG_DATA_FORMAT_1_REVERSED 0x3C |
||
| 3937 | #define V_008F14_IMG_DATA_FORMAT_32_AS_8 0x3D |
||
| 3938 | #define V_008F14_IMG_DATA_FORMAT_32_AS_8_8 0x3E |
||
| 3939 | #define V_008F14_IMG_DATA_FORMAT_32_AS_32_32_32_32 0x3F |
||
| 3940 | #define S_008F14_NUM_FORMAT(x) (((x) & 0x0F) << 26) |
||
| 3941 | #define G_008F14_NUM_FORMAT(x) (((x) >> 26) & 0x0F) |
||
| 3942 | #define C_008F14_NUM_FORMAT 0xC3FFFFFF |
||
| 3943 | #define V_008F14_IMG_NUM_FORMAT_UNORM 0x00 |
||
| 3944 | #define V_008F14_IMG_NUM_FORMAT_SNORM 0x01 |
||
| 3945 | #define V_008F14_IMG_NUM_FORMAT_USCALED 0x02 |
||
| 3946 | #define V_008F14_IMG_NUM_FORMAT_SSCALED 0x03 |
||
| 3947 | #define V_008F14_IMG_NUM_FORMAT_UINT 0x04 |
||
| 3948 | #define V_008F14_IMG_NUM_FORMAT_SINT 0x05 |
||
| 3949 | #define V_008F14_IMG_NUM_FORMAT_SNORM_OGL 0x06 |
||
| 3950 | #define V_008F14_IMG_NUM_FORMAT_FLOAT 0x07 |
||
| 3951 | #define V_008F14_IMG_NUM_FORMAT_RESERVED_8 0x08 |
||
| 3952 | #define V_008F14_IMG_NUM_FORMAT_SRGB 0x09 |
||
| 3953 | #define V_008F14_IMG_NUM_FORMAT_UBNORM 0x0A |
||
| 3954 | #define V_008F14_IMG_NUM_FORMAT_UBNORM_OGL 0x0B |
||
| 3955 | #define V_008F14_IMG_NUM_FORMAT_UBINT 0x0C |
||
| 3956 | #define V_008F14_IMG_NUM_FORMAT_UBSCALED 0x0D |
||
| 3957 | #define V_008F14_IMG_NUM_FORMAT_RESERVED_14 0x0E |
||
| 3958 | #define V_008F14_IMG_NUM_FORMAT_RESERVED_15 0x0F |
||
| 3959 | /* CIK */ |
||
| 3960 | #define S_008F14_MTYPE(x) (((x) & 0x03) << 30) |
||
| 3961 | #define G_008F14_MTYPE(x) (((x) >> 30) & 0x03) |
||
| 3962 | #define C_008F14_MTYPE 0x3FFFFFFF |
||
| 3963 | /* */ |
||
| 3964 | #define R_008F18_SQ_IMG_RSRC_WORD2 0x008F18 |
||
| 3965 | #define S_008F18_WIDTH(x) (((x) & 0x3FFF) << 0) |
||
| 3966 | #define G_008F18_WIDTH(x) (((x) >> 0) & 0x3FFF) |
||
| 3967 | #define C_008F18_WIDTH 0xFFFFC000 |
||
| 3968 | #define S_008F18_HEIGHT(x) (((x) & 0x3FFF) << 14) |
||
| 3969 | #define G_008F18_HEIGHT(x) (((x) >> 14) & 0x3FFF) |
||
| 3970 | #define C_008F18_HEIGHT 0xF0003FFF |
||
| 3971 | #define S_008F18_PERF_MOD(x) (((x) & 0x07) << 28) |
||
| 3972 | #define G_008F18_PERF_MOD(x) (((x) >> 28) & 0x07) |
||
| 3973 | #define C_008F18_PERF_MOD 0x8FFFFFFF |
||
| 3974 | #define S_008F18_INTERLACED(x) (((x) & 0x1) << 31) |
||
| 3975 | #define G_008F18_INTERLACED(x) (((x) >> 31) & 0x1) |
||
| 3976 | #define C_008F18_INTERLACED 0x7FFFFFFF |
||
| 3977 | #define R_008F1C_SQ_IMG_RSRC_WORD3 0x008F1C |
||
| 3978 | #define S_008F1C_DST_SEL_X(x) (((x) & 0x07) << 0) |
||
| 3979 | #define G_008F1C_DST_SEL_X(x) (((x) >> 0) & 0x07) |
||
| 3980 | #define C_008F1C_DST_SEL_X 0xFFFFFFF8 |
||
| 3981 | #define V_008F1C_SQ_SEL_0 0x00 |
||
| 3982 | #define V_008F1C_SQ_SEL_1 0x01 |
||
| 3983 | #define V_008F1C_SQ_SEL_RESERVED_0 0x02 |
||
| 3984 | #define V_008F1C_SQ_SEL_RESERVED_1 0x03 |
||
| 3985 | #define V_008F1C_SQ_SEL_X 0x04 |
||
| 3986 | #define V_008F1C_SQ_SEL_Y 0x05 |
||
| 3987 | #define V_008F1C_SQ_SEL_Z 0x06 |
||
| 3988 | #define V_008F1C_SQ_SEL_W 0x07 |
||
| 3989 | #define S_008F1C_DST_SEL_Y(x) (((x) & 0x07) << 3) |
||
| 3990 | #define G_008F1C_DST_SEL_Y(x) (((x) >> 3) & 0x07) |
||
| 3991 | #define C_008F1C_DST_SEL_Y 0xFFFFFFC7 |
||
| 3992 | #define V_008F1C_SQ_SEL_0 0x00 |
||
| 3993 | #define V_008F1C_SQ_SEL_1 0x01 |
||
| 3994 | #define V_008F1C_SQ_SEL_RESERVED_0 0x02 |
||
| 3995 | #define V_008F1C_SQ_SEL_RESERVED_1 0x03 |
||
| 3996 | #define V_008F1C_SQ_SEL_X 0x04 |
||
| 3997 | #define V_008F1C_SQ_SEL_Y 0x05 |
||
| 3998 | #define V_008F1C_SQ_SEL_Z 0x06 |
||
| 3999 | #define V_008F1C_SQ_SEL_W 0x07 |
||
| 4000 | #define S_008F1C_DST_SEL_Z(x) (((x) & 0x07) << 6) |
||
| 4001 | #define G_008F1C_DST_SEL_Z(x) (((x) >> 6) & 0x07) |
||
| 4002 | #define C_008F1C_DST_SEL_Z 0xFFFFFE3F |
||
| 4003 | #define V_008F1C_SQ_SEL_0 0x00 |
||
| 4004 | #define V_008F1C_SQ_SEL_1 0x01 |
||
| 4005 | #define V_008F1C_SQ_SEL_RESERVED_0 0x02 |
||
| 4006 | #define V_008F1C_SQ_SEL_RESERVED_1 0x03 |
||
| 4007 | #define V_008F1C_SQ_SEL_X 0x04 |
||
| 4008 | #define V_008F1C_SQ_SEL_Y 0x05 |
||
| 4009 | #define V_008F1C_SQ_SEL_Z 0x06 |
||
| 4010 | #define V_008F1C_SQ_SEL_W 0x07 |
||
| 4011 | #define S_008F1C_DST_SEL_W(x) (((x) & 0x07) << 9) |
||
| 4012 | #define G_008F1C_DST_SEL_W(x) (((x) >> 9) & 0x07) |
||
| 4013 | #define C_008F1C_DST_SEL_W 0xFFFFF1FF |
||
| 4014 | #define V_008F1C_SQ_SEL_0 0x00 |
||
| 4015 | #define V_008F1C_SQ_SEL_1 0x01 |
||
| 4016 | #define V_008F1C_SQ_SEL_RESERVED_0 0x02 |
||
| 4017 | #define V_008F1C_SQ_SEL_RESERVED_1 0x03 |
||
| 4018 | #define V_008F1C_SQ_SEL_X 0x04 |
||
| 4019 | #define V_008F1C_SQ_SEL_Y 0x05 |
||
| 4020 | #define V_008F1C_SQ_SEL_Z 0x06 |
||
| 4021 | #define V_008F1C_SQ_SEL_W 0x07 |
||
| 4022 | #define S_008F1C_BASE_LEVEL(x) (((x) & 0x0F) << 12) |
||
| 4023 | #define G_008F1C_BASE_LEVEL(x) (((x) >> 12) & 0x0F) |
||
| 4024 | #define C_008F1C_BASE_LEVEL 0xFFFF0FFF |
||
| 4025 | #define S_008F1C_LAST_LEVEL(x) (((x) & 0x0F) << 16) |
||
| 4026 | #define G_008F1C_LAST_LEVEL(x) (((x) >> 16) & 0x0F) |
||
| 4027 | #define C_008F1C_LAST_LEVEL 0xFFF0FFFF |
||
| 4028 | #define S_008F1C_TILING_INDEX(x) (((x) & 0x1F) << 20) |
||
| 4029 | #define G_008F1C_TILING_INDEX(x) (((x) >> 20) & 0x1F) |
||
| 4030 | #define C_008F1C_TILING_INDEX 0xFE0FFFFF |
||
| 4031 | #define S_008F1C_POW2_PAD(x) (((x) & 0x1) << 25) |
||
| 4032 | #define G_008F1C_POW2_PAD(x) (((x) >> 25) & 0x1) |
||
| 4033 | #define C_008F1C_POW2_PAD 0xFDFFFFFF |
||
| 4034 | /* CIK */ |
||
| 4035 | #define S_008F1C_MTYPE(x) (((x) & 0x1) << 26) |
||
| 4036 | #define G_008F1C_MTYPE(x) (((x) >> 26) & 0x1) |
||
| 4037 | #define C_008F1C_MTYPE 0xFBFFFFFF |
||
| 4038 | #define S_008F1C_ATC(x) (((x) & 0x1) << 27) |
||
| 4039 | #define G_008F1C_ATC(x) (((x) >> 27) & 0x1) |
||
| 4040 | #define C_008F1C_ATC 0xF7FFFFFF |
||
| 4041 | /* */ |
||
| 4042 | #define S_008F1C_TYPE(x) (((x) & 0x0F) << 28) |
||
| 4043 | #define G_008F1C_TYPE(x) (((x) >> 28) & 0x0F) |
||
| 4044 | #define C_008F1C_TYPE 0x0FFFFFFF |
||
| 4045 | #define V_008F1C_SQ_RSRC_IMG_RSVD_0 0x00 |
||
| 4046 | #define V_008F1C_SQ_RSRC_IMG_RSVD_1 0x01 |
||
| 4047 | #define V_008F1C_SQ_RSRC_IMG_RSVD_2 0x02 |
||
| 4048 | #define V_008F1C_SQ_RSRC_IMG_RSVD_3 0x03 |
||
| 4049 | #define V_008F1C_SQ_RSRC_IMG_RSVD_4 0x04 |
||
| 4050 | #define V_008F1C_SQ_RSRC_IMG_RSVD_5 0x05 |
||
| 4051 | #define V_008F1C_SQ_RSRC_IMG_RSVD_6 0x06 |
||
| 4052 | #define V_008F1C_SQ_RSRC_IMG_RSVD_7 0x07 |
||
| 4053 | #define V_008F1C_SQ_RSRC_IMG_1D 0x08 |
||
| 4054 | #define V_008F1C_SQ_RSRC_IMG_2D 0x09 |
||
| 4055 | #define V_008F1C_SQ_RSRC_IMG_3D 0x0A |
||
| 4056 | #define V_008F1C_SQ_RSRC_IMG_CUBE 0x0B |
||
| 4057 | #define V_008F1C_SQ_RSRC_IMG_1D_ARRAY 0x0C |
||
| 4058 | #define V_008F1C_SQ_RSRC_IMG_2D_ARRAY 0x0D |
||
| 4059 | #define V_008F1C_SQ_RSRC_IMG_2D_MSAA 0x0E |
||
| 4060 | #define V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY 0x0F |
||
| 4061 | #define R_008F20_SQ_IMG_RSRC_WORD4 0x008F20 |
||
| 4062 | #define S_008F20_DEPTH(x) (((x) & 0x1FFF) << 0) |
||
| 4063 | #define G_008F20_DEPTH(x) (((x) >> 0) & 0x1FFF) |
||
| 4064 | #define C_008F20_DEPTH 0xFFFFE000 |
||
| 4065 | #define S_008F20_PITCH(x) (((x) & 0x3FFF) << 13) |
||
| 4066 | #define G_008F20_PITCH(x) (((x) >> 13) & 0x3FFF) |
||
| 4067 | #define C_008F20_PITCH 0xF8001FFF |
||
| 4068 | #define R_008F24_SQ_IMG_RSRC_WORD5 0x008F24 |
||
| 4069 | #define S_008F24_BASE_ARRAY(x) (((x) & 0x1FFF) << 0) |
||
| 4070 | #define G_008F24_BASE_ARRAY(x) (((x) >> 0) & 0x1FFF) |
||
| 4071 | #define C_008F24_BASE_ARRAY 0xFFFFE000 |
||
| 4072 | #define S_008F24_LAST_ARRAY(x) (((x) & 0x1FFF) << 13) |
||
| 4073 | #define G_008F24_LAST_ARRAY(x) (((x) >> 13) & 0x1FFF) |
||
| 4074 | #define C_008F24_LAST_ARRAY 0xFC001FFF |
||
| 4075 | #define R_008F28_SQ_IMG_RSRC_WORD6 0x008F28 |
||
| 4076 | #define S_008F28_MIN_LOD_WARN(x) (((x) & 0xFFF) << 0) |
||
| 4077 | #define G_008F28_MIN_LOD_WARN(x) (((x) >> 0) & 0xFFF) |
||
| 4078 | #define C_008F28_MIN_LOD_WARN 0xFFFFF000 |
||
| 4079 | /* CIK */ |
||
| 4080 | #define S_008F28_COUNTER_BANK_ID(x) (((x) & 0xFF) << 12) |
||
| 4081 | #define G_008F28_COUNTER_BANK_ID(x) (((x) >> 12) & 0xFF) |
||
| 4082 | #define C_008F28_COUNTER_BANK_ID 0xFFF00FFF |
||
| 4083 | #define S_008F28_LOD_HDW_CNT_EN(x) (((x) & 0x1) << 20) |
||
| 4084 | #define G_008F28_LOD_HDW_CNT_EN(x) (((x) >> 20) & 0x1) |
||
| 4085 | #define C_008F28_LOD_HDW_CNT_EN 0xFFEFFFFF |
||
| 4086 | /* */ |
||
| 4087 | #define R_008F2C_SQ_IMG_RSRC_WORD7 0x008F2C |
||
| 4088 | #define R_008F30_SQ_IMG_SAMP_WORD0 0x008F30 |
||
| 4089 | #define S_008F30_CLAMP_X(x) (((x) & 0x07) << 0) |
||
| 4090 | #define G_008F30_CLAMP_X(x) (((x) >> 0) & 0x07) |
||
| 4091 | #define C_008F30_CLAMP_X 0xFFFFFFF8 |
||
| 4092 | #define V_008F30_SQ_TEX_WRAP 0x00 |
||
| 4093 | #define V_008F30_SQ_TEX_MIRROR 0x01 |
||
| 4094 | #define V_008F30_SQ_TEX_CLAMP_LAST_TEXEL 0x02 |
||
| 4095 | #define V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL 0x03 |
||
| 4096 | #define V_008F30_SQ_TEX_CLAMP_HALF_BORDER 0x04 |
||
| 4097 | #define V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER 0x05 |
||
| 4098 | #define V_008F30_SQ_TEX_CLAMP_BORDER 0x06 |
||
| 4099 | #define V_008F30_SQ_TEX_MIRROR_ONCE_BORDER 0x07 |
||
| 4100 | #define S_008F30_CLAMP_Y(x) (((x) & 0x07) << 3) |
||
| 4101 | #define G_008F30_CLAMP_Y(x) (((x) >> 3) & 0x07) |
||
| 4102 | #define C_008F30_CLAMP_Y 0xFFFFFFC7 |
||
| 4103 | #define V_008F30_SQ_TEX_WRAP 0x00 |
||
| 4104 | #define V_008F30_SQ_TEX_MIRROR 0x01 |
||
| 4105 | #define V_008F30_SQ_TEX_CLAMP_LAST_TEXEL 0x02 |
||
| 4106 | #define V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL 0x03 |
||
| 4107 | #define V_008F30_SQ_TEX_CLAMP_HALF_BORDER 0x04 |
||
| 4108 | #define V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER 0x05 |
||
| 4109 | #define V_008F30_SQ_TEX_CLAMP_BORDER 0x06 |
||
| 4110 | #define V_008F30_SQ_TEX_MIRROR_ONCE_BORDER 0x07 |
||
| 4111 | #define S_008F30_CLAMP_Z(x) (((x) & 0x07) << 6) |
||
| 4112 | #define G_008F30_CLAMP_Z(x) (((x) >> 6) & 0x07) |
||
| 4113 | #define C_008F30_CLAMP_Z 0xFFFFFE3F |
||
| 4114 | #define V_008F30_SQ_TEX_WRAP 0x00 |
||
| 4115 | #define V_008F30_SQ_TEX_MIRROR 0x01 |
||
| 4116 | #define V_008F30_SQ_TEX_CLAMP_LAST_TEXEL 0x02 |
||
| 4117 | #define V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL 0x03 |
||
| 4118 | #define V_008F30_SQ_TEX_CLAMP_HALF_BORDER 0x04 |
||
| 4119 | #define V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER 0x05 |
||
| 4120 | #define V_008F30_SQ_TEX_CLAMP_BORDER 0x06 |
||
| 4121 | #define V_008F30_SQ_TEX_MIRROR_ONCE_BORDER 0x07 |
||
| 4122 | #define S_008F30_DEPTH_COMPARE_FUNC(x) (((x) & 0x07) << 12) |
||
| 4123 | #define G_008F30_DEPTH_COMPARE_FUNC(x) (((x) >> 12) & 0x07) |
||
| 4124 | #define C_008F30_DEPTH_COMPARE_FUNC 0xFFFF8FFF |
||
| 4125 | #define V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER 0x00 |
||
| 4126 | #define V_008F30_SQ_TEX_DEPTH_COMPARE_LESS 0x01 |
||
| 4127 | #define V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL 0x02 |
||
| 4128 | #define V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL 0x03 |
||
| 4129 | #define V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER 0x04 |
||
| 4130 | #define V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL 0x05 |
||
| 4131 | #define V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL 0x06 |
||
| 4132 | #define V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS 0x07 |
||
| 4133 | #define S_008F30_FORCE_UNNORMALIZED(x) (((x) & 0x1) << 15) |
||
| 4134 | #define G_008F30_FORCE_UNNORMALIZED(x) (((x) >> 15) & 0x1) |
||
| 4135 | #define C_008F30_FORCE_UNNORMALIZED 0xFFFF7FFF |
||
| 4136 | #define S_008F30_MC_COORD_TRUNC(x) (((x) & 0x1) << 19) |
||
| 4137 | #define G_008F30_MC_COORD_TRUNC(x) (((x) >> 19) & 0x1) |
||
| 4138 | #define C_008F30_MC_COORD_TRUNC 0xFFF7FFFF |
||
| 4139 | #define S_008F30_FORCE_DEGAMMA(x) (((x) & 0x1) << 20) |
||
| 4140 | #define G_008F30_FORCE_DEGAMMA(x) (((x) >> 20) & 0x1) |
||
| 4141 | #define C_008F30_FORCE_DEGAMMA 0xFFEFFFFF |
||
| 4142 | #define S_008F30_TRUNC_COORD(x) (((x) & 0x1) << 27) |
||
| 4143 | #define G_008F30_TRUNC_COORD(x) (((x) >> 27) & 0x1) |
||
| 4144 | #define C_008F30_TRUNC_COORD 0xF7FFFFFF |
||
| 4145 | #define S_008F30_DISABLE_CUBE_WRAP(x) (((x) & 0x1) << 28) |
||
| 4146 | #define G_008F30_DISABLE_CUBE_WRAP(x) (((x) >> 28) & 0x1) |
||
| 4147 | #define C_008F30_DISABLE_CUBE_WRAP 0xEFFFFFFF |
||
| 4148 | #define S_008F30_FILTER_MODE(x) (((x) & 0x03) << 29) |
||
| 4149 | #define G_008F30_FILTER_MODE(x) (((x) >> 29) & 0x03) |
||
| 4150 | #define C_008F30_FILTER_MODE 0x9FFFFFFF |
||
| 4151 | #define R_008F34_SQ_IMG_SAMP_WORD1 0x008F34 |
||
| 4152 | #define S_008F34_MIN_LOD(x) (((x) & 0xFFF) << 0) |
||
| 4153 | #define G_008F34_MIN_LOD(x) (((x) >> 0) & 0xFFF) |
||
| 4154 | #define C_008F34_MIN_LOD 0xFFFFF000 |
||
| 4155 | #define S_008F34_MAX_LOD(x) (((x) & 0xFFF) << 12) |
||
| 4156 | #define G_008F34_MAX_LOD(x) (((x) >> 12) & 0xFFF) |
||
| 4157 | #define C_008F34_MAX_LOD 0xFF000FFF |
||
| 4158 | #define S_008F34_PERF_MIP(x) (((x) & 0x0F) << 24) |
||
| 4159 | #define G_008F34_PERF_MIP(x) (((x) >> 24) & 0x0F) |
||
| 4160 | #define C_008F34_PERF_MIP 0xF0FFFFFF |
||
| 4161 | #define S_008F34_PERF_Z(x) (((x) & 0x0F) << 28) |
||
| 4162 | #define G_008F34_PERF_Z(x) (((x) >> 28) & 0x0F) |
||
| 4163 | #define C_008F34_PERF_Z 0x0FFFFFFF |
||
| 4164 | #define R_008F38_SQ_IMG_SAMP_WORD2 0x008F38 |
||
| 4165 | #define S_008F38_LOD_BIAS(x) (((x) & 0x3FFF) << 0) |
||
| 4166 | #define G_008F38_LOD_BIAS(x) (((x) >> 0) & 0x3FFF) |
||
| 4167 | #define C_008F38_LOD_BIAS 0xFFFFC000 |
||
| 4168 | #define S_008F38_LOD_BIAS_SEC(x) (((x) & 0x3F) << 14) |
||
| 4169 | #define G_008F38_LOD_BIAS_SEC(x) (((x) >> 14) & 0x3F) |
||
| 4170 | #define C_008F38_LOD_BIAS_SEC 0xFFF03FFF |
||
| 4171 | #define S_008F38_XY_MAG_FILTER(x) (((x) & 0x03) << 20) |
||
| 4172 | #define G_008F38_XY_MAG_FILTER(x) (((x) >> 20) & 0x03) |
||
| 4173 | #define C_008F38_XY_MAG_FILTER 0xFFCFFFFF |
||
| 4174 | #define V_008F38_SQ_TEX_XY_FILTER_POINT 0x00 |
||
| 4175 | #define V_008F38_SQ_TEX_XY_FILTER_BILINEAR 0x01 |
||
| 4176 | #define S_008F38_XY_MIN_FILTER(x) (((x) & 0x03) << 22) |
||
| 4177 | #define G_008F38_XY_MIN_FILTER(x) (((x) >> 22) & 0x03) |
||
| 4178 | #define C_008F38_XY_MIN_FILTER 0xFF3FFFFF |
||
| 4179 | #define V_008F38_SQ_TEX_XY_FILTER_POINT 0x00 |
||
| 4180 | #define V_008F38_SQ_TEX_XY_FILTER_BILINEAR 0x01 |
||
| 4181 | #define S_008F38_Z_FILTER(x) (((x) & 0x03) << 24) |
||
| 4182 | #define G_008F38_Z_FILTER(x) (((x) >> 24) & 0x03) |
||
| 4183 | #define C_008F38_Z_FILTER 0xFCFFFFFF |
||
| 4184 | #define V_008F38_SQ_TEX_Z_FILTER_NONE 0x00 |
||
| 4185 | #define V_008F38_SQ_TEX_Z_FILTER_POINT 0x01 |
||
| 4186 | #define V_008F38_SQ_TEX_Z_FILTER_LINEAR 0x02 |
||
| 4187 | #define S_008F38_MIP_FILTER(x) (((x) & 0x03) << 26) |
||
| 4188 | #define G_008F38_MIP_FILTER(x) (((x) >> 26) & 0x03) |
||
| 4189 | #define C_008F38_MIP_FILTER 0xF3FFFFFF |
||
| 4190 | #define V_008F38_SQ_TEX_Z_FILTER_NONE 0x00 |
||
| 4191 | #define V_008F38_SQ_TEX_Z_FILTER_POINT 0x01 |
||
| 4192 | #define V_008F38_SQ_TEX_Z_FILTER_LINEAR 0x02 |
||
| 4193 | #define S_008F38_MIP_POINT_PRECLAMP(x) (((x) & 0x1) << 28) |
||
| 4194 | #define G_008F38_MIP_POINT_PRECLAMP(x) (((x) >> 28) & 0x1) |
||
| 4195 | #define C_008F38_MIP_POINT_PRECLAMP 0xEFFFFFFF |
||
| 4196 | #define S_008F38_DISABLE_LSB_CEIL(x) (((x) & 0x1) << 29) |
||
| 4197 | #define G_008F38_DISABLE_LSB_CEIL(x) (((x) >> 29) & 0x1) |
||
| 4198 | #define C_008F38_DISABLE_LSB_CEIL 0xDFFFFFFF |
||
| 4199 | #define S_008F38_FILTER_PREC_FIX(x) (((x) & 0x1) << 30) |
||
| 4200 | #define G_008F38_FILTER_PREC_FIX(x) (((x) >> 30) & 0x1) |
||
| 4201 | #define C_008F38_FILTER_PREC_FIX 0xBFFFFFFF |
||
| 4202 | #define R_008F3C_SQ_IMG_SAMP_WORD3 0x008F3C |
||
| 4203 | #define S_008F3C_BORDER_COLOR_PTR(x) (((x) & 0xFFF) << 0) |
||
| 4204 | #define G_008F3C_BORDER_COLOR_PTR(x) (((x) >> 0) & 0xFFF) |
||
| 4205 | #define C_008F3C_BORDER_COLOR_PTR 0xFFFFF000 |
||
| 4206 | #define S_008F3C_BORDER_COLOR_TYPE(x) (((x) & 0x03) << 30) |
||
| 4207 | #define G_008F3C_BORDER_COLOR_TYPE(x) (((x) >> 30) & 0x03) |
||
| 4208 | #define C_008F3C_BORDER_COLOR_TYPE 0x3FFFFFFF |
||
| 4209 | #define V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK 0x00 |
||
| 4210 | #define V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK 0x01 |
||
| 4211 | #define V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE 0x02 |
||
| 4212 | #define V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER 0x03 |
||
| 4213 | #define R_0090DC_SPI_DYN_GPR_LOCK_EN 0x0090DC /* not on CIK */ |
||
| 4214 | #define S_0090DC_VS_LOW_THRESHOLD(x) (((x) & 0x0F) << 0) |
||
| 4215 | #define G_0090DC_VS_LOW_THRESHOLD(x) (((x) >> 0) & 0x0F) |
||
| 4216 | #define C_0090DC_VS_LOW_THRESHOLD 0xFFFFFFF0 |
||
| 4217 | #define S_0090DC_GS_LOW_THRESHOLD(x) (((x) & 0x0F) << 4) |
||
| 4218 | #define G_0090DC_GS_LOW_THRESHOLD(x) (((x) >> 4) & 0x0F) |
||
| 4219 | #define C_0090DC_GS_LOW_THRESHOLD 0xFFFFFF0F |
||
| 4220 | #define S_0090DC_ES_LOW_THRESHOLD(x) (((x) & 0x0F) << 8) |
||
| 4221 | #define G_0090DC_ES_LOW_THRESHOLD(x) (((x) >> 8) & 0x0F) |
||
| 4222 | #define C_0090DC_ES_LOW_THRESHOLD 0xFFFFF0FF |
||
| 4223 | #define S_0090DC_HS_LOW_THRESHOLD(x) (((x) & 0x0F) << 12) |
||
| 4224 | #define G_0090DC_HS_LOW_THRESHOLD(x) (((x) >> 12) & 0x0F) |
||
| 4225 | #define C_0090DC_HS_LOW_THRESHOLD 0xFFFF0FFF |
||
| 4226 | #define S_0090DC_LS_LOW_THRESHOLD(x) (((x) & 0x0F) << 16) |
||
| 4227 | #define G_0090DC_LS_LOW_THRESHOLD(x) (((x) >> 16) & 0x0F) |
||
| 4228 | #define C_0090DC_LS_LOW_THRESHOLD 0xFFF0FFFF |
||
| 4229 | #define R_0090E0_SPI_STATIC_THREAD_MGMT_1 0x0090E0 /* not on CIK */ |
||
| 4230 | #define S_0090E0_PS_CU_EN(x) (((x) & 0xFFFF) << 0) |
||
| 4231 | #define G_0090E0_PS_CU_EN(x) (((x) >> 0) & 0xFFFF) |
||
| 4232 | #define C_0090E0_PS_CU_EN 0xFFFF0000 |
||
| 4233 | #define S_0090E0_VS_CU_EN(x) (((x) & 0xFFFF) << 16) |
||
| 4234 | #define G_0090E0_VS_CU_EN(x) (((x) >> 16) & 0xFFFF) |
||
| 4235 | #define C_0090E0_VS_CU_EN 0x0000FFFF |
||
| 4236 | #define R_0090E4_SPI_STATIC_THREAD_MGMT_2 0x0090E4 /* not on CIK */ |
||
| 4237 | #define S_0090E4_GS_CU_EN(x) (((x) & 0xFFFF) << 0) |
||
| 4238 | #define G_0090E4_GS_CU_EN(x) (((x) >> 0) & 0xFFFF) |
||
| 4239 | #define C_0090E4_GS_CU_EN 0xFFFF0000 |
||
| 4240 | #define S_0090E4_ES_CU_EN(x) (((x) & 0xFFFF) << 16) |
||
| 4241 | #define G_0090E4_ES_CU_EN(x) (((x) >> 16) & 0xFFFF) |
||
| 4242 | #define C_0090E4_ES_CU_EN 0x0000FFFF |
||
| 4243 | #define R_0090E8_SPI_STATIC_THREAD_MGMT_3 0x0090E8 /* not on CIK */ |
||
| 4244 | #define S_0090E8_LSHS_CU_EN(x) (((x) & 0xFFFF) << 0) |
||
| 4245 | #define G_0090E8_LSHS_CU_EN(x) (((x) >> 0) & 0xFFFF) |
||
| 4246 | #define C_0090E8_LSHS_CU_EN 0xFFFF0000 |
||
| 4247 | #define R_0090EC_SPI_PS_MAX_WAVE_ID 0x0090EC |
||
| 4248 | #define S_0090EC_MAX_WAVE_ID(x) (((x) & 0xFFF) << 0) |
||
| 4249 | #define G_0090EC_MAX_WAVE_ID(x) (((x) >> 0) & 0xFFF) |
||
| 4250 | #define C_0090EC_MAX_WAVE_ID 0xFFFFF000 |
||
| 4251 | /* CIK */ |
||
| 4252 | #define R_0090E8_SPI_PS_MAX_WAVE_ID 0x0090E8 |
||
| 4253 | #define S_0090E8_MAX_WAVE_ID(x) (((x) & 0xFFF) << 0) |
||
| 4254 | #define G_0090E8_MAX_WAVE_ID(x) (((x) >> 0) & 0xFFF) |
||
| 4255 | #define C_0090E8_MAX_WAVE_ID 0xFFFFF000 |
||
| 4256 | /* */ |
||
| 4257 | #define R_0090F0_SPI_ARB_PRIORITY 0x0090F0 |
||
| 4258 | #define S_0090F0_RING_ORDER_TS0(x) (((x) & 0x07) << 0) |
||
| 4259 | #define G_0090F0_RING_ORDER_TS0(x) (((x) >> 0) & 0x07) |
||
| 4260 | #define C_0090F0_RING_ORDER_TS0 0xFFFFFFF8 |
||
| 4261 | #define V_0090F0_X_R0 0x00 |
||
| 4262 | #define S_0090F0_RING_ORDER_TS1(x) (((x) & 0x07) << 3) |
||
| 4263 | #define G_0090F0_RING_ORDER_TS1(x) (((x) >> 3) & 0x07) |
||
| 4264 | #define C_0090F0_RING_ORDER_TS1 0xFFFFFFC7 |
||
| 4265 | #define S_0090F0_RING_ORDER_TS2(x) (((x) & 0x07) << 6) |
||
| 4266 | #define G_0090F0_RING_ORDER_TS2(x) (((x) >> 6) & 0x07) |
||
| 4267 | #define C_0090F0_RING_ORDER_TS2 0xFFFFFE3F |
||
| 4268 | /* CIK */ |
||
| 4269 | #define R_00C700_SPI_ARB_PRIORITY 0x00C700 |
||
| 4270 | #define S_00C700_PIPE_ORDER_TS0(x) (((x) & 0x07) << 0) |
||
| 4271 | #define G_00C700_PIPE_ORDER_TS0(x) (((x) >> 0) & 0x07) |
||
| 4272 | #define C_00C700_PIPE_ORDER_TS0 0xFFFFFFF8 |
||
| 4273 | #define S_00C700_PIPE_ORDER_TS1(x) (((x) & 0x07) << 3) |
||
| 4274 | #define G_00C700_PIPE_ORDER_TS1(x) (((x) >> 3) & 0x07) |
||
| 4275 | #define C_00C700_PIPE_ORDER_TS1 0xFFFFFFC7 |
||
| 4276 | #define S_00C700_PIPE_ORDER_TS2(x) (((x) & 0x07) << 6) |
||
| 4277 | #define G_00C700_PIPE_ORDER_TS2(x) (((x) >> 6) & 0x07) |
||
| 4278 | #define C_00C700_PIPE_ORDER_TS2 0xFFFFFE3F |
||
| 4279 | #define S_00C700_PIPE_ORDER_TS3(x) (((x) & 0x07) << 9) |
||
| 4280 | #define G_00C700_PIPE_ORDER_TS3(x) (((x) >> 9) & 0x07) |
||
| 4281 | #define C_00C700_PIPE_ORDER_TS3 0xFFFFF1FF |
||
| 4282 | #define S_00C700_TS0_DUR_MULT(x) (((x) & 0x03) << 12) |
||
| 4283 | #define G_00C700_TS0_DUR_MULT(x) (((x) >> 12) & 0x03) |
||
| 4284 | #define C_00C700_TS0_DUR_MULT 0xFFFFCFFF |
||
| 4285 | #define S_00C700_TS1_DUR_MULT(x) (((x) & 0x03) << 14) |
||
| 4286 | #define G_00C700_TS1_DUR_MULT(x) (((x) >> 14) & 0x03) |
||
| 4287 | #define C_00C700_TS1_DUR_MULT 0xFFFF3FFF |
||
| 4288 | #define S_00C700_TS2_DUR_MULT(x) (((x) & 0x03) << 16) |
||
| 4289 | #define G_00C700_TS2_DUR_MULT(x) (((x) >> 16) & 0x03) |
||
| 4290 | #define C_00C700_TS2_DUR_MULT 0xFFFCFFFF |
||
| 4291 | #define S_00C700_TS3_DUR_MULT(x) (((x) & 0x03) << 18) |
||
| 4292 | #define G_00C700_TS3_DUR_MULT(x) (((x) >> 18) & 0x03) |
||
| 4293 | #define C_00C700_TS3_DUR_MULT 0xFFF3FFFF |
||
| 4294 | /* */ |
||
| 4295 | #define R_0090F4_SPI_ARB_CYCLES_0 0x0090F4 /* moved to 0xC704 on CIK */ |
||
| 4296 | #define S_0090F4_TS0_DURATION(x) (((x) & 0xFFFF) << 0) |
||
| 4297 | #define G_0090F4_TS0_DURATION(x) (((x) >> 0) & 0xFFFF) |
||
| 4298 | #define C_0090F4_TS0_DURATION 0xFFFF0000 |
||
| 4299 | #define S_0090F4_TS1_DURATION(x) (((x) & 0xFFFF) << 16) |
||
| 4300 | #define G_0090F4_TS1_DURATION(x) (((x) >> 16) & 0xFFFF) |
||
| 4301 | #define C_0090F4_TS1_DURATION 0x0000FFFF |
||
| 4302 | #define R_0090F8_SPI_ARB_CYCLES_1 0x0090F8 /* moved to 0xC708 on CIK */ |
||
| 4303 | #define S_0090F8_TS2_DURATION(x) (((x) & 0xFFFF) << 0) |
||
| 4304 | #define G_0090F8_TS2_DURATION(x) (((x) >> 0) & 0xFFFF) |
||
| 4305 | #define C_0090F8_TS2_DURATION 0xFFFF0000 |
||
| 4306 | /* CIK */ |
||
| 4307 | #define R_008F40_SQ_FLAT_SCRATCH_WORD0 0x008F40 |
||
| 4308 | #define S_008F40_SIZE(x) (((x) & 0x7FFFF) << 0) |
||
| 4309 | #define G_008F40_SIZE(x) (((x) >> 0) & 0x7FFFF) |
||
| 4310 | #define C_008F40_SIZE 0xFFF80000 |
||
| 4311 | #define R_008F44_SQ_FLAT_SCRATCH_WORD1 0x008F44 |
||
| 4312 | #define S_008F44_OFFSET(x) (((x) & 0xFFFFFF) << 0) |
||
| 4313 | #define G_008F44_OFFSET(x) (((x) >> 0) & 0xFFFFFF) |
||
| 4314 | #define C_008F44_OFFSET 0xFF000000 |
||
| 4315 | /* */ |
||
| 4316 | #define R_009100_SPI_CONFIG_CNTL 0x009100 |
||
| 4317 | #define S_009100_GPR_WRITE_PRIORITY(x) (((x) & 0x1FFFFF) << 0) |
||
| 4318 | #define G_009100_GPR_WRITE_PRIORITY(x) (((x) >> 0) & 0x1FFFFF) |
||
| 4319 | #define C_009100_GPR_WRITE_PRIORITY 0xFFE00000 |
||
| 4320 | #define S_009100_EXP_PRIORITY_ORDER(x) (((x) & 0x07) << 21) |
||
| 4321 | #define G_009100_EXP_PRIORITY_ORDER(x) (((x) >> 21) & 0x07) |
||
| 4322 | #define C_009100_EXP_PRIORITY_ORDER 0xFF1FFFFF |
||
| 4323 | #define S_009100_ENABLE_SQG_TOP_EVENTS(x) (((x) & 0x1) << 24) |
||
| 4324 | #define G_009100_ENABLE_SQG_TOP_EVENTS(x) (((x) >> 24) & 0x1) |
||
| 4325 | #define C_009100_ENABLE_SQG_TOP_EVENTS 0xFEFFFFFF |
||
| 4326 | #define S_009100_ENABLE_SQG_BOP_EVENTS(x) (((x) & 0x1) << 25) |
||
| 4327 | #define G_009100_ENABLE_SQG_BOP_EVENTS(x) (((x) >> 25) & 0x1) |
||
| 4328 | #define C_009100_ENABLE_SQG_BOP_EVENTS 0xFDFFFFFF |
||
| 4329 | #define S_009100_RSRC_MGMT_RESET(x) (((x) & 0x1) << 26) |
||
| 4330 | #define G_009100_RSRC_MGMT_RESET(x) (((x) >> 26) & 0x1) |
||
| 4331 | #define C_009100_RSRC_MGMT_RESET 0xFBFFFFFF |
||
| 4332 | #define R_00913C_SPI_CONFIG_CNTL_1 0x00913C |
||
| 4333 | #define S_00913C_VTX_DONE_DELAY(x) (((x) & 0x0F) << 0) |
||
| 4334 | #define G_00913C_VTX_DONE_DELAY(x) (((x) >> 0) & 0x0F) |
||
| 4335 | #define C_00913C_VTX_DONE_DELAY 0xFFFFFFF0 |
||
| 4336 | #define V_00913C_X_DELAY_14_CLKS 0x00 |
||
| 4337 | #define V_00913C_X_DELAY_16_CLKS 0x01 |
||
| 4338 | #define V_00913C_X_DELAY_18_CLKS 0x02 |
||
| 4339 | #define V_00913C_X_DELAY_20_CLKS 0x03 |
||
| 4340 | #define V_00913C_X_DELAY_22_CLKS 0x04 |
||
| 4341 | #define V_00913C_X_DELAY_24_CLKS 0x05 |
||
| 4342 | #define V_00913C_X_DELAY_26_CLKS 0x06 |
||
| 4343 | #define V_00913C_X_DELAY_28_CLKS 0x07 |
||
| 4344 | #define V_00913C_X_DELAY_30_CLKS 0x08 |
||
| 4345 | #define V_00913C_X_DELAY_32_CLKS 0x09 |
||
| 4346 | #define V_00913C_X_DELAY_34_CLKS 0x0A |
||
| 4347 | #define V_00913C_X_DELAY_4_CLKS 0x0B |
||
| 4348 | #define V_00913C_X_DELAY_6_CLKS 0x0C |
||
| 4349 | #define V_00913C_X_DELAY_8_CLKS 0x0D |
||
| 4350 | #define V_00913C_X_DELAY_10_CLKS 0x0E |
||
| 4351 | #define V_00913C_X_DELAY_12_CLKS 0x0F |
||
| 4352 | #define S_00913C_INTERP_ONE_PRIM_PER_ROW(x) (((x) & 0x1) << 4) |
||
| 4353 | #define G_00913C_INTERP_ONE_PRIM_PER_ROW(x) (((x) >> 4) & 0x1) |
||
| 4354 | #define C_00913C_INTERP_ONE_PRIM_PER_ROW 0xFFFFFFEF |
||
| 4355 | #define S_00913C_PC_LIMIT_ENABLE(x) (((x) & 0x1) << 6) |
||
| 4356 | #define G_00913C_PC_LIMIT_ENABLE(x) (((x) >> 6) & 0x1) |
||
| 4357 | #define C_00913C_PC_LIMIT_ENABLE 0xFFFFFFBF |
||
| 4358 | #define S_00913C_PC_LIMIT_STRICT(x) (((x) & 0x1) << 7) |
||
| 4359 | #define G_00913C_PC_LIMIT_STRICT(x) (((x) >> 7) & 0x1) |
||
| 4360 | #define C_00913C_PC_LIMIT_STRICT 0xFFFFFF7F |
||
| 4361 | #define S_00913C_PC_LIMIT_SIZE(x) (((x) & 0xFFFF) << 16) |
||
| 4362 | #define G_00913C_PC_LIMIT_SIZE(x) (((x) >> 16) & 0xFFFF) |
||
| 4363 | #define C_00913C_PC_LIMIT_SIZE 0x0000FFFF |
||
| 4364 | #define R_00936C_SPI_RESOURCE_RESERVE_CU_AB_0 0x00936C |
||
| 4365 | #define S_00936C_TYPE_A(x) (((x) & 0x0F) << 0) |
||
| 4366 | #define G_00936C_TYPE_A(x) (((x) >> 0) & 0x0F) |
||
| 4367 | #define C_00936C_TYPE_A 0xFFFFFFF0 |
||
| 4368 | #define S_00936C_VGPR_A(x) (((x) & 0x07) << 4) |
||
| 4369 | #define G_00936C_VGPR_A(x) (((x) >> 4) & 0x07) |
||
| 4370 | #define C_00936C_VGPR_A 0xFFFFFF8F |
||
| 4371 | #define S_00936C_SGPR_A(x) (((x) & 0x07) << 7) |
||
| 4372 | #define G_00936C_SGPR_A(x) (((x) >> 7) & 0x07) |
||
| 4373 | #define C_00936C_SGPR_A 0xFFFFFC7F |
||
| 4374 | #define S_00936C_LDS_A(x) (((x) & 0x07) << 10) |
||
| 4375 | #define G_00936C_LDS_A(x) (((x) >> 10) & 0x07) |
||
| 4376 | #define C_00936C_LDS_A 0xFFFFE3FF |
||
| 4377 | #define S_00936C_WAVES_A(x) (((x) & 0x03) << 13) |
||
| 4378 | #define G_00936C_WAVES_A(x) (((x) >> 13) & 0x03) |
||
| 4379 | #define C_00936C_WAVES_A 0xFFFF9FFF |
||
| 4380 | #define S_00936C_EN_A(x) (((x) & 0x1) << 15) |
||
| 4381 | #define G_00936C_EN_A(x) (((x) >> 15) & 0x1) |
||
| 4382 | #define C_00936C_EN_A 0xFFFF7FFF |
||
| 4383 | #define S_00936C_TYPE_B(x) (((x) & 0x0F) << 16) |
||
| 4384 | #define G_00936C_TYPE_B(x) (((x) >> 16) & 0x0F) |
||
| 4385 | #define C_00936C_TYPE_B 0xFFF0FFFF |
||
| 4386 | #define S_00936C_VGPR_B(x) (((x) & 0x07) << 20) |
||
| 4387 | #define G_00936C_VGPR_B(x) (((x) >> 20) & 0x07) |
||
| 4388 | #define C_00936C_VGPR_B 0xFF8FFFFF |
||
| 4389 | #define S_00936C_SGPR_B(x) (((x) & 0x07) << 23) |
||
| 4390 | #define G_00936C_SGPR_B(x) (((x) >> 23) & 0x07) |
||
| 4391 | #define C_00936C_SGPR_B 0xFC7FFFFF |
||
| 4392 | #define S_00936C_LDS_B(x) (((x) & 0x07) << 26) |
||
| 4393 | #define G_00936C_LDS_B(x) (((x) >> 26) & 0x07) |
||
| 4394 | #define C_00936C_LDS_B 0xE3FFFFFF |
||
| 4395 | #define S_00936C_WAVES_B(x) (((x) & 0x03) << 29) |
||
| 4396 | #define G_00936C_WAVES_B(x) (((x) >> 29) & 0x03) |
||
| 4397 | #define C_00936C_WAVES_B 0x9FFFFFFF |
||
| 4398 | #define S_00936C_EN_B(x) (((x) & 0x1) << 31) |
||
| 4399 | #define G_00936C_EN_B(x) (((x) >> 31) & 0x1) |
||
| 4400 | #define C_00936C_EN_B 0x7FFFFFFF |
||
| 4401 | #define R_00950C_TA_CS_BC_BASE_ADDR 0x00950C |
||
| 4402 | /* CIK */ |
||
| 4403 | #define R_030E00_TA_CS_BC_BASE_ADDR 0x030E00 |
||
| 4404 | #define R_030E04_TA_CS_BC_BASE_ADDR_HI 0x030E04 |
||
| 4405 | #define S_030E04_ADDRESS(x) (((x) & 0xFF) << 0) |
||
| 4406 | #define G_030E04_ADDRESS(x) (((x) >> 0) & 0xFF) |
||
| 4407 | #define C_030E04_ADDRESS 0xFFFFFF00 |
||
| 4408 | /* */ |
||
| 4409 | #define R_009858_DB_SUBTILE_CONTROL 0x009858 |
||
| 4410 | #define S_009858_MSAA1_X(x) (((x) & 0x03) << 0) |
||
| 4411 | #define G_009858_MSAA1_X(x) (((x) >> 0) & 0x03) |
||
| 4412 | #define C_009858_MSAA1_X 0xFFFFFFFC |
||
| 4413 | #define S_009858_MSAA1_Y(x) (((x) & 0x03) << 2) |
||
| 4414 | #define G_009858_MSAA1_Y(x) (((x) >> 2) & 0x03) |
||
| 4415 | #define C_009858_MSAA1_Y 0xFFFFFFF3 |
||
| 4416 | #define S_009858_MSAA2_X(x) (((x) & 0x03) << 4) |
||
| 4417 | #define G_009858_MSAA2_X(x) (((x) >> 4) & 0x03) |
||
| 4418 | #define C_009858_MSAA2_X 0xFFFFFFCF |
||
| 4419 | #define S_009858_MSAA2_Y(x) (((x) & 0x03) << 6) |
||
| 4420 | #define G_009858_MSAA2_Y(x) (((x) >> 6) & 0x03) |
||
| 4421 | #define C_009858_MSAA2_Y 0xFFFFFF3F |
||
| 4422 | #define S_009858_MSAA4_X(x) (((x) & 0x03) << 8) |
||
| 4423 | #define G_009858_MSAA4_X(x) (((x) >> 8) & 0x03) |
||
| 4424 | #define C_009858_MSAA4_X 0xFFFFFCFF |
||
| 4425 | #define S_009858_MSAA4_Y(x) (((x) & 0x03) << 10) |
||
| 4426 | #define G_009858_MSAA4_Y(x) (((x) >> 10) & 0x03) |
||
| 4427 | #define C_009858_MSAA4_Y 0xFFFFF3FF |
||
| 4428 | #define S_009858_MSAA8_X(x) (((x) & 0x03) << 12) |
||
| 4429 | #define G_009858_MSAA8_X(x) (((x) >> 12) & 0x03) |
||
| 4430 | #define C_009858_MSAA8_X 0xFFFFCFFF |
||
| 4431 | #define S_009858_MSAA8_Y(x) (((x) & 0x03) << 14) |
||
| 4432 | #define G_009858_MSAA8_Y(x) (((x) >> 14) & 0x03) |
||
| 4433 | #define C_009858_MSAA8_Y 0xFFFF3FFF |
||
| 4434 | #define S_009858_MSAA16_X(x) (((x) & 0x03) << 16) |
||
| 4435 | #define G_009858_MSAA16_X(x) (((x) >> 16) & 0x03) |
||
| 4436 | #define C_009858_MSAA16_X 0xFFFCFFFF |
||
| 4437 | #define S_009858_MSAA16_Y(x) (((x) & 0x03) << 18) |
||
| 4438 | #define G_009858_MSAA16_Y(x) (((x) >> 18) & 0x03) |
||
| 4439 | #define C_009858_MSAA16_Y 0xFFF3FFFF |
||
| 4440 | #define R_009910_GB_TILE_MODE0 0x009910 |
||
| 4441 | #define S_009910_MICRO_TILE_MODE(x) (((x) & 0x03) << 0) |
||
| 4442 | #define G_009910_MICRO_TILE_MODE(x) (((x) >> 0) & 0x03) |
||
| 4443 | #define C_009910_MICRO_TILE_MODE 0xFFFFFFFC |
||
| 4444 | #define V_009910_ADDR_SURF_DISPLAY_MICRO_TILING 0x00 |
||
| 4445 | #define V_009910_ADDR_SURF_THIN_MICRO_TILING 0x01 |
||
| 4446 | #define V_009910_ADDR_SURF_DEPTH_MICRO_TILING 0x02 |
||
| 4447 | #define V_009910_ADDR_SURF_THICK_MICRO_TILING 0x03 |
||
| 4448 | #define S_009910_ARRAY_MODE(x) (((x) & 0x0F) << 2) |
||
| 4449 | #define G_009910_ARRAY_MODE(x) (((x) >> 2) & 0x0F) |
||
| 4450 | #define C_009910_ARRAY_MODE 0xFFFFFFC3 |
||
| 4451 | #define V_009910_ARRAY_LINEAR_GENERAL 0x00 |
||
| 4452 | #define V_009910_ARRAY_LINEAR_ALIGNED 0x01 |
||
| 4453 | #define V_009910_ARRAY_1D_TILED_THIN1 0x02 |
||
| 4454 | #define V_009910_ARRAY_1D_TILED_THICK 0x03 |
||
| 4455 | #define V_009910_ARRAY_2D_TILED_THIN1 0x04 |
||
| 4456 | #define V_009910_ARRAY_2D_TILED_THICK 0x07 |
||
| 4457 | #define V_009910_ARRAY_2D_TILED_XTHICK 0x08 |
||
| 4458 | #define V_009910_ARRAY_3D_TILED_THIN1 0x0C |
||
| 4459 | #define V_009910_ARRAY_3D_TILED_THICK 0x0D |
||
| 4460 | #define V_009910_ARRAY_3D_TILED_XTHICK 0x0E |
||
| 4461 | #define V_009910_ARRAY_POWER_SAVE 0x0F |
||
| 4462 | #define S_009910_PIPE_CONFIG(x) (((x) & 0x1F) << 6) |
||
| 4463 | #define G_009910_PIPE_CONFIG(x) (((x) >> 6) & 0x1F) |
||
| 4464 | #define C_009910_PIPE_CONFIG 0xFFFFF83F |
||
| 4465 | #define V_009910_ADDR_SURF_P2 0x00 |
||
| 4466 | #define V_009910_ADDR_SURF_P2_RESERVED0 0x01 |
||
| 4467 | #define V_009910_ADDR_SURF_P2_RESERVED1 0x02 |
||
| 4468 | #define V_009910_ADDR_SURF_P2_RESERVED2 0x03 |
||
| 4469 | #define V_009910_X_ADDR_SURF_P4_8X16 0x04 |
||
| 4470 | #define V_009910_X_ADDR_SURF_P4_16X16 0x05 |
||
| 4471 | #define V_009910_X_ADDR_SURF_P4_16X32 0x06 |
||
| 4472 | #define V_009910_X_ADDR_SURF_P4_32X32 0x07 |
||
| 4473 | #define V_009910_X_ADDR_SURF_P8_16X16_8X16 0x08 |
||
| 4474 | #define V_009910_X_ADDR_SURF_P8_16X32_8X16 0x09 |
||
| 4475 | #define V_009910_X_ADDR_SURF_P8_32X32_8X16 0x0A |
||
| 4476 | #define V_009910_X_ADDR_SURF_P8_16X32_16X16 0x0B |
||
| 4477 | #define V_009910_X_ADDR_SURF_P8_32X32_16X16 0x0C |
||
| 4478 | #define V_009910_X_ADDR_SURF_P8_32X32_16X32 0x0D |
||
| 4479 | #define V_009910_X_ADDR_SURF_P8_32X64_32X32 0x0E |
||
| 4480 | #define S_009910_TILE_SPLIT(x) (((x) & 0x07) << 11) |
||
| 4481 | #define G_009910_TILE_SPLIT(x) (((x) >> 11) & 0x07) |
||
| 4482 | #define C_009910_TILE_SPLIT 0xFFFFC7FF |
||
| 4483 | #define V_009910_ADDR_SURF_TILE_SPLIT_64B 0x00 |
||
| 4484 | #define V_009910_ADDR_SURF_TILE_SPLIT_128B 0x01 |
||
| 4485 | #define V_009910_ADDR_SURF_TILE_SPLIT_256B 0x02 |
||
| 4486 | #define V_009910_ADDR_SURF_TILE_SPLIT_512B 0x03 |
||
| 4487 | #define V_009910_ADDR_SURF_TILE_SPLIT_1KB 0x04 |
||
| 4488 | #define V_009910_ADDR_SURF_TILE_SPLIT_2KB 0x05 |
||
| 4489 | #define V_009910_ADDR_SURF_TILE_SPLIT_4KB 0x06 |
||
| 4490 | #define S_009910_BANK_WIDTH(x) (((x) & 0x03) << 14) |
||
| 4491 | #define G_009910_BANK_WIDTH(x) (((x) >> 14) & 0x03) |
||
| 4492 | #define C_009910_BANK_WIDTH 0xFFFF3FFF |
||
| 4493 | #define V_009910_ADDR_SURF_BANK_WIDTH_1 0x00 |
||
| 4494 | #define V_009910_ADDR_SURF_BANK_WIDTH_2 0x01 |
||
| 4495 | #define V_009910_ADDR_SURF_BANK_WIDTH_4 0x02 |
||
| 4496 | #define V_009910_ADDR_SURF_BANK_WIDTH_8 0x03 |
||
| 4497 | #define S_009910_BANK_HEIGHT(x) (((x) & 0x03) << 16) |
||
| 4498 | #define G_009910_BANK_HEIGHT(x) (((x) >> 16) & 0x03) |
||
| 4499 | #define C_009910_BANK_HEIGHT 0xFFFCFFFF |
||
| 4500 | #define V_009910_ADDR_SURF_BANK_HEIGHT_1 0x00 |
||
| 4501 | #define V_009910_ADDR_SURF_BANK_HEIGHT_2 0x01 |
||
| 4502 | #define V_009910_ADDR_SURF_BANK_HEIGHT_4 0x02 |
||
| 4503 | #define V_009910_ADDR_SURF_BANK_HEIGHT_8 0x03 |
||
| 4504 | #define S_009910_MACRO_TILE_ASPECT(x) (((x) & 0x03) << 18) |
||
| 4505 | #define G_009910_MACRO_TILE_ASPECT(x) (((x) >> 18) & 0x03) |
||
| 4506 | #define C_009910_MACRO_TILE_ASPECT 0xFFF3FFFF |
||
| 4507 | #define V_009910_ADDR_SURF_MACRO_ASPECT_1 0x00 |
||
| 4508 | #define V_009910_ADDR_SURF_MACRO_ASPECT_2 0x01 |
||
| 4509 | #define V_009910_ADDR_SURF_MACRO_ASPECT_4 0x02 |
||
| 4510 | #define V_009910_ADDR_SURF_MACRO_ASPECT_8 0x03 |
||
| 4511 | #define S_009910_NUM_BANKS(x) (((x) & 0x03) << 20) |
||
| 4512 | #define G_009910_NUM_BANKS(x) (((x) >> 20) & 0x03) |
||
| 4513 | #define C_009910_NUM_BANKS 0xFFCFFFFF |
||
| 4514 | #define V_009910_ADDR_SURF_2_BANK 0x00 |
||
| 4515 | #define V_009910_ADDR_SURF_4_BANK 0x01 |
||
| 4516 | #define V_009910_ADDR_SURF_8_BANK 0x02 |
||
| 4517 | #define V_009910_ADDR_SURF_16_BANK 0x03 |
||
| 4518 | /* CIK */ |
||
| 4519 | #define R_00B01C_SPI_SHADER_PGM_RSRC3_PS 0x00B01C |
||
| 4520 | #define S_00B01C_CU_EN(x) (((x) & 0xFFFF) << 0) |
||
| 4521 | #define G_00B01C_CU_EN(x) (((x) >> 0) & 0xFFFF) |
||
| 4522 | #define C_00B01C_CU_EN 0xFFFF0000 |
||
| 4523 | #define S_00B01C_WAVE_LIMIT(x) (((x) & 0x3F) << 16) |
||
| 4524 | #define G_00B01C_WAVE_LIMIT(x) (((x) >> 16) & 0x3F) |
||
| 4525 | #define C_00B01C_WAVE_LIMIT 0xFFC0FFFF |
||
| 4526 | #define S_00B01C_LOCK_LOW_THRESHOLD(x) (((x) & 0x0F) << 22) |
||
| 4527 | #define G_00B01C_LOCK_LOW_THRESHOLD(x) (((x) >> 22) & 0x0F) |
||
| 4528 | #define C_00B01C_LOCK_LOW_THRESHOLD 0xFC3FFFFF |
||
| 4529 | /* */ |
||
| 4530 | #define R_00B020_SPI_SHADER_PGM_LO_PS 0x00B020 |
||
| 4531 | #define R_00B024_SPI_SHADER_PGM_HI_PS 0x00B024 |
||
| 4532 | #define S_00B024_MEM_BASE(x) (((x) & 0xFF) << 0) |
||
| 4533 | #define G_00B024_MEM_BASE(x) (((x) >> 0) & 0xFF) |
||
| 4534 | #define C_00B024_MEM_BASE 0xFFFFFF00 |
||
| 4535 | #define R_00B028_SPI_SHADER_PGM_RSRC1_PS 0x00B028 |
||
| 4536 | #define S_00B028_VGPRS(x) (((x) & 0x3F) << 0) |
||
| 4537 | #define G_00B028_VGPRS(x) (((x) >> 0) & 0x3F) |
||
| 4538 | #define C_00B028_VGPRS 0xFFFFFFC0 |
||
| 4539 | #define S_00B028_SGPRS(x) (((x) & 0x0F) << 6) |
||
| 4540 | #define G_00B028_SGPRS(x) (((x) >> 6) & 0x0F) |
||
| 4541 | #define C_00B028_SGPRS 0xFFFFFC3F |
||
| 4542 | #define S_00B028_PRIORITY(x) (((x) & 0x03) << 10) |
||
| 4543 | #define G_00B028_PRIORITY(x) (((x) >> 10) & 0x03) |
||
| 4544 | #define C_00B028_PRIORITY 0xFFFFF3FF |
||
| 4545 | #define S_00B028_FLOAT_MODE(x) (((x) & 0xFF) << 12) |
||
| 4546 | #define G_00B028_FLOAT_MODE(x) (((x) >> 12) & 0xFF) |
||
| 4547 | #define C_00B028_FLOAT_MODE 0xFFF00FFF |
||
| 4548 | #define S_00B028_PRIV(x) (((x) & 0x1) << 20) |
||
| 4549 | #define G_00B028_PRIV(x) (((x) >> 20) & 0x1) |
||
| 4550 | #define C_00B028_PRIV 0xFFEFFFFF |
||
| 4551 | #define S_00B028_DX10_CLAMP(x) (((x) & 0x1) << 21) |
||
| 4552 | #define G_00B028_DX10_CLAMP(x) (((x) >> 21) & 0x1) |
||
| 4553 | #define C_00B028_DX10_CLAMP 0xFFDFFFFF |
||
| 4554 | #define S_00B028_DEBUG_MODE(x) (((x) & 0x1) << 22) |
||
| 4555 | #define G_00B028_DEBUG_MODE(x) (((x) >> 22) & 0x1) |
||
| 4556 | #define C_00B028_DEBUG_MODE 0xFFBFFFFF |
||
| 4557 | #define S_00B028_IEEE_MODE(x) (((x) & 0x1) << 23) |
||
| 4558 | #define G_00B028_IEEE_MODE(x) (((x) >> 23) & 0x1) |
||
| 4559 | #define C_00B028_IEEE_MODE 0xFF7FFFFF |
||
| 4560 | #define S_00B028_CU_GROUP_DISABLE(x) (((x) & 0x1) << 24) |
||
| 4561 | #define G_00B028_CU_GROUP_DISABLE(x) (((x) >> 24) & 0x1) |
||
| 4562 | #define C_00B028_CU_GROUP_DISABLE 0xFEFFFFFF |
||
| 4563 | /* CIK */ |
||
| 4564 | #define S_00B028_CACHE_CTL(x) (((x) & 0x07) << 25) |
||
| 4565 | #define G_00B028_CACHE_CTL(x) (((x) >> 25) & 0x07) |
||
| 4566 | #define C_00B028_CACHE_CTL 0xF1FFFFFF |
||
| 4567 | #define S_00B028_CDBG_USER(x) (((x) & 0x1) << 28) |
||
| 4568 | #define G_00B028_CDBG_USER(x) (((x) >> 28) & 0x1) |
||
| 4569 | #define C_00B028_CDBG_USER 0xEFFFFFFF |
||
| 4570 | /* */ |
||
| 4571 | #define R_00B02C_SPI_SHADER_PGM_RSRC2_PS 0x00B02C |
||
| 4572 | #define S_00B02C_SCRATCH_EN(x) (((x) & 0x1) << 0) |
||
| 4573 | #define G_00B02C_SCRATCH_EN(x) (((x) >> 0) & 0x1) |
||
| 4574 | #define C_00B02C_SCRATCH_EN 0xFFFFFFFE |
||
| 4575 | #define S_00B02C_USER_SGPR(x) (((x) & 0x1F) << 1) |
||
| 4576 | #define G_00B02C_USER_SGPR(x) (((x) >> 1) & 0x1F) |
||
| 4577 | #define C_00B02C_USER_SGPR 0xFFFFFFC1 |
||
| 4578 | #define S_00B02C_WAVE_CNT_EN(x) (((x) & 0x1) << 7) |
||
| 4579 | #define G_00B02C_WAVE_CNT_EN(x) (((x) >> 7) & 0x1) |
||
| 4580 | #define C_00B02C_WAVE_CNT_EN 0xFFFFFF7F |
||
| 4581 | #define S_00B02C_EXTRA_LDS_SIZE(x) (((x) & 0xFF) << 8) |
||
| 4582 | #define G_00B02C_EXTRA_LDS_SIZE(x) (((x) >> 8) & 0xFF) |
||
| 4583 | #define C_00B02C_EXTRA_LDS_SIZE 0xFFFF00FF |
||
| 4584 | #define S_00B02C_EXCP_EN(x) (((x) & 0x7F) << 16) /* mask is 0x1FF on CIK */ |
||
| 4585 | #define G_00B02C_EXCP_EN(x) (((x) >> 16) & 0x7F) /* mask is 0x1FF on CIK */ |
||
| 4586 | #define C_00B02C_EXCP_EN 0xFF80FFFF /* mask is 0x1FF on CIK */ |
||
| 4587 | #define R_00B030_SPI_SHADER_USER_DATA_PS_0 0x00B030 |
||
| 4588 | #define R_00B034_SPI_SHADER_USER_DATA_PS_1 0x00B034 |
||
| 4589 | #define R_00B038_SPI_SHADER_USER_DATA_PS_2 0x00B038 |
||
| 4590 | #define R_00B03C_SPI_SHADER_USER_DATA_PS_3 0x00B03C |
||
| 4591 | #define R_00B040_SPI_SHADER_USER_DATA_PS_4 0x00B040 |
||
| 4592 | #define R_00B044_SPI_SHADER_USER_DATA_PS_5 0x00B044 |
||
| 4593 | #define R_00B048_SPI_SHADER_USER_DATA_PS_6 0x00B048 |
||
| 4594 | #define R_00B04C_SPI_SHADER_USER_DATA_PS_7 0x00B04C |
||
| 4595 | #define R_00B050_SPI_SHADER_USER_DATA_PS_8 0x00B050 |
||
| 4596 | #define R_00B054_SPI_SHADER_USER_DATA_PS_9 0x00B054 |
||
| 4597 | #define R_00B058_SPI_SHADER_USER_DATA_PS_10 0x00B058 |
||
| 4598 | #define R_00B05C_SPI_SHADER_USER_DATA_PS_11 0x00B05C |
||
| 4599 | #define R_00B060_SPI_SHADER_USER_DATA_PS_12 0x00B060 |
||
| 4600 | #define R_00B064_SPI_SHADER_USER_DATA_PS_13 0x00B064 |
||
| 4601 | #define R_00B068_SPI_SHADER_USER_DATA_PS_14 0x00B068 |
||
| 4602 | #define R_00B06C_SPI_SHADER_USER_DATA_PS_15 0x00B06C |
||
| 4603 | /* CIK */ |
||
| 4604 | #define R_00B118_SPI_SHADER_PGM_RSRC3_VS 0x00B118 |
||
| 4605 | #define S_00B118_CU_EN(x) (((x) & 0xFFFF) << 0) |
||
| 4606 | #define G_00B118_CU_EN(x) (((x) >> 0) & 0xFFFF) |
||
| 4607 | #define C_00B118_CU_EN 0xFFFF0000 |
||
| 4608 | #define S_00B118_WAVE_LIMIT(x) (((x) & 0x3F) << 16) |
||
| 4609 | #define G_00B118_WAVE_LIMIT(x) (((x) >> 16) & 0x3F) |
||
| 4610 | #define C_00B118_WAVE_LIMIT 0xFFC0FFFF |
||
| 4611 | #define S_00B118_LOCK_LOW_THRESHOLD(x) (((x) & 0x0F) << 22) |
||
| 4612 | #define G_00B118_LOCK_LOW_THRESHOLD(x) (((x) >> 22) & 0x0F) |
||
| 4613 | #define C_00B118_LOCK_LOW_THRESHOLD 0xFC3FFFFF |
||
| 4614 | #define R_00B11C_SPI_SHADER_LATE_ALLOC_VS 0x00B11C |
||
| 4615 | #define S_00B11C_LIMIT(x) (((x) & 0x3F) << 0) |
||
| 4616 | #define G_00B11C_LIMIT(x) (((x) >> 0) & 0x3F) |
||
| 4617 | #define C_00B11C_LIMIT 0xFFFFFFC0 |
||
| 4618 | /* */ |
||
| 4619 | #define R_00B120_SPI_SHADER_PGM_LO_VS 0x00B120 |
||
| 4620 | #define R_00B124_SPI_SHADER_PGM_HI_VS 0x00B124 |
||
| 4621 | #define S_00B124_MEM_BASE(x) (((x) & 0xFF) << 0) |
||
| 4622 | #define G_00B124_MEM_BASE(x) (((x) >> 0) & 0xFF) |
||
| 4623 | #define C_00B124_MEM_BASE 0xFFFFFF00 |
||
| 4624 | #define R_00B128_SPI_SHADER_PGM_RSRC1_VS 0x00B128 |
||
| 4625 | #define S_00B128_VGPRS(x) (((x) & 0x3F) << 0) |
||
| 4626 | #define G_00B128_VGPRS(x) (((x) >> 0) & 0x3F) |
||
| 4627 | #define C_00B128_VGPRS 0xFFFFFFC0 |
||
| 4628 | #define S_00B128_SGPRS(x) (((x) & 0x0F) << 6) |
||
| 4629 | #define G_00B128_SGPRS(x) (((x) >> 6) & 0x0F) |
||
| 4630 | #define C_00B128_SGPRS 0xFFFFFC3F |
||
| 4631 | #define S_00B128_PRIORITY(x) (((x) & 0x03) << 10) |
||
| 4632 | #define G_00B128_PRIORITY(x) (((x) >> 10) & 0x03) |
||
| 4633 | #define C_00B128_PRIORITY 0xFFFFF3FF |
||
| 4634 | #define S_00B128_FLOAT_MODE(x) (((x) & 0xFF) << 12) |
||
| 4635 | #define G_00B128_FLOAT_MODE(x) (((x) >> 12) & 0xFF) |
||
| 4636 | #define C_00B128_FLOAT_MODE 0xFFF00FFF |
||
| 4637 | #define S_00B128_PRIV(x) (((x) & 0x1) << 20) |
||
| 4638 | #define G_00B128_PRIV(x) (((x) >> 20) & 0x1) |
||
| 4639 | #define C_00B128_PRIV 0xFFEFFFFF |
||
| 4640 | #define S_00B128_DX10_CLAMP(x) (((x) & 0x1) << 21) |
||
| 4641 | #define G_00B128_DX10_CLAMP(x) (((x) >> 21) & 0x1) |
||
| 4642 | #define C_00B128_DX10_CLAMP 0xFFDFFFFF |
||
| 4643 | #define S_00B128_DEBUG_MODE(x) (((x) & 0x1) << 22) |
||
| 4644 | #define G_00B128_DEBUG_MODE(x) (((x) >> 22) & 0x1) |
||
| 4645 | #define C_00B128_DEBUG_MODE 0xFFBFFFFF |
||
| 4646 | #define S_00B128_IEEE_MODE(x) (((x) & 0x1) << 23) |
||
| 4647 | #define G_00B128_IEEE_MODE(x) (((x) >> 23) & 0x1) |
||
| 4648 | #define C_00B128_IEEE_MODE 0xFF7FFFFF |
||
| 4649 | #define S_00B128_VGPR_COMP_CNT(x) (((x) & 0x03) << 24) |
||
| 4650 | #define G_00B128_VGPR_COMP_CNT(x) (((x) >> 24) & 0x03) |
||
| 4651 | #define C_00B128_VGPR_COMP_CNT 0xFCFFFFFF |
||
| 4652 | #define S_00B128_CU_GROUP_ENABLE(x) (((x) & 0x1) << 26) |
||
| 4653 | #define G_00B128_CU_GROUP_ENABLE(x) (((x) >> 26) & 0x1) |
||
| 4654 | #define C_00B128_CU_GROUP_ENABLE 0xFBFFFFFF |
||
| 4655 | /* CIK */ |
||
| 4656 | #define S_00B128_CACHE_CTL(x) (((x) & 0x07) << 27) |
||
| 4657 | #define G_00B128_CACHE_CTL(x) (((x) >> 27) & 0x07) |
||
| 4658 | #define C_00B128_CACHE_CTL 0xC7FFFFFF |
||
| 4659 | #define S_00B128_CDBG_USER(x) (((x) & 0x1) << 30) |
||
| 4660 | #define G_00B128_CDBG_USER(x) (((x) >> 30) & 0x1) |
||
| 4661 | #define C_00B128_CDBG_USER 0xBFFFFFFF |
||
| 4662 | /* */ |
||
| 4663 | #define R_00B12C_SPI_SHADER_PGM_RSRC2_VS 0x00B12C |
||
| 4664 | #define S_00B12C_SCRATCH_EN(x) (((x) & 0x1) << 0) |
||
| 4665 | #define G_00B12C_SCRATCH_EN(x) (((x) >> 0) & 0x1) |
||
| 4666 | #define C_00B12C_SCRATCH_EN 0xFFFFFFFE |
||
| 4667 | #define S_00B12C_USER_SGPR(x) (((x) & 0x1F) << 1) |
||
| 4668 | #define G_00B12C_USER_SGPR(x) (((x) >> 1) & 0x1F) |
||
| 4669 | #define C_00B12C_USER_SGPR 0xFFFFFFC1 |
||
| 4670 | #define S_00B12C_OC_LDS_EN(x) (((x) & 0x1) << 7) |
||
| 4671 | #define G_00B12C_OC_LDS_EN(x) (((x) >> 7) & 0x1) |
||
| 4672 | #define C_00B12C_OC_LDS_EN 0xFFFFFF7F |
||
| 4673 | #define S_00B12C_SO_BASE0_EN(x) (((x) & 0x1) << 8) |
||
| 4674 | #define G_00B12C_SO_BASE0_EN(x) (((x) >> 8) & 0x1) |
||
| 4675 | #define C_00B12C_SO_BASE0_EN 0xFFFFFEFF |
||
| 4676 | #define S_00B12C_SO_BASE1_EN(x) (((x) & 0x1) << 9) |
||
| 4677 | #define G_00B12C_SO_BASE1_EN(x) (((x) >> 9) & 0x1) |
||
| 4678 | #define C_00B12C_SO_BASE1_EN 0xFFFFFDFF |
||
| 4679 | #define S_00B12C_SO_BASE2_EN(x) (((x) & 0x1) << 10) |
||
| 4680 | #define G_00B12C_SO_BASE2_EN(x) (((x) >> 10) & 0x1) |
||
| 4681 | #define C_00B12C_SO_BASE2_EN 0xFFFFFBFF |
||
| 4682 | #define S_00B12C_SO_BASE3_EN(x) (((x) & 0x1) << 11) |
||
| 4683 | #define G_00B12C_SO_BASE3_EN(x) (((x) >> 11) & 0x1) |
||
| 4684 | #define C_00B12C_SO_BASE3_EN 0xFFFFF7FF |
||
| 4685 | #define S_00B12C_SO_EN(x) (((x) & 0x1) << 12) |
||
| 4686 | #define G_00B12C_SO_EN(x) (((x) >> 12) & 0x1) |
||
| 4687 | #define C_00B12C_SO_EN 0xFFFFEFFF |
||
| 4688 | #define S_00B12C_EXCP_EN(x) (((x) & 0x7F) << 13) /* mask is 0x1FF on CIK */ |
||
| 4689 | #define G_00B12C_EXCP_EN(x) (((x) >> 13) & 0x7F) /* mask is 0x1FF on CIK */ |
||
| 4690 | #define C_00B12C_EXCP_EN 0xFFF01FFF /* mask is 0x1FF on CIK */ |
||
| 4691 | #define R_00B130_SPI_SHADER_USER_DATA_VS_0 0x00B130 |
||
| 4692 | #define R_00B134_SPI_SHADER_USER_DATA_VS_1 0x00B134 |
||
| 4693 | #define R_00B138_SPI_SHADER_USER_DATA_VS_2 0x00B138 |
||
| 4694 | #define R_00B13C_SPI_SHADER_USER_DATA_VS_3 0x00B13C |
||
| 4695 | #define R_00B140_SPI_SHADER_USER_DATA_VS_4 0x00B140 |
||
| 4696 | #define R_00B144_SPI_SHADER_USER_DATA_VS_5 0x00B144 |
||
| 4697 | #define R_00B148_SPI_SHADER_USER_DATA_VS_6 0x00B148 |
||
| 4698 | #define R_00B14C_SPI_SHADER_USER_DATA_VS_7 0x00B14C |
||
| 4699 | #define R_00B150_SPI_SHADER_USER_DATA_VS_8 0x00B150 |
||
| 4700 | #define R_00B154_SPI_SHADER_USER_DATA_VS_9 0x00B154 |
||
| 4701 | #define R_00B158_SPI_SHADER_USER_DATA_VS_10 0x00B158 |
||
| 4702 | #define R_00B15C_SPI_SHADER_USER_DATA_VS_11 0x00B15C |
||
| 4703 | #define R_00B160_SPI_SHADER_USER_DATA_VS_12 0x00B160 |
||
| 4704 | #define R_00B164_SPI_SHADER_USER_DATA_VS_13 0x00B164 |
||
| 4705 | #define R_00B168_SPI_SHADER_USER_DATA_VS_14 0x00B168 |
||
| 4706 | #define R_00B16C_SPI_SHADER_USER_DATA_VS_15 0x00B16C |
||
| 4707 | /* CIK */ |
||
| 4708 | #define R_00B21C_SPI_SHADER_PGM_RSRC3_GS 0x00B21C |
||
| 4709 | #define S_00B21C_CU_EN(x) (((x) & 0xFFFF) << 0) |
||
| 4710 | #define G_00B21C_CU_EN(x) (((x) >> 0) & 0xFFFF) |
||
| 4711 | #define C_00B21C_CU_EN 0xFFFF0000 |
||
| 4712 | #define S_00B21C_WAVE_LIMIT(x) (((x) & 0x3F) << 16) |
||
| 4713 | #define G_00B21C_WAVE_LIMIT(x) (((x) >> 16) & 0x3F) |
||
| 4714 | #define C_00B21C_WAVE_LIMIT 0xFFC0FFFF |
||
| 4715 | #define S_00B21C_LOCK_LOW_THRESHOLD(x) (((x) & 0x0F) << 22) |
||
| 4716 | #define G_00B21C_LOCK_LOW_THRESHOLD(x) (((x) >> 22) & 0x0F) |
||
| 4717 | #define C_00B21C_LOCK_LOW_THRESHOLD 0xFC3FFFFF |
||
| 4718 | /* */ |
||
| 4719 | #define R_00B220_SPI_SHADER_PGM_LO_GS 0x00B220 |
||
| 4720 | #define R_00B224_SPI_SHADER_PGM_HI_GS 0x00B224 |
||
| 4721 | #define S_00B224_MEM_BASE(x) (((x) & 0xFF) << 0) |
||
| 4722 | #define G_00B224_MEM_BASE(x) (((x) >> 0) & 0xFF) |
||
| 4723 | #define C_00B224_MEM_BASE 0xFFFFFF00 |
||
| 4724 | #define R_00B228_SPI_SHADER_PGM_RSRC1_GS 0x00B228 |
||
| 4725 | #define S_00B228_VGPRS(x) (((x) & 0x3F) << 0) |
||
| 4726 | #define G_00B228_VGPRS(x) (((x) >> 0) & 0x3F) |
||
| 4727 | #define C_00B228_VGPRS 0xFFFFFFC0 |
||
| 4728 | #define S_00B228_SGPRS(x) (((x) & 0x0F) << 6) |
||
| 4729 | #define G_00B228_SGPRS(x) (((x) >> 6) & 0x0F) |
||
| 4730 | #define C_00B228_SGPRS 0xFFFFFC3F |
||
| 4731 | #define S_00B228_PRIORITY(x) (((x) & 0x03) << 10) |
||
| 4732 | #define G_00B228_PRIORITY(x) (((x) >> 10) & 0x03) |
||
| 4733 | #define C_00B228_PRIORITY 0xFFFFF3FF |
||
| 4734 | #define S_00B228_FLOAT_MODE(x) (((x) & 0xFF) << 12) |
||
| 4735 | #define G_00B228_FLOAT_MODE(x) (((x) >> 12) & 0xFF) |
||
| 4736 | #define C_00B228_FLOAT_MODE 0xFFF00FFF |
||
| 4737 | #define S_00B228_PRIV(x) (((x) & 0x1) << 20) |
||
| 4738 | #define G_00B228_PRIV(x) (((x) >> 20) & 0x1) |
||
| 4739 | #define C_00B228_PRIV 0xFFEFFFFF |
||
| 4740 | #define S_00B228_DX10_CLAMP(x) (((x) & 0x1) << 21) |
||
| 4741 | #define G_00B228_DX10_CLAMP(x) (((x) >> 21) & 0x1) |
||
| 4742 | #define C_00B228_DX10_CLAMP 0xFFDFFFFF |
||
| 4743 | #define S_00B228_DEBUG_MODE(x) (((x) & 0x1) << 22) |
||
| 4744 | #define G_00B228_DEBUG_MODE(x) (((x) >> 22) & 0x1) |
||
| 4745 | #define C_00B228_DEBUG_MODE 0xFFBFFFFF |
||
| 4746 | #define S_00B228_IEEE_MODE(x) (((x) & 0x1) << 23) |
||
| 4747 | #define G_00B228_IEEE_MODE(x) (((x) >> 23) & 0x1) |
||
| 4748 | #define C_00B228_IEEE_MODE 0xFF7FFFFF |
||
| 4749 | #define S_00B228_CU_GROUP_ENABLE(x) (((x) & 0x1) << 24) |
||
| 4750 | #define G_00B228_CU_GROUP_ENABLE(x) (((x) >> 24) & 0x1) |
||
| 4751 | #define C_00B228_CU_GROUP_ENABLE 0xFEFFFFFF |
||
| 4752 | /* CIK */ |
||
| 4753 | #define S_00B228_CACHE_CTL(x) (((x) & 0x07) << 25) |
||
| 4754 | #define G_00B228_CACHE_CTL(x) (((x) >> 25) & 0x07) |
||
| 4755 | #define C_00B228_CACHE_CTL 0xF1FFFFFF |
||
| 4756 | #define S_00B228_CDBG_USER(x) (((x) & 0x1) << 28) |
||
| 4757 | #define G_00B228_CDBG_USER(x) (((x) >> 28) & 0x1) |
||
| 4758 | #define C_00B228_CDBG_USER 0xEFFFFFFF |
||
| 4759 | /* */ |
||
| 4760 | #define R_00B22C_SPI_SHADER_PGM_RSRC2_GS 0x00B22C |
||
| 4761 | #define S_00B22C_SCRATCH_EN(x) (((x) & 0x1) << 0) |
||
| 4762 | #define G_00B22C_SCRATCH_EN(x) (((x) >> 0) & 0x1) |
||
| 4763 | #define C_00B22C_SCRATCH_EN 0xFFFFFFFE |
||
| 4764 | #define S_00B22C_USER_SGPR(x) (((x) & 0x1F) << 1) |
||
| 4765 | #define G_00B22C_USER_SGPR(x) (((x) >> 1) & 0x1F) |
||
| 4766 | #define C_00B22C_USER_SGPR 0xFFFFFFC1 |
||
| 4767 | #define S_00B22C_EXCP_EN(x) (((x) & 0x7F) << 7) /* mask is 0x1FF on CIK */ |
||
| 4768 | #define G_00B22C_EXCP_EN(x) (((x) >> 7) & 0x7F) /* mask is 0x1FF on CIK */ |
||
| 4769 | #define C_00B22C_EXCP_EN 0xFFFFC07F /* mask is 0x1FF on CIK */ |
||
| 4770 | #define R_00B230_SPI_SHADER_USER_DATA_GS_0 0x00B230 |
||
| 4771 | /* CIK */ |
||
| 4772 | #define R_00B31C_SPI_SHADER_PGM_RSRC3_ES 0x00B31C |
||
| 4773 | #define S_00B31C_CU_EN(x) (((x) & 0xFFFF) << 0) |
||
| 4774 | #define G_00B31C_CU_EN(x) (((x) >> 0) & 0xFFFF) |
||
| 4775 | #define C_00B31C_CU_EN 0xFFFF0000 |
||
| 4776 | #define S_00B31C_WAVE_LIMIT(x) (((x) & 0x3F) << 16) |
||
| 4777 | #define G_00B31C_WAVE_LIMIT(x) (((x) >> 16) & 0x3F) |
||
| 4778 | #define C_00B31C_WAVE_LIMIT 0xFFC0FFFF |
||
| 4779 | #define S_00B31C_LOCK_LOW_THRESHOLD(x) (((x) & 0x0F) << 22) |
||
| 4780 | #define G_00B31C_LOCK_LOW_THRESHOLD(x) (((x) >> 22) & 0x0F) |
||
| 4781 | #define C_00B31C_LOCK_LOW_THRESHOLD 0xFC3FFFFF |
||
| 4782 | /* */ |
||
| 4783 | #define R_00B320_SPI_SHADER_PGM_LO_ES 0x00B320 |
||
| 4784 | #define R_00B324_SPI_SHADER_PGM_HI_ES 0x00B324 |
||
| 4785 | #define S_00B324_MEM_BASE(x) (((x) & 0xFF) << 0) |
||
| 4786 | #define G_00B324_MEM_BASE(x) (((x) >> 0) & 0xFF) |
||
| 4787 | #define C_00B324_MEM_BASE 0xFFFFFF00 |
||
| 4788 | #define R_00B328_SPI_SHADER_PGM_RSRC1_ES 0x00B328 |
||
| 4789 | #define S_00B328_VGPRS(x) (((x) & 0x3F) << 0) |
||
| 4790 | #define G_00B328_VGPRS(x) (((x) >> 0) & 0x3F) |
||
| 4791 | #define C_00B328_VGPRS 0xFFFFFFC0 |
||
| 4792 | #define S_00B328_SGPRS(x) (((x) & 0x0F) << 6) |
||
| 4793 | #define G_00B328_SGPRS(x) (((x) >> 6) & 0x0F) |
||
| 4794 | #define C_00B328_SGPRS 0xFFFFFC3F |
||
| 4795 | #define S_00B328_PRIORITY(x) (((x) & 0x03) << 10) |
||
| 4796 | #define G_00B328_PRIORITY(x) (((x) >> 10) & 0x03) |
||
| 4797 | #define C_00B328_PRIORITY 0xFFFFF3FF |
||
| 4798 | #define S_00B328_FLOAT_MODE(x) (((x) & 0xFF) << 12) |
||
| 4799 | #define G_00B328_FLOAT_MODE(x) (((x) >> 12) & 0xFF) |
||
| 4800 | #define C_00B328_FLOAT_MODE 0xFFF00FFF |
||
| 4801 | #define S_00B328_PRIV(x) (((x) & 0x1) << 20) |
||
| 4802 | #define G_00B328_PRIV(x) (((x) >> 20) & 0x1) |
||
| 4803 | #define C_00B328_PRIV 0xFFEFFFFF |
||
| 4804 | #define S_00B328_DX10_CLAMP(x) (((x) & 0x1) << 21) |
||
| 4805 | #define G_00B328_DX10_CLAMP(x) (((x) >> 21) & 0x1) |
||
| 4806 | #define C_00B328_DX10_CLAMP 0xFFDFFFFF |
||
| 4807 | #define S_00B328_DEBUG_MODE(x) (((x) & 0x1) << 22) |
||
| 4808 | #define G_00B328_DEBUG_MODE(x) (((x) >> 22) & 0x1) |
||
| 4809 | #define C_00B328_DEBUG_MODE 0xFFBFFFFF |
||
| 4810 | #define S_00B328_IEEE_MODE(x) (((x) & 0x1) << 23) |
||
| 4811 | #define G_00B328_IEEE_MODE(x) (((x) >> 23) & 0x1) |
||
| 4812 | #define C_00B328_IEEE_MODE 0xFF7FFFFF |
||
| 4813 | #define S_00B328_VGPR_COMP_CNT(x) (((x) & 0x03) << 24) |
||
| 4814 | #define G_00B328_VGPR_COMP_CNT(x) (((x) >> 24) & 0x03) |
||
| 4815 | #define C_00B328_VGPR_COMP_CNT 0xFCFFFFFF |
||
| 4816 | #define S_00B328_CU_GROUP_ENABLE(x) (((x) & 0x1) << 26) |
||
| 4817 | #define G_00B328_CU_GROUP_ENABLE(x) (((x) >> 26) & 0x1) |
||
| 4818 | #define C_00B328_CU_GROUP_ENABLE 0xFBFFFFFF |
||
| 4819 | /* CIK */ |
||
| 4820 | #define S_00B328_CACHE_CTL(x) (((x) & 0x07) << 27) |
||
| 4821 | #define G_00B328_CACHE_CTL(x) (((x) >> 27) & 0x07) |
||
| 4822 | #define C_00B328_CACHE_CTL 0xC7FFFFFF |
||
| 4823 | #define S_00B328_CDBG_USER(x) (((x) & 0x1) << 30) |
||
| 4824 | #define G_00B328_CDBG_USER(x) (((x) >> 30) & 0x1) |
||
| 4825 | #define C_00B328_CDBG_USER 0xBFFFFFFF |
||
| 4826 | /* */ |
||
| 4827 | #define R_00B32C_SPI_SHADER_PGM_RSRC2_ES 0x00B32C |
||
| 4828 | #define S_00B32C_SCRATCH_EN(x) (((x) & 0x1) << 0) |
||
| 4829 | #define G_00B32C_SCRATCH_EN(x) (((x) >> 0) & 0x1) |
||
| 4830 | #define C_00B32C_SCRATCH_EN 0xFFFFFFFE |
||
| 4831 | #define S_00B32C_USER_SGPR(x) (((x) & 0x1F) << 1) |
||
| 4832 | #define G_00B32C_USER_SGPR(x) (((x) >> 1) & 0x1F) |
||
| 4833 | #define C_00B32C_USER_SGPR 0xFFFFFFC1 |
||
| 4834 | #define S_00B32C_OC_LDS_EN(x) (((x) & 0x1) << 7) |
||
| 4835 | #define G_00B32C_OC_LDS_EN(x) (((x) >> 7) & 0x1) |
||
| 4836 | #define C_00B32C_OC_LDS_EN 0xFFFFFF7F |
||
| 4837 | #define S_00B32C_EXCP_EN(x) (((x) & 0x7F) << 8) /* mask is 0x1FF on CIK */ |
||
| 4838 | #define G_00B32C_EXCP_EN(x) (((x) >> 8) & 0x7F) /* mask is 0x1FF on CIK */ |
||
| 4839 | #define C_00B32C_EXCP_EN 0xFFFF80FF /* mask is 0x1FF on CIK */ |
||
| 4840 | #define S_00B32C_LDS_SIZE(x) (((x) & 0x1FF) << 20) /* CIK, for on-chip GS */ |
||
| 4841 | #define G_00B32C_LDS_SIZE(x) (((x) >> 20) & 0x1FF) /* CIK, for on-chip GS */ |
||
| 4842 | #define C_00B32C_LDS_SIZE 0xE00FFFFF /* CIK, for on-chip GS */ |
||
| 4843 | #define R_00B330_SPI_SHADER_USER_DATA_ES_0 0x00B330 |
||
| 4844 | /* CIK */ |
||
| 4845 | #define R_00B41C_SPI_SHADER_PGM_RSRC3_HS 0x00B41C |
||
| 4846 | #define S_00B41C_WAVE_LIMIT(x) (((x) & 0x3F) << 0) |
||
| 4847 | #define G_00B41C_WAVE_LIMIT(x) (((x) >> 0) & 0x3F) |
||
| 4848 | #define C_00B41C_WAVE_LIMIT 0xFFFFFFC0 |
||
| 4849 | #define S_00B41C_LOCK_LOW_THRESHOLD(x) (((x) & 0x0F) << 6) |
||
| 4850 | #define G_00B41C_LOCK_LOW_THRESHOLD(x) (((x) >> 6) & 0x0F) |
||
| 4851 | #define C_00B41C_LOCK_LOW_THRESHOLD 0xFFFFFC3F |
||
| 4852 | /* */ |
||
| 4853 | #define R_00B420_SPI_SHADER_PGM_LO_HS 0x00B420 |
||
| 4854 | #define R_00B424_SPI_SHADER_PGM_HI_HS 0x00B424 |
||
| 4855 | #define S_00B424_MEM_BASE(x) (((x) & 0xFF) << 0) |
||
| 4856 | #define G_00B424_MEM_BASE(x) (((x) >> 0) & 0xFF) |
||
| 4857 | #define C_00B424_MEM_BASE 0xFFFFFF00 |
||
| 4858 | #define R_00B428_SPI_SHADER_PGM_RSRC1_HS 0x00B428 |
||
| 4859 | #define S_00B428_VGPRS(x) (((x) & 0x3F) << 0) |
||
| 4860 | #define G_00B428_VGPRS(x) (((x) >> 0) & 0x3F) |
||
| 4861 | #define C_00B428_VGPRS 0xFFFFFFC0 |
||
| 4862 | #define S_00B428_SGPRS(x) (((x) & 0x0F) << 6) |
||
| 4863 | #define G_00B428_SGPRS(x) (((x) >> 6) & 0x0F) |
||
| 4864 | #define C_00B428_SGPRS 0xFFFFFC3F |
||
| 4865 | #define S_00B428_PRIORITY(x) (((x) & 0x03) << 10) |
||
| 4866 | #define G_00B428_PRIORITY(x) (((x) >> 10) & 0x03) |
||
| 4867 | #define C_00B428_PRIORITY 0xFFFFF3FF |
||
| 4868 | #define S_00B428_FLOAT_MODE(x) (((x) & 0xFF) << 12) |
||
| 4869 | #define G_00B428_FLOAT_MODE(x) (((x) >> 12) & 0xFF) |
||
| 4870 | #define C_00B428_FLOAT_MODE 0xFFF00FFF |
||
| 4871 | #define S_00B428_PRIV(x) (((x) & 0x1) << 20) |
||
| 4872 | #define G_00B428_PRIV(x) (((x) >> 20) & 0x1) |
||
| 4873 | #define C_00B428_PRIV 0xFFEFFFFF |
||
| 4874 | #define S_00B428_DX10_CLAMP(x) (((x) & 0x1) << 21) |
||
| 4875 | #define G_00B428_DX10_CLAMP(x) (((x) >> 21) & 0x1) |
||
| 4876 | #define C_00B428_DX10_CLAMP 0xFFDFFFFF |
||
| 4877 | #define S_00B428_DEBUG_MODE(x) (((x) & 0x1) << 22) |
||
| 4878 | #define G_00B428_DEBUG_MODE(x) (((x) >> 22) & 0x1) |
||
| 4879 | #define C_00B428_DEBUG_MODE 0xFFBFFFFF |
||
| 4880 | #define S_00B428_IEEE_MODE(x) (((x) & 0x1) << 23) |
||
| 4881 | #define G_00B428_IEEE_MODE(x) (((x) >> 23) & 0x1) |
||
| 4882 | #define C_00B428_IEEE_MODE 0xFF7FFFFF |
||
| 4883 | /* CIK */ |
||
| 4884 | #define S_00B428_CACHE_CTL(x) (((x) & 0x07) << 24) |
||
| 4885 | #define G_00B428_CACHE_CTL(x) (((x) >> 24) & 0x07) |
||
| 4886 | #define C_00B428_CACHE_CTL 0xF8FFFFFF |
||
| 4887 | #define S_00B428_CDBG_USER(x) (((x) & 0x1) << 27) |
||
| 4888 | #define G_00B428_CDBG_USER(x) (((x) >> 27) & 0x1) |
||
| 4889 | #define C_00B428_CDBG_USER 0xF7FFFFFF |
||
| 4890 | /* */ |
||
| 4891 | #define R_00B42C_SPI_SHADER_PGM_RSRC2_HS 0x00B42C |
||
| 4892 | #define S_00B42C_SCRATCH_EN(x) (((x) & 0x1) << 0) |
||
| 4893 | #define G_00B42C_SCRATCH_EN(x) (((x) >> 0) & 0x1) |
||
| 4894 | #define C_00B42C_SCRATCH_EN 0xFFFFFFFE |
||
| 4895 | #define S_00B42C_USER_SGPR(x) (((x) & 0x1F) << 1) |
||
| 4896 | #define G_00B42C_USER_SGPR(x) (((x) >> 1) & 0x1F) |
||
| 4897 | #define C_00B42C_USER_SGPR 0xFFFFFFC1 |
||
| 4898 | #define S_00B42C_OC_LDS_EN(x) (((x) & 0x1) << 7) |
||
| 4899 | #define G_00B42C_OC_LDS_EN(x) (((x) >> 7) & 0x1) |
||
| 4900 | #define C_00B42C_OC_LDS_EN 0xFFFFFF7F |
||
| 4901 | #define S_00B42C_TG_SIZE_EN(x) (((x) & 0x1) << 8) |
||
| 4902 | #define G_00B42C_TG_SIZE_EN(x) (((x) >> 8) & 0x1) |
||
| 4903 | #define C_00B42C_TG_SIZE_EN 0xFFFFFEFF |
||
| 4904 | #define S_00B42C_EXCP_EN(x) (((x) & 0x7F) << 9) /* mask is 0x1FF on CIK */ |
||
| 4905 | #define G_00B42C_EXCP_EN(x) (((x) >> 9) & 0x7F) /* mask is 0x1FF on CIK */ |
||
| 4906 | #define C_00B42C_EXCP_EN 0xFFFF01FF /* mask is 0x1FF on CIK */ |
||
| 4907 | #define R_00B430_SPI_SHADER_USER_DATA_HS_0 0x00B430 |
||
| 4908 | /* CIK */ |
||
| 4909 | #define R_00B51C_SPI_SHADER_PGM_RSRC3_LS 0x00B51C |
||
| 4910 | #define S_00B51C_CU_EN(x) (((x) & 0xFFFF) << 0) |
||
| 4911 | #define G_00B51C_CU_EN(x) (((x) >> 0) & 0xFFFF) |
||
| 4912 | #define C_00B51C_CU_EN 0xFFFF0000 |
||
| 4913 | #define S_00B51C_WAVE_LIMIT(x) (((x) & 0x3F) << 16) |
||
| 4914 | #define G_00B51C_WAVE_LIMIT(x) (((x) >> 16) & 0x3F) |
||
| 4915 | #define C_00B51C_WAVE_LIMIT 0xFFC0FFFF |
||
| 4916 | #define S_00B51C_LOCK_LOW_THRESHOLD(x) (((x) & 0x0F) << 22) |
||
| 4917 | #define G_00B51C_LOCK_LOW_THRESHOLD(x) (((x) >> 22) & 0x0F) |
||
| 4918 | #define C_00B51C_LOCK_LOW_THRESHOLD 0xFC3FFFFF |
||
| 4919 | /* */ |
||
| 4920 | #define R_00B520_SPI_SHADER_PGM_LO_LS 0x00B520 |
||
| 4921 | #define R_00B524_SPI_SHADER_PGM_HI_LS 0x00B524 |
||
| 4922 | #define S_00B524_MEM_BASE(x) (((x) & 0xFF) << 0) |
||
| 4923 | #define G_00B524_MEM_BASE(x) (((x) >> 0) & 0xFF) |
||
| 4924 | #define C_00B524_MEM_BASE 0xFFFFFF00 |
||
| 4925 | #define R_00B528_SPI_SHADER_PGM_RSRC1_LS 0x00B528 |
||
| 4926 | #define S_00B528_VGPRS(x) (((x) & 0x3F) << 0) |
||
| 4927 | #define G_00B528_VGPRS(x) (((x) >> 0) & 0x3F) |
||
| 4928 | #define C_00B528_VGPRS 0xFFFFFFC0 |
||
| 4929 | #define S_00B528_SGPRS(x) (((x) & 0x0F) << 6) |
||
| 4930 | #define G_00B528_SGPRS(x) (((x) >> 6) & 0x0F) |
||
| 4931 | #define C_00B528_SGPRS 0xFFFFFC3F |
||
| 4932 | #define S_00B528_PRIORITY(x) (((x) & 0x03) << 10) |
||
| 4933 | #define G_00B528_PRIORITY(x) (((x) >> 10) & 0x03) |
||
| 4934 | #define C_00B528_PRIORITY 0xFFFFF3FF |
||
| 4935 | #define S_00B528_FLOAT_MODE(x) (((x) & 0xFF) << 12) |
||
| 4936 | #define G_00B528_FLOAT_MODE(x) (((x) >> 12) & 0xFF) |
||
| 4937 | #define C_00B528_FLOAT_MODE 0xFFF00FFF |
||
| 4938 | #define S_00B528_PRIV(x) (((x) & 0x1) << 20) |
||
| 4939 | #define G_00B528_PRIV(x) (((x) >> 20) & 0x1) |
||
| 4940 | #define C_00B528_PRIV 0xFFEFFFFF |
||
| 4941 | #define S_00B528_DX10_CLAMP(x) (((x) & 0x1) << 21) |
||
| 4942 | #define G_00B528_DX10_CLAMP(x) (((x) >> 21) & 0x1) |
||
| 4943 | #define C_00B528_DX10_CLAMP 0xFFDFFFFF |
||
| 4944 | #define S_00B528_DEBUG_MODE(x) (((x) & 0x1) << 22) |
||
| 4945 | #define G_00B528_DEBUG_MODE(x) (((x) >> 22) & 0x1) |
||
| 4946 | #define C_00B528_DEBUG_MODE 0xFFBFFFFF |
||
| 4947 | #define S_00B528_IEEE_MODE(x) (((x) & 0x1) << 23) |
||
| 4948 | #define G_00B528_IEEE_MODE(x) (((x) >> 23) & 0x1) |
||
| 4949 | #define C_00B528_IEEE_MODE 0xFF7FFFFF |
||
| 4950 | #define S_00B528_VGPR_COMP_CNT(x) (((x) & 0x03) << 24) |
||
| 4951 | #define G_00B528_VGPR_COMP_CNT(x) (((x) >> 24) & 0x03) |
||
| 4952 | #define C_00B528_VGPR_COMP_CNT 0xFCFFFFFF |
||
| 4953 | /* CIK */ |
||
| 4954 | #define S_00B528_CACHE_CTL(x) (((x) & 0x07) << 26) |
||
| 4955 | #define G_00B528_CACHE_CTL(x) (((x) >> 26) & 0x07) |
||
| 4956 | #define C_00B528_CACHE_CTL 0xE3FFFFFF |
||
| 4957 | #define S_00B528_CDBG_USER(x) (((x) & 0x1) << 29) |
||
| 4958 | #define G_00B528_CDBG_USER(x) (((x) >> 29) & 0x1) |
||
| 4959 | #define C_00B528_CDBG_USER 0xDFFFFFFF |
||
| 4960 | /* */ |
||
| 4961 | #define R_00B52C_SPI_SHADER_PGM_RSRC2_LS 0x00B52C |
||
| 4962 | #define S_00B52C_SCRATCH_EN(x) (((x) & 0x1) << 0) |
||
| 4963 | #define G_00B52C_SCRATCH_EN(x) (((x) >> 0) & 0x1) |
||
| 4964 | #define C_00B52C_SCRATCH_EN 0xFFFFFFFE |
||
| 4965 | #define S_00B52C_USER_SGPR(x) (((x) & 0x1F) << 1) |
||
| 4966 | #define G_00B52C_USER_SGPR(x) (((x) >> 1) & 0x1F) |
||
| 4967 | #define C_00B52C_USER_SGPR 0xFFFFFFC1 |
||
| 4968 | #define S_00B52C_LDS_SIZE(x) (((x) & 0x1FF) << 7) |
||
| 4969 | #define G_00B52C_LDS_SIZE(x) (((x) >> 7) & 0x1FF) |
||
| 4970 | #define C_00B52C_LDS_SIZE 0xFFFF007F |
||
| 4971 | #define S_00B52C_EXCP_EN(x) (((x) & 0x7F) << 16) /* mask is 0x1FF on CIK */ |
||
| 4972 | #define G_00B52C_EXCP_EN(x) (((x) >> 16) & 0x7F) /* mask is 0x1FF on CIK */ |
||
| 4973 | #define C_00B52C_EXCP_EN 0xFF80FFFF /* mask is 0x1FF on CIK */ |
||
| 4974 | #define R_00B530_SPI_SHADER_USER_DATA_LS_0 0x00B530 |
||
| 4975 | #define R_00B800_COMPUTE_DISPATCH_INITIATOR 0x00B800 |
||
| 4976 | #define S_00B800_COMPUTE_SHADER_EN(x) (((x) & 0x1) << 0) |
||
| 4977 | #define G_00B800_COMPUTE_SHADER_EN(x) (((x) >> 0) & 0x1) |
||
| 4978 | #define C_00B800_COMPUTE_SHADER_EN 0xFFFFFFFE |
||
| 4979 | #define S_00B800_PARTIAL_TG_EN(x) (((x) & 0x1) << 1) |
||
| 4980 | #define G_00B800_PARTIAL_TG_EN(x) (((x) >> 1) & 0x1) |
||
| 4981 | #define C_00B800_PARTIAL_TG_EN 0xFFFFFFFD |
||
| 4982 | #define S_00B800_FORCE_START_AT_000(x) (((x) & 0x1) << 2) |
||
| 4983 | #define G_00B800_FORCE_START_AT_000(x) (((x) >> 2) & 0x1) |
||
| 4984 | #define C_00B800_FORCE_START_AT_000 0xFFFFFFFB |
||
| 4985 | #define S_00B800_ORDERED_APPEND_ENBL(x) (((x) & 0x1) << 3) |
||
| 4986 | #define G_00B800_ORDERED_APPEND_ENBL(x) (((x) >> 3) & 0x1) |
||
| 4987 | #define C_00B800_ORDERED_APPEND_ENBL 0xFFFFFFF7 |
||
| 4988 | /* CIK */ |
||
| 4989 | #define S_00B800_ORDERED_APPEND_MODE(x) (((x) & 0x1) << 4) |
||
| 4990 | #define G_00B800_ORDERED_APPEND_MODE(x) (((x) >> 4) & 0x1) |
||
| 4991 | #define C_00B800_ORDERED_APPEND_MODE 0xFFFFFFEF |
||
| 4992 | #define S_00B800_USE_THREAD_DIMENSIONS(x) (((x) & 0x1) << 5) |
||
| 4993 | #define G_00B800_USE_THREAD_DIMENSIONS(x) (((x) >> 5) & 0x1) |
||
| 4994 | #define C_00B800_USE_THREAD_DIMENSIONS 0xFFFFFFDF |
||
| 4995 | #define S_00B800_ORDER_MODE(x) (((x) & 0x1) << 6) |
||
| 4996 | #define G_00B800_ORDER_MODE(x) (((x) >> 6) & 0x1) |
||
| 4997 | #define C_00B800_ORDER_MODE 0xFFFFFFBF |
||
| 4998 | #define S_00B800_DISPATCH_CACHE_CNTL(x) (((x) & 0x07) << 7) |
||
| 4999 | #define G_00B800_DISPATCH_CACHE_CNTL(x) (((x) >> 7) & 0x07) |
||
| 5000 | #define C_00B800_DISPATCH_CACHE_CNTL 0xFFFFFC7F |
||
| 5001 | #define S_00B800_SCALAR_L1_INV_VOL(x) (((x) & 0x1) << 10) |
||
| 5002 | #define G_00B800_SCALAR_L1_INV_VOL(x) (((x) >> 10) & 0x1) |
||
| 5003 | #define C_00B800_SCALAR_L1_INV_VOL 0xFFFFFBFF |
||
| 5004 | #define S_00B800_VECTOR_L1_INV_VOL(x) (((x) & 0x1) << 11) |
||
| 5005 | #define G_00B800_VECTOR_L1_INV_VOL(x) (((x) >> 11) & 0x1) |
||
| 5006 | #define C_00B800_VECTOR_L1_INV_VOL 0xFFFFF7FF |
||
| 5007 | #define S_00B800_DATA_ATC(x) (((x) & 0x1) << 12) |
||
| 5008 | #define G_00B800_DATA_ATC(x) (((x) >> 12) & 0x1) |
||
| 5009 | #define C_00B800_DATA_ATC 0xFFFFEFFF |
||
| 5010 | #define S_00B800_RESTORE(x) (((x) & 0x1) << 14) |
||
| 5011 | #define G_00B800_RESTORE(x) (((x) >> 14) & 0x1) |
||
| 5012 | #define C_00B800_RESTORE 0xFFFFBFFF |
||
| 5013 | /* */ |
||
| 5014 | #define R_00B804_COMPUTE_DIM_X 0x00B804 |
||
| 5015 | #define R_00B808_COMPUTE_DIM_Y 0x00B808 |
||
| 5016 | #define R_00B80C_COMPUTE_DIM_Z 0x00B80C |
||
| 5017 | #define R_00B810_COMPUTE_START_X 0x00B810 |
||
| 5018 | #define R_00B814_COMPUTE_START_Y 0x00B814 |
||
| 5019 | #define R_00B818_COMPUTE_START_Z 0x00B818 |
||
| 5020 | #define R_00B81C_COMPUTE_NUM_THREAD_X 0x00B81C |
||
| 5021 | #define S_00B81C_NUM_THREAD_FULL(x) (((x) & 0xFFFF) << 0) |
||
| 5022 | #define G_00B81C_NUM_THREAD_FULL(x) (((x) >> 0) & 0xFFFF) |
||
| 5023 | #define C_00B81C_NUM_THREAD_FULL 0xFFFF0000 |
||
| 5024 | #define S_00B81C_NUM_THREAD_PARTIAL(x) (((x) & 0xFFFF) << 16) |
||
| 5025 | #define G_00B81C_NUM_THREAD_PARTIAL(x) (((x) >> 16) & 0xFFFF) |
||
| 5026 | #define C_00B81C_NUM_THREAD_PARTIAL 0x0000FFFF |
||
| 5027 | #define R_00B820_COMPUTE_NUM_THREAD_Y 0x00B820 |
||
| 5028 | #define S_00B820_NUM_THREAD_FULL(x) (((x) & 0xFFFF) << 0) |
||
| 5029 | #define G_00B820_NUM_THREAD_FULL(x) (((x) >> 0) & 0xFFFF) |
||
| 5030 | #define C_00B820_NUM_THREAD_FULL 0xFFFF0000 |
||
| 5031 | #define S_00B820_NUM_THREAD_PARTIAL(x) (((x) & 0xFFFF) << 16) |
||
| 5032 | #define G_00B820_NUM_THREAD_PARTIAL(x) (((x) >> 16) & 0xFFFF) |
||
| 5033 | #define C_00B820_NUM_THREAD_PARTIAL 0x0000FFFF |
||
| 5034 | #define R_00B824_COMPUTE_NUM_THREAD_Z 0x00B824 |
||
| 5035 | #define S_00B824_NUM_THREAD_FULL(x) (((x) & 0xFFFF) << 0) |
||
| 5036 | #define G_00B824_NUM_THREAD_FULL(x) (((x) >> 0) & 0xFFFF) |
||
| 5037 | #define C_00B824_NUM_THREAD_FULL 0xFFFF0000 |
||
| 5038 | #define S_00B824_NUM_THREAD_PARTIAL(x) (((x) & 0xFFFF) << 16) |
||
| 5039 | #define G_00B824_NUM_THREAD_PARTIAL(x) (((x) >> 16) & 0xFFFF) |
||
| 5040 | #define C_00B824_NUM_THREAD_PARTIAL 0x0000FFFF |
||
| 5041 | #define R_00B82C_COMPUTE_MAX_WAVE_ID 0x00B82C /* moved to 0xCD20 on CIK */ |
||
| 5042 | #define S_00B82C_MAX_WAVE_ID(x) (((x) & 0xFFF) << 0) |
||
| 5043 | #define G_00B82C_MAX_WAVE_ID(x) (((x) >> 0) & 0xFFF) |
||
| 5044 | #define C_00B82C_MAX_WAVE_ID 0xFFFFF000 |
||
| 5045 | #define R_00B830_COMPUTE_PGM_LO 0x00B830 |
||
| 5046 | #define R_00B834_COMPUTE_PGM_HI 0x00B834 |
||
| 5047 | #define S_00B834_DATA(x) (((x) & 0xFF) << 0) |
||
| 5048 | #define G_00B834_DATA(x) (((x) >> 0) & 0xFF) |
||
| 5049 | #define C_00B834_DATA 0xFFFFFF00 |
||
| 5050 | /* CIK */ |
||
| 5051 | #define S_00B834_INST_ATC(x) (((x) & 0x1) << 8) |
||
| 5052 | #define G_00B834_INST_ATC(x) (((x) >> 8) & 0x1) |
||
| 5053 | #define C_00B834_INST_ATC 0xFFFFFEFF |
||
| 5054 | /* */ |
||
| 5055 | #define R_00B848_COMPUTE_PGM_RSRC1 0x00B848 |
||
| 5056 | #define S_00B848_VGPRS(x) (((x) & 0x3F) << 0) |
||
| 5057 | #define G_00B848_VGPRS(x) (((x) >> 0) & 0x3F) |
||
| 5058 | #define C_00B848_VGPRS 0xFFFFFFC0 |
||
| 5059 | #define S_00B848_SGPRS(x) (((x) & 0x0F) << 6) |
||
| 5060 | #define G_00B848_SGPRS(x) (((x) >> 6) & 0x0F) |
||
| 5061 | #define C_00B848_SGPRS 0xFFFFFC3F |
||
| 5062 | #define S_00B848_PRIORITY(x) (((x) & 0x03) << 10) |
||
| 5063 | #define G_00B848_PRIORITY(x) (((x) >> 10) & 0x03) |
||
| 5064 | #define C_00B848_PRIORITY 0xFFFFF3FF |
||
| 5065 | #define S_00B848_FLOAT_MODE(x) (((x) & 0xFF) << 12) |
||
| 5066 | #define G_00B848_FLOAT_MODE(x) (((x) >> 12) & 0xFF) |
||
| 5067 | #define C_00B848_FLOAT_MODE 0xFFF00FFF |
||
| 5068 | #define S_00B848_PRIV(x) (((x) & 0x1) << 20) |
||
| 5069 | #define G_00B848_PRIV(x) (((x) >> 20) & 0x1) |
||
| 5070 | #define C_00B848_PRIV 0xFFEFFFFF |
||
| 5071 | #define S_00B848_DX10_CLAMP(x) (((x) & 0x1) << 21) |
||
| 5072 | #define G_00B848_DX10_CLAMP(x) (((x) >> 21) & 0x1) |
||
| 5073 | #define C_00B848_DX10_CLAMP 0xFFDFFFFF |
||
| 5074 | #define S_00B848_DEBUG_MODE(x) (((x) & 0x1) << 22) |
||
| 5075 | #define G_00B848_DEBUG_MODE(x) (((x) >> 22) & 0x1) |
||
| 5076 | #define C_00B848_DEBUG_MODE 0xFFBFFFFF |
||
| 5077 | #define S_00B848_IEEE_MODE(x) (((x) & 0x1) << 23) |
||
| 5078 | #define G_00B848_IEEE_MODE(x) (((x) >> 23) & 0x1) |
||
| 5079 | #define C_00B848_IEEE_MODE 0xFF7FFFFF |
||
| 5080 | /* CIK */ |
||
| 5081 | #define S_00B848_BULKY(x) (((x) & 0x1) << 24) |
||
| 5082 | #define G_00B848_BULKY(x) (((x) >> 24) & 0x1) |
||
| 5083 | #define C_00B848_BULKY 0xFEFFFFFF |
||
| 5084 | #define S_00B848_CDBG_USER(x) (((x) & 0x1) << 25) |
||
| 5085 | #define G_00B848_CDBG_USER(x) (((x) >> 25) & 0x1) |
||
| 5086 | #define C_00B848_CDBG_USER 0xFDFFFFFF |
||
| 5087 | /* */ |
||
| 5088 | #define R_00B84C_COMPUTE_PGM_RSRC2 0x00B84C |
||
| 5089 | #define S_00B84C_SCRATCH_EN(x) (((x) & 0x1) << 0) |
||
| 5090 | #define G_00B84C_SCRATCH_EN(x) (((x) >> 0) & 0x1) |
||
| 5091 | #define C_00B84C_SCRATCH_EN 0xFFFFFFFE |
||
| 5092 | #define S_00B84C_USER_SGPR(x) (((x) & 0x1F) << 1) |
||
| 5093 | #define G_00B84C_USER_SGPR(x) (((x) >> 1) & 0x1F) |
||
| 5094 | #define C_00B84C_USER_SGPR 0xFFFFFFC1 |
||
| 5095 | #define S_00B84C_TGID_X_EN(x) (((x) & 0x1) << 7) |
||
| 5096 | #define G_00B84C_TGID_X_EN(x) (((x) >> 7) & 0x1) |
||
| 5097 | #define C_00B84C_TGID_X_EN 0xFFFFFF7F |
||
| 5098 | #define S_00B84C_TGID_Y_EN(x) (((x) & 0x1) << 8) |
||
| 5099 | #define G_00B84C_TGID_Y_EN(x) (((x) >> 8) & 0x1) |
||
| 5100 | #define C_00B84C_TGID_Y_EN 0xFFFFFEFF |
||
| 5101 | #define S_00B84C_TGID_Z_EN(x) (((x) & 0x1) << 9) |
||
| 5102 | #define G_00B84C_TGID_Z_EN(x) (((x) >> 9) & 0x1) |
||
| 5103 | #define C_00B84C_TGID_Z_EN 0xFFFFFDFF |
||
| 5104 | #define S_00B84C_TG_SIZE_EN(x) (((x) & 0x1) << 10) |
||
| 5105 | #define G_00B84C_TG_SIZE_EN(x) (((x) >> 10) & 0x1) |
||
| 5106 | #define C_00B84C_TG_SIZE_EN 0xFFFFFBFF |
||
| 5107 | #define S_00B84C_TIDIG_COMP_CNT(x) (((x) & 0x03) << 11) |
||
| 5108 | #define G_00B84C_TIDIG_COMP_CNT(x) (((x) >> 11) & 0x03) |
||
| 5109 | #define C_00B84C_TIDIG_COMP_CNT 0xFFFFE7FF |
||
| 5110 | /* CIK */ |
||
| 5111 | #define S_00B84C_EXCP_EN_MSB(x) (((x) & 0x03) << 13) |
||
| 5112 | #define G_00B84C_EXCP_EN_MSB(x) (((x) >> 13) & 0x03) |
||
| 5113 | #define C_00B84C_EXCP_EN_MSB 0xFFFF9FFF |
||
| 5114 | /* */ |
||
| 5115 | #define S_00B84C_LDS_SIZE(x) (((x) & 0x1FF) << 15) |
||
| 5116 | #define G_00B84C_LDS_SIZE(x) (((x) >> 15) & 0x1FF) |
||
| 5117 | #define C_00B84C_LDS_SIZE 0xFF007FFF |
||
| 5118 | #define S_00B84C_EXCP_EN(x) (((x) & 0x7F) << 24) |
||
| 5119 | #define G_00B84C_EXCP_EN(x) (((x) >> 24) & 0x7F) |
||
| 5120 | #define C_00B84C_EXCP_EN 0x80FFFFFF |
||
| 5121 | #define R_00B854_COMPUTE_RESOURCE_LIMITS 0x00B854 |
||
| 5122 | #define S_00B854_WAVES_PER_SH(x) (((x) & 0x3F) << 0) /* mask is 0x3FF on CIK */ |
||
| 5123 | #define G_00B854_WAVES_PER_SH(x) (((x) >> 0) & 0x3F) /* mask is 0x3FF on CIK */ |
||
| 5124 | #define C_00B854_WAVES_PER_SH 0xFFFFFFC0 /* mask is 0x3FF on CIK */ |
||
| 5125 | #define S_00B854_TG_PER_CU(x) (((x) & 0x0F) << 12) |
||
| 5126 | #define G_00B854_TG_PER_CU(x) (((x) >> 12) & 0x0F) |
||
| 5127 | #define C_00B854_TG_PER_CU 0xFFFF0FFF |
||
| 5128 | #define S_00B854_LOCK_THRESHOLD(x) (((x) & 0x3F) << 16) |
||
| 5129 | #define G_00B854_LOCK_THRESHOLD(x) (((x) >> 16) & 0x3F) |
||
| 5130 | #define C_00B854_LOCK_THRESHOLD 0xFFC0FFFF |
||
| 5131 | #define S_00B854_SIMD_DEST_CNTL(x) (((x) & 0x1) << 22) |
||
| 5132 | #define G_00B854_SIMD_DEST_CNTL(x) (((x) >> 22) & 0x1) |
||
| 5133 | #define C_00B854_SIMD_DEST_CNTL 0xFFBFFFFF |
||
| 5134 | /* CIK */ |
||
| 5135 | #define S_00B854_FORCE_SIMD_DIST(x) (((x) & 0x1) << 23) |
||
| 5136 | #define G_00B854_FORCE_SIMD_DIST(x) (((x) >> 23) & 0x1) |
||
| 5137 | #define C_00B854_FORCE_SIMD_DIST 0xFF7FFFFF |
||
| 5138 | #define S_00B854_CU_GROUP_COUNT(x) (((x) & 0x07) << 24) |
||
| 5139 | #define G_00B854_CU_GROUP_COUNT(x) (((x) >> 24) & 0x07) |
||
| 5140 | #define C_00B854_CU_GROUP_COUNT 0xF8FFFFFF |
||
| 5141 | /* */ |
||
| 5142 | #define R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 0x00B858 |
||
| 5143 | #define S_00B858_SH0_CU_EN(x) (((x) & 0xFFFF) << 0) |
||
| 5144 | #define G_00B858_SH0_CU_EN(x) (((x) >> 0) & 0xFFFF) |
||
| 5145 | #define C_00B858_SH0_CU_EN 0xFFFF0000 |
||
| 5146 | #define S_00B858_SH1_CU_EN(x) (((x) & 0xFFFF) << 16) |
||
| 5147 | #define G_00B858_SH1_CU_EN(x) (((x) >> 16) & 0xFFFF) |
||
| 5148 | #define C_00B858_SH1_CU_EN 0x0000FFFF |
||
| 5149 | #define R_00B85C_COMPUTE_STATIC_THREAD_MGMT_SE1 0x00B85C |
||
| 5150 | #define S_00B85C_SH0_CU_EN(x) (((x) & 0xFFFF) << 0) |
||
| 5151 | #define G_00B85C_SH0_CU_EN(x) (((x) >> 0) & 0xFFFF) |
||
| 5152 | #define C_00B85C_SH0_CU_EN 0xFFFF0000 |
||
| 5153 | #define S_00B85C_SH1_CU_EN(x) (((x) & 0xFFFF) << 16) |
||
| 5154 | #define G_00B85C_SH1_CU_EN(x) (((x) >> 16) & 0xFFFF) |
||
| 5155 | #define C_00B85C_SH1_CU_EN 0x0000FFFF |
||
| 5156 | #define R_00B860_COMPUTE_TMPRING_SIZE 0x00B860 |
||
| 5157 | #define S_00B860_WAVES(x) (((x) & 0xFFF) << 0) |
||
| 5158 | #define G_00B860_WAVES(x) (((x) >> 0) & 0xFFF) |
||
| 5159 | #define C_00B860_WAVES 0xFFFFF000 |
||
| 5160 | #define S_00B860_WAVESIZE(x) (((x) & 0x1FFF) << 12) |
||
| 5161 | #define G_00B860_WAVESIZE(x) (((x) >> 12) & 0x1FFF) |
||
| 5162 | #define C_00B860_WAVESIZE 0xFE000FFF |
||
| 5163 | #define R_00B900_COMPUTE_USER_DATA_0 0x00B900 |
||
| 5164 | #define R_028000_DB_RENDER_CONTROL 0x028000 |
||
| 5165 | #define S_028000_DEPTH_CLEAR_ENABLE(x) (((x) & 0x1) << 0) |
||
| 5166 | #define G_028000_DEPTH_CLEAR_ENABLE(x) (((x) >> 0) & 0x1) |
||
| 5167 | #define C_028000_DEPTH_CLEAR_ENABLE 0xFFFFFFFE |
||
| 5168 | #define S_028000_STENCIL_CLEAR_ENABLE(x) (((x) & 0x1) << 1) |
||
| 5169 | #define G_028000_STENCIL_CLEAR_ENABLE(x) (((x) >> 1) & 0x1) |
||
| 5170 | #define C_028000_STENCIL_CLEAR_ENABLE 0xFFFFFFFD |
||
| 5171 | #define S_028000_DEPTH_COPY(x) (((x) & 0x1) << 2) |
||
| 5172 | #define G_028000_DEPTH_COPY(x) (((x) >> 2) & 0x1) |
||
| 5173 | #define C_028000_DEPTH_COPY 0xFFFFFFFB |
||
| 5174 | #define S_028000_STENCIL_COPY(x) (((x) & 0x1) << 3) |
||
| 5175 | #define G_028000_STENCIL_COPY(x) (((x) >> 3) & 0x1) |
||
| 5176 | #define C_028000_STENCIL_COPY 0xFFFFFFF7 |
||
| 5177 | #define S_028000_RESUMMARIZE_ENABLE(x) (((x) & 0x1) << 4) |
||
| 5178 | #define G_028000_RESUMMARIZE_ENABLE(x) (((x) >> 4) & 0x1) |
||
| 5179 | #define C_028000_RESUMMARIZE_ENABLE 0xFFFFFFEF |
||
| 5180 | #define S_028000_STENCIL_COMPRESS_DISABLE(x) (((x) & 0x1) << 5) |
||
| 5181 | #define G_028000_STENCIL_COMPRESS_DISABLE(x) (((x) >> 5) & 0x1) |
||
| 5182 | #define C_028000_STENCIL_COMPRESS_DISABLE 0xFFFFFFDF |
||
| 5183 | #define S_028000_DEPTH_COMPRESS_DISABLE(x) (((x) & 0x1) << 6) |
||
| 5184 | #define G_028000_DEPTH_COMPRESS_DISABLE(x) (((x) >> 6) & 0x1) |
||
| 5185 | #define C_028000_DEPTH_COMPRESS_DISABLE 0xFFFFFFBF |
||
| 5186 | #define S_028000_COPY_CENTROID(x) (((x) & 0x1) << 7) |
||
| 5187 | #define G_028000_COPY_CENTROID(x) (((x) >> 7) & 0x1) |
||
| 5188 | #define C_028000_COPY_CENTROID 0xFFFFFF7F |
||
| 5189 | #define S_028000_COPY_SAMPLE(x) (((x) & 0x0F) << 8) |
||
| 5190 | #define G_028000_COPY_SAMPLE(x) (((x) >> 8) & 0x0F) |
||
| 5191 | #define C_028000_COPY_SAMPLE 0xFFFFF0FF |
||
| 5192 | #define R_028004_DB_COUNT_CONTROL 0x028004 |
||
| 5193 | #define S_028004_ZPASS_INCREMENT_DISABLE(x) (((x) & 0x1) << 0) |
||
| 5194 | #define G_028004_ZPASS_INCREMENT_DISABLE(x) (((x) >> 0) & 0x1) |
||
| 5195 | #define C_028004_ZPASS_INCREMENT_DISABLE 0xFFFFFFFE |
||
| 5196 | #define S_028004_PERFECT_ZPASS_COUNTS(x) (((x) & 0x1) << 1) |
||
| 5197 | #define G_028004_PERFECT_ZPASS_COUNTS(x) (((x) >> 1) & 0x1) |
||
| 5198 | #define C_028004_PERFECT_ZPASS_COUNTS 0xFFFFFFFD |
||
| 5199 | #define S_028004_SAMPLE_RATE(x) (((x) & 0x07) << 4) |
||
| 5200 | #define G_028004_SAMPLE_RATE(x) (((x) >> 4) & 0x07) |
||
| 5201 | #define C_028004_SAMPLE_RATE 0xFFFFFF8F |
||
| 5202 | /* CIK */ |
||
| 5203 | #define S_028004_ZPASS_ENABLE(x) (((x) & 0x0F) << 8) |
||
| 5204 | #define G_028004_ZPASS_ENABLE(x) (((x) >> 8) & 0x0F) |
||
| 5205 | #define C_028004_ZPASS_ENABLE 0xFFFFF0FF |
||
| 5206 | #define S_028004_ZFAIL_ENABLE(x) (((x) & 0x0F) << 12) |
||
| 5207 | #define G_028004_ZFAIL_ENABLE(x) (((x) >> 12) & 0x0F) |
||
| 5208 | #define C_028004_ZFAIL_ENABLE 0xFFFF0FFF |
||
| 5209 | #define S_028004_SFAIL_ENABLE(x) (((x) & 0x0F) << 16) |
||
| 5210 | #define G_028004_SFAIL_ENABLE(x) (((x) >> 16) & 0x0F) |
||
| 5211 | #define C_028004_SFAIL_ENABLE 0xFFF0FFFF |
||
| 5212 | #define S_028004_DBFAIL_ENABLE(x) (((x) & 0x0F) << 20) |
||
| 5213 | #define G_028004_DBFAIL_ENABLE(x) (((x) >> 20) & 0x0F) |
||
| 5214 | #define C_028004_DBFAIL_ENABLE 0xFF0FFFFF |
||
| 5215 | #define S_028004_SLICE_EVEN_ENABLE(x) (((x) & 0x0F) << 24) |
||
| 5216 | #define G_028004_SLICE_EVEN_ENABLE(x) (((x) >> 24) & 0x0F) |
||
| 5217 | #define C_028004_SLICE_EVEN_ENABLE 0xF0FFFFFF |
||
| 5218 | #define S_028004_SLICE_ODD_ENABLE(x) (((x) & 0x0F) << 28) |
||
| 5219 | #define G_028004_SLICE_ODD_ENABLE(x) (((x) >> 28) & 0x0F) |
||
| 5220 | #define C_028004_SLICE_ODD_ENABLE 0x0FFFFFFF |
||
| 5221 | /* */ |
||
| 5222 | #define R_028008_DB_DEPTH_VIEW 0x028008 |
||
| 5223 | #define S_028008_SLICE_START(x) (((x) & 0x7FF) << 0) |
||
| 5224 | #define G_028008_SLICE_START(x) (((x) >> 0) & 0x7FF) |
||
| 5225 | #define C_028008_SLICE_START 0xFFFFF800 |
||
| 5226 | #define S_028008_SLICE_MAX(x) (((x) & 0x7FF) << 13) |
||
| 5227 | #define G_028008_SLICE_MAX(x) (((x) >> 13) & 0x7FF) |
||
| 5228 | #define C_028008_SLICE_MAX 0xFF001FFF |
||
| 5229 | #define S_028008_Z_READ_ONLY(x) (((x) & 0x1) << 24) |
||
| 5230 | #define G_028008_Z_READ_ONLY(x) (((x) >> 24) & 0x1) |
||
| 5231 | #define C_028008_Z_READ_ONLY 0xFEFFFFFF |
||
| 5232 | #define S_028008_STENCIL_READ_ONLY(x) (((x) & 0x1) << 25) |
||
| 5233 | #define G_028008_STENCIL_READ_ONLY(x) (((x) >> 25) & 0x1) |
||
| 5234 | #define C_028008_STENCIL_READ_ONLY 0xFDFFFFFF |
||
| 5235 | #define R_02800C_DB_RENDER_OVERRIDE 0x02800C |
||
| 5236 | #define S_02800C_FORCE_HIZ_ENABLE(x) (((x) & 0x03) << 0) |
||
| 5237 | #define G_02800C_FORCE_HIZ_ENABLE(x) (((x) >> 0) & 0x03) |
||
| 5238 | #define C_02800C_FORCE_HIZ_ENABLE 0xFFFFFFFC |
||
| 5239 | #define V_02800C_FORCE_OFF 0x00 |
||
| 5240 | #define V_02800C_FORCE_ENABLE 0x01 |
||
| 5241 | #define V_02800C_FORCE_DISABLE 0x02 |
||
| 5242 | #define V_02800C_FORCE_RESERVED 0x03 |
||
| 5243 | #define S_02800C_FORCE_HIS_ENABLE0(x) (((x) & 0x03) << 2) |
||
| 5244 | #define G_02800C_FORCE_HIS_ENABLE0(x) (((x) >> 2) & 0x03) |
||
| 5245 | #define C_02800C_FORCE_HIS_ENABLE0 0xFFFFFFF3 |
||
| 5246 | #define V_02800C_FORCE_OFF 0x00 |
||
| 5247 | #define V_02800C_FORCE_ENABLE 0x01 |
||
| 5248 | #define V_02800C_FORCE_DISABLE 0x02 |
||
| 5249 | #define V_02800C_FORCE_RESERVED 0x03 |
||
| 5250 | #define S_02800C_FORCE_HIS_ENABLE1(x) (((x) & 0x03) << 4) |
||
| 5251 | #define G_02800C_FORCE_HIS_ENABLE1(x) (((x) >> 4) & 0x03) |
||
| 5252 | #define C_02800C_FORCE_HIS_ENABLE1 0xFFFFFFCF |
||
| 5253 | #define V_02800C_FORCE_OFF 0x00 |
||
| 5254 | #define V_02800C_FORCE_ENABLE 0x01 |
||
| 5255 | #define V_02800C_FORCE_DISABLE 0x02 |
||
| 5256 | #define V_02800C_FORCE_RESERVED 0x03 |
||
| 5257 | #define S_02800C_FORCE_SHADER_Z_ORDER(x) (((x) & 0x1) << 6) |
||
| 5258 | #define G_02800C_FORCE_SHADER_Z_ORDER(x) (((x) >> 6) & 0x1) |
||
| 5259 | #define C_02800C_FORCE_SHADER_Z_ORDER 0xFFFFFFBF |
||
| 5260 | #define S_02800C_FAST_Z_DISABLE(x) (((x) & 0x1) << 7) |
||
| 5261 | #define G_02800C_FAST_Z_DISABLE(x) (((x) >> 7) & 0x1) |
||
| 5262 | #define C_02800C_FAST_Z_DISABLE 0xFFFFFF7F |
||
| 5263 | #define S_02800C_FAST_STENCIL_DISABLE(x) (((x) & 0x1) << 8) |
||
| 5264 | #define G_02800C_FAST_STENCIL_DISABLE(x) (((x) >> 8) & 0x1) |
||
| 5265 | #define C_02800C_FAST_STENCIL_DISABLE 0xFFFFFEFF |
||
| 5266 | #define S_02800C_NOOP_CULL_DISABLE(x) (((x) & 0x1) << 9) |
||
| 5267 | #define G_02800C_NOOP_CULL_DISABLE(x) (((x) >> 9) & 0x1) |
||
| 5268 | #define C_02800C_NOOP_CULL_DISABLE 0xFFFFFDFF |
||
| 5269 | #define S_02800C_FORCE_COLOR_KILL(x) (((x) & 0x1) << 10) |
||
| 5270 | #define G_02800C_FORCE_COLOR_KILL(x) (((x) >> 10) & 0x1) |
||
| 5271 | #define C_02800C_FORCE_COLOR_KILL 0xFFFFFBFF |
||
| 5272 | #define S_02800C_FORCE_Z_READ(x) (((x) & 0x1) << 11) |
||
| 5273 | #define G_02800C_FORCE_Z_READ(x) (((x) >> 11) & 0x1) |
||
| 5274 | #define C_02800C_FORCE_Z_READ 0xFFFFF7FF |
||
| 5275 | #define S_02800C_FORCE_STENCIL_READ(x) (((x) & 0x1) << 12) |
||
| 5276 | #define G_02800C_FORCE_STENCIL_READ(x) (((x) >> 12) & 0x1) |
||
| 5277 | #define C_02800C_FORCE_STENCIL_READ 0xFFFFEFFF |
||
| 5278 | #define S_02800C_FORCE_FULL_Z_RANGE(x) (((x) & 0x03) << 13) |
||
| 5279 | #define G_02800C_FORCE_FULL_Z_RANGE(x) (((x) >> 13) & 0x03) |
||
| 5280 | #define C_02800C_FORCE_FULL_Z_RANGE 0xFFFF9FFF |
||
| 5281 | #define V_02800C_FORCE_OFF 0x00 |
||
| 5282 | #define V_02800C_FORCE_ENABLE 0x01 |
||
| 5283 | #define V_02800C_FORCE_DISABLE 0x02 |
||
| 5284 | #define V_02800C_FORCE_RESERVED 0x03 |
||
| 5285 | #define S_02800C_FORCE_QC_SMASK_CONFLICT(x) (((x) & 0x1) << 15) |
||
| 5286 | #define G_02800C_FORCE_QC_SMASK_CONFLICT(x) (((x) >> 15) & 0x1) |
||
| 5287 | #define C_02800C_FORCE_QC_SMASK_CONFLICT 0xFFFF7FFF |
||
| 5288 | #define S_02800C_DISABLE_VIEWPORT_CLAMP(x) (((x) & 0x1) << 16) |
||
| 5289 | #define G_02800C_DISABLE_VIEWPORT_CLAMP(x) (((x) >> 16) & 0x1) |
||
| 5290 | #define C_02800C_DISABLE_VIEWPORT_CLAMP 0xFFFEFFFF |
||
| 5291 | #define S_02800C_IGNORE_SC_ZRANGE(x) (((x) & 0x1) << 17) |
||
| 5292 | #define G_02800C_IGNORE_SC_ZRANGE(x) (((x) >> 17) & 0x1) |
||
| 5293 | #define C_02800C_IGNORE_SC_ZRANGE 0xFFFDFFFF |
||
| 5294 | #define S_02800C_DISABLE_FULLY_COVERED(x) (((x) & 0x1) << 18) |
||
| 5295 | #define G_02800C_DISABLE_FULLY_COVERED(x) (((x) >> 18) & 0x1) |
||
| 5296 | #define C_02800C_DISABLE_FULLY_COVERED 0xFFFBFFFF |
||
| 5297 | #define S_02800C_FORCE_Z_LIMIT_SUMM(x) (((x) & 0x03) << 19) |
||
| 5298 | #define G_02800C_FORCE_Z_LIMIT_SUMM(x) (((x) >> 19) & 0x03) |
||
| 5299 | #define C_02800C_FORCE_Z_LIMIT_SUMM 0xFFE7FFFF |
||
| 5300 | #define V_02800C_FORCE_SUMM_OFF 0x00 |
||
| 5301 | #define V_02800C_FORCE_SUMM_MINZ 0x01 |
||
| 5302 | #define V_02800C_FORCE_SUMM_MAXZ 0x02 |
||
| 5303 | #define V_02800C_FORCE_SUMM_BOTH 0x03 |
||
| 5304 | #define S_02800C_MAX_TILES_IN_DTT(x) (((x) & 0x1F) << 21) |
||
| 5305 | #define G_02800C_MAX_TILES_IN_DTT(x) (((x) >> 21) & 0x1F) |
||
| 5306 | #define C_02800C_MAX_TILES_IN_DTT 0xFC1FFFFF |
||
| 5307 | #define S_02800C_DISABLE_TILE_RATE_TILES(x) (((x) & 0x1) << 26) |
||
| 5308 | #define G_02800C_DISABLE_TILE_RATE_TILES(x) (((x) >> 26) & 0x1) |
||
| 5309 | #define C_02800C_DISABLE_TILE_RATE_TILES 0xFBFFFFFF |
||
| 5310 | #define S_02800C_FORCE_Z_DIRTY(x) (((x) & 0x1) << 27) |
||
| 5311 | #define G_02800C_FORCE_Z_DIRTY(x) (((x) >> 27) & 0x1) |
||
| 5312 | #define C_02800C_FORCE_Z_DIRTY 0xF7FFFFFF |
||
| 5313 | #define S_02800C_FORCE_STENCIL_DIRTY(x) (((x) & 0x1) << 28) |
||
| 5314 | #define G_02800C_FORCE_STENCIL_DIRTY(x) (((x) >> 28) & 0x1) |
||
| 5315 | #define C_02800C_FORCE_STENCIL_DIRTY 0xEFFFFFFF |
||
| 5316 | #define S_02800C_FORCE_Z_VALID(x) (((x) & 0x1) << 29) |
||
| 5317 | #define G_02800C_FORCE_Z_VALID(x) (((x) >> 29) & 0x1) |
||
| 5318 | #define C_02800C_FORCE_Z_VALID 0xDFFFFFFF |
||
| 5319 | #define S_02800C_FORCE_STENCIL_VALID(x) (((x) & 0x1) << 30) |
||
| 5320 | #define G_02800C_FORCE_STENCIL_VALID(x) (((x) >> 30) & 0x1) |
||
| 5321 | #define C_02800C_FORCE_STENCIL_VALID 0xBFFFFFFF |
||
| 5322 | #define S_02800C_PRESERVE_COMPRESSION(x) (((x) & 0x1) << 31) |
||
| 5323 | #define G_02800C_PRESERVE_COMPRESSION(x) (((x) >> 31) & 0x1) |
||
| 5324 | #define C_02800C_PRESERVE_COMPRESSION 0x7FFFFFFF |
||
| 5325 | #define R_028010_DB_RENDER_OVERRIDE2 0x028010 |
||
| 5326 | #define S_028010_PARTIAL_SQUAD_LAUNCH_CONTROL(x) (((x) & 0x03) << 0) |
||
| 5327 | #define G_028010_PARTIAL_SQUAD_LAUNCH_CONTROL(x) (((x) >> 0) & 0x03) |
||
| 5328 | #define C_028010_PARTIAL_SQUAD_LAUNCH_CONTROL 0xFFFFFFFC |
||
| 5329 | #define V_028010_PSLC_AUTO 0x00 |
||
| 5330 | #define V_028010_PSLC_ON_HANG_ONLY 0x01 |
||
| 5331 | #define V_028010_PSLC_ASAP 0x02 |
||
| 5332 | #define V_028010_PSLC_COUNTDOWN 0x03 |
||
| 5333 | #define S_028010_PARTIAL_SQUAD_LAUNCH_COUNTDOWN(x) (((x) & 0x07) << 2) |
||
| 5334 | #define G_028010_PARTIAL_SQUAD_LAUNCH_COUNTDOWN(x) (((x) >> 2) & 0x07) |
||
| 5335 | #define C_028010_PARTIAL_SQUAD_LAUNCH_COUNTDOWN 0xFFFFFFE3 |
||
| 5336 | #define S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(x) (((x) & 0x1) << 5) |
||
| 5337 | #define G_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(x) (((x) >> 5) & 0x1) |
||
| 5338 | #define C_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION 0xFFFFFFDF |
||
| 5339 | #define S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(x) (((x) & 0x1) << 6) |
||
| 5340 | #define G_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(x) (((x) >> 6) & 0x1) |
||
| 5341 | #define C_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION 0xFFFFFFBF |
||
| 5342 | #define S_028010_DISABLE_COLOR_ON_VALIDATION(x) (((x) & 0x1) << 7) |
||
| 5343 | #define G_028010_DISABLE_COLOR_ON_VALIDATION(x) (((x) >> 7) & 0x1) |
||
| 5344 | #define C_028010_DISABLE_COLOR_ON_VALIDATION 0xFFFFFF7F |
||
| 5345 | #define S_028010_DECOMPRESS_Z_ON_FLUSH(x) (((x) & 0x1) << 8) |
||
| 5346 | #define G_028010_DECOMPRESS_Z_ON_FLUSH(x) (((x) >> 8) & 0x1) |
||
| 5347 | #define C_028010_DECOMPRESS_Z_ON_FLUSH 0xFFFFFEFF |
||
| 5348 | #define S_028010_DISABLE_REG_SNOOP(x) (((x) & 0x1) << 9) |
||
| 5349 | #define G_028010_DISABLE_REG_SNOOP(x) (((x) >> 9) & 0x1) |
||
| 5350 | #define C_028010_DISABLE_REG_SNOOP 0xFFFFFDFF |
||
| 5351 | #define S_028010_DEPTH_BOUNDS_HIER_DEPTH_DISABLE(x) (((x) & 0x1) << 10) |
||
| 5352 | #define G_028010_DEPTH_BOUNDS_HIER_DEPTH_DISABLE(x) (((x) >> 10) & 0x1) |
||
| 5353 | #define C_028010_DEPTH_BOUNDS_HIER_DEPTH_DISABLE 0xFFFFFBFF |
||
| 5354 | /* CIK */ |
||
| 5355 | #define S_028010_SEPARATE_HIZS_FUNC_ENABLE(x) (((x) & 0x1) << 11) |
||
| 5356 | #define G_028010_SEPARATE_HIZS_FUNC_ENABLE(x) (((x) >> 11) & 0x1) |
||
| 5357 | #define C_028010_SEPARATE_HIZS_FUNC_ENABLE 0xFFFFF7FF |
||
| 5358 | #define S_028010_HIZ_ZFUNC(x) (((x) & 0x07) << 12) |
||
| 5359 | #define G_028010_HIZ_ZFUNC(x) (((x) >> 12) & 0x07) |
||
| 5360 | #define C_028010_HIZ_ZFUNC 0xFFFF8FFF |
||
| 5361 | #define S_028010_HIS_SFUNC_FF(x) (((x) & 0x07) << 15) |
||
| 5362 | #define G_028010_HIS_SFUNC_FF(x) (((x) >> 15) & 0x07) |
||
| 5363 | #define C_028010_HIS_SFUNC_FF 0xFFFC7FFF |
||
| 5364 | #define S_028010_HIS_SFUNC_BF(x) (((x) & 0x07) << 18) |
||
| 5365 | #define G_028010_HIS_SFUNC_BF(x) (((x) >> 18) & 0x07) |
||
| 5366 | #define C_028010_HIS_SFUNC_BF 0xFFE3FFFF |
||
| 5367 | #define S_028010_PRESERVE_ZRANGE(x) (((x) & 0x1) << 21) |
||
| 5368 | #define G_028010_PRESERVE_ZRANGE(x) (((x) >> 21) & 0x1) |
||
| 5369 | #define C_028010_PRESERVE_ZRANGE 0xFFDFFFFF |
||
| 5370 | #define S_028010_PRESERVE_SRESULTS(x) (((x) & 0x1) << 22) |
||
| 5371 | #define G_028010_PRESERVE_SRESULTS(x) (((x) >> 22) & 0x1) |
||
| 5372 | #define C_028010_PRESERVE_SRESULTS 0xFFBFFFFF |
||
| 5373 | #define S_028010_DISABLE_FAST_PASS(x) (((x) & 0x1) << 23) |
||
| 5374 | #define G_028010_DISABLE_FAST_PASS(x) (((x) >> 23) & 0x1) |
||
| 5375 | #define C_028010_DISABLE_FAST_PASS 0xFF7FFFFF |
||
| 5376 | /* */ |
||
| 5377 | #define R_028014_DB_HTILE_DATA_BASE 0x028014 |
||
| 5378 | #define R_028020_DB_DEPTH_BOUNDS_MIN 0x028020 |
||
| 5379 | #define R_028024_DB_DEPTH_BOUNDS_MAX 0x028024 |
||
| 5380 | #define R_028028_DB_STENCIL_CLEAR 0x028028 |
||
| 5381 | #define S_028028_CLEAR(x) (((x) & 0xFF) << 0) |
||
| 5382 | #define G_028028_CLEAR(x) (((x) >> 0) & 0xFF) |
||
| 5383 | #define C_028028_CLEAR 0xFFFFFF00 |
||
| 5384 | #define R_02802C_DB_DEPTH_CLEAR 0x02802C |
||
| 5385 | #define R_028030_PA_SC_SCREEN_SCISSOR_TL 0x028030 |
||
| 5386 | #define S_028030_TL_X(x) (((x) & 0xFFFF) << 0) |
||
| 5387 | #define G_028030_TL_X(x) (((x) >> 0) & 0xFFFF) |
||
| 5388 | #define C_028030_TL_X 0xFFFF0000 |
||
| 5389 | #define S_028030_TL_Y(x) (((x) & 0xFFFF) << 16) |
||
| 5390 | #define G_028030_TL_Y(x) (((x) >> 16) & 0xFFFF) |
||
| 5391 | #define C_028030_TL_Y 0x0000FFFF |
||
| 5392 | #define R_028034_PA_SC_SCREEN_SCISSOR_BR 0x028034 |
||
| 5393 | #define S_028034_BR_X(x) (((x) & 0xFFFF) << 0) |
||
| 5394 | #define G_028034_BR_X(x) (((x) >> 0) & 0xFFFF) |
||
| 5395 | #define C_028034_BR_X 0xFFFF0000 |
||
| 5396 | #define S_028034_BR_Y(x) (((x) & 0xFFFF) << 16) |
||
| 5397 | #define G_028034_BR_Y(x) (((x) >> 16) & 0xFFFF) |
||
| 5398 | #define C_028034_BR_Y 0x0000FFFF |
||
| 5399 | #define R_02803C_DB_DEPTH_INFO 0x02803C |
||
| 5400 | #define S_02803C_ADDR5_SWIZZLE_MASK(x) (((x) & 0x0F) << 0) |
||
| 5401 | #define G_02803C_ADDR5_SWIZZLE_MASK(x) (((x) >> 0) & 0x0F) |
||
| 5402 | #define C_02803C_ADDR5_SWIZZLE_MASK 0xFFFFFFF0 |
||
| 5403 | /* CIK */ |
||
| 5404 | #define S_02803C_ARRAY_MODE(x) (((x) & 0x0F) << 4) |
||
| 5405 | #define G_02803C_ARRAY_MODE(x) (((x) >> 4) & 0x0F) |
||
| 5406 | #define C_02803C_ARRAY_MODE 0xFFFFFF0F |
||
| 5407 | #define V_02803C_ARRAY_LINEAR_GENERAL 0x00 |
||
| 5408 | #define V_02803C_ARRAY_LINEAR_ALIGNED 0x01 |
||
| 5409 | #define V_02803C_ARRAY_1D_TILED_THIN1 0x02 |
||
| 5410 | #define V_02803C_ARRAY_2D_TILED_THIN1 0x04 |
||
| 5411 | #define V_02803C_ARRAY_PRT_TILED_THIN1 0x05 |
||
| 5412 | #define V_02803C_ARRAY_PRT_2D_TILED_THIN1 0x06 |
||
| 5413 | #define S_02803C_PIPE_CONFIG(x) (((x) & 0x1F) << 8) |
||
| 5414 | #define G_02803C_PIPE_CONFIG(x) (((x) >> 8) & 0x1F) |
||
| 5415 | #define C_02803C_PIPE_CONFIG 0xFFFFE0FF |
||
| 5416 | #define V_02803C_ADDR_SURF_P2 0x00 |
||
| 5417 | #define V_02803C_X_ADDR_SURF_P4_8X16 0x04 |
||
| 5418 | #define V_02803C_X_ADDR_SURF_P4_16X16 0x05 |
||
| 5419 | #define V_02803C_X_ADDR_SURF_P4_16X32 0x06 |
||
| 5420 | #define V_02803C_X_ADDR_SURF_P4_32X32 0x07 |
||
| 5421 | #define V_02803C_X_ADDR_SURF_P8_16X16_8X16 0x08 |
||
| 5422 | #define V_02803C_X_ADDR_SURF_P8_16X32_8X16 0x09 |
||
| 5423 | #define V_02803C_X_ADDR_SURF_P8_32X32_8X16 0x0A |
||
| 5424 | #define V_02803C_X_ADDR_SURF_P8_16X32_16X16 0x0B |
||
| 5425 | #define V_02803C_X_ADDR_SURF_P8_32X32_16X16 0x0C |
||
| 5426 | #define V_02803C_X_ADDR_SURF_P8_32X32_16X32 0x0D |
||
| 5427 | #define V_02803C_X_ADDR_SURF_P8_32X64_32X32 0x0E |
||
| 5428 | #define V_02803C_X_ADDR_SURF_P16_32X32_8X16 0x10 |
||
| 5429 | #define V_02803C_X_ADDR_SURF_P16_32X32_16X16 0x11 |
||
| 5430 | #define S_02803C_BANK_WIDTH(x) (((x) & 0x03) << 13) |
||
| 5431 | #define G_02803C_BANK_WIDTH(x) (((x) >> 13) & 0x03) |
||
| 5432 | #define C_02803C_BANK_WIDTH 0xFFFF9FFF |
||
| 5433 | #define V_02803C_ADDR_SURF_BANK_WIDTH_1 0x00 |
||
| 5434 | #define V_02803C_ADDR_SURF_BANK_WIDTH_2 0x01 |
||
| 5435 | #define V_02803C_ADDR_SURF_BANK_WIDTH_4 0x02 |
||
| 5436 | #define V_02803C_ADDR_SURF_BANK_WIDTH_8 0x03 |
||
| 5437 | #define S_02803C_BANK_HEIGHT(x) (((x) & 0x03) << 15) |
||
| 5438 | #define G_02803C_BANK_HEIGHT(x) (((x) >> 15) & 0x03) |
||
| 5439 | #define C_02803C_BANK_HEIGHT 0xFFFE7FFF |
||
| 5440 | #define V_02803C_ADDR_SURF_BANK_HEIGHT_1 0x00 |
||
| 5441 | #define V_02803C_ADDR_SURF_BANK_HEIGHT_2 0x01 |
||
| 5442 | #define V_02803C_ADDR_SURF_BANK_HEIGHT_4 0x02 |
||
| 5443 | #define V_02803C_ADDR_SURF_BANK_HEIGHT_8 0x03 |
||
| 5444 | #define S_02803C_MACRO_TILE_ASPECT(x) (((x) & 0x03) << 17) |
||
| 5445 | #define G_02803C_MACRO_TILE_ASPECT(x) (((x) >> 17) & 0x03) |
||
| 5446 | #define C_02803C_MACRO_TILE_ASPECT 0xFFF9FFFF |
||
| 5447 | #define V_02803C_ADDR_SURF_MACRO_ASPECT_1 0x00 |
||
| 5448 | #define V_02803C_ADDR_SURF_MACRO_ASPECT_2 0x01 |
||
| 5449 | #define V_02803C_ADDR_SURF_MACRO_ASPECT_4 0x02 |
||
| 5450 | #define V_02803C_ADDR_SURF_MACRO_ASPECT_8 0x03 |
||
| 5451 | #define S_02803C_NUM_BANKS(x) (((x) & 0x03) << 19) |
||
| 5452 | #define G_02803C_NUM_BANKS(x) (((x) >> 19) & 0x03) |
||
| 5453 | #define C_02803C_NUM_BANKS 0xFFE7FFFF |
||
| 5454 | #define V_02803C_ADDR_SURF_2_BANK 0x00 |
||
| 5455 | #define V_02803C_ADDR_SURF_4_BANK 0x01 |
||
| 5456 | #define V_02803C_ADDR_SURF_8_BANK 0x02 |
||
| 5457 | #define V_02803C_ADDR_SURF_16_BANK 0x03 |
||
| 5458 | /* */ |
||
| 5459 | #define R_028040_DB_Z_INFO 0x028040 |
||
| 5460 | #define S_028040_FORMAT(x) (((x) & 0x03) << 0) |
||
| 5461 | #define G_028040_FORMAT(x) (((x) >> 0) & 0x03) |
||
| 5462 | #define C_028040_FORMAT 0xFFFFFFFC |
||
| 5463 | #define V_028040_Z_INVALID 0x00 |
||
| 5464 | #define V_028040_Z_16 0x01 |
||
| 5465 | #define V_028040_Z_24 0x02 /* deprecated */ |
||
| 5466 | #define V_028040_Z_32_FLOAT 0x03 |
||
| 5467 | #define S_028040_NUM_SAMPLES(x) (((x) & 0x03) << 2) |
||
| 5468 | #define G_028040_NUM_SAMPLES(x) (((x) >> 2) & 0x03) |
||
| 5469 | #define C_028040_NUM_SAMPLES 0xFFFFFFF3 |
||
| 5470 | #define S_028040_TILE_MODE_INDEX(x) (((x) & 0x07) << 20) /* not on CIK */ |
||
| 5471 | #define G_028040_TILE_MODE_INDEX(x) (((x) >> 20) & 0x07) /* not on CIK */ |
||
| 5472 | #define C_028040_TILE_MODE_INDEX 0xFF8FFFFF /* not on CIK */ |
||
| 5473 | /* CIK */ |
||
| 5474 | #define S_028040_TILE_SPLIT(x) (((x) & 0x07) << 13) |
||
| 5475 | #define G_028040_TILE_SPLIT(x) (((x) >> 13) & 0x07) |
||
| 5476 | #define C_028040_TILE_SPLIT 0xFFFF1FFF |
||
| 5477 | #define V_028040_ADDR_SURF_TILE_SPLIT_64B 0x00 |
||
| 5478 | #define V_028040_ADDR_SURF_TILE_SPLIT_128B 0x01 |
||
| 5479 | #define V_028040_ADDR_SURF_TILE_SPLIT_256B 0x02 |
||
| 5480 | #define V_028040_ADDR_SURF_TILE_SPLIT_512B 0x03 |
||
| 5481 | #define V_028040_ADDR_SURF_TILE_SPLIT_1KB 0x04 |
||
| 5482 | #define V_028040_ADDR_SURF_TILE_SPLIT_2KB 0x05 |
||
| 5483 | #define V_028040_ADDR_SURF_TILE_SPLIT_4KB 0x06 |
||
| 5484 | /* */ |
||
| 5485 | #define S_028040_ALLOW_EXPCLEAR(x) (((x) & 0x1) << 27) |
||
| 5486 | #define G_028040_ALLOW_EXPCLEAR(x) (((x) >> 27) & 0x1) |
||
| 5487 | #define C_028040_ALLOW_EXPCLEAR 0xF7FFFFFF |
||
| 5488 | #define S_028040_READ_SIZE(x) (((x) & 0x1) << 28) |
||
| 5489 | #define G_028040_READ_SIZE(x) (((x) >> 28) & 0x1) |
||
| 5490 | #define C_028040_READ_SIZE 0xEFFFFFFF |
||
| 5491 | #define S_028040_TILE_SURFACE_ENABLE(x) (((x) & 0x1) << 29) |
||
| 5492 | #define G_028040_TILE_SURFACE_ENABLE(x) (((x) >> 29) & 0x1) |
||
| 5493 | #define C_028040_TILE_SURFACE_ENABLE 0xDFFFFFFF |
||
| 5494 | #define S_028040_ZRANGE_PRECISION(x) (((x) & 0x1) << 31) |
||
| 5495 | #define G_028040_ZRANGE_PRECISION(x) (((x) >> 31) & 0x1) |
||
| 5496 | #define C_028040_ZRANGE_PRECISION 0x7FFFFFFF |
||
| 5497 | #define R_028044_DB_STENCIL_INFO 0x028044 |
||
| 5498 | #define S_028044_FORMAT(x) (((x) & 0x1) << 0) |
||
| 5499 | #define G_028044_FORMAT(x) (((x) >> 0) & 0x1) |
||
| 5500 | #define C_028044_FORMAT 0xFFFFFFFE |
||
| 5501 | #define V_028044_STENCIL_INVALID 0x00 |
||
| 5502 | #define V_028044_STENCIL_8 0x01 |
||
| 5503 | #define S_028044_TILE_MODE_INDEX(x) (((x) & 0x07) << 20) /* not on CIK */ |
||
| 5504 | #define G_028044_TILE_MODE_INDEX(x) (((x) >> 20) & 0x07) /* not on CIK */ |
||
| 5505 | #define C_028044_TILE_MODE_INDEX 0xFF8FFFFF /* not on CIK */ |
||
| 5506 | /* CIK */ |
||
| 5507 | #define S_028044_TILE_SPLIT(x) (((x) & 0x07) << 13) |
||
| 5508 | #define G_028044_TILE_SPLIT(x) (((x) >> 13) & 0x07) |
||
| 5509 | #define C_028044_TILE_SPLIT 0xFFFF1FFF |
||
| 5510 | #define V_028044_ADDR_SURF_TILE_SPLIT_64B 0x00 |
||
| 5511 | #define V_028044_ADDR_SURF_TILE_SPLIT_128B 0x01 |
||
| 5512 | #define V_028044_ADDR_SURF_TILE_SPLIT_256B 0x02 |
||
| 5513 | #define V_028044_ADDR_SURF_TILE_SPLIT_512B 0x03 |
||
| 5514 | #define V_028044_ADDR_SURF_TILE_SPLIT_1KB 0x04 |
||
| 5515 | #define V_028044_ADDR_SURF_TILE_SPLIT_2KB 0x05 |
||
| 5516 | #define V_028044_ADDR_SURF_TILE_SPLIT_4KB 0x06 |
||
| 5517 | /* */ |
||
| 5518 | #define S_028044_ALLOW_EXPCLEAR(x) (((x) & 0x1) << 27) |
||
| 5519 | #define G_028044_ALLOW_EXPCLEAR(x) (((x) >> 27) & 0x1) |
||
| 5520 | #define C_028044_ALLOW_EXPCLEAR 0xF7FFFFFF |
||
| 5521 | #define S_028044_TILE_STENCIL_DISABLE(x) (((x) & 0x1) << 29) |
||
| 5522 | #define G_028044_TILE_STENCIL_DISABLE(x) (((x) >> 29) & 0x1) |
||
| 5523 | #define C_028044_TILE_STENCIL_DISABLE 0xDFFFFFFF |
||
| 5524 | #define R_028048_DB_Z_READ_BASE 0x028048 |
||
| 5525 | #define R_02804C_DB_STENCIL_READ_BASE 0x02804C |
||
| 5526 | #define R_028050_DB_Z_WRITE_BASE 0x028050 |
||
| 5527 | #define R_028054_DB_STENCIL_WRITE_BASE 0x028054 |
||
| 5528 | #define R_028058_DB_DEPTH_SIZE 0x028058 |
||
| 5529 | #define S_028058_PITCH_TILE_MAX(x) (((x) & 0x7FF) << 0) |
||
| 5530 | #define G_028058_PITCH_TILE_MAX(x) (((x) >> 0) & 0x7FF) |
||
| 5531 | #define C_028058_PITCH_TILE_MAX 0xFFFFF800 |
||
| 5532 | #define S_028058_HEIGHT_TILE_MAX(x) (((x) & 0x7FF) << 11) |
||
| 5533 | #define G_028058_HEIGHT_TILE_MAX(x) (((x) >> 11) & 0x7FF) |
||
| 5534 | #define C_028058_HEIGHT_TILE_MAX 0xFFC007FF |
||
| 5535 | #define R_02805C_DB_DEPTH_SLICE 0x02805C |
||
| 5536 | #define S_02805C_SLICE_TILE_MAX(x) (((x) & 0x3FFFFF) << 0) |
||
| 5537 | #define G_02805C_SLICE_TILE_MAX(x) (((x) >> 0) & 0x3FFFFF) |
||
| 5538 | #define C_02805C_SLICE_TILE_MAX 0xFFC00000 |
||
| 5539 | #define R_028080_TA_BC_BASE_ADDR 0x028080 |
||
| 5540 | /* CIK */ |
||
| 5541 | #define R_028084_TA_BC_BASE_ADDR_HI 0x028084 |
||
| 5542 | #define S_028084_ADDRESS(x) (((x) & 0xFF) << 0) |
||
| 5543 | #define G_028084_ADDRESS(x) (((x) >> 0) & 0xFF) |
||
| 5544 | #define C_028084_ADDRESS 0xFFFFFF00 |
||
| 5545 | /* */ |
||
| 5546 | #define R_028200_PA_SC_WINDOW_OFFSET 0x028200 |
||
| 5547 | #define S_028200_WINDOW_X_OFFSET(x) (((x) & 0xFFFF) << 0) |
||
| 5548 | #define G_028200_WINDOW_X_OFFSET(x) (((x) >> 0) & 0xFFFF) |
||
| 5549 | #define C_028200_WINDOW_X_OFFSET 0xFFFF0000 |
||
| 5550 | #define S_028200_WINDOW_Y_OFFSET(x) (((x) & 0xFFFF) << 16) |
||
| 5551 | #define G_028200_WINDOW_Y_OFFSET(x) (((x) >> 16) & 0xFFFF) |
||
| 5552 | #define C_028200_WINDOW_Y_OFFSET 0x0000FFFF |
||
| 5553 | #define R_028204_PA_SC_WINDOW_SCISSOR_TL 0x028204 |
||
| 5554 | #define S_028204_TL_X(x) (((x) & 0x7FFF) << 0) |
||
| 5555 | #define G_028204_TL_X(x) (((x) >> 0) & 0x7FFF) |
||
| 5556 | #define C_028204_TL_X 0xFFFF8000 |
||
| 5557 | #define S_028204_TL_Y(x) (((x) & 0x7FFF) << 16) |
||
| 5558 | #define G_028204_TL_Y(x) (((x) >> 16) & 0x7FFF) |
||
| 5559 | #define C_028204_TL_Y 0x8000FFFF |
||
| 5560 | #define S_028204_WINDOW_OFFSET_DISABLE(x) (((x) & 0x1) << 31) |
||
| 5561 | #define G_028204_WINDOW_OFFSET_DISABLE(x) (((x) >> 31) & 0x1) |
||
| 5562 | #define C_028204_WINDOW_OFFSET_DISABLE 0x7FFFFFFF |
||
| 5563 | #define R_028208_PA_SC_WINDOW_SCISSOR_BR 0x028208 |
||
| 5564 | #define S_028208_BR_X(x) (((x) & 0x7FFF) << 0) |
||
| 5565 | #define G_028208_BR_X(x) (((x) >> 0) & 0x7FFF) |
||
| 5566 | #define C_028208_BR_X 0xFFFF8000 |
||
| 5567 | #define S_028208_BR_Y(x) (((x) & 0x7FFF) << 16) |
||
| 5568 | #define G_028208_BR_Y(x) (((x) >> 16) & 0x7FFF) |
||
| 5569 | #define C_028208_BR_Y 0x8000FFFF |
||
| 5570 | #define R_02820C_PA_SC_CLIPRECT_RULE 0x02820C |
||
| 5571 | #define S_02820C_CLIP_RULE(x) (((x) & 0xFFFF) << 0) |
||
| 5572 | #define G_02820C_CLIP_RULE(x) (((x) >> 0) & 0xFFFF) |
||
| 5573 | #define C_02820C_CLIP_RULE 0xFFFF0000 |
||
| 5574 | #define R_028210_PA_SC_CLIPRECT_0_TL 0x028210 |
||
| 5575 | #define S_028210_TL_X(x) (((x) & 0x7FFF) << 0) |
||
| 5576 | #define G_028210_TL_X(x) (((x) >> 0) & 0x7FFF) |
||
| 5577 | #define C_028210_TL_X 0xFFFF8000 |
||
| 5578 | #define S_028210_TL_Y(x) (((x) & 0x7FFF) << 16) |
||
| 5579 | #define G_028210_TL_Y(x) (((x) >> 16) & 0x7FFF) |
||
| 5580 | #define C_028210_TL_Y 0x8000FFFF |
||
| 5581 | #define R_028214_PA_SC_CLIPRECT_0_BR 0x028214 |
||
| 5582 | #define S_028214_BR_X(x) (((x) & 0x7FFF) << 0) |
||
| 5583 | #define G_028214_BR_X(x) (((x) >> 0) & 0x7FFF) |
||
| 5584 | #define C_028214_BR_X 0xFFFF8000 |
||
| 5585 | #define S_028214_BR_Y(x) (((x) & 0x7FFF) << 16) |
||
| 5586 | #define G_028214_BR_Y(x) (((x) >> 16) & 0x7FFF) |
||
| 5587 | #define C_028214_BR_Y 0x8000FFFF |
||
| 5588 | #define R_028218_PA_SC_CLIPRECT_1_TL 0x028218 |
||
| 5589 | #define R_02821C_PA_SC_CLIPRECT_1_BR 0x02821C |
||
| 5590 | #define R_028220_PA_SC_CLIPRECT_2_TL 0x028220 |
||
| 5591 | #define R_028224_PA_SC_CLIPRECT_2_BR 0x028224 |
||
| 5592 | #define R_028228_PA_SC_CLIPRECT_3_TL 0x028228 |
||
| 5593 | #define R_02822C_PA_SC_CLIPRECT_3_BR 0x02822C |
||
| 5594 | #define R_028230_PA_SC_EDGERULE 0x028230 |
||
| 5595 | #define S_028230_ER_TRI(x) (((x) & 0x0F) << 0) |
||
| 5596 | #define G_028230_ER_TRI(x) (((x) >> 0) & 0x0F) |
||
| 5597 | #define C_028230_ER_TRI 0xFFFFFFF0 |
||
| 5598 | #define S_028230_ER_POINT(x) (((x) & 0x0F) << 4) |
||
| 5599 | #define G_028230_ER_POINT(x) (((x) >> 4) & 0x0F) |
||
| 5600 | #define C_028230_ER_POINT 0xFFFFFF0F |
||
| 5601 | #define S_028230_ER_RECT(x) (((x) & 0x0F) << 8) |
||
| 5602 | #define G_028230_ER_RECT(x) (((x) >> 8) & 0x0F) |
||
| 5603 | #define C_028230_ER_RECT 0xFFFFF0FF |
||
| 5604 | #define S_028230_ER_LINE_LR(x) (((x) & 0x3F) << 12) |
||
| 5605 | #define G_028230_ER_LINE_LR(x) (((x) >> 12) & 0x3F) |
||
| 5606 | #define C_028230_ER_LINE_LR 0xFFFC0FFF |
||
| 5607 | #define S_028230_ER_LINE_RL(x) (((x) & 0x3F) << 18) |
||
| 5608 | #define G_028230_ER_LINE_RL(x) (((x) >> 18) & 0x3F) |
||
| 5609 | #define C_028230_ER_LINE_RL 0xFF03FFFF |
||
| 5610 | #define S_028230_ER_LINE_TB(x) (((x) & 0x0F) << 24) |
||
| 5611 | #define G_028230_ER_LINE_TB(x) (((x) >> 24) & 0x0F) |
||
| 5612 | #define C_028230_ER_LINE_TB 0xF0FFFFFF |
||
| 5613 | #define S_028230_ER_LINE_BT(x) (((x) & 0x0F) << 28) |
||
| 5614 | #define G_028230_ER_LINE_BT(x) (((x) >> 28) & 0x0F) |
||
| 5615 | #define C_028230_ER_LINE_BT 0x0FFFFFFF |
||
| 5616 | #define R_028234_PA_SU_HARDWARE_SCREEN_OFFSET 0x028234 |
||
| 5617 | #define S_028234_HW_SCREEN_OFFSET_X(x) (((x) & 0x1FF) << 0) |
||
| 5618 | #define G_028234_HW_SCREEN_OFFSET_X(x) (((x) >> 0) & 0x1FF) |
||
| 5619 | #define C_028234_HW_SCREEN_OFFSET_X 0xFFFFFE00 |
||
| 5620 | #define S_028234_HW_SCREEN_OFFSET_Y(x) (((x) & 0x1FF) << 16) |
||
| 5621 | #define G_028234_HW_SCREEN_OFFSET_Y(x) (((x) >> 16) & 0x1FF) |
||
| 5622 | #define C_028234_HW_SCREEN_OFFSET_Y 0xFE00FFFF |
||
| 5623 | #define R_028238_CB_TARGET_MASK 0x028238 |
||
| 5624 | #define S_028238_TARGET0_ENABLE(x) (((x) & 0x0F) << 0) |
||
| 5625 | #define G_028238_TARGET0_ENABLE(x) (((x) >> 0) & 0x0F) |
||
| 5626 | #define C_028238_TARGET0_ENABLE 0xFFFFFFF0 |
||
| 5627 | #define S_028238_TARGET1_ENABLE(x) (((x) & 0x0F) << 4) |
||
| 5628 | #define G_028238_TARGET1_ENABLE(x) (((x) >> 4) & 0x0F) |
||
| 5629 | #define C_028238_TARGET1_ENABLE 0xFFFFFF0F |
||
| 5630 | #define S_028238_TARGET2_ENABLE(x) (((x) & 0x0F) << 8) |
||
| 5631 | #define G_028238_TARGET2_ENABLE(x) (((x) >> 8) & 0x0F) |
||
| 5632 | #define C_028238_TARGET2_ENABLE 0xFFFFF0FF |
||
| 5633 | #define S_028238_TARGET3_ENABLE(x) (((x) & 0x0F) << 12) |
||
| 5634 | #define G_028238_TARGET3_ENABLE(x) (((x) >> 12) & 0x0F) |
||
| 5635 | #define C_028238_TARGET3_ENABLE 0xFFFF0FFF |
||
| 5636 | #define S_028238_TARGET4_ENABLE(x) (((x) & 0x0F) << 16) |
||
| 5637 | #define G_028238_TARGET4_ENABLE(x) (((x) >> 16) & 0x0F) |
||
| 5638 | #define C_028238_TARGET4_ENABLE 0xFFF0FFFF |
||
| 5639 | #define S_028238_TARGET5_ENABLE(x) (((x) & 0x0F) << 20) |
||
| 5640 | #define G_028238_TARGET5_ENABLE(x) (((x) >> 20) & 0x0F) |
||
| 5641 | #define C_028238_TARGET5_ENABLE 0xFF0FFFFF |
||
| 5642 | #define S_028238_TARGET6_ENABLE(x) (((x) & 0x0F) << 24) |
||
| 5643 | #define G_028238_TARGET6_ENABLE(x) (((x) >> 24) & 0x0F) |
||
| 5644 | #define C_028238_TARGET6_ENABLE 0xF0FFFFFF |
||
| 5645 | #define S_028238_TARGET7_ENABLE(x) (((x) & 0x0F) << 28) |
||
| 5646 | #define G_028238_TARGET7_ENABLE(x) (((x) >> 28) & 0x0F) |
||
| 5647 | #define C_028238_TARGET7_ENABLE 0x0FFFFFFF |
||
| 5648 | #define R_02823C_CB_SHADER_MASK 0x02823C |
||
| 5649 | #define S_02823C_OUTPUT0_ENABLE(x) (((x) & 0x0F) << 0) |
||
| 5650 | #define G_02823C_OUTPUT0_ENABLE(x) (((x) >> 0) & 0x0F) |
||
| 5651 | #define C_02823C_OUTPUT0_ENABLE 0xFFFFFFF0 |
||
| 5652 | #define S_02823C_OUTPUT1_ENABLE(x) (((x) & 0x0F) << 4) |
||
| 5653 | #define G_02823C_OUTPUT1_ENABLE(x) (((x) >> 4) & 0x0F) |
||
| 5654 | #define C_02823C_OUTPUT1_ENABLE 0xFFFFFF0F |
||
| 5655 | #define S_02823C_OUTPUT2_ENABLE(x) (((x) & 0x0F) << 8) |
||
| 5656 | #define G_02823C_OUTPUT2_ENABLE(x) (((x) >> 8) & 0x0F) |
||
| 5657 | #define C_02823C_OUTPUT2_ENABLE 0xFFFFF0FF |
||
| 5658 | #define S_02823C_OUTPUT3_ENABLE(x) (((x) & 0x0F) << 12) |
||
| 5659 | #define G_02823C_OUTPUT3_ENABLE(x) (((x) >> 12) & 0x0F) |
||
| 5660 | #define C_02823C_OUTPUT3_ENABLE 0xFFFF0FFF |
||
| 5661 | #define S_02823C_OUTPUT4_ENABLE(x) (((x) & 0x0F) << 16) |
||
| 5662 | #define G_02823C_OUTPUT4_ENABLE(x) (((x) >> 16) & 0x0F) |
||
| 5663 | #define C_02823C_OUTPUT4_ENABLE 0xFFF0FFFF |
||
| 5664 | #define S_02823C_OUTPUT5_ENABLE(x) (((x) & 0x0F) << 20) |
||
| 5665 | #define G_02823C_OUTPUT5_ENABLE(x) (((x) >> 20) & 0x0F) |
||
| 5666 | #define C_02823C_OUTPUT5_ENABLE 0xFF0FFFFF |
||
| 5667 | #define S_02823C_OUTPUT6_ENABLE(x) (((x) & 0x0F) << 24) |
||
| 5668 | #define G_02823C_OUTPUT6_ENABLE(x) (((x) >> 24) & 0x0F) |
||
| 5669 | #define C_02823C_OUTPUT6_ENABLE 0xF0FFFFFF |
||
| 5670 | #define S_02823C_OUTPUT7_ENABLE(x) (((x) & 0x0F) << 28) |
||
| 5671 | #define G_02823C_OUTPUT7_ENABLE(x) (((x) >> 28) & 0x0F) |
||
| 5672 | #define C_02823C_OUTPUT7_ENABLE 0x0FFFFFFF |
||
| 5673 | #define R_028240_PA_SC_GENERIC_SCISSOR_TL 0x028240 |
||
| 5674 | #define S_028240_TL_X(x) (((x) & 0x7FFF) << 0) |
||
| 5675 | #define G_028240_TL_X(x) (((x) >> 0) & 0x7FFF) |
||
| 5676 | #define C_028240_TL_X 0xFFFF8000 |
||
| 5677 | #define S_028240_TL_Y(x) (((x) & 0x7FFF) << 16) |
||
| 5678 | #define G_028240_TL_Y(x) (((x) >> 16) & 0x7FFF) |
||
| 5679 | #define C_028240_TL_Y 0x8000FFFF |
||
| 5680 | #define S_028240_WINDOW_OFFSET_DISABLE(x) (((x) & 0x1) << 31) |
||
| 5681 | #define G_028240_WINDOW_OFFSET_DISABLE(x) (((x) >> 31) & 0x1) |
||
| 5682 | #define C_028240_WINDOW_OFFSET_DISABLE 0x7FFFFFFF |
||
| 5683 | #define R_028244_PA_SC_GENERIC_SCISSOR_BR 0x028244 |
||
| 5684 | #define S_028244_BR_X(x) (((x) & 0x7FFF) << 0) |
||
| 5685 | #define G_028244_BR_X(x) (((x) >> 0) & 0x7FFF) |
||
| 5686 | #define C_028244_BR_X 0xFFFF8000 |
||
| 5687 | #define S_028244_BR_Y(x) (((x) & 0x7FFF) << 16) |
||
| 5688 | #define G_028244_BR_Y(x) (((x) >> 16) & 0x7FFF) |
||
| 5689 | #define C_028244_BR_Y 0x8000FFFF |
||
| 5690 | #define R_028250_PA_SC_VPORT_SCISSOR_0_TL 0x028250 |
||
| 5691 | #define S_028250_TL_X(x) (((x) & 0x7FFF) << 0) |
||
| 5692 | #define G_028250_TL_X(x) (((x) >> 0) & 0x7FFF) |
||
| 5693 | #define C_028250_TL_X 0xFFFF8000 |
||
| 5694 | #define S_028250_TL_Y(x) (((x) & 0x7FFF) << 16) |
||
| 5695 | #define G_028250_TL_Y(x) (((x) >> 16) & 0x7FFF) |
||
| 5696 | #define C_028250_TL_Y 0x8000FFFF |
||
| 5697 | #define S_028250_WINDOW_OFFSET_DISABLE(x) (((x) & 0x1) << 31) |
||
| 5698 | #define G_028250_WINDOW_OFFSET_DISABLE(x) (((x) >> 31) & 0x1) |
||
| 5699 | #define C_028250_WINDOW_OFFSET_DISABLE 0x7FFFFFFF |
||
| 5700 | #define R_028254_PA_SC_VPORT_SCISSOR_0_BR 0x028254 |
||
| 5701 | #define S_028254_BR_X(x) (((x) & 0x7FFF) << 0) |
||
| 5702 | #define G_028254_BR_X(x) (((x) >> 0) & 0x7FFF) |
||
| 5703 | #define C_028254_BR_X 0xFFFF8000 |
||
| 5704 | #define S_028254_BR_Y(x) (((x) & 0x7FFF) << 16) |
||
| 5705 | #define G_028254_BR_Y(x) (((x) >> 16) & 0x7FFF) |
||
| 5706 | #define C_028254_BR_Y 0x8000FFFF |
||
| 5707 | #define R_0282D0_PA_SC_VPORT_ZMIN_0 0x0282D0 |
||
| 5708 | #define R_0282D4_PA_SC_VPORT_ZMAX_0 0x0282D4 |
||
| 5709 | #define R_028350_PA_SC_RASTER_CONFIG 0x028350 |
||
| 5710 | #define S_028350_RB_MAP_PKR0(x) (((x) & 0x03) << 0) |
||
| 5711 | #define G_028350_RB_MAP_PKR0(x) (((x) >> 0) & 0x03) |
||
| 5712 | #define C_028350_RB_MAP_PKR0 0xFFFFFFFC |
||
| 5713 | #define V_028350_RASTER_CONFIG_RB_MAP_0 0x00 |
||
| 5714 | #define V_028350_RASTER_CONFIG_RB_MAP_1 0x01 |
||
| 5715 | #define V_028350_RASTER_CONFIG_RB_MAP_2 0x02 |
||
| 5716 | #define V_028350_RASTER_CONFIG_RB_MAP_3 0x03 |
||
| 5717 | #define S_028350_RB_MAP_PKR1(x) (((x) & 0x03) << 2) |
||
| 5718 | #define G_028350_RB_MAP_PKR1(x) (((x) >> 2) & 0x03) |
||
| 5719 | #define C_028350_RB_MAP_PKR1 0xFFFFFFF3 |
||
| 5720 | #define V_028350_RASTER_CONFIG_RB_MAP_0 0x00 |
||
| 5721 | #define V_028350_RASTER_CONFIG_RB_MAP_1 0x01 |
||
| 5722 | #define V_028350_RASTER_CONFIG_RB_MAP_2 0x02 |
||
| 5723 | #define V_028350_RASTER_CONFIG_RB_MAP_3 0x03 |
||
| 5724 | #define S_028350_RB_XSEL2(x) (((x) & 0x03) << 4) |
||
| 5725 | #define G_028350_RB_XSEL2(x) (((x) >> 4) & 0x03) |
||
| 5726 | #define C_028350_RB_XSEL2 0xFFFFFFCF |
||
| 5727 | #define V_028350_RASTER_CONFIG_RB_XSEL2_0 0x00 |
||
| 5728 | #define V_028350_RASTER_CONFIG_RB_XSEL2_1 0x01 |
||
| 5729 | #define V_028350_RASTER_CONFIG_RB_XSEL2_2 0x02 |
||
| 5730 | #define V_028350_RASTER_CONFIG_RB_XSEL2_3 0x03 |
||
| 5731 | #define S_028350_RB_XSEL(x) (((x) & 0x1) << 6) |
||
| 5732 | #define G_028350_RB_XSEL(x) (((x) >> 6) & 0x1) |
||
| 5733 | #define C_028350_RB_XSEL 0xFFFFFFBF |
||
| 5734 | #define S_028350_RB_YSEL(x) (((x) & 0x1) << 7) |
||
| 5735 | #define G_028350_RB_YSEL(x) (((x) >> 7) & 0x1) |
||
| 5736 | #define C_028350_RB_YSEL 0xFFFFFF7F |
||
| 5737 | #define S_028350_PKR_MAP(x) (((x) & 0x03) << 8) |
||
| 5738 | #define G_028350_PKR_MAP(x) (((x) >> 8) & 0x03) |
||
| 5739 | #define C_028350_PKR_MAP 0xFFFFFCFF |
||
| 5740 | #define V_028350_RASTER_CONFIG_PKR_MAP_0 0x00 |
||
| 5741 | #define V_028350_RASTER_CONFIG_PKR_MAP_1 0x01 |
||
| 5742 | #define V_028350_RASTER_CONFIG_PKR_MAP_2 0x02 |
||
| 5743 | #define V_028350_RASTER_CONFIG_PKR_MAP_3 0x03 |
||
| 5744 | #define S_028350_PKR_XSEL(x) (((x) & 0x03) << 10) |
||
| 5745 | #define G_028350_PKR_XSEL(x) (((x) >> 10) & 0x03) |
||
| 5746 | #define C_028350_PKR_XSEL 0xFFFFF3FF |
||
| 5747 | #define V_028350_RASTER_CONFIG_PKR_XSEL_0 0x00 |
||
| 5748 | #define V_028350_RASTER_CONFIG_PKR_XSEL_1 0x01 |
||
| 5749 | #define V_028350_RASTER_CONFIG_PKR_XSEL_2 0x02 |
||
| 5750 | #define V_028350_RASTER_CONFIG_PKR_XSEL_3 0x03 |
||
| 5751 | #define S_028350_PKR_YSEL(x) (((x) & 0x03) << 12) |
||
| 5752 | #define G_028350_PKR_YSEL(x) (((x) >> 12) & 0x03) |
||
| 5753 | #define C_028350_PKR_YSEL 0xFFFFCFFF |
||
| 5754 | #define V_028350_RASTER_CONFIG_PKR_YSEL_0 0x00 |
||
| 5755 | #define V_028350_RASTER_CONFIG_PKR_YSEL_1 0x01 |
||
| 5756 | #define V_028350_RASTER_CONFIG_PKR_YSEL_2 0x02 |
||
| 5757 | #define V_028350_RASTER_CONFIG_PKR_YSEL_3 0x03 |
||
| 5758 | #define S_028350_PKR_XSEL2(x) (((x) & 0x03) << 14) |
||
| 5759 | #define G_028350_PKR_XSEL2(x) (((x) >> 14) & 0x03) |
||
| 5760 | #define C_028350_PKR_XSEL2 0xFFFF3FFF |
||
| 5761 | #define V_028350_RASTER_CONFIG_PKR_XSEL2_0 0x00 |
||
| 5762 | #define V_028350_RASTER_CONFIG_PKR_XSEL2_1 0x01 |
||
| 5763 | #define V_028350_RASTER_CONFIG_PKR_XSEL2_2 0x02 |
||
| 5764 | #define V_028350_RASTER_CONFIG_PKR_XSEL2_3 0x03 |
||
| 5765 | #define S_028350_SC_MAP(x) (((x) & 0x03) << 16) |
||
| 5766 | #define G_028350_SC_MAP(x) (((x) >> 16) & 0x03) |
||
| 5767 | #define C_028350_SC_MAP 0xFFFCFFFF |
||
| 5768 | #define V_028350_RASTER_CONFIG_SC_MAP_0 0x00 |
||
| 5769 | #define V_028350_RASTER_CONFIG_SC_MAP_1 0x01 |
||
| 5770 | #define V_028350_RASTER_CONFIG_SC_MAP_2 0x02 |
||
| 5771 | #define V_028350_RASTER_CONFIG_SC_MAP_3 0x03 |
||
| 5772 | #define S_028350_SC_XSEL(x) (((x) & 0x03) << 18) |
||
| 5773 | #define G_028350_SC_XSEL(x) (((x) >> 18) & 0x03) |
||
| 5774 | #define C_028350_SC_XSEL 0xFFF3FFFF |
||
| 5775 | #define V_028350_RASTER_CONFIG_SC_XSEL_8_WIDE_TILE 0x00 |
||
| 5776 | #define V_028350_RASTER_CONFIG_SC_XSEL_16_WIDE_TILE 0x01 |
||
| 5777 | #define V_028350_RASTER_CONFIG_SC_XSEL_32_WIDE_TILE 0x02 |
||
| 5778 | #define V_028350_RASTER_CONFIG_SC_XSEL_64_WIDE_TILE 0x03 |
||
| 5779 | #define S_028350_SC_YSEL(x) (((x) & 0x03) << 20) |
||
| 5780 | #define G_028350_SC_YSEL(x) (((x) >> 20) & 0x03) |
||
| 5781 | #define C_028350_SC_YSEL 0xFFCFFFFF |
||
| 5782 | #define V_028350_RASTER_CONFIG_SC_YSEL_8_WIDE_TILE 0x00 |
||
| 5783 | #define V_028350_RASTER_CONFIG_SC_YSEL_16_WIDE_TILE 0x01 |
||
| 5784 | #define V_028350_RASTER_CONFIG_SC_YSEL_32_WIDE_TILE 0x02 |
||
| 5785 | #define V_028350_RASTER_CONFIG_SC_YSEL_64_WIDE_TILE 0x03 |
||
| 5786 | #define S_028350_SE_MAP(x) (((x) & 0x03) << 24) |
||
| 5787 | #define G_028350_SE_MAP(x) (((x) >> 24) & 0x03) |
||
| 5788 | #define C_028350_SE_MAP 0xFCFFFFFF |
||
| 5789 | #define V_028350_RASTER_CONFIG_SE_MAP_0 0x00 |
||
| 5790 | #define V_028350_RASTER_CONFIG_SE_MAP_1 0x01 |
||
| 5791 | #define V_028350_RASTER_CONFIG_SE_MAP_2 0x02 |
||
| 5792 | #define V_028350_RASTER_CONFIG_SE_MAP_3 0x03 |
||
| 5793 | #define S_028350_SE_XSEL(x) (((x) & 0x03) << 26) |
||
| 5794 | #define G_028350_SE_XSEL(x) (((x) >> 26) & 0x03) |
||
| 5795 | #define C_028350_SE_XSEL 0xF3FFFFFF |
||
| 5796 | #define V_028350_RASTER_CONFIG_SE_XSEL_8_WIDE_TILE 0x00 |
||
| 5797 | #define V_028350_RASTER_CONFIG_SE_XSEL_16_WIDE_TILE 0x01 |
||
| 5798 | #define V_028350_RASTER_CONFIG_SE_XSEL_32_WIDE_TILE 0x02 |
||
| 5799 | #define V_028350_RASTER_CONFIG_SE_XSEL_64_WIDE_TILE 0x03 |
||
| 5800 | #define S_028350_SE_YSEL(x) (((x) & 0x03) << 28) |
||
| 5801 | #define G_028350_SE_YSEL(x) (((x) >> 28) & 0x03) |
||
| 5802 | #define C_028350_SE_YSEL 0xCFFFFFFF |
||
| 5803 | #define V_028350_RASTER_CONFIG_SE_YSEL_8_WIDE_TILE 0x00 |
||
| 5804 | #define V_028350_RASTER_CONFIG_SE_YSEL_16_WIDE_TILE 0x01 |
||
| 5805 | #define V_028350_RASTER_CONFIG_SE_YSEL_32_WIDE_TILE 0x02 |
||
| 5806 | #define V_028350_RASTER_CONFIG_SE_YSEL_64_WIDE_TILE 0x03 |
||
| 5807 | /* CIK */ |
||
| 5808 | #define R_028354_PA_SC_RASTER_CONFIG_1 0x028354 |
||
| 5809 | #define S_028354_SE_PAIR_MAP(x) (((x) & 0x03) << 0) |
||
| 5810 | #define G_028354_SE_PAIR_MAP(x) (((x) >> 0) & 0x03) |
||
| 5811 | #define C_028354_SE_PAIR_MAP 0xFFFFFFFC |
||
| 5812 | #define V_028354_RASTER_CONFIG_SE_PAIR_MAP_0 0x00 |
||
| 5813 | #define V_028354_RASTER_CONFIG_SE_PAIR_MAP_1 0x01 |
||
| 5814 | #define V_028354_RASTER_CONFIG_SE_PAIR_MAP_2 0x02 |
||
| 5815 | #define V_028354_RASTER_CONFIG_SE_PAIR_MAP_3 0x03 |
||
| 5816 | #define S_028354_SE_PAIR_XSEL(x) (((x) & 0x03) << 2) |
||
| 5817 | #define G_028354_SE_PAIR_XSEL(x) (((x) >> 2) & 0x03) |
||
| 5818 | #define C_028354_SE_PAIR_XSEL 0xFFFFFFF3 |
||
| 5819 | #define V_028354_RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE 0x00 |
||
| 5820 | #define V_028354_RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE 0x01 |
||
| 5821 | #define V_028354_RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE 0x02 |
||
| 5822 | #define V_028354_RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE 0x03 |
||
| 5823 | #define S_028354_SE_PAIR_YSEL(x) (((x) & 0x03) << 4) |
||
| 5824 | #define G_028354_SE_PAIR_YSEL(x) (((x) >> 4) & 0x03) |
||
| 5825 | #define C_028354_SE_PAIR_YSEL 0xFFFFFFCF |
||
| 5826 | #define V_028354_RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE 0x00 |
||
| 5827 | #define V_028354_RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE 0x01 |
||
| 5828 | #define V_028354_RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE 0x02 |
||
| 5829 | #define V_028354_RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE 0x03 |
||
| 5830 | /* */ |
||
| 5831 | #define R_028400_VGT_MAX_VTX_INDX 0x028400 |
||
| 5832 | #define R_028404_VGT_MIN_VTX_INDX 0x028404 |
||
| 5833 | #define R_028408_VGT_INDX_OFFSET 0x028408 |
||
| 5834 | #define R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX 0x02840C |
||
| 5835 | #define R_028414_CB_BLEND_RED 0x028414 |
||
| 5836 | #define R_028418_CB_BLEND_GREEN 0x028418 |
||
| 5837 | #define R_02841C_CB_BLEND_BLUE 0x02841C |
||
| 5838 | #define R_028420_CB_BLEND_ALPHA 0x028420 |
||
| 5839 | #define R_02842C_DB_STENCIL_CONTROL 0x02842C |
||
| 5840 | #define S_02842C_STENCILFAIL(x) (((x) & 0x0F) << 0) |
||
| 5841 | #define G_02842C_STENCILFAIL(x) (((x) >> 0) & 0x0F) |
||
| 5842 | #define C_02842C_STENCILFAIL 0xFFFFFFF0 |
||
| 5843 | #define V_02842C_STENCIL_KEEP 0x00 |
||
| 5844 | #define V_02842C_STENCIL_ZERO 0x01 |
||
| 5845 | #define V_02842C_STENCIL_ONES 0x02 |
||
| 5846 | #define V_02842C_STENCIL_REPLACE_TEST 0x03 |
||
| 5847 | #define V_02842C_STENCIL_REPLACE_OP 0x04 |
||
| 5848 | #define V_02842C_STENCIL_ADD_CLAMP 0x05 |
||
| 5849 | #define V_02842C_STENCIL_SUB_CLAMP 0x06 |
||
| 5850 | #define V_02842C_STENCIL_INVERT 0x07 |
||
| 5851 | #define V_02842C_STENCIL_ADD_WRAP 0x08 |
||
| 5852 | #define V_02842C_STENCIL_SUB_WRAP 0x09 |
||
| 5853 | #define V_02842C_STENCIL_AND 0x0A |
||
| 5854 | #define V_02842C_STENCIL_OR 0x0B |
||
| 5855 | #define V_02842C_STENCIL_XOR 0x0C |
||
| 5856 | #define V_02842C_STENCIL_NAND 0x0D |
||
| 5857 | #define V_02842C_STENCIL_NOR 0x0E |
||
| 5858 | #define V_02842C_STENCIL_XNOR 0x0F |
||
| 5859 | #define S_02842C_STENCILZPASS(x) (((x) & 0x0F) << 4) |
||
| 5860 | #define G_02842C_STENCILZPASS(x) (((x) >> 4) & 0x0F) |
||
| 5861 | #define C_02842C_STENCILZPASS 0xFFFFFF0F |
||
| 5862 | #define V_02842C_STENCIL_KEEP 0x00 |
||
| 5863 | #define V_02842C_STENCIL_ZERO 0x01 |
||
| 5864 | #define V_02842C_STENCIL_ONES 0x02 |
||
| 5865 | #define V_02842C_STENCIL_REPLACE_TEST 0x03 |
||
| 5866 | #define V_02842C_STENCIL_REPLACE_OP 0x04 |
||
| 5867 | #define V_02842C_STENCIL_ADD_CLAMP 0x05 |
||
| 5868 | #define V_02842C_STENCIL_SUB_CLAMP 0x06 |
||
| 5869 | #define V_02842C_STENCIL_INVERT 0x07 |
||
| 5870 | #define V_02842C_STENCIL_ADD_WRAP 0x08 |
||
| 5871 | #define V_02842C_STENCIL_SUB_WRAP 0x09 |
||
| 5872 | #define V_02842C_STENCIL_AND 0x0A |
||
| 5873 | #define V_02842C_STENCIL_OR 0x0B |
||
| 5874 | #define V_02842C_STENCIL_XOR 0x0C |
||
| 5875 | #define V_02842C_STENCIL_NAND 0x0D |
||
| 5876 | #define V_02842C_STENCIL_NOR 0x0E |
||
| 5877 | #define V_02842C_STENCIL_XNOR 0x0F |
||
| 5878 | #define S_02842C_STENCILZFAIL(x) (((x) & 0x0F) << 8) |
||
| 5879 | #define G_02842C_STENCILZFAIL(x) (((x) >> 8) & 0x0F) |
||
| 5880 | #define C_02842C_STENCILZFAIL 0xFFFFF0FF |
||
| 5881 | #define V_02842C_STENCIL_KEEP 0x00 |
||
| 5882 | #define V_02842C_STENCIL_ZERO 0x01 |
||
| 5883 | #define V_02842C_STENCIL_ONES 0x02 |
||
| 5884 | #define V_02842C_STENCIL_REPLACE_TEST 0x03 |
||
| 5885 | #define V_02842C_STENCIL_REPLACE_OP 0x04 |
||
| 5886 | #define V_02842C_STENCIL_ADD_CLAMP 0x05 |
||
| 5887 | #define V_02842C_STENCIL_SUB_CLAMP 0x06 |
||
| 5888 | #define V_02842C_STENCIL_INVERT 0x07 |
||
| 5889 | #define V_02842C_STENCIL_ADD_WRAP 0x08 |
||
| 5890 | #define V_02842C_STENCIL_SUB_WRAP 0x09 |
||
| 5891 | #define V_02842C_STENCIL_AND 0x0A |
||
| 5892 | #define V_02842C_STENCIL_OR 0x0B |
||
| 5893 | #define V_02842C_STENCIL_XOR 0x0C |
||
| 5894 | #define V_02842C_STENCIL_NAND 0x0D |
||
| 5895 | #define V_02842C_STENCIL_NOR 0x0E |
||
| 5896 | #define V_02842C_STENCIL_XNOR 0x0F |
||
| 5897 | #define S_02842C_STENCILFAIL_BF(x) (((x) & 0x0F) << 12) |
||
| 5898 | #define G_02842C_STENCILFAIL_BF(x) (((x) >> 12) & 0x0F) |
||
| 5899 | #define C_02842C_STENCILFAIL_BF 0xFFFF0FFF |
||
| 5900 | #define V_02842C_STENCIL_KEEP 0x00 |
||
| 5901 | #define V_02842C_STENCIL_ZERO 0x01 |
||
| 5902 | #define V_02842C_STENCIL_ONES 0x02 |
||
| 5903 | #define V_02842C_STENCIL_REPLACE_TEST 0x03 |
||
| 5904 | #define V_02842C_STENCIL_REPLACE_OP 0x04 |
||
| 5905 | #define V_02842C_STENCIL_ADD_CLAMP 0x05 |
||
| 5906 | #define V_02842C_STENCIL_SUB_CLAMP 0x06 |
||
| 5907 | #define V_02842C_STENCIL_INVERT 0x07 |
||
| 5908 | #define V_02842C_STENCIL_ADD_WRAP 0x08 |
||
| 5909 | #define V_02842C_STENCIL_SUB_WRAP 0x09 |
||
| 5910 | #define V_02842C_STENCIL_AND 0x0A |
||
| 5911 | #define V_02842C_STENCIL_OR 0x0B |
||
| 5912 | #define V_02842C_STENCIL_XOR 0x0C |
||
| 5913 | #define V_02842C_STENCIL_NAND 0x0D |
||
| 5914 | #define V_02842C_STENCIL_NOR 0x0E |
||
| 5915 | #define V_02842C_STENCIL_XNOR 0x0F |
||
| 5916 | #define S_02842C_STENCILZPASS_BF(x) (((x) & 0x0F) << 16) |
||
| 5917 | #define G_02842C_STENCILZPASS_BF(x) (((x) >> 16) & 0x0F) |
||
| 5918 | #define C_02842C_STENCILZPASS_BF 0xFFF0FFFF |
||
| 5919 | #define V_02842C_STENCIL_KEEP 0x00 |
||
| 5920 | #define V_02842C_STENCIL_ZERO 0x01 |
||
| 5921 | #define V_02842C_STENCIL_ONES 0x02 |
||
| 5922 | #define V_02842C_STENCIL_REPLACE_TEST 0x03 |
||
| 5923 | #define V_02842C_STENCIL_REPLACE_OP 0x04 |
||
| 5924 | #define V_02842C_STENCIL_ADD_CLAMP 0x05 |
||
| 5925 | #define V_02842C_STENCIL_SUB_CLAMP 0x06 |
||
| 5926 | #define V_02842C_STENCIL_INVERT 0x07 |
||
| 5927 | #define V_02842C_STENCIL_ADD_WRAP 0x08 |
||
| 5928 | #define V_02842C_STENCIL_SUB_WRAP 0x09 |
||
| 5929 | #define V_02842C_STENCIL_AND 0x0A |
||
| 5930 | #define V_02842C_STENCIL_OR 0x0B |
||
| 5931 | #define V_02842C_STENCIL_XOR 0x0C |
||
| 5932 | #define V_02842C_STENCIL_NAND 0x0D |
||
| 5933 | #define V_02842C_STENCIL_NOR 0x0E |
||
| 5934 | #define V_02842C_STENCIL_XNOR 0x0F |
||
| 5935 | #define S_02842C_STENCILZFAIL_BF(x) (((x) & 0x0F) << 20) |
||
| 5936 | #define G_02842C_STENCILZFAIL_BF(x) (((x) >> 20) & 0x0F) |
||
| 5937 | #define C_02842C_STENCILZFAIL_BF 0xFF0FFFFF |
||
| 5938 | #define V_02842C_STENCIL_KEEP 0x00 |
||
| 5939 | #define V_02842C_STENCIL_ZERO 0x01 |
||
| 5940 | #define V_02842C_STENCIL_ONES 0x02 |
||
| 5941 | #define V_02842C_STENCIL_REPLACE_TEST 0x03 |
||
| 5942 | #define V_02842C_STENCIL_REPLACE_OP 0x04 |
||
| 5943 | #define V_02842C_STENCIL_ADD_CLAMP 0x05 |
||
| 5944 | #define V_02842C_STENCIL_SUB_CLAMP 0x06 |
||
| 5945 | #define V_02842C_STENCIL_INVERT 0x07 |
||
| 5946 | #define V_02842C_STENCIL_ADD_WRAP 0x08 |
||
| 5947 | #define V_02842C_STENCIL_SUB_WRAP 0x09 |
||
| 5948 | #define V_02842C_STENCIL_AND 0x0A |
||
| 5949 | #define V_02842C_STENCIL_OR 0x0B |
||
| 5950 | #define V_02842C_STENCIL_XOR 0x0C |
||
| 5951 | #define V_02842C_STENCIL_NAND 0x0D |
||
| 5952 | #define V_02842C_STENCIL_NOR 0x0E |
||
| 5953 | #define V_02842C_STENCIL_XNOR 0x0F |
||
| 5954 | #define R_028430_DB_STENCILREFMASK 0x028430 |
||
| 5955 | #define S_028430_STENCILTESTVAL(x) (((x) & 0xFF) << 0) |
||
| 5956 | #define G_028430_STENCILTESTVAL(x) (((x) >> 0) & 0xFF) |
||
| 5957 | #define C_028430_STENCILTESTVAL 0xFFFFFF00 |
||
| 5958 | #define S_028430_STENCILMASK(x) (((x) & 0xFF) << 8) |
||
| 5959 | #define G_028430_STENCILMASK(x) (((x) >> 8) & 0xFF) |
||
| 5960 | #define C_028430_STENCILMASK 0xFFFF00FF |
||
| 5961 | #define S_028430_STENCILWRITEMASK(x) (((x) & 0xFF) << 16) |
||
| 5962 | #define G_028430_STENCILWRITEMASK(x) (((x) >> 16) & 0xFF) |
||
| 5963 | #define C_028430_STENCILWRITEMASK 0xFF00FFFF |
||
| 5964 | #define S_028430_STENCILOPVAL(x) (((x) & 0xFF) << 24) |
||
| 5965 | #define G_028430_STENCILOPVAL(x) (((x) >> 24) & 0xFF) |
||
| 5966 | #define C_028430_STENCILOPVAL 0x00FFFFFF |
||
| 5967 | #define R_028434_DB_STENCILREFMASK_BF 0x028434 |
||
| 5968 | #define S_028434_STENCILTESTVAL_BF(x) (((x) & 0xFF) << 0) |
||
| 5969 | #define G_028434_STENCILTESTVAL_BF(x) (((x) >> 0) & 0xFF) |
||
| 5970 | #define C_028434_STENCILTESTVAL_BF 0xFFFFFF00 |
||
| 5971 | #define S_028434_STENCILMASK_BF(x) (((x) & 0xFF) << 8) |
||
| 5972 | #define G_028434_STENCILMASK_BF(x) (((x) >> 8) & 0xFF) |
||
| 5973 | #define C_028434_STENCILMASK_BF 0xFFFF00FF |
||
| 5974 | #define S_028434_STENCILWRITEMASK_BF(x) (((x) & 0xFF) << 16) |
||
| 5975 | #define G_028434_STENCILWRITEMASK_BF(x) (((x) >> 16) & 0xFF) |
||
| 5976 | #define C_028434_STENCILWRITEMASK_BF 0xFF00FFFF |
||
| 5977 | #define S_028434_STENCILOPVAL_BF(x) (((x) & 0xFF) << 24) |
||
| 5978 | #define G_028434_STENCILOPVAL_BF(x) (((x) >> 24) & 0xFF) |
||
| 5979 | #define C_028434_STENCILOPVAL_BF 0x00FFFFFF |
||
| 5980 | #define R_02843C_PA_CL_VPORT_XSCALE_0 0x02843C |
||
| 5981 | #define R_028440_PA_CL_VPORT_XOFFSET_0 0x028440 |
||
| 5982 | #define R_028444_PA_CL_VPORT_YSCALE_0 0x028444 |
||
| 5983 | #define R_028448_PA_CL_VPORT_YOFFSET_0 0x028448 |
||
| 5984 | #define R_02844C_PA_CL_VPORT_ZSCALE_0 0x02844C |
||
| 5985 | #define R_028450_PA_CL_VPORT_ZOFFSET_0 0x028450 |
||
| 5986 | #define R_0285BC_PA_CL_UCP_0_X 0x0285BC |
||
| 5987 | #define R_0285C0_PA_CL_UCP_0_Y 0x0285C0 |
||
| 5988 | #define R_0285C4_PA_CL_UCP_0_Z 0x0285C4 |
||
| 5989 | #define R_0285C8_PA_CL_UCP_0_W 0x0285C8 |
||
| 5990 | #define R_0285CC_PA_CL_UCP_1_X 0x0285CC |
||
| 5991 | #define R_0285D0_PA_CL_UCP_1_Y 0x0285D0 |
||
| 5992 | #define R_0285D4_PA_CL_UCP_1_Z 0x0285D4 |
||
| 5993 | #define R_0285D8_PA_CL_UCP_1_W 0x0285D8 |
||
| 5994 | #define R_0285DC_PA_CL_UCP_2_X 0x0285DC |
||
| 5995 | #define R_0285E0_PA_CL_UCP_2_Y 0x0285E0 |
||
| 5996 | #define R_0285E4_PA_CL_UCP_2_Z 0x0285E4 |
||
| 5997 | #define R_0285E8_PA_CL_UCP_2_W 0x0285E8 |
||
| 5998 | #define R_0285EC_PA_CL_UCP_3_X 0x0285EC |
||
| 5999 | #define R_0285F0_PA_CL_UCP_3_Y 0x0285F0 |
||
| 6000 | #define R_0285F4_PA_CL_UCP_3_Z 0x0285F4 |
||
| 6001 | #define R_0285F8_PA_CL_UCP_3_W 0x0285F8 |
||
| 6002 | #define R_0285FC_PA_CL_UCP_4_X 0x0285FC |
||
| 6003 | #define R_028600_PA_CL_UCP_4_Y 0x028600 |
||
| 6004 | #define R_028604_PA_CL_UCP_4_Z 0x028604 |
||
| 6005 | #define R_028608_PA_CL_UCP_4_W 0x028608 |
||
| 6006 | #define R_02860C_PA_CL_UCP_5_X 0x02860C |
||
| 6007 | #define R_028610_PA_CL_UCP_5_Y 0x028610 |
||
| 6008 | #define R_028614_PA_CL_UCP_5_Z 0x028614 |
||
| 6009 | #define R_028618_PA_CL_UCP_5_W 0x028618 |
||
| 6010 | #define R_028644_SPI_PS_INPUT_CNTL_0 0x028644 |
||
| 6011 | #define S_028644_OFFSET(x) (((x) & 0x3F) << 0) |
||
| 6012 | #define G_028644_OFFSET(x) (((x) >> 0) & 0x3F) |
||
| 6013 | #define C_028644_OFFSET 0xFFFFFFC0 |
||
| 6014 | #define S_028644_DEFAULT_VAL(x) (((x) & 0x03) << 8) |
||
| 6015 | #define G_028644_DEFAULT_VAL(x) (((x) >> 8) & 0x03) |
||
| 6016 | #define C_028644_DEFAULT_VAL 0xFFFFFCFF |
||
| 6017 | #define V_028644_X_0_0F 0x00 |
||
| 6018 | #define S_028644_FLAT_SHADE(x) (((x) & 0x1) << 10) |
||
| 6019 | #define G_028644_FLAT_SHADE(x) (((x) >> 10) & 0x1) |
||
| 6020 | #define C_028644_FLAT_SHADE 0xFFFFFBFF |
||
| 6021 | #define S_028644_CYL_WRAP(x) (((x) & 0x0F) << 13) |
||
| 6022 | #define G_028644_CYL_WRAP(x) (((x) >> 13) & 0x0F) |
||
| 6023 | #define C_028644_CYL_WRAP 0xFFFE1FFF |
||
| 6024 | #define S_028644_PT_SPRITE_TEX(x) (((x) & 0x1) << 17) |
||
| 6025 | #define G_028644_PT_SPRITE_TEX(x) (((x) >> 17) & 0x1) |
||
| 6026 | #define C_028644_PT_SPRITE_TEX 0xFFFDFFFF |
||
| 6027 | /* CIK */ |
||
| 6028 | #define S_028644_DUP(x) (((x) & 0x1) << 18) |
||
| 6029 | #define G_028644_DUP(x) (((x) >> 18) & 0x1) |
||
| 6030 | #define C_028644_DUP 0xFFFBFFFF |
||
| 6031 | /* */ |
||
| 6032 | #define R_028648_SPI_PS_INPUT_CNTL_1 0x028648 |
||
| 6033 | #define R_02864C_SPI_PS_INPUT_CNTL_2 0x02864C |
||
| 6034 | #define R_028650_SPI_PS_INPUT_CNTL_3 0x028650 |
||
| 6035 | #define R_028654_SPI_PS_INPUT_CNTL_4 0x028654 |
||
| 6036 | #define R_028658_SPI_PS_INPUT_CNTL_5 0x028658 |
||
| 6037 | #define R_02865C_SPI_PS_INPUT_CNTL_6 0x02865C |
||
| 6038 | #define R_028660_SPI_PS_INPUT_CNTL_7 0x028660 |
||
| 6039 | #define R_028664_SPI_PS_INPUT_CNTL_8 0x028664 |
||
| 6040 | #define R_028668_SPI_PS_INPUT_CNTL_9 0x028668 |
||
| 6041 | #define R_02866C_SPI_PS_INPUT_CNTL_10 0x02866C |
||
| 6042 | #define R_028670_SPI_PS_INPUT_CNTL_11 0x028670 |
||
| 6043 | #define R_028674_SPI_PS_INPUT_CNTL_12 0x028674 |
||
| 6044 | #define R_028678_SPI_PS_INPUT_CNTL_13 0x028678 |
||
| 6045 | #define R_02867C_SPI_PS_INPUT_CNTL_14 0x02867C |
||
| 6046 | #define R_028680_SPI_PS_INPUT_CNTL_15 0x028680 |
||
| 6047 | #define R_028684_SPI_PS_INPUT_CNTL_16 0x028684 |
||
| 6048 | #define R_028688_SPI_PS_INPUT_CNTL_17 0x028688 |
||
| 6049 | #define R_02868C_SPI_PS_INPUT_CNTL_18 0x02868C |
||
| 6050 | #define R_028690_SPI_PS_INPUT_CNTL_19 0x028690 |
||
| 6051 | #define R_028694_SPI_PS_INPUT_CNTL_20 0x028694 |
||
| 6052 | #define R_028698_SPI_PS_INPUT_CNTL_21 0x028698 |
||
| 6053 | #define R_02869C_SPI_PS_INPUT_CNTL_22 0x02869C |
||
| 6054 | #define R_0286A0_SPI_PS_INPUT_CNTL_23 0x0286A0 |
||
| 6055 | #define R_0286A4_SPI_PS_INPUT_CNTL_24 0x0286A4 |
||
| 6056 | #define R_0286A8_SPI_PS_INPUT_CNTL_25 0x0286A8 |
||
| 6057 | #define R_0286AC_SPI_PS_INPUT_CNTL_26 0x0286AC |
||
| 6058 | #define R_0286B0_SPI_PS_INPUT_CNTL_27 0x0286B0 |
||
| 6059 | #define R_0286B4_SPI_PS_INPUT_CNTL_28 0x0286B4 |
||
| 6060 | #define R_0286B8_SPI_PS_INPUT_CNTL_29 0x0286B8 |
||
| 6061 | #define R_0286BC_SPI_PS_INPUT_CNTL_30 0x0286BC |
||
| 6062 | #define R_0286C0_SPI_PS_INPUT_CNTL_31 0x0286C0 |
||
| 6063 | #define R_0286C4_SPI_VS_OUT_CONFIG 0x0286C4 |
||
| 6064 | #define S_0286C4_VS_EXPORT_COUNT(x) (((x) & 0x1F) << 1) |
||
| 6065 | #define G_0286C4_VS_EXPORT_COUNT(x) (((x) >> 1) & 0x1F) |
||
| 6066 | #define C_0286C4_VS_EXPORT_COUNT 0xFFFFFFC1 |
||
| 6067 | #define S_0286C4_VS_HALF_PACK(x) (((x) & 0x1) << 6) |
||
| 6068 | #define G_0286C4_VS_HALF_PACK(x) (((x) >> 6) & 0x1) |
||
| 6069 | #define C_0286C4_VS_HALF_PACK 0xFFFFFFBF |
||
| 6070 | #define S_0286C4_VS_EXPORTS_FOG(x) (((x) & 0x1) << 7) /* not on CIK */ |
||
| 6071 | #define G_0286C4_VS_EXPORTS_FOG(x) (((x) >> 7) & 0x1) /* not on CIK */ |
||
| 6072 | #define C_0286C4_VS_EXPORTS_FOG 0xFFFFFF7F /* not on CIK */ |
||
| 6073 | #define S_0286C4_VS_OUT_FOG_VEC_ADDR(x) (((x) & 0x1F) << 8) /* not on CIK */ |
||
| 6074 | #define G_0286C4_VS_OUT_FOG_VEC_ADDR(x) (((x) >> 8) & 0x1F) /* not on CIK */ |
||
| 6075 | #define C_0286C4_VS_OUT_FOG_VEC_ADDR 0xFFFFE0FF /* not on CIK */ |
||
| 6076 | #define R_0286CC_SPI_PS_INPUT_ENA 0x0286CC |
||
| 6077 | #define S_0286CC_PERSP_SAMPLE_ENA(x) (((x) & 0x1) << 0) |
||
| 6078 | #define G_0286CC_PERSP_SAMPLE_ENA(x) (((x) >> 0) & 0x1) |
||
| 6079 | #define C_0286CC_PERSP_SAMPLE_ENA 0xFFFFFFFE |
||
| 6080 | #define S_0286CC_PERSP_CENTER_ENA(x) (((x) & 0x1) << 1) |
||
| 6081 | #define G_0286CC_PERSP_CENTER_ENA(x) (((x) >> 1) & 0x1) |
||
| 6082 | #define C_0286CC_PERSP_CENTER_ENA 0xFFFFFFFD |
||
| 6083 | #define S_0286CC_PERSP_CENTROID_ENA(x) (((x) & 0x1) << 2) |
||
| 6084 | #define G_0286CC_PERSP_CENTROID_ENA(x) (((x) >> 2) & 0x1) |
||
| 6085 | #define C_0286CC_PERSP_CENTROID_ENA 0xFFFFFFFB |
||
| 6086 | #define S_0286CC_PERSP_PULL_MODEL_ENA(x) (((x) & 0x1) << 3) |
||
| 6087 | #define G_0286CC_PERSP_PULL_MODEL_ENA(x) (((x) >> 3) & 0x1) |
||
| 6088 | #define C_0286CC_PERSP_PULL_MODEL_ENA 0xFFFFFFF7 |
||
| 6089 | #define S_0286CC_LINEAR_SAMPLE_ENA(x) (((x) & 0x1) << 4) |
||
| 6090 | #define G_0286CC_LINEAR_SAMPLE_ENA(x) (((x) >> 4) & 0x1) |
||
| 6091 | #define C_0286CC_LINEAR_SAMPLE_ENA 0xFFFFFFEF |
||
| 6092 | #define S_0286CC_LINEAR_CENTER_ENA(x) (((x) & 0x1) << 5) |
||
| 6093 | #define G_0286CC_LINEAR_CENTER_ENA(x) (((x) >> 5) & 0x1) |
||
| 6094 | #define C_0286CC_LINEAR_CENTER_ENA 0xFFFFFFDF |
||
| 6095 | #define S_0286CC_LINEAR_CENTROID_ENA(x) (((x) & 0x1) << 6) |
||
| 6096 | #define G_0286CC_LINEAR_CENTROID_ENA(x) (((x) >> 6) & 0x1) |
||
| 6097 | #define C_0286CC_LINEAR_CENTROID_ENA 0xFFFFFFBF |
||
| 6098 | #define S_0286CC_LINE_STIPPLE_TEX_ENA(x) (((x) & 0x1) << 7) |
||
| 6099 | #define G_0286CC_LINE_STIPPLE_TEX_ENA(x) (((x) >> 7) & 0x1) |
||
| 6100 | #define C_0286CC_LINE_STIPPLE_TEX_ENA 0xFFFFFF7F |
||
| 6101 | #define S_0286CC_POS_X_FLOAT_ENA(x) (((x) & 0x1) << 8) |
||
| 6102 | #define G_0286CC_POS_X_FLOAT_ENA(x) (((x) >> 8) & 0x1) |
||
| 6103 | #define C_0286CC_POS_X_FLOAT_ENA 0xFFFFFEFF |
||
| 6104 | #define S_0286CC_POS_Y_FLOAT_ENA(x) (((x) & 0x1) << 9) |
||
| 6105 | #define G_0286CC_POS_Y_FLOAT_ENA(x) (((x) >> 9) & 0x1) |
||
| 6106 | #define C_0286CC_POS_Y_FLOAT_ENA 0xFFFFFDFF |
||
| 6107 | #define S_0286CC_POS_Z_FLOAT_ENA(x) (((x) & 0x1) << 10) |
||
| 6108 | #define G_0286CC_POS_Z_FLOAT_ENA(x) (((x) >> 10) & 0x1) |
||
| 6109 | #define C_0286CC_POS_Z_FLOAT_ENA 0xFFFFFBFF |
||
| 6110 | #define S_0286CC_POS_W_FLOAT_ENA(x) (((x) & 0x1) << 11) |
||
| 6111 | #define G_0286CC_POS_W_FLOAT_ENA(x) (((x) >> 11) & 0x1) |
||
| 6112 | #define C_0286CC_POS_W_FLOAT_ENA 0xFFFFF7FF |
||
| 6113 | #define S_0286CC_FRONT_FACE_ENA(x) (((x) & 0x1) << 12) |
||
| 6114 | #define G_0286CC_FRONT_FACE_ENA(x) (((x) >> 12) & 0x1) |
||
| 6115 | #define C_0286CC_FRONT_FACE_ENA 0xFFFFEFFF |
||
| 6116 | #define S_0286CC_ANCILLARY_ENA(x) (((x) & 0x1) << 13) |
||
| 6117 | #define G_0286CC_ANCILLARY_ENA(x) (((x) >> 13) & 0x1) |
||
| 6118 | #define C_0286CC_ANCILLARY_ENA 0xFFFFDFFF |
||
| 6119 | #define S_0286CC_SAMPLE_COVERAGE_ENA(x) (((x) & 0x1) << 14) |
||
| 6120 | #define G_0286CC_SAMPLE_COVERAGE_ENA(x) (((x) >> 14) & 0x1) |
||
| 6121 | #define C_0286CC_SAMPLE_COVERAGE_ENA 0xFFFFBFFF |
||
| 6122 | #define S_0286CC_POS_FIXED_PT_ENA(x) (((x) & 0x1) << 15) |
||
| 6123 | #define G_0286CC_POS_FIXED_PT_ENA(x) (((x) >> 15) & 0x1) |
||
| 6124 | #define C_0286CC_POS_FIXED_PT_ENA 0xFFFF7FFF |
||
| 6125 | #define R_0286D0_SPI_PS_INPUT_ADDR 0x0286D0 |
||
| 6126 | #define S_0286D0_PERSP_SAMPLE_ENA(x) (((x) & 0x1) << 0) |
||
| 6127 | #define G_0286D0_PERSP_SAMPLE_ENA(x) (((x) >> 0) & 0x1) |
||
| 6128 | #define C_0286D0_PERSP_SAMPLE_ENA 0xFFFFFFFE |
||
| 6129 | #define S_0286D0_PERSP_CENTER_ENA(x) (((x) & 0x1) << 1) |
||
| 6130 | #define G_0286D0_PERSP_CENTER_ENA(x) (((x) >> 1) & 0x1) |
||
| 6131 | #define C_0286D0_PERSP_CENTER_ENA 0xFFFFFFFD |
||
| 6132 | #define S_0286D0_PERSP_CENTROID_ENA(x) (((x) & 0x1) << 2) |
||
| 6133 | #define G_0286D0_PERSP_CENTROID_ENA(x) (((x) >> 2) & 0x1) |
||
| 6134 | #define C_0286D0_PERSP_CENTROID_ENA 0xFFFFFFFB |
||
| 6135 | #define S_0286D0_PERSP_PULL_MODEL_ENA(x) (((x) & 0x1) << 3) |
||
| 6136 | #define G_0286D0_PERSP_PULL_MODEL_ENA(x) (((x) >> 3) & 0x1) |
||
| 6137 | #define C_0286D0_PERSP_PULL_MODEL_ENA 0xFFFFFFF7 |
||
| 6138 | #define S_0286D0_LINEAR_SAMPLE_ENA(x) (((x) & 0x1) << 4) |
||
| 6139 | #define G_0286D0_LINEAR_SAMPLE_ENA(x) (((x) >> 4) & 0x1) |
||
| 6140 | #define C_0286D0_LINEAR_SAMPLE_ENA 0xFFFFFFEF |
||
| 6141 | #define S_0286D0_LINEAR_CENTER_ENA(x) (((x) & 0x1) << 5) |
||
| 6142 | #define G_0286D0_LINEAR_CENTER_ENA(x) (((x) >> 5) & 0x1) |
||
| 6143 | #define C_0286D0_LINEAR_CENTER_ENA 0xFFFFFFDF |
||
| 6144 | #define S_0286D0_LINEAR_CENTROID_ENA(x) (((x) & 0x1) << 6) |
||
| 6145 | #define G_0286D0_LINEAR_CENTROID_ENA(x) (((x) >> 6) & 0x1) |
||
| 6146 | #define C_0286D0_LINEAR_CENTROID_ENA 0xFFFFFFBF |
||
| 6147 | #define S_0286D0_LINE_STIPPLE_TEX_ENA(x) (((x) & 0x1) << 7) |
||
| 6148 | #define G_0286D0_LINE_STIPPLE_TEX_ENA(x) (((x) >> 7) & 0x1) |
||
| 6149 | #define C_0286D0_LINE_STIPPLE_TEX_ENA 0xFFFFFF7F |
||
| 6150 | #define S_0286D0_POS_X_FLOAT_ENA(x) (((x) & 0x1) << 8) |
||
| 6151 | #define G_0286D0_POS_X_FLOAT_ENA(x) (((x) >> 8) & 0x1) |
||
| 6152 | #define C_0286D0_POS_X_FLOAT_ENA 0xFFFFFEFF |
||
| 6153 | #define S_0286D0_POS_Y_FLOAT_ENA(x) (((x) & 0x1) << 9) |
||
| 6154 | #define G_0286D0_POS_Y_FLOAT_ENA(x) (((x) >> 9) & 0x1) |
||
| 6155 | #define C_0286D0_POS_Y_FLOAT_ENA 0xFFFFFDFF |
||
| 6156 | #define S_0286D0_POS_Z_FLOAT_ENA(x) (((x) & 0x1) << 10) |
||
| 6157 | #define G_0286D0_POS_Z_FLOAT_ENA(x) (((x) >> 10) & 0x1) |
||
| 6158 | #define C_0286D0_POS_Z_FLOAT_ENA 0xFFFFFBFF |
||
| 6159 | #define S_0286D0_POS_W_FLOAT_ENA(x) (((x) & 0x1) << 11) |
||
| 6160 | #define G_0286D0_POS_W_FLOAT_ENA(x) (((x) >> 11) & 0x1) |
||
| 6161 | #define C_0286D0_POS_W_FLOAT_ENA 0xFFFFF7FF |
||
| 6162 | #define S_0286D0_FRONT_FACE_ENA(x) (((x) & 0x1) << 12) |
||
| 6163 | #define G_0286D0_FRONT_FACE_ENA(x) (((x) >> 12) & 0x1) |
||
| 6164 | #define C_0286D0_FRONT_FACE_ENA 0xFFFFEFFF |
||
| 6165 | #define S_0286D0_ANCILLARY_ENA(x) (((x) & 0x1) << 13) |
||
| 6166 | #define G_0286D0_ANCILLARY_ENA(x) (((x) >> 13) & 0x1) |
||
| 6167 | #define C_0286D0_ANCILLARY_ENA 0xFFFFDFFF |
||
| 6168 | #define S_0286D0_SAMPLE_COVERAGE_ENA(x) (((x) & 0x1) << 14) |
||
| 6169 | #define G_0286D0_SAMPLE_COVERAGE_ENA(x) (((x) >> 14) & 0x1) |
||
| 6170 | #define C_0286D0_SAMPLE_COVERAGE_ENA 0xFFFFBFFF |
||
| 6171 | #define S_0286D0_POS_FIXED_PT_ENA(x) (((x) & 0x1) << 15) |
||
| 6172 | #define G_0286D0_POS_FIXED_PT_ENA(x) (((x) >> 15) & 0x1) |
||
| 6173 | #define C_0286D0_POS_FIXED_PT_ENA 0xFFFF7FFF |
||
| 6174 | #define R_0286D4_SPI_INTERP_CONTROL_0 0x0286D4 |
||
| 6175 | #define S_0286D4_FLAT_SHADE_ENA(x) (((x) & 0x1) << 0) |
||
| 6176 | #define G_0286D4_FLAT_SHADE_ENA(x) (((x) >> 0) & 0x1) |
||
| 6177 | #define C_0286D4_FLAT_SHADE_ENA 0xFFFFFFFE |
||
| 6178 | #define S_0286D4_PNT_SPRITE_ENA(x) (((x) & 0x1) << 1) |
||
| 6179 | #define G_0286D4_PNT_SPRITE_ENA(x) (((x) >> 1) & 0x1) |
||
| 6180 | #define C_0286D4_PNT_SPRITE_ENA 0xFFFFFFFD |
||
| 6181 | #define S_0286D4_PNT_SPRITE_OVRD_X(x) (((x) & 0x07) << 2) |
||
| 6182 | #define G_0286D4_PNT_SPRITE_OVRD_X(x) (((x) >> 2) & 0x07) |
||
| 6183 | #define C_0286D4_PNT_SPRITE_OVRD_X 0xFFFFFFE3 |
||
| 6184 | #define V_0286D4_SPI_PNT_SPRITE_SEL_0 0x00 |
||
| 6185 | #define V_0286D4_SPI_PNT_SPRITE_SEL_1 0x01 |
||
| 6186 | #define V_0286D4_SPI_PNT_SPRITE_SEL_S 0x02 |
||
| 6187 | #define V_0286D4_SPI_PNT_SPRITE_SEL_T 0x03 |
||
| 6188 | #define V_0286D4_SPI_PNT_SPRITE_SEL_NONE 0x04 |
||
| 6189 | #define S_0286D4_PNT_SPRITE_OVRD_Y(x) (((x) & 0x07) << 5) |
||
| 6190 | #define G_0286D4_PNT_SPRITE_OVRD_Y(x) (((x) >> 5) & 0x07) |
||
| 6191 | #define C_0286D4_PNT_SPRITE_OVRD_Y 0xFFFFFF1F |
||
| 6192 | #define V_0286D4_SPI_PNT_SPRITE_SEL_0 0x00 |
||
| 6193 | #define V_0286D4_SPI_PNT_SPRITE_SEL_1 0x01 |
||
| 6194 | #define V_0286D4_SPI_PNT_SPRITE_SEL_S 0x02 |
||
| 6195 | #define V_0286D4_SPI_PNT_SPRITE_SEL_T 0x03 |
||
| 6196 | #define V_0286D4_SPI_PNT_SPRITE_SEL_NONE 0x04 |
||
| 6197 | #define S_0286D4_PNT_SPRITE_OVRD_Z(x) (((x) & 0x07) << 8) |
||
| 6198 | #define G_0286D4_PNT_SPRITE_OVRD_Z(x) (((x) >> 8) & 0x07) |
||
| 6199 | #define C_0286D4_PNT_SPRITE_OVRD_Z 0xFFFFF8FF |
||
| 6200 | #define V_0286D4_SPI_PNT_SPRITE_SEL_0 0x00 |
||
| 6201 | #define V_0286D4_SPI_PNT_SPRITE_SEL_1 0x01 |
||
| 6202 | #define V_0286D4_SPI_PNT_SPRITE_SEL_S 0x02 |
||
| 6203 | #define V_0286D4_SPI_PNT_SPRITE_SEL_T 0x03 |
||
| 6204 | #define V_0286D4_SPI_PNT_SPRITE_SEL_NONE 0x04 |
||
| 6205 | #define S_0286D4_PNT_SPRITE_OVRD_W(x) (((x) & 0x07) << 11) |
||
| 6206 | #define G_0286D4_PNT_SPRITE_OVRD_W(x) (((x) >> 11) & 0x07) |
||
| 6207 | #define C_0286D4_PNT_SPRITE_OVRD_W 0xFFFFC7FF |
||
| 6208 | #define V_0286D4_SPI_PNT_SPRITE_SEL_0 0x00 |
||
| 6209 | #define V_0286D4_SPI_PNT_SPRITE_SEL_1 0x01 |
||
| 6210 | #define V_0286D4_SPI_PNT_SPRITE_SEL_S 0x02 |
||
| 6211 | #define V_0286D4_SPI_PNT_SPRITE_SEL_T 0x03 |
||
| 6212 | #define V_0286D4_SPI_PNT_SPRITE_SEL_NONE 0x04 |
||
| 6213 | #define S_0286D4_PNT_SPRITE_TOP_1(x) (((x) & 0x1) << 14) |
||
| 6214 | #define G_0286D4_PNT_SPRITE_TOP_1(x) (((x) >> 14) & 0x1) |
||
| 6215 | #define C_0286D4_PNT_SPRITE_TOP_1 0xFFFFBFFF |
||
| 6216 | #define R_0286D8_SPI_PS_IN_CONTROL 0x0286D8 |
||
| 6217 | #define S_0286D8_NUM_INTERP(x) (((x) & 0x3F) << 0) |
||
| 6218 | #define G_0286D8_NUM_INTERP(x) (((x) >> 0) & 0x3F) |
||
| 6219 | #define C_0286D8_NUM_INTERP 0xFFFFFFC0 |
||
| 6220 | #define S_0286D8_PARAM_GEN(x) (((x) & 0x1) << 6) |
||
| 6221 | #define G_0286D8_PARAM_GEN(x) (((x) >> 6) & 0x1) |
||
| 6222 | #define C_0286D8_PARAM_GEN 0xFFFFFFBF |
||
| 6223 | #define S_0286D8_FOG_ADDR(x) (((x) & 0x7F) << 7) /* not on CIK */ |
||
| 6224 | #define G_0286D8_FOG_ADDR(x) (((x) >> 7) & 0x7F) /* not on CIK */ |
||
| 6225 | #define C_0286D8_FOG_ADDR 0xFFFFC07F /* not on CIK */ |
||
| 6226 | #define S_0286D8_BC_OPTIMIZE_DISABLE(x) (((x) & 0x1) << 14) |
||
| 6227 | #define G_0286D8_BC_OPTIMIZE_DISABLE(x) (((x) >> 14) & 0x1) |
||
| 6228 | #define C_0286D8_BC_OPTIMIZE_DISABLE 0xFFFFBFFF |
||
| 6229 | #define S_0286D8_PASS_FOG_THROUGH_PS(x) (((x) & 0x1) << 15) /* not on CIK */ |
||
| 6230 | #define G_0286D8_PASS_FOG_THROUGH_PS(x) (((x) >> 15) & 0x1) /* not on CIK */ |
||
| 6231 | #define C_0286D8_PASS_FOG_THROUGH_PS 0xFFFF7FFF /* not on CIK */ |
||
| 6232 | #define R_0286E0_SPI_BARYC_CNTL 0x0286E0 |
||
| 6233 | #define S_0286E0_PERSP_CENTER_CNTL(x) (((x) & 0x1) << 0) |
||
| 6234 | #define G_0286E0_PERSP_CENTER_CNTL(x) (((x) >> 0) & 0x1) |
||
| 6235 | #define C_0286E0_PERSP_CENTER_CNTL 0xFFFFFFFE |
||
| 6236 | #define S_0286E0_PERSP_CENTROID_CNTL(x) (((x) & 0x1) << 4) |
||
| 6237 | #define G_0286E0_PERSP_CENTROID_CNTL(x) (((x) >> 4) & 0x1) |
||
| 6238 | #define C_0286E0_PERSP_CENTROID_CNTL 0xFFFFFFEF |
||
| 6239 | #define S_0286E0_LINEAR_CENTER_CNTL(x) (((x) & 0x1) << 8) |
||
| 6240 | #define G_0286E0_LINEAR_CENTER_CNTL(x) (((x) >> 8) & 0x1) |
||
| 6241 | #define C_0286E0_LINEAR_CENTER_CNTL 0xFFFFFEFF |
||
| 6242 | #define S_0286E0_LINEAR_CENTROID_CNTL(x) (((x) & 0x1) << 12) |
||
| 6243 | #define G_0286E0_LINEAR_CENTROID_CNTL(x) (((x) >> 12) & 0x1) |
||
| 6244 | #define C_0286E0_LINEAR_CENTROID_CNTL 0xFFFFEFFF |
||
| 6245 | #define S_0286E0_POS_FLOAT_LOCATION(x) (((x) & 0x03) << 16) |
||
| 6246 | #define G_0286E0_POS_FLOAT_LOCATION(x) (((x) >> 16) & 0x03) |
||
| 6247 | #define C_0286E0_POS_FLOAT_LOCATION 0xFFFCFFFF |
||
| 6248 | #define V_0286E0_X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT 0x00 |
||
| 6249 | #define S_0286E0_POS_FLOAT_ULC(x) (((x) & 0x1) << 20) |
||
| 6250 | #define G_0286E0_POS_FLOAT_ULC(x) (((x) >> 20) & 0x1) |
||
| 6251 | #define C_0286E0_POS_FLOAT_ULC 0xFFEFFFFF |
||
| 6252 | #define S_0286E0_FRONT_FACE_ALL_BITS(x) (((x) & 0x1) << 24) |
||
| 6253 | #define G_0286E0_FRONT_FACE_ALL_BITS(x) (((x) >> 24) & 0x1) |
||
| 6254 | #define C_0286E0_FRONT_FACE_ALL_BITS 0xFEFFFFFF |
||
| 6255 | #define R_0286E8_SPI_TMPRING_SIZE 0x0286E8 |
||
| 6256 | #define S_0286E8_WAVES(x) (((x) & 0xFFF) << 0) |
||
| 6257 | #define G_0286E8_WAVES(x) (((x) >> 0) & 0xFFF) |
||
| 6258 | #define C_0286E8_WAVES 0xFFFFF000 |
||
| 6259 | #define S_0286E8_WAVESIZE(x) (((x) & 0x1FFF) << 12) |
||
| 6260 | #define G_0286E8_WAVESIZE(x) (((x) >> 12) & 0x1FFF) |
||
| 6261 | #define C_0286E8_WAVESIZE 0xFE000FFF |
||
| 6262 | #define R_028704_SPI_WAVE_MGMT_1 0x028704 /* not on CIK */ |
||
| 6263 | #define S_028704_NUM_PS_WAVES(x) (((x) & 0x3F) << 0) |
||
| 6264 | #define G_028704_NUM_PS_WAVES(x) (((x) >> 0) & 0x3F) |
||
| 6265 | #define C_028704_NUM_PS_WAVES 0xFFFFFFC0 |
||
| 6266 | #define S_028704_NUM_VS_WAVES(x) (((x) & 0x3F) << 6) |
||
| 6267 | #define G_028704_NUM_VS_WAVES(x) (((x) >> 6) & 0x3F) |
||
| 6268 | #define C_028704_NUM_VS_WAVES 0xFFFFF03F |
||
| 6269 | #define S_028704_NUM_GS_WAVES(x) (((x) & 0x3F) << 12) |
||
| 6270 | #define G_028704_NUM_GS_WAVES(x) (((x) >> 12) & 0x3F) |
||
| 6271 | #define C_028704_NUM_GS_WAVES 0xFFFC0FFF |
||
| 6272 | #define S_028704_NUM_ES_WAVES(x) (((x) & 0x3F) << 18) |
||
| 6273 | #define G_028704_NUM_ES_WAVES(x) (((x) >> 18) & 0x3F) |
||
| 6274 | #define C_028704_NUM_ES_WAVES 0xFF03FFFF |
||
| 6275 | #define S_028704_NUM_HS_WAVES(x) (((x) & 0x3F) << 24) |
||
| 6276 | #define G_028704_NUM_HS_WAVES(x) (((x) >> 24) & 0x3F) |
||
| 6277 | #define C_028704_NUM_HS_WAVES 0xC0FFFFFF |
||
| 6278 | #define R_028708_SPI_WAVE_MGMT_2 0x028708 /* not on CIK */ |
||
| 6279 | #define S_028708_NUM_LS_WAVES(x) (((x) & 0x3F) << 0) |
||
| 6280 | #define G_028708_NUM_LS_WAVES(x) (((x) >> 0) & 0x3F) |
||
| 6281 | #define C_028708_NUM_LS_WAVES 0xFFFFFFC0 |
||
| 6282 | #define R_02870C_SPI_SHADER_POS_FORMAT 0x02870C |
||
| 6283 | #define S_02870C_POS0_EXPORT_FORMAT(x) (((x) & 0x0F) << 0) |
||
| 6284 | #define G_02870C_POS0_EXPORT_FORMAT(x) (((x) >> 0) & 0x0F) |
||
| 6285 | #define C_02870C_POS0_EXPORT_FORMAT 0xFFFFFFF0 |
||
| 6286 | #define V_02870C_SPI_SHADER_NONE 0x00 |
||
| 6287 | #define V_02870C_SPI_SHADER_1COMP 0x01 |
||
| 6288 | #define V_02870C_SPI_SHADER_2COMP 0x02 |
||
| 6289 | #define V_02870C_SPI_SHADER_4COMPRESS 0x03 |
||
| 6290 | #define V_02870C_SPI_SHADER_4COMP 0x04 |
||
| 6291 | #define S_02870C_POS1_EXPORT_FORMAT(x) (((x) & 0x0F) << 4) |
||
| 6292 | #define G_02870C_POS1_EXPORT_FORMAT(x) (((x) >> 4) & 0x0F) |
||
| 6293 | #define C_02870C_POS1_EXPORT_FORMAT 0xFFFFFF0F |
||
| 6294 | #define V_02870C_SPI_SHADER_NONE 0x00 |
||
| 6295 | #define V_02870C_SPI_SHADER_1COMP 0x01 |
||
| 6296 | #define V_02870C_SPI_SHADER_2COMP 0x02 |
||
| 6297 | #define V_02870C_SPI_SHADER_4COMPRESS 0x03 |
||
| 6298 | #define V_02870C_SPI_SHADER_4COMP 0x04 |
||
| 6299 | #define S_02870C_POS2_EXPORT_FORMAT(x) (((x) & 0x0F) << 8) |
||
| 6300 | #define G_02870C_POS2_EXPORT_FORMAT(x) (((x) >> 8) & 0x0F) |
||
| 6301 | #define C_02870C_POS2_EXPORT_FORMAT 0xFFFFF0FF |
||
| 6302 | #define V_02870C_SPI_SHADER_NONE 0x00 |
||
| 6303 | #define V_02870C_SPI_SHADER_1COMP 0x01 |
||
| 6304 | #define V_02870C_SPI_SHADER_2COMP 0x02 |
||
| 6305 | #define V_02870C_SPI_SHADER_4COMPRESS 0x03 |
||
| 6306 | #define V_02870C_SPI_SHADER_4COMP 0x04 |
||
| 6307 | #define S_02870C_POS3_EXPORT_FORMAT(x) (((x) & 0x0F) << 12) |
||
| 6308 | #define G_02870C_POS3_EXPORT_FORMAT(x) (((x) >> 12) & 0x0F) |
||
| 6309 | #define C_02870C_POS3_EXPORT_FORMAT 0xFFFF0FFF |
||
| 6310 | #define V_02870C_SPI_SHADER_NONE 0x00 |
||
| 6311 | #define V_02870C_SPI_SHADER_1COMP 0x01 |
||
| 6312 | #define V_02870C_SPI_SHADER_2COMP 0x02 |
||
| 6313 | #define V_02870C_SPI_SHADER_4COMPRESS 0x03 |
||
| 6314 | #define V_02870C_SPI_SHADER_4COMP 0x04 |
||
| 6315 | #define R_028710_SPI_SHADER_Z_FORMAT 0x028710 |
||
| 6316 | #define S_028710_Z_EXPORT_FORMAT(x) (((x) & 0x0F) << 0) |
||
| 6317 | #define G_028710_Z_EXPORT_FORMAT(x) (((x) >> 0) & 0x0F) |
||
| 6318 | #define C_028710_Z_EXPORT_FORMAT 0xFFFFFFF0 |
||
| 6319 | #define V_028710_SPI_SHADER_ZERO 0x00 |
||
| 6320 | #define V_028710_SPI_SHADER_32_R 0x01 |
||
| 6321 | #define V_028710_SPI_SHADER_32_GR 0x02 |
||
| 6322 | #define V_028710_SPI_SHADER_32_AR 0x03 |
||
| 6323 | #define V_028710_SPI_SHADER_FP16_ABGR 0x04 |
||
| 6324 | #define V_028710_SPI_SHADER_UNORM16_ABGR 0x05 |
||
| 6325 | #define V_028710_SPI_SHADER_SNORM16_ABGR 0x06 |
||
| 6326 | #define V_028710_SPI_SHADER_UINT16_ABGR 0x07 |
||
| 6327 | #define V_028710_SPI_SHADER_SINT16_ABGR 0x08 |
||
| 6328 | #define V_028710_SPI_SHADER_32_ABGR 0x09 |
||
| 6329 | #define R_028714_SPI_SHADER_COL_FORMAT 0x028714 |
||
| 6330 | #define S_028714_COL0_EXPORT_FORMAT(x) (((x) & 0x0F) << 0) |
||
| 6331 | #define G_028714_COL0_EXPORT_FORMAT(x) (((x) >> 0) & 0x0F) |
||
| 6332 | #define C_028714_COL0_EXPORT_FORMAT 0xFFFFFFF0 |
||
| 6333 | #define V_028714_SPI_SHADER_ZERO 0x00 |
||
| 6334 | #define V_028714_SPI_SHADER_32_R 0x01 |
||
| 6335 | #define V_028714_SPI_SHADER_32_GR 0x02 |
||
| 6336 | #define V_028714_SPI_SHADER_32_AR 0x03 |
||
| 6337 | #define V_028714_SPI_SHADER_FP16_ABGR 0x04 |
||
| 6338 | #define V_028714_SPI_SHADER_UNORM16_ABGR 0x05 |
||
| 6339 | #define V_028714_SPI_SHADER_SNORM16_ABGR 0x06 |
||
| 6340 | #define V_028714_SPI_SHADER_UINT16_ABGR 0x07 |
||
| 6341 | #define V_028714_SPI_SHADER_SINT16_ABGR 0x08 |
||
| 6342 | #define V_028714_SPI_SHADER_32_ABGR 0x09 |
||
| 6343 | #define S_028714_COL1_EXPORT_FORMAT(x) (((x) & 0x0F) << 4) |
||
| 6344 | #define G_028714_COL1_EXPORT_FORMAT(x) (((x) >> 4) & 0x0F) |
||
| 6345 | #define C_028714_COL1_EXPORT_FORMAT 0xFFFFFF0F |
||
| 6346 | #define V_028714_SPI_SHADER_ZERO 0x00 |
||
| 6347 | #define V_028714_SPI_SHADER_32_R 0x01 |
||
| 6348 | #define V_028714_SPI_SHADER_32_GR 0x02 |
||
| 6349 | #define V_028714_SPI_SHADER_32_AR 0x03 |
||
| 6350 | #define V_028714_SPI_SHADER_FP16_ABGR 0x04 |
||
| 6351 | #define V_028714_SPI_SHADER_UNORM16_ABGR 0x05 |
||
| 6352 | #define V_028714_SPI_SHADER_SNORM16_ABGR 0x06 |
||
| 6353 | #define V_028714_SPI_SHADER_UINT16_ABGR 0x07 |
||
| 6354 | #define V_028714_SPI_SHADER_SINT16_ABGR 0x08 |
||
| 6355 | #define V_028714_SPI_SHADER_32_ABGR 0x09 |
||
| 6356 | #define S_028714_COL2_EXPORT_FORMAT(x) (((x) & 0x0F) << 8) |
||
| 6357 | #define G_028714_COL2_EXPORT_FORMAT(x) (((x) >> 8) & 0x0F) |
||
| 6358 | #define C_028714_COL2_EXPORT_FORMAT 0xFFFFF0FF |
||
| 6359 | #define V_028714_SPI_SHADER_ZERO 0x00 |
||
| 6360 | #define V_028714_SPI_SHADER_32_R 0x01 |
||
| 6361 | #define V_028714_SPI_SHADER_32_GR 0x02 |
||
| 6362 | #define V_028714_SPI_SHADER_32_AR 0x03 |
||
| 6363 | #define V_028714_SPI_SHADER_FP16_ABGR 0x04 |
||
| 6364 | #define V_028714_SPI_SHADER_UNORM16_ABGR 0x05 |
||
| 6365 | #define V_028714_SPI_SHADER_SNORM16_ABGR 0x06 |
||
| 6366 | #define V_028714_SPI_SHADER_UINT16_ABGR 0x07 |
||
| 6367 | #define V_028714_SPI_SHADER_SINT16_ABGR 0x08 |
||
| 6368 | #define V_028714_SPI_SHADER_32_ABGR 0x09 |
||
| 6369 | #define S_028714_COL3_EXPORT_FORMAT(x) (((x) & 0x0F) << 12) |
||
| 6370 | #define G_028714_COL3_EXPORT_FORMAT(x) (((x) >> 12) & 0x0F) |
||
| 6371 | #define C_028714_COL3_EXPORT_FORMAT 0xFFFF0FFF |
||
| 6372 | #define V_028714_SPI_SHADER_ZERO 0x00 |
||
| 6373 | #define V_028714_SPI_SHADER_32_R 0x01 |
||
| 6374 | #define V_028714_SPI_SHADER_32_GR 0x02 |
||
| 6375 | #define V_028714_SPI_SHADER_32_AR 0x03 |
||
| 6376 | #define V_028714_SPI_SHADER_FP16_ABGR 0x04 |
||
| 6377 | #define V_028714_SPI_SHADER_UNORM16_ABGR 0x05 |
||
| 6378 | #define V_028714_SPI_SHADER_SNORM16_ABGR 0x06 |
||
| 6379 | #define V_028714_SPI_SHADER_UINT16_ABGR 0x07 |
||
| 6380 | #define V_028714_SPI_SHADER_SINT16_ABGR 0x08 |
||
| 6381 | #define V_028714_SPI_SHADER_32_ABGR 0x09 |
||
| 6382 | #define S_028714_COL4_EXPORT_FORMAT(x) (((x) & 0x0F) << 16) |
||
| 6383 | #define G_028714_COL4_EXPORT_FORMAT(x) (((x) >> 16) & 0x0F) |
||
| 6384 | #define C_028714_COL4_EXPORT_FORMAT 0xFFF0FFFF |
||
| 6385 | #define V_028714_SPI_SHADER_ZERO 0x00 |
||
| 6386 | #define V_028714_SPI_SHADER_32_R 0x01 |
||
| 6387 | #define V_028714_SPI_SHADER_32_GR 0x02 |
||
| 6388 | #define V_028714_SPI_SHADER_32_AR 0x03 |
||
| 6389 | #define V_028714_SPI_SHADER_FP16_ABGR 0x04 |
||
| 6390 | #define V_028714_SPI_SHADER_UNORM16_ABGR 0x05 |
||
| 6391 | #define V_028714_SPI_SHADER_SNORM16_ABGR 0x06 |
||
| 6392 | #define V_028714_SPI_SHADER_UINT16_ABGR 0x07 |
||
| 6393 | #define V_028714_SPI_SHADER_SINT16_ABGR 0x08 |
||
| 6394 | #define V_028714_SPI_SHADER_32_ABGR 0x09 |
||
| 6395 | #define S_028714_COL5_EXPORT_FORMAT(x) (((x) & 0x0F) << 20) |
||
| 6396 | #define G_028714_COL5_EXPORT_FORMAT(x) (((x) >> 20) & 0x0F) |
||
| 6397 | #define C_028714_COL5_EXPORT_FORMAT 0xFF0FFFFF |
||
| 6398 | #define V_028714_SPI_SHADER_ZERO 0x00 |
||
| 6399 | #define V_028714_SPI_SHADER_32_R 0x01 |
||
| 6400 | #define V_028714_SPI_SHADER_32_GR 0x02 |
||
| 6401 | #define V_028714_SPI_SHADER_32_AR 0x03 |
||
| 6402 | #define V_028714_SPI_SHADER_FP16_ABGR 0x04 |
||
| 6403 | #define V_028714_SPI_SHADER_UNORM16_ABGR 0x05 |
||
| 6404 | #define V_028714_SPI_SHADER_SNORM16_ABGR 0x06 |
||
| 6405 | #define V_028714_SPI_SHADER_UINT16_ABGR 0x07 |
||
| 6406 | #define V_028714_SPI_SHADER_SINT16_ABGR 0x08 |
||
| 6407 | #define V_028714_SPI_SHADER_32_ABGR 0x09 |
||
| 6408 | #define S_028714_COL6_EXPORT_FORMAT(x) (((x) & 0x0F) << 24) |
||
| 6409 | #define G_028714_COL6_EXPORT_FORMAT(x) (((x) >> 24) & 0x0F) |
||
| 6410 | #define C_028714_COL6_EXPORT_FORMAT 0xF0FFFFFF |
||
| 6411 | #define V_028714_SPI_SHADER_ZERO 0x00 |
||
| 6412 | #define V_028714_SPI_SHADER_32_R 0x01 |
||
| 6413 | #define V_028714_SPI_SHADER_32_GR 0x02 |
||
| 6414 | #define V_028714_SPI_SHADER_32_AR 0x03 |
||
| 6415 | #define V_028714_SPI_SHADER_FP16_ABGR 0x04 |
||
| 6416 | #define V_028714_SPI_SHADER_UNORM16_ABGR 0x05 |
||
| 6417 | #define V_028714_SPI_SHADER_SNORM16_ABGR 0x06 |
||
| 6418 | #define V_028714_SPI_SHADER_UINT16_ABGR 0x07 |
||
| 6419 | #define V_028714_SPI_SHADER_SINT16_ABGR 0x08 |
||
| 6420 | #define V_028714_SPI_SHADER_32_ABGR 0x09 |
||
| 6421 | #define S_028714_COL7_EXPORT_FORMAT(x) (((x) & 0x0F) << 28) |
||
| 6422 | #define G_028714_COL7_EXPORT_FORMAT(x) (((x) >> 28) & 0x0F) |
||
| 6423 | #define C_028714_COL7_EXPORT_FORMAT 0x0FFFFFFF |
||
| 6424 | #define V_028714_SPI_SHADER_ZERO 0x00 |
||
| 6425 | #define V_028714_SPI_SHADER_32_R 0x01 |
||
| 6426 | #define V_028714_SPI_SHADER_32_GR 0x02 |
||
| 6427 | #define V_028714_SPI_SHADER_32_AR 0x03 |
||
| 6428 | #define V_028714_SPI_SHADER_FP16_ABGR 0x04 |
||
| 6429 | #define V_028714_SPI_SHADER_UNORM16_ABGR 0x05 |
||
| 6430 | #define V_028714_SPI_SHADER_SNORM16_ABGR 0x06 |
||
| 6431 | #define V_028714_SPI_SHADER_UINT16_ABGR 0x07 |
||
| 6432 | #define V_028714_SPI_SHADER_SINT16_ABGR 0x08 |
||
| 6433 | #define V_028714_SPI_SHADER_32_ABGR 0x09 |
||
| 6434 | #define R_028780_CB_BLEND0_CONTROL 0x028780 |
||
| 6435 | #define S_028780_COLOR_SRCBLEND(x) (((x) & 0x1F) << 0) |
||
| 6436 | #define G_028780_COLOR_SRCBLEND(x) (((x) >> 0) & 0x1F) |
||
| 6437 | #define C_028780_COLOR_SRCBLEND 0xFFFFFFE0 |
||
| 6438 | #define V_028780_BLEND_ZERO 0x00 |
||
| 6439 | #define V_028780_BLEND_ONE 0x01 |
||
| 6440 | #define V_028780_BLEND_SRC_COLOR 0x02 |
||
| 6441 | #define V_028780_BLEND_ONE_MINUS_SRC_COLOR 0x03 |
||
| 6442 | #define V_028780_BLEND_SRC_ALPHA 0x04 |
||
| 6443 | #define V_028780_BLEND_ONE_MINUS_SRC_ALPHA 0x05 |
||
| 6444 | #define V_028780_BLEND_DST_ALPHA 0x06 |
||
| 6445 | #define V_028780_BLEND_ONE_MINUS_DST_ALPHA 0x07 |
||
| 6446 | #define V_028780_BLEND_DST_COLOR 0x08 |
||
| 6447 | #define V_028780_BLEND_ONE_MINUS_DST_COLOR 0x09 |
||
| 6448 | #define V_028780_BLEND_SRC_ALPHA_SATURATE 0x0A |
||
| 6449 | #define V_028780_BLEND_CONSTANT_COLOR 0x0D |
||
| 6450 | #define V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR 0x0E |
||
| 6451 | #define V_028780_BLEND_SRC1_COLOR 0x0F |
||
| 6452 | #define V_028780_BLEND_INV_SRC1_COLOR 0x10 |
||
| 6453 | #define V_028780_BLEND_SRC1_ALPHA 0x11 |
||
| 6454 | #define V_028780_BLEND_INV_SRC1_ALPHA 0x12 |
||
| 6455 | #define V_028780_BLEND_CONSTANT_ALPHA 0x13 |
||
| 6456 | #define V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA 0x14 |
||
| 6457 | #define S_028780_COLOR_COMB_FCN(x) (((x) & 0x07) << 5) |
||
| 6458 | #define G_028780_COLOR_COMB_FCN(x) (((x) >> 5) & 0x07) |
||
| 6459 | #define C_028780_COLOR_COMB_FCN 0xFFFFFF1F |
||
| 6460 | #define V_028780_COMB_DST_PLUS_SRC 0x00 |
||
| 6461 | #define V_028780_COMB_SRC_MINUS_DST 0x01 |
||
| 6462 | #define V_028780_COMB_MIN_DST_SRC 0x02 |
||
| 6463 | #define V_028780_COMB_MAX_DST_SRC 0x03 |
||
| 6464 | #define V_028780_COMB_DST_MINUS_SRC 0x04 |
||
| 6465 | #define S_028780_COLOR_DESTBLEND(x) (((x) & 0x1F) << 8) |
||
| 6466 | #define G_028780_COLOR_DESTBLEND(x) (((x) >> 8) & 0x1F) |
||
| 6467 | #define C_028780_COLOR_DESTBLEND 0xFFFFE0FF |
||
| 6468 | #define V_028780_BLEND_ZERO 0x00 |
||
| 6469 | #define V_028780_BLEND_ONE 0x01 |
||
| 6470 | #define V_028780_BLEND_SRC_COLOR 0x02 |
||
| 6471 | #define V_028780_BLEND_ONE_MINUS_SRC_COLOR 0x03 |
||
| 6472 | #define V_028780_BLEND_SRC_ALPHA 0x04 |
||
| 6473 | #define V_028780_BLEND_ONE_MINUS_SRC_ALPHA 0x05 |
||
| 6474 | #define V_028780_BLEND_DST_ALPHA 0x06 |
||
| 6475 | #define V_028780_BLEND_ONE_MINUS_DST_ALPHA 0x07 |
||
| 6476 | #define V_028780_BLEND_DST_COLOR 0x08 |
||
| 6477 | #define V_028780_BLEND_ONE_MINUS_DST_COLOR 0x09 |
||
| 6478 | #define V_028780_BLEND_SRC_ALPHA_SATURATE 0x0A |
||
| 6479 | #define V_028780_BLEND_CONSTANT_COLOR 0x0D |
||
| 6480 | #define V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR 0x0E |
||
| 6481 | #define V_028780_BLEND_SRC1_COLOR 0x0F |
||
| 6482 | #define V_028780_BLEND_INV_SRC1_COLOR 0x10 |
||
| 6483 | #define V_028780_BLEND_SRC1_ALPHA 0x11 |
||
| 6484 | #define V_028780_BLEND_INV_SRC1_ALPHA 0x12 |
||
| 6485 | #define V_028780_BLEND_CONSTANT_ALPHA 0x13 |
||
| 6486 | #define V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA 0x14 |
||
| 6487 | #define S_028780_ALPHA_SRCBLEND(x) (((x) & 0x1F) << 16) |
||
| 6488 | #define G_028780_ALPHA_SRCBLEND(x) (((x) >> 16) & 0x1F) |
||
| 6489 | #define C_028780_ALPHA_SRCBLEND 0xFFE0FFFF |
||
| 6490 | #define V_028780_BLEND_ZERO 0x00 |
||
| 6491 | #define V_028780_BLEND_ONE 0x01 |
||
| 6492 | #define V_028780_BLEND_SRC_COLOR 0x02 |
||
| 6493 | #define V_028780_BLEND_ONE_MINUS_SRC_COLOR 0x03 |
||
| 6494 | #define V_028780_BLEND_SRC_ALPHA 0x04 |
||
| 6495 | #define V_028780_BLEND_ONE_MINUS_SRC_ALPHA 0x05 |
||
| 6496 | #define V_028780_BLEND_DST_ALPHA 0x06 |
||
| 6497 | #define V_028780_BLEND_ONE_MINUS_DST_ALPHA 0x07 |
||
| 6498 | #define V_028780_BLEND_DST_COLOR 0x08 |
||
| 6499 | #define V_028780_BLEND_ONE_MINUS_DST_COLOR 0x09 |
||
| 6500 | #define V_028780_BLEND_SRC_ALPHA_SATURATE 0x0A |
||
| 6501 | #define V_028780_BLEND_CONSTANT_COLOR 0x0D |
||
| 6502 | #define V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR 0x0E |
||
| 6503 | #define V_028780_BLEND_SRC1_COLOR 0x0F |
||
| 6504 | #define V_028780_BLEND_INV_SRC1_COLOR 0x10 |
||
| 6505 | #define V_028780_BLEND_SRC1_ALPHA 0x11 |
||
| 6506 | #define V_028780_BLEND_INV_SRC1_ALPHA 0x12 |
||
| 6507 | #define V_028780_BLEND_CONSTANT_ALPHA 0x13 |
||
| 6508 | #define V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA 0x14 |
||
| 6509 | #define S_028780_ALPHA_COMB_FCN(x) (((x) & 0x07) << 21) |
||
| 6510 | #define G_028780_ALPHA_COMB_FCN(x) (((x) >> 21) & 0x07) |
||
| 6511 | #define C_028780_ALPHA_COMB_FCN 0xFF1FFFFF |
||
| 6512 | #define V_028780_COMB_DST_PLUS_SRC 0x00 |
||
| 6513 | #define V_028780_COMB_SRC_MINUS_DST 0x01 |
||
| 6514 | #define V_028780_COMB_MIN_DST_SRC 0x02 |
||
| 6515 | #define V_028780_COMB_MAX_DST_SRC 0x03 |
||
| 6516 | #define V_028780_COMB_DST_MINUS_SRC 0x04 |
||
| 6517 | #define S_028780_ALPHA_DESTBLEND(x) (((x) & 0x1F) << 24) |
||
| 6518 | #define G_028780_ALPHA_DESTBLEND(x) (((x) >> 24) & 0x1F) |
||
| 6519 | #define C_028780_ALPHA_DESTBLEND 0xE0FFFFFF |
||
| 6520 | #define V_028780_BLEND_ZERO 0x00 |
||
| 6521 | #define V_028780_BLEND_ONE 0x01 |
||
| 6522 | #define V_028780_BLEND_SRC_COLOR 0x02 |
||
| 6523 | #define V_028780_BLEND_ONE_MINUS_SRC_COLOR 0x03 |
||
| 6524 | #define V_028780_BLEND_SRC_ALPHA 0x04 |
||
| 6525 | #define V_028780_BLEND_ONE_MINUS_SRC_ALPHA 0x05 |
||
| 6526 | #define V_028780_BLEND_DST_ALPHA 0x06 |
||
| 6527 | #define V_028780_BLEND_ONE_MINUS_DST_ALPHA 0x07 |
||
| 6528 | #define V_028780_BLEND_DST_COLOR 0x08 |
||
| 6529 | #define V_028780_BLEND_ONE_MINUS_DST_COLOR 0x09 |
||
| 6530 | #define V_028780_BLEND_SRC_ALPHA_SATURATE 0x0A |
||
| 6531 | #define V_028780_BLEND_CONSTANT_COLOR 0x0D |
||
| 6532 | #define V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR 0x0E |
||
| 6533 | #define V_028780_BLEND_SRC1_COLOR 0x0F |
||
| 6534 | #define V_028780_BLEND_INV_SRC1_COLOR 0x10 |
||
| 6535 | #define V_028780_BLEND_SRC1_ALPHA 0x11 |
||
| 6536 | #define V_028780_BLEND_INV_SRC1_ALPHA 0x12 |
||
| 6537 | #define V_028780_BLEND_CONSTANT_ALPHA 0x13 |
||
| 6538 | #define V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA 0x14 |
||
| 6539 | #define S_028780_SEPARATE_ALPHA_BLEND(x) (((x) & 0x1) << 29) |
||
| 6540 | #define G_028780_SEPARATE_ALPHA_BLEND(x) (((x) >> 29) & 0x1) |
||
| 6541 | #define C_028780_SEPARATE_ALPHA_BLEND 0xDFFFFFFF |
||
| 6542 | #define S_028780_ENABLE(x) (((x) & 0x1) << 30) |
||
| 6543 | #define G_028780_ENABLE(x) (((x) >> 30) & 0x1) |
||
| 6544 | #define C_028780_ENABLE 0xBFFFFFFF |
||
| 6545 | #define S_028780_DISABLE_ROP3(x) (((x) & 0x1) << 31) |
||
| 6546 | #define G_028780_DISABLE_ROP3(x) (((x) >> 31) & 0x1) |
||
| 6547 | #define C_028780_DISABLE_ROP3 0x7FFFFFFF |
||
| 6548 | #define R_028784_CB_BLEND1_CONTROL 0x028784 |
||
| 6549 | #define R_028788_CB_BLEND2_CONTROL 0x028788 |
||
| 6550 | #define R_02878C_CB_BLEND3_CONTROL 0x02878C |
||
| 6551 | #define R_028790_CB_BLEND4_CONTROL 0x028790 |
||
| 6552 | #define R_028794_CB_BLEND5_CONTROL 0x028794 |
||
| 6553 | #define R_028798_CB_BLEND6_CONTROL 0x028798 |
||
| 6554 | #define R_02879C_CB_BLEND7_CONTROL 0x02879C |
||
| 6555 | #define R_0287D4_PA_CL_POINT_X_RAD 0x0287D4 |
||
| 6556 | #define R_0287D8_PA_CL_POINT_Y_RAD 0x0287D8 |
||
| 6557 | #define R_0287DC_PA_CL_POINT_SIZE 0x0287DC |
||
| 6558 | #define R_0287E0_PA_CL_POINT_CULL_RAD 0x0287E0 |
||
| 6559 | #define R_0287E4_VGT_DMA_BASE_HI 0x0287E4 |
||
| 6560 | #define S_0287E4_BASE_ADDR(x) (((x) & 0xFF) << 0) |
||
| 6561 | #define G_0287E4_BASE_ADDR(x) (((x) >> 0) & 0xFF) |
||
| 6562 | #define C_0287E4_BASE_ADDR 0xFFFFFF00 |
||
| 6563 | #define R_0287E8_VGT_DMA_BASE 0x0287E8 |
||
| 6564 | #define R_0287F0_VGT_DRAW_INITIATOR 0x0287F0 |
||
| 6565 | #define S_0287F0_SOURCE_SELECT(x) (((x) & 0x03) << 0) |
||
| 6566 | #define G_0287F0_SOURCE_SELECT(x) (((x) >> 0) & 0x03) |
||
| 6567 | #define C_0287F0_SOURCE_SELECT 0xFFFFFFFC |
||
| 6568 | #define V_0287F0_DI_SRC_SEL_DMA 0x00 |
||
| 6569 | #define V_0287F0_DI_SRC_SEL_IMMEDIATE 0x01 /* not on CIK */ |
||
| 6570 | #define V_0287F0_DI_SRC_SEL_AUTO_INDEX 0x02 |
||
| 6571 | #define V_0287F0_DI_SRC_SEL_RESERVED 0x03 |
||
| 6572 | #define S_0287F0_MAJOR_MODE(x) (((x) & 0x03) << 2) |
||
| 6573 | #define G_0287F0_MAJOR_MODE(x) (((x) >> 2) & 0x03) |
||
| 6574 | #define C_0287F0_MAJOR_MODE 0xFFFFFFF3 |
||
| 6575 | #define V_0287F0_DI_MAJOR_MODE_0 0x00 |
||
| 6576 | #define V_0287F0_DI_MAJOR_MODE_1 0x01 |
||
| 6577 | #define S_0287F0_NOT_EOP(x) (((x) & 0x1) << 5) |
||
| 6578 | #define G_0287F0_NOT_EOP(x) (((x) >> 5) & 0x1) |
||
| 6579 | #define C_0287F0_NOT_EOP 0xFFFFFFDF |
||
| 6580 | #define S_0287F0_USE_OPAQUE(x) (((x) & 0x1) << 6) |
||
| 6581 | #define G_0287F0_USE_OPAQUE(x) (((x) >> 6) & 0x1) |
||
| 6582 | #define C_0287F0_USE_OPAQUE 0xFFFFFFBF |
||
| 6583 | #define R_0287F4_VGT_IMMED_DATA 0x0287F4 /* not on CIK */ |
||
| 6584 | #define R_028800_DB_DEPTH_CONTROL 0x028800 |
||
| 6585 | #define S_028800_STENCIL_ENABLE(x) (((x) & 0x1) << 0) |
||
| 6586 | #define G_028800_STENCIL_ENABLE(x) (((x) >> 0) & 0x1) |
||
| 6587 | #define C_028800_STENCIL_ENABLE 0xFFFFFFFE |
||
| 6588 | #define S_028800_Z_ENABLE(x) (((x) & 0x1) << 1) |
||
| 6589 | #define G_028800_Z_ENABLE(x) (((x) >> 1) & 0x1) |
||
| 6590 | #define C_028800_Z_ENABLE 0xFFFFFFFD |
||
| 6591 | #define S_028800_Z_WRITE_ENABLE(x) (((x) & 0x1) << 2) |
||
| 6592 | #define G_028800_Z_WRITE_ENABLE(x) (((x) >> 2) & 0x1) |
||
| 6593 | #define C_028800_Z_WRITE_ENABLE 0xFFFFFFFB |
||
| 6594 | #define S_028800_DEPTH_BOUNDS_ENABLE(x) (((x) & 0x1) << 3) |
||
| 6595 | #define G_028800_DEPTH_BOUNDS_ENABLE(x) (((x) >> 3) & 0x1) |
||
| 6596 | #define C_028800_DEPTH_BOUNDS_ENABLE 0xFFFFFFF7 |
||
| 6597 | #define S_028800_ZFUNC(x) (((x) & 0x07) << 4) |
||
| 6598 | #define G_028800_ZFUNC(x) (((x) >> 4) & 0x07) |
||
| 6599 | #define C_028800_ZFUNC 0xFFFFFF8F |
||
| 6600 | #define V_028800_FRAG_NEVER 0x00 |
||
| 6601 | #define V_028800_FRAG_LESS 0x01 |
||
| 6602 | #define V_028800_FRAG_EQUAL 0x02 |
||
| 6603 | #define V_028800_FRAG_LEQUAL 0x03 |
||
| 6604 | #define V_028800_FRAG_GREATER 0x04 |
||
| 6605 | #define V_028800_FRAG_NOTEQUAL 0x05 |
||
| 6606 | #define V_028800_FRAG_GEQUAL 0x06 |
||
| 6607 | #define V_028800_FRAG_ALWAYS 0x07 |
||
| 6608 | #define S_028800_BACKFACE_ENABLE(x) (((x) & 0x1) << 7) |
||
| 6609 | #define G_028800_BACKFACE_ENABLE(x) (((x) >> 7) & 0x1) |
||
| 6610 | #define C_028800_BACKFACE_ENABLE 0xFFFFFF7F |
||
| 6611 | #define S_028800_STENCILFUNC(x) (((x) & 0x07) << 8) |
||
| 6612 | #define G_028800_STENCILFUNC(x) (((x) >> 8) & 0x07) |
||
| 6613 | #define C_028800_STENCILFUNC 0xFFFFF8FF |
||
| 6614 | #define V_028800_REF_NEVER 0x00 |
||
| 6615 | #define V_028800_REF_LESS 0x01 |
||
| 6616 | #define V_028800_REF_EQUAL 0x02 |
||
| 6617 | #define V_028800_REF_LEQUAL 0x03 |
||
| 6618 | #define V_028800_REF_GREATER 0x04 |
||
| 6619 | #define V_028800_REF_NOTEQUAL 0x05 |
||
| 6620 | #define V_028800_REF_GEQUAL 0x06 |
||
| 6621 | #define V_028800_REF_ALWAYS 0x07 |
||
| 6622 | #define S_028800_STENCILFUNC_BF(x) (((x) & 0x07) << 20) |
||
| 6623 | #define G_028800_STENCILFUNC_BF(x) (((x) >> 20) & 0x07) |
||
| 6624 | #define C_028800_STENCILFUNC_BF 0xFF8FFFFF |
||
| 6625 | #define V_028800_REF_NEVER 0x00 |
||
| 6626 | #define V_028800_REF_LESS 0x01 |
||
| 6627 | #define V_028800_REF_EQUAL 0x02 |
||
| 6628 | #define V_028800_REF_LEQUAL 0x03 |
||
| 6629 | #define V_028800_REF_GREATER 0x04 |
||
| 6630 | #define V_028800_REF_NOTEQUAL 0x05 |
||
| 6631 | #define V_028800_REF_GEQUAL 0x06 |
||
| 6632 | #define V_028800_REF_ALWAYS 0x07 |
||
| 6633 | #define S_028800_ENABLE_COLOR_WRITES_ON_DEPTH_FAIL(x) (((x) & 0x1) << 30) |
||
| 6634 | #define G_028800_ENABLE_COLOR_WRITES_ON_DEPTH_FAIL(x) (((x) >> 30) & 0x1) |
||
| 6635 | #define C_028800_ENABLE_COLOR_WRITES_ON_DEPTH_FAIL 0xBFFFFFFF |
||
| 6636 | #define S_028800_DISABLE_COLOR_WRITES_ON_DEPTH_PASS(x) (((x) & 0x1) << 31) |
||
| 6637 | #define G_028800_DISABLE_COLOR_WRITES_ON_DEPTH_PASS(x) (((x) >> 31) & 0x1) |
||
| 6638 | #define C_028800_DISABLE_COLOR_WRITES_ON_DEPTH_PASS 0x7FFFFFFF |
||
| 6639 | #define R_028804_DB_EQAA 0x028804 |
||
| 6640 | #define S_028804_MAX_ANCHOR_SAMPLES(x) (((x) & 0x7) << 0) |
||
| 6641 | #define G_028804_MAX_ANCHOR_SAMPLES(x) (((x) >> 0) & 0x7) |
||
| 6642 | #define C_028804_MAX_ANCHOR_SAMPLES (~(((~0) & 0x7) << 0)) |
||
| 6643 | #define S_028804_PS_ITER_SAMPLES(x) (((x) & 0x7) << 4) |
||
| 6644 | #define G_028804_PS_ITER_SAMPLES(x) (((x) >> 4) & 0x7) |
||
| 6645 | #define C_028804_PS_ITER_SAMPLES (~(((~0) & 0x7) << 4)) |
||
| 6646 | #define S_028804_MASK_EXPORT_NUM_SAMPLES(x) (((x) & 0x7) << 8) |
||
| 6647 | #define G_028804_MASK_EXPORT_NUM_SAMPLES(x) (((x) >> 8) & 0x7) |
||
| 6648 | #define C_028804_MASK_EXPORT_NUM_SAMPLES (~(((~0) & 0x7) << 8)) |
||
| 6649 | #define S_028804_ALPHA_TO_MASK_NUM_SAMPLES(x) (((x) & 0x7) << 12) |
||
| 6650 | #define G_028804_ALPHA_TO_MASK_NUM_SAMPLES(x) (((x) >> 12) & 0x7) |
||
| 6651 | #define C_028804_ALPHA_TO_MASK_NUM_SAMPLES (~(((~0) & 0x7) << 12)) |
||
| 6652 | #define S_028804_HIGH_QUALITY_INTERSECTIONS(x) (((x) & 0x1) << 16) |
||
| 6653 | #define G_028804_HIGH_QUALITY_INTERSECTIONS(x) (((x) >> 16) & 0x1) |
||
| 6654 | #define C_028804_HIGH_QUALITY_INTERSECTIONS (~(((~0) & 0x1) << 16)) |
||
| 6655 | #define S_028804_INCOHERENT_EQAA_READS(x) (((x) & 0x1) << 17) |
||
| 6656 | #define G_028804_INCOHERENT_EQAA_READS(x) (((x) >> 17) & 0x1) |
||
| 6657 | #define C_028804_INCOHERENT_EQAA_READS (~(((~0) & 0x1) << 17)) |
||
| 6658 | #define S_028804_INTERPOLATE_COMP_Z(x) (((x) & 0x1) << 18) |
||
| 6659 | #define G_028804_INTERPOLATE_COMP_Z(x) (((x) >> 18) & 0x1) |
||
| 6660 | #define C_028804_INTERPOLATE_COMP_Z (~(((~0) >> 18) & 0x1)) |
||
| 6661 | #define S_028804_INTERPOLATE_SRC_Z(x) (((x) & 0x1) << 19) |
||
| 6662 | #define G_028804_INTERPOLATE_SRC_Z(x) (((x) >> 19) & 0x1) |
||
| 6663 | #define C_028804_INTERPOLATE_SRC_Z (~(((~0) & 0x1) << 19)) |
||
| 6664 | #define S_028804_STATIC_ANCHOR_ASSOCIATIONS(x) (((x) & 0x1) << 20) |
||
| 6665 | #define G_028804_STATIC_ANCHOR_ASSOCIATIONS(x) (((x) >> 20) & 0x1) |
||
| 6666 | #define C_028804_STATIC_ANCHOR_ASSOCIATIONS (~(((~0) & 0x1) << 20)) |
||
| 6667 | #define S_028804_ALPHA_TO_MASK_EQAA_DISABLE(x) (((x) & 0x1) << 21) |
||
| 6668 | #define G_028804_ALPHA_TO_MASK_EQAA_DISABLE(x) (((x) >> 21) & 0x1) |
||
| 6669 | #define C_028804_ALPHA_TO_MASK_EQAA_DISABLE (~(((~0) & 0x1) << 21)) |
||
| 6670 | #define R_028808_CB_COLOR_CONTROL 0x028808 |
||
| 6671 | #define S_028808_DEGAMMA_ENABLE(x) (((x) & 0x1) << 3) |
||
| 6672 | #define G_028808_DEGAMMA_ENABLE(x) (((x) >> 3) & 0x1) |
||
| 6673 | #define C_028808_DEGAMMA_ENABLE 0xFFFFFFF7 |
||
| 6674 | #define S_028808_MODE(x) (((x) & 0x07) << 4) |
||
| 6675 | #define G_028808_MODE(x) (((x) >> 4) & 0x07) |
||
| 6676 | #define C_028808_MODE 0xFFFFFF8F |
||
| 6677 | #define V_028808_CB_DISABLE 0x00 |
||
| 6678 | #define V_028808_CB_NORMAL 0x01 |
||
| 6679 | #define V_028808_CB_ELIMINATE_FAST_CLEAR 0x02 |
||
| 6680 | #define V_028808_CB_RESOLVE 0x03 |
||
| 6681 | #define V_028808_CB_FMASK_DECOMPRESS 0x05 |
||
| 6682 | #define S_028808_ROP3(x) (((x) & 0xFF) << 16) |
||
| 6683 | #define G_028808_ROP3(x) (((x) >> 16) & 0xFF) |
||
| 6684 | #define C_028808_ROP3 0xFF00FFFF |
||
| 6685 | #define V_028808_X_0X00 0x00 |
||
| 6686 | #define V_028808_X_0X05 0x05 |
||
| 6687 | #define V_028808_X_0X0A 0x0A |
||
| 6688 | #define V_028808_X_0X0F 0x0F |
||
| 6689 | #define V_028808_X_0X11 0x11 |
||
| 6690 | #define V_028808_X_0X22 0x22 |
||
| 6691 | #define V_028808_X_0X33 0x33 |
||
| 6692 | #define V_028808_X_0X44 0x44 |
||
| 6693 | #define V_028808_X_0X50 0x50 |
||
| 6694 | #define V_028808_X_0X55 0x55 |
||
| 6695 | #define V_028808_X_0X5A 0x5A |
||
| 6696 | #define V_028808_X_0X5F 0x5F |
||
| 6697 | #define V_028808_X_0X66 0x66 |
||
| 6698 | #define V_028808_X_0X77 0x77 |
||
| 6699 | #define V_028808_X_0X88 0x88 |
||
| 6700 | #define V_028808_X_0X99 0x99 |
||
| 6701 | #define V_028808_X_0XA0 0xA0 |
||
| 6702 | #define V_028808_X_0XA5 0xA5 |
||
| 6703 | #define V_028808_X_0XAA 0xAA |
||
| 6704 | #define V_028808_X_0XAF 0xAF |
||
| 6705 | #define V_028808_X_0XBB 0xBB |
||
| 6706 | #define V_028808_X_0XCC 0xCC |
||
| 6707 | #define V_028808_X_0XDD 0xDD |
||
| 6708 | #define V_028808_X_0XEE 0xEE |
||
| 6709 | #define V_028808_X_0XF0 0xF0 |
||
| 6710 | #define V_028808_X_0XF5 0xF5 |
||
| 6711 | #define V_028808_X_0XFA 0xFA |
||
| 6712 | #define V_028808_X_0XFF 0xFF |
||
| 6713 | #define R_02880C_DB_SHADER_CONTROL 0x02880C |
||
| 6714 | #define S_02880C_Z_EXPORT_ENABLE(x) (((x) & 0x1) << 0) |
||
| 6715 | #define G_02880C_Z_EXPORT_ENABLE(x) (((x) >> 0) & 0x1) |
||
| 6716 | #define C_02880C_Z_EXPORT_ENABLE 0xFFFFFFFE |
||
| 6717 | #define S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(x) (((x) & 0x1) << 1) |
||
| 6718 | #define G_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(x) (((x) >> 1) & 0x1) |
||
| 6719 | #define C_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE 0xFFFFFFFD |
||
| 6720 | #define S_02880C_STENCIL_OP_VAL_EXPORT_ENABLE(x) (((x) & 0x1) << 2) |
||
| 6721 | #define G_02880C_STENCIL_OP_VAL_EXPORT_ENABLE(x) (((x) >> 2) & 0x1) |
||
| 6722 | #define C_02880C_STENCIL_OP_VAL_EXPORT_ENABLE 0xFFFFFFFB |
||
| 6723 | #define S_02880C_Z_ORDER(x) (((x) & 0x03) << 4) |
||
| 6724 | #define G_02880C_Z_ORDER(x) (((x) >> 4) & 0x03) |
||
| 6725 | #define C_02880C_Z_ORDER 0xFFFFFFCF |
||
| 6726 | #define V_02880C_LATE_Z 0x00 |
||
| 6727 | #define V_02880C_EARLY_Z_THEN_LATE_Z 0x01 |
||
| 6728 | #define V_02880C_RE_Z 0x02 |
||
| 6729 | #define V_02880C_EARLY_Z_THEN_RE_Z 0x03 |
||
| 6730 | #define S_02880C_KILL_ENABLE(x) (((x) & 0x1) << 6) |
||
| 6731 | #define G_02880C_KILL_ENABLE(x) (((x) >> 6) & 0x1) |
||
| 6732 | #define C_02880C_KILL_ENABLE 0xFFFFFFBF |
||
| 6733 | #define S_02880C_COVERAGE_TO_MASK_ENABLE(x) (((x) & 0x1) << 7) |
||
| 6734 | #define G_02880C_COVERAGE_TO_MASK_ENABLE(x) (((x) >> 7) & 0x1) |
||
| 6735 | #define C_02880C_COVERAGE_TO_MASK_ENABLE 0xFFFFFF7F |
||
| 6736 | #define S_02880C_MASK_EXPORT_ENABLE(x) (((x) & 0x1) << 8) |
||
| 6737 | #define G_02880C_MASK_EXPORT_ENABLE(x) (((x) >> 8) & 0x1) |
||
| 6738 | #define C_02880C_MASK_EXPORT_ENABLE 0xFFFFFEFF |
||
| 6739 | #define S_02880C_EXEC_ON_HIER_FAIL(x) (((x) & 0x1) << 9) |
||
| 6740 | #define G_02880C_EXEC_ON_HIER_FAIL(x) (((x) >> 9) & 0x1) |
||
| 6741 | #define C_02880C_EXEC_ON_HIER_FAIL 0xFFFFFDFF |
||
| 6742 | #define S_02880C_EXEC_ON_NOOP(x) (((x) & 0x1) << 10) |
||
| 6743 | #define G_02880C_EXEC_ON_NOOP(x) (((x) >> 10) & 0x1) |
||
| 6744 | #define C_02880C_EXEC_ON_NOOP 0xFFFFFBFF |
||
| 6745 | #define S_02880C_ALPHA_TO_MASK_DISABLE(x) (((x) & 0x1) << 11) |
||
| 6746 | #define G_02880C_ALPHA_TO_MASK_DISABLE(x) (((x) >> 11) & 0x1) |
||
| 6747 | #define C_02880C_ALPHA_TO_MASK_DISABLE 0xFFFFF7FF |
||
| 6748 | #define S_02880C_DEPTH_BEFORE_SHADER(x) (((x) & 0x1) << 12) |
||
| 6749 | #define G_02880C_DEPTH_BEFORE_SHADER(x) (((x) >> 12) & 0x1) |
||
| 6750 | #define C_02880C_DEPTH_BEFORE_SHADER 0xFFFFEFFF |
||
| 6751 | /* CIK */ |
||
| 6752 | #define S_02880C_CONSERVATIVE_Z_EXPORT(x) (((x) & 0x03) << 13) |
||
| 6753 | #define G_02880C_CONSERVATIVE_Z_EXPORT(x) (((x) >> 13) & 0x03) |
||
| 6754 | #define C_02880C_CONSERVATIVE_Z_EXPORT 0xFFFF9FFF |
||
| 6755 | #define V_02880C_EXPORT_ANY_Z 0 |
||
| 6756 | #define V_02880C_EXPORT_LESS_THAN_Z 1 |
||
| 6757 | #define V_02880C_EXPORT_GREATER_THAN_Z 2 |
||
| 6758 | #define V_02880C_EXPORT_RESERVED 3 |
||
| 6759 | /* */ |
||
| 6760 | #define R_028810_PA_CL_CLIP_CNTL 0x028810 |
||
| 6761 | #define S_028810_UCP_ENA_0(x) (((x) & 0x1) << 0) |
||
| 6762 | #define G_028810_UCP_ENA_0(x) (((x) >> 0) & 0x1) |
||
| 6763 | #define C_028810_UCP_ENA_0 0xFFFFFFFE |
||
| 6764 | #define S_028810_UCP_ENA_1(x) (((x) & 0x1) << 1) |
||
| 6765 | #define G_028810_UCP_ENA_1(x) (((x) >> 1) & 0x1) |
||
| 6766 | #define C_028810_UCP_ENA_1 0xFFFFFFFD |
||
| 6767 | #define S_028810_UCP_ENA_2(x) (((x) & 0x1) << 2) |
||
| 6768 | #define G_028810_UCP_ENA_2(x) (((x) >> 2) & 0x1) |
||
| 6769 | #define C_028810_UCP_ENA_2 0xFFFFFFFB |
||
| 6770 | #define S_028810_UCP_ENA_3(x) (((x) & 0x1) << 3) |
||
| 6771 | #define G_028810_UCP_ENA_3(x) (((x) >> 3) & 0x1) |
||
| 6772 | #define C_028810_UCP_ENA_3 0xFFFFFFF7 |
||
| 6773 | #define S_028810_UCP_ENA_4(x) (((x) & 0x1) << 4) |
||
| 6774 | #define G_028810_UCP_ENA_4(x) (((x) >> 4) & 0x1) |
||
| 6775 | #define C_028810_UCP_ENA_4 0xFFFFFFEF |
||
| 6776 | #define S_028810_UCP_ENA_5(x) (((x) & 0x1) << 5) |
||
| 6777 | #define G_028810_UCP_ENA_5(x) (((x) >> 5) & 0x1) |
||
| 6778 | #define C_028810_UCP_ENA_5 0xFFFFFFDF |
||
| 6779 | #define S_028810_PS_UCP_Y_SCALE_NEG(x) (((x) & 0x1) << 13) |
||
| 6780 | #define G_028810_PS_UCP_Y_SCALE_NEG(x) (((x) >> 13) & 0x1) |
||
| 6781 | #define C_028810_PS_UCP_Y_SCALE_NEG 0xFFFFDFFF |
||
| 6782 | #define S_028810_PS_UCP_MODE(x) (((x) & 0x03) << 14) |
||
| 6783 | #define G_028810_PS_UCP_MODE(x) (((x) >> 14) & 0x03) |
||
| 6784 | #define C_028810_PS_UCP_MODE 0xFFFF3FFF |
||
| 6785 | #define S_028810_CLIP_DISABLE(x) (((x) & 0x1) << 16) |
||
| 6786 | #define G_028810_CLIP_DISABLE(x) (((x) >> 16) & 0x1) |
||
| 6787 | #define C_028810_CLIP_DISABLE 0xFFFEFFFF |
||
| 6788 | #define S_028810_UCP_CULL_ONLY_ENA(x) (((x) & 0x1) << 17) |
||
| 6789 | #define G_028810_UCP_CULL_ONLY_ENA(x) (((x) >> 17) & 0x1) |
||
| 6790 | #define C_028810_UCP_CULL_ONLY_ENA 0xFFFDFFFF |
||
| 6791 | #define S_028810_BOUNDARY_EDGE_FLAG_ENA(x) (((x) & 0x1) << 18) |
||
| 6792 | #define G_028810_BOUNDARY_EDGE_FLAG_ENA(x) (((x) >> 18) & 0x1) |
||
| 6793 | #define C_028810_BOUNDARY_EDGE_FLAG_ENA 0xFFFBFFFF |
||
| 6794 | #define S_028810_DX_CLIP_SPACE_DEF(x) (((x) & 0x1) << 19) |
||
| 6795 | #define G_028810_DX_CLIP_SPACE_DEF(x) (((x) >> 19) & 0x1) |
||
| 6796 | #define C_028810_DX_CLIP_SPACE_DEF 0xFFF7FFFF |
||
| 6797 | #define S_028810_DIS_CLIP_ERR_DETECT(x) (((x) & 0x1) << 20) |
||
| 6798 | #define G_028810_DIS_CLIP_ERR_DETECT(x) (((x) >> 20) & 0x1) |
||
| 6799 | #define C_028810_DIS_CLIP_ERR_DETECT 0xFFEFFFFF |
||
| 6800 | #define S_028810_VTX_KILL_OR(x) (((x) & 0x1) << 21) |
||
| 6801 | #define G_028810_VTX_KILL_OR(x) (((x) >> 21) & 0x1) |
||
| 6802 | #define C_028810_VTX_KILL_OR 0xFFDFFFFF |
||
| 6803 | #define S_028810_DX_RASTERIZATION_KILL(x) (((x) & 0x1) << 22) |
||
| 6804 | #define G_028810_DX_RASTERIZATION_KILL(x) (((x) >> 22) & 0x1) |
||
| 6805 | #define C_028810_DX_RASTERIZATION_KILL 0xFFBFFFFF |
||
| 6806 | #define S_028810_DX_LINEAR_ATTR_CLIP_ENA(x) (((x) & 0x1) << 24) |
||
| 6807 | #define G_028810_DX_LINEAR_ATTR_CLIP_ENA(x) (((x) >> 24) & 0x1) |
||
| 6808 | #define C_028810_DX_LINEAR_ATTR_CLIP_ENA 0xFEFFFFFF |
||
| 6809 | #define S_028810_VTE_VPORT_PROVOKE_DISABLE(x) (((x) & 0x1) << 25) |
||
| 6810 | #define G_028810_VTE_VPORT_PROVOKE_DISABLE(x) (((x) >> 25) & 0x1) |
||
| 6811 | #define C_028810_VTE_VPORT_PROVOKE_DISABLE 0xFDFFFFFF |
||
| 6812 | #define S_028810_ZCLIP_NEAR_DISABLE(x) (((x) & 0x1) << 26) |
||
| 6813 | #define G_028810_ZCLIP_NEAR_DISABLE(x) (((x) >> 26) & 0x1) |
||
| 6814 | #define C_028810_ZCLIP_NEAR_DISABLE 0xFBFFFFFF |
||
| 6815 | #define S_028810_ZCLIP_FAR_DISABLE(x) (((x) & 0x1) << 27) |
||
| 6816 | #define G_028810_ZCLIP_FAR_DISABLE(x) (((x) >> 27) & 0x1) |
||
| 6817 | #define C_028810_ZCLIP_FAR_DISABLE 0xF7FFFFFF |
||
| 6818 | #define R_028814_PA_SU_SC_MODE_CNTL 0x028814 |
||
| 6819 | #define S_028814_CULL_FRONT(x) (((x) & 0x1) << 0) |
||
| 6820 | #define G_028814_CULL_FRONT(x) (((x) >> 0) & 0x1) |
||
| 6821 | #define C_028814_CULL_FRONT 0xFFFFFFFE |
||
| 6822 | #define S_028814_CULL_BACK(x) (((x) & 0x1) << 1) |
||
| 6823 | #define G_028814_CULL_BACK(x) (((x) >> 1) & 0x1) |
||
| 6824 | #define C_028814_CULL_BACK 0xFFFFFFFD |
||
| 6825 | #define S_028814_FACE(x) (((x) & 0x1) << 2) |
||
| 6826 | #define G_028814_FACE(x) (((x) >> 2) & 0x1) |
||
| 6827 | #define C_028814_FACE 0xFFFFFFFB |
||
| 6828 | #define S_028814_POLY_MODE(x) (((x) & 0x03) << 3) |
||
| 6829 | #define G_028814_POLY_MODE(x) (((x) >> 3) & 0x03) |
||
| 6830 | #define C_028814_POLY_MODE 0xFFFFFFE7 |
||
| 6831 | #define V_028814_X_DISABLE_POLY_MODE 0x00 |
||
| 6832 | #define V_028814_X_DUAL_MODE 0x01 |
||
| 6833 | #define S_028814_POLYMODE_FRONT_PTYPE(x) (((x) & 0x07) << 5) |
||
| 6834 | #define G_028814_POLYMODE_FRONT_PTYPE(x) (((x) >> 5) & 0x07) |
||
| 6835 | #define C_028814_POLYMODE_FRONT_PTYPE 0xFFFFFF1F |
||
| 6836 | #define V_028814_X_DRAW_POINTS 0x00 |
||
| 6837 | #define V_028814_X_DRAW_LINES 0x01 |
||
| 6838 | #define V_028814_X_DRAW_TRIANGLES 0x02 |
||
| 6839 | #define S_028814_POLYMODE_BACK_PTYPE(x) (((x) & 0x07) << 8) |
||
| 6840 | #define G_028814_POLYMODE_BACK_PTYPE(x) (((x) >> 8) & 0x07) |
||
| 6841 | #define C_028814_POLYMODE_BACK_PTYPE 0xFFFFF8FF |
||
| 6842 | #define V_028814_X_DRAW_POINTS 0x00 |
||
| 6843 | #define V_028814_X_DRAW_LINES 0x01 |
||
| 6844 | #define V_028814_X_DRAW_TRIANGLES 0x02 |
||
| 6845 | #define S_028814_POLY_OFFSET_FRONT_ENABLE(x) (((x) & 0x1) << 11) |
||
| 6846 | #define G_028814_POLY_OFFSET_FRONT_ENABLE(x) (((x) >> 11) & 0x1) |
||
| 6847 | #define C_028814_POLY_OFFSET_FRONT_ENABLE 0xFFFFF7FF |
||
| 6848 | #define S_028814_POLY_OFFSET_BACK_ENABLE(x) (((x) & 0x1) << 12) |
||
| 6849 | #define G_028814_POLY_OFFSET_BACK_ENABLE(x) (((x) >> 12) & 0x1) |
||
| 6850 | #define C_028814_POLY_OFFSET_BACK_ENABLE 0xFFFFEFFF |
||
| 6851 | #define S_028814_POLY_OFFSET_PARA_ENABLE(x) (((x) & 0x1) << 13) |
||
| 6852 | #define G_028814_POLY_OFFSET_PARA_ENABLE(x) (((x) >> 13) & 0x1) |
||
| 6853 | #define C_028814_POLY_OFFSET_PARA_ENABLE 0xFFFFDFFF |
||
| 6854 | #define S_028814_VTX_WINDOW_OFFSET_ENABLE(x) (((x) & 0x1) << 16) |
||
| 6855 | #define G_028814_VTX_WINDOW_OFFSET_ENABLE(x) (((x) >> 16) & 0x1) |
||
| 6856 | #define C_028814_VTX_WINDOW_OFFSET_ENABLE 0xFFFEFFFF |
||
| 6857 | #define S_028814_PROVOKING_VTX_LAST(x) (((x) & 0x1) << 19) |
||
| 6858 | #define G_028814_PROVOKING_VTX_LAST(x) (((x) >> 19) & 0x1) |
||
| 6859 | #define C_028814_PROVOKING_VTX_LAST 0xFFF7FFFF |
||
| 6860 | #define S_028814_PERSP_CORR_DIS(x) (((x) & 0x1) << 20) |
||
| 6861 | #define G_028814_PERSP_CORR_DIS(x) (((x) >> 20) & 0x1) |
||
| 6862 | #define C_028814_PERSP_CORR_DIS 0xFFEFFFFF |
||
| 6863 | #define S_028814_MULTI_PRIM_IB_ENA(x) (((x) & 0x1) << 21) |
||
| 6864 | #define G_028814_MULTI_PRIM_IB_ENA(x) (((x) >> 21) & 0x1) |
||
| 6865 | #define C_028814_MULTI_PRIM_IB_ENA 0xFFDFFFFF |
||
| 6866 | #define R_028818_PA_CL_VTE_CNTL 0x028818 |
||
| 6867 | #define S_028818_VPORT_X_SCALE_ENA(x) (((x) & 0x1) << 0) |
||
| 6868 | #define G_028818_VPORT_X_SCALE_ENA(x) (((x) >> 0) & 0x1) |
||
| 6869 | #define C_028818_VPORT_X_SCALE_ENA 0xFFFFFFFE |
||
| 6870 | #define S_028818_VPORT_X_OFFSET_ENA(x) (((x) & 0x1) << 1) |
||
| 6871 | #define G_028818_VPORT_X_OFFSET_ENA(x) (((x) >> 1) & 0x1) |
||
| 6872 | #define C_028818_VPORT_X_OFFSET_ENA 0xFFFFFFFD |
||
| 6873 | #define S_028818_VPORT_Y_SCALE_ENA(x) (((x) & 0x1) << 2) |
||
| 6874 | #define G_028818_VPORT_Y_SCALE_ENA(x) (((x) >> 2) & 0x1) |
||
| 6875 | #define C_028818_VPORT_Y_SCALE_ENA 0xFFFFFFFB |
||
| 6876 | #define S_028818_VPORT_Y_OFFSET_ENA(x) (((x) & 0x1) << 3) |
||
| 6877 | #define G_028818_VPORT_Y_OFFSET_ENA(x) (((x) >> 3) & 0x1) |
||
| 6878 | #define C_028818_VPORT_Y_OFFSET_ENA 0xFFFFFFF7 |
||
| 6879 | #define S_028818_VPORT_Z_SCALE_ENA(x) (((x) & 0x1) << 4) |
||
| 6880 | #define G_028818_VPORT_Z_SCALE_ENA(x) (((x) >> 4) & 0x1) |
||
| 6881 | #define C_028818_VPORT_Z_SCALE_ENA 0xFFFFFFEF |
||
| 6882 | #define S_028818_VPORT_Z_OFFSET_ENA(x) (((x) & 0x1) << 5) |
||
| 6883 | #define G_028818_VPORT_Z_OFFSET_ENA(x) (((x) >> 5) & 0x1) |
||
| 6884 | #define C_028818_VPORT_Z_OFFSET_ENA 0xFFFFFFDF |
||
| 6885 | #define S_028818_VTX_XY_FMT(x) (((x) & 0x1) << 8) |
||
| 6886 | #define G_028818_VTX_XY_FMT(x) (((x) >> 8) & 0x1) |
||
| 6887 | #define C_028818_VTX_XY_FMT 0xFFFFFEFF |
||
| 6888 | #define S_028818_VTX_Z_FMT(x) (((x) & 0x1) << 9) |
||
| 6889 | #define G_028818_VTX_Z_FMT(x) (((x) >> 9) & 0x1) |
||
| 6890 | #define C_028818_VTX_Z_FMT 0xFFFFFDFF |
||
| 6891 | #define S_028818_VTX_W0_FMT(x) (((x) & 0x1) << 10) |
||
| 6892 | #define G_028818_VTX_W0_FMT(x) (((x) >> 10) & 0x1) |
||
| 6893 | #define C_028818_VTX_W0_FMT 0xFFFFFBFF |
||
| 6894 | #define R_02881C_PA_CL_VS_OUT_CNTL 0x02881C |
||
| 6895 | #define S_02881C_CLIP_DIST_ENA_0(x) (((x) & 0x1) << 0) |
||
| 6896 | #define G_02881C_CLIP_DIST_ENA_0(x) (((x) >> 0) & 0x1) |
||
| 6897 | #define C_02881C_CLIP_DIST_ENA_0 0xFFFFFFFE |
||
| 6898 | #define S_02881C_CLIP_DIST_ENA_1(x) (((x) & 0x1) << 1) |
||
| 6899 | #define G_02881C_CLIP_DIST_ENA_1(x) (((x) >> 1) & 0x1) |
||
| 6900 | #define C_02881C_CLIP_DIST_ENA_1 0xFFFFFFFD |
||
| 6901 | #define S_02881C_CLIP_DIST_ENA_2(x) (((x) & 0x1) << 2) |
||
| 6902 | #define G_02881C_CLIP_DIST_ENA_2(x) (((x) >> 2) & 0x1) |
||
| 6903 | #define C_02881C_CLIP_DIST_ENA_2 0xFFFFFFFB |
||
| 6904 | #define S_02881C_CLIP_DIST_ENA_3(x) (((x) & 0x1) << 3) |
||
| 6905 | #define G_02881C_CLIP_DIST_ENA_3(x) (((x) >> 3) & 0x1) |
||
| 6906 | #define C_02881C_CLIP_DIST_ENA_3 0xFFFFFFF7 |
||
| 6907 | #define S_02881C_CLIP_DIST_ENA_4(x) (((x) & 0x1) << 4) |
||
| 6908 | #define G_02881C_CLIP_DIST_ENA_4(x) (((x) >> 4) & 0x1) |
||
| 6909 | #define C_02881C_CLIP_DIST_ENA_4 0xFFFFFFEF |
||
| 6910 | #define S_02881C_CLIP_DIST_ENA_5(x) (((x) & 0x1) << 5) |
||
| 6911 | #define G_02881C_CLIP_DIST_ENA_5(x) (((x) >> 5) & 0x1) |
||
| 6912 | #define C_02881C_CLIP_DIST_ENA_5 0xFFFFFFDF |
||
| 6913 | #define S_02881C_CLIP_DIST_ENA_6(x) (((x) & 0x1) << 6) |
||
| 6914 | #define G_02881C_CLIP_DIST_ENA_6(x) (((x) >> 6) & 0x1) |
||
| 6915 | #define C_02881C_CLIP_DIST_ENA_6 0xFFFFFFBF |
||
| 6916 | #define S_02881C_CLIP_DIST_ENA_7(x) (((x) & 0x1) << 7) |
||
| 6917 | #define G_02881C_CLIP_DIST_ENA_7(x) (((x) >> 7) & 0x1) |
||
| 6918 | #define C_02881C_CLIP_DIST_ENA_7 0xFFFFFF7F |
||
| 6919 | #define S_02881C_CULL_DIST_ENA_0(x) (((x) & 0x1) << 8) |
||
| 6920 | #define G_02881C_CULL_DIST_ENA_0(x) (((x) >> 8) & 0x1) |
||
| 6921 | #define C_02881C_CULL_DIST_ENA_0 0xFFFFFEFF |
||
| 6922 | #define S_02881C_CULL_DIST_ENA_1(x) (((x) & 0x1) << 9) |
||
| 6923 | #define G_02881C_CULL_DIST_ENA_1(x) (((x) >> 9) & 0x1) |
||
| 6924 | #define C_02881C_CULL_DIST_ENA_1 0xFFFFFDFF |
||
| 6925 | #define S_02881C_CULL_DIST_ENA_2(x) (((x) & 0x1) << 10) |
||
| 6926 | #define G_02881C_CULL_DIST_ENA_2(x) (((x) >> 10) & 0x1) |
||
| 6927 | #define C_02881C_CULL_DIST_ENA_2 0xFFFFFBFF |
||
| 6928 | #define S_02881C_CULL_DIST_ENA_3(x) (((x) & 0x1) << 11) |
||
| 6929 | #define G_02881C_CULL_DIST_ENA_3(x) (((x) >> 11) & 0x1) |
||
| 6930 | #define C_02881C_CULL_DIST_ENA_3 0xFFFFF7FF |
||
| 6931 | #define S_02881C_CULL_DIST_ENA_4(x) (((x) & 0x1) << 12) |
||
| 6932 | #define G_02881C_CULL_DIST_ENA_4(x) (((x) >> 12) & 0x1) |
||
| 6933 | #define C_02881C_CULL_DIST_ENA_4 0xFFFFEFFF |
||
| 6934 | #define S_02881C_CULL_DIST_ENA_5(x) (((x) & 0x1) << 13) |
||
| 6935 | #define G_02881C_CULL_DIST_ENA_5(x) (((x) >> 13) & 0x1) |
||
| 6936 | #define C_02881C_CULL_DIST_ENA_5 0xFFFFDFFF |
||
| 6937 | #define S_02881C_CULL_DIST_ENA_6(x) (((x) & 0x1) << 14) |
||
| 6938 | #define G_02881C_CULL_DIST_ENA_6(x) (((x) >> 14) & 0x1) |
||
| 6939 | #define C_02881C_CULL_DIST_ENA_6 0xFFFFBFFF |
||
| 6940 | #define S_02881C_CULL_DIST_ENA_7(x) (((x) & 0x1) << 15) |
||
| 6941 | #define G_02881C_CULL_DIST_ENA_7(x) (((x) >> 15) & 0x1) |
||
| 6942 | #define C_02881C_CULL_DIST_ENA_7 0xFFFF7FFF |
||
| 6943 | #define S_02881C_USE_VTX_POINT_SIZE(x) (((x) & 0x1) << 16) |
||
| 6944 | #define G_02881C_USE_VTX_POINT_SIZE(x) (((x) >> 16) & 0x1) |
||
| 6945 | #define C_02881C_USE_VTX_POINT_SIZE 0xFFFEFFFF |
||
| 6946 | #define S_02881C_USE_VTX_EDGE_FLAG(x) (((x) & 0x1) << 17) |
||
| 6947 | #define G_02881C_USE_VTX_EDGE_FLAG(x) (((x) >> 17) & 0x1) |
||
| 6948 | #define C_02881C_USE_VTX_EDGE_FLAG 0xFFFDFFFF |
||
| 6949 | #define S_02881C_USE_VTX_RENDER_TARGET_INDX(x) (((x) & 0x1) << 18) |
||
| 6950 | #define G_02881C_USE_VTX_RENDER_TARGET_INDX(x) (((x) >> 18) & 0x1) |
||
| 6951 | #define C_02881C_USE_VTX_RENDER_TARGET_INDX 0xFFFBFFFF |
||
| 6952 | #define S_02881C_USE_VTX_VIEWPORT_INDX(x) (((x) & 0x1) << 19) |
||
| 6953 | #define G_02881C_USE_VTX_VIEWPORT_INDX(x) (((x) >> 19) & 0x1) |
||
| 6954 | #define C_02881C_USE_VTX_VIEWPORT_INDX 0xFFF7FFFF |
||
| 6955 | #define S_02881C_USE_VTX_KILL_FLAG(x) (((x) & 0x1) << 20) |
||
| 6956 | #define G_02881C_USE_VTX_KILL_FLAG(x) (((x) >> 20) & 0x1) |
||
| 6957 | #define C_02881C_USE_VTX_KILL_FLAG 0xFFEFFFFF |
||
| 6958 | #define S_02881C_VS_OUT_MISC_VEC_ENA(x) (((x) & 0x1) << 21) |
||
| 6959 | #define G_02881C_VS_OUT_MISC_VEC_ENA(x) (((x) >> 21) & 0x1) |
||
| 6960 | #define C_02881C_VS_OUT_MISC_VEC_ENA 0xFFDFFFFF |
||
| 6961 | #define S_02881C_VS_OUT_CCDIST0_VEC_ENA(x) (((x) & 0x1) << 22) |
||
| 6962 | #define G_02881C_VS_OUT_CCDIST0_VEC_ENA(x) (((x) >> 22) & 0x1) |
||
| 6963 | #define C_02881C_VS_OUT_CCDIST0_VEC_ENA 0xFFBFFFFF |
||
| 6964 | #define S_02881C_VS_OUT_CCDIST1_VEC_ENA(x) (((x) & 0x1) << 23) |
||
| 6965 | #define G_02881C_VS_OUT_CCDIST1_VEC_ENA(x) (((x) >> 23) & 0x1) |
||
| 6966 | #define C_02881C_VS_OUT_CCDIST1_VEC_ENA 0xFF7FFFFF |
||
| 6967 | #define S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(x) (((x) & 0x1) << 24) |
||
| 6968 | #define G_02881C_VS_OUT_MISC_SIDE_BUS_ENA(x) (((x) >> 24) & 0x1) |
||
| 6969 | #define C_02881C_VS_OUT_MISC_SIDE_BUS_ENA 0xFEFFFFFF |
||
| 6970 | #define S_02881C_USE_VTX_GS_CUT_FLAG(x) (((x) & 0x1) << 25) |
||
| 6971 | #define G_02881C_USE_VTX_GS_CUT_FLAG(x) (((x) >> 25) & 0x1) |
||
| 6972 | #define C_02881C_USE_VTX_GS_CUT_FLAG 0xFDFFFFFF |
||
| 6973 | #define R_028820_PA_CL_NANINF_CNTL 0x028820 |
||
| 6974 | #define S_028820_VTE_XY_INF_DISCARD(x) (((x) & 0x1) << 0) |
||
| 6975 | #define G_028820_VTE_XY_INF_DISCARD(x) (((x) >> 0) & 0x1) |
||
| 6976 | #define C_028820_VTE_XY_INF_DISCARD 0xFFFFFFFE |
||
| 6977 | #define S_028820_VTE_Z_INF_DISCARD(x) (((x) & 0x1) << 1) |
||
| 6978 | #define G_028820_VTE_Z_INF_DISCARD(x) (((x) >> 1) & 0x1) |
||
| 6979 | #define C_028820_VTE_Z_INF_DISCARD 0xFFFFFFFD |
||
| 6980 | #define S_028820_VTE_W_INF_DISCARD(x) (((x) & 0x1) << 2) |
||
| 6981 | #define G_028820_VTE_W_INF_DISCARD(x) (((x) >> 2) & 0x1) |
||
| 6982 | #define C_028820_VTE_W_INF_DISCARD 0xFFFFFFFB |
||
| 6983 | #define S_028820_VTE_0XNANINF_IS_0(x) (((x) & 0x1) << 3) |
||
| 6984 | #define G_028820_VTE_0XNANINF_IS_0(x) (((x) >> 3) & 0x1) |
||
| 6985 | #define C_028820_VTE_0XNANINF_IS_0 0xFFFFFFF7 |
||
| 6986 | #define S_028820_VTE_XY_NAN_RETAIN(x) (((x) & 0x1) << 4) |
||
| 6987 | #define G_028820_VTE_XY_NAN_RETAIN(x) (((x) >> 4) & 0x1) |
||
| 6988 | #define C_028820_VTE_XY_NAN_RETAIN 0xFFFFFFEF |
||
| 6989 | #define S_028820_VTE_Z_NAN_RETAIN(x) (((x) & 0x1) << 5) |
||
| 6990 | #define G_028820_VTE_Z_NAN_RETAIN(x) (((x) >> 5) & 0x1) |
||
| 6991 | #define C_028820_VTE_Z_NAN_RETAIN 0xFFFFFFDF |
||
| 6992 | #define S_028820_VTE_W_NAN_RETAIN(x) (((x) & 0x1) << 6) |
||
| 6993 | #define G_028820_VTE_W_NAN_RETAIN(x) (((x) >> 6) & 0x1) |
||
| 6994 | #define C_028820_VTE_W_NAN_RETAIN 0xFFFFFFBF |
||
| 6995 | #define S_028820_VTE_W_RECIP_NAN_IS_0(x) (((x) & 0x1) << 7) |
||
| 6996 | #define G_028820_VTE_W_RECIP_NAN_IS_0(x) (((x) >> 7) & 0x1) |
||
| 6997 | #define C_028820_VTE_W_RECIP_NAN_IS_0 0xFFFFFF7F |
||
| 6998 | #define S_028820_VS_XY_NAN_TO_INF(x) (((x) & 0x1) << 8) |
||
| 6999 | #define G_028820_VS_XY_NAN_TO_INF(x) (((x) >> 8) & 0x1) |
||
| 7000 | #define C_028820_VS_XY_NAN_TO_INF 0xFFFFFEFF |
||
| 7001 | #define S_028820_VS_XY_INF_RETAIN(x) (((x) & 0x1) << 9) |
||
| 7002 | #define G_028820_VS_XY_INF_RETAIN(x) (((x) >> 9) & 0x1) |
||
| 7003 | #define C_028820_VS_XY_INF_RETAIN 0xFFFFFDFF |
||
| 7004 | #define S_028820_VS_Z_NAN_TO_INF(x) (((x) & 0x1) << 10) |
||
| 7005 | #define G_028820_VS_Z_NAN_TO_INF(x) (((x) >> 10) & 0x1) |
||
| 7006 | #define C_028820_VS_Z_NAN_TO_INF 0xFFFFFBFF |
||
| 7007 | #define S_028820_VS_Z_INF_RETAIN(x) (((x) & 0x1) << 11) |
||
| 7008 | #define G_028820_VS_Z_INF_RETAIN(x) (((x) >> 11) & 0x1) |
||
| 7009 | #define C_028820_VS_Z_INF_RETAIN 0xFFFFF7FF |
||
| 7010 | #define S_028820_VS_W_NAN_TO_INF(x) (((x) & 0x1) << 12) |
||
| 7011 | #define G_028820_VS_W_NAN_TO_INF(x) (((x) >> 12) & 0x1) |
||
| 7012 | #define C_028820_VS_W_NAN_TO_INF 0xFFFFEFFF |
||
| 7013 | #define S_028820_VS_W_INF_RETAIN(x) (((x) & 0x1) << 13) |
||
| 7014 | #define G_028820_VS_W_INF_RETAIN(x) (((x) >> 13) & 0x1) |
||
| 7015 | #define C_028820_VS_W_INF_RETAIN 0xFFFFDFFF |
||
| 7016 | #define S_028820_VS_CLIP_DIST_INF_DISCARD(x) (((x) & 0x1) << 14) |
||
| 7017 | #define G_028820_VS_CLIP_DIST_INF_DISCARD(x) (((x) >> 14) & 0x1) |
||
| 7018 | #define C_028820_VS_CLIP_DIST_INF_DISCARD 0xFFFFBFFF |
||
| 7019 | #define S_028820_VTE_NO_OUTPUT_NEG_0(x) (((x) & 0x1) << 20) |
||
| 7020 | #define G_028820_VTE_NO_OUTPUT_NEG_0(x) (((x) >> 20) & 0x1) |
||
| 7021 | #define C_028820_VTE_NO_OUTPUT_NEG_0 0xFFEFFFFF |
||
| 7022 | #define R_028824_PA_SU_LINE_STIPPLE_CNTL 0x028824 |
||
| 7023 | #define S_028824_LINE_STIPPLE_RESET(x) (((x) & 0x03) << 0) |
||
| 7024 | #define G_028824_LINE_STIPPLE_RESET(x) (((x) >> 0) & 0x03) |
||
| 7025 | #define C_028824_LINE_STIPPLE_RESET 0xFFFFFFFC |
||
| 7026 | #define S_028824_EXPAND_FULL_LENGTH(x) (((x) & 0x1) << 2) |
||
| 7027 | #define G_028824_EXPAND_FULL_LENGTH(x) (((x) >> 2) & 0x1) |
||
| 7028 | #define C_028824_EXPAND_FULL_LENGTH 0xFFFFFFFB |
||
| 7029 | #define S_028824_FRACTIONAL_ACCUM(x) (((x) & 0x1) << 3) |
||
| 7030 | #define G_028824_FRACTIONAL_ACCUM(x) (((x) >> 3) & 0x1) |
||
| 7031 | #define C_028824_FRACTIONAL_ACCUM 0xFFFFFFF7 |
||
| 7032 | #define S_028824_DIAMOND_ADJUST(x) (((x) & 0x1) << 4) |
||
| 7033 | #define G_028824_DIAMOND_ADJUST(x) (((x) >> 4) & 0x1) |
||
| 7034 | #define C_028824_DIAMOND_ADJUST 0xFFFFFFEF |
||
| 7035 | #define R_028828_PA_SU_LINE_STIPPLE_SCALE 0x028828 |
||
| 7036 | #define R_02882C_PA_SU_PRIM_FILTER_CNTL 0x02882C |
||
| 7037 | #define S_02882C_TRIANGLE_FILTER_DISABLE(x) (((x) & 0x1) << 0) |
||
| 7038 | #define G_02882C_TRIANGLE_FILTER_DISABLE(x) (((x) >> 0) & 0x1) |
||
| 7039 | #define C_02882C_TRIANGLE_FILTER_DISABLE 0xFFFFFFFE |
||
| 7040 | #define S_02882C_LINE_FILTER_DISABLE(x) (((x) & 0x1) << 1) |
||
| 7041 | #define G_02882C_LINE_FILTER_DISABLE(x) (((x) >> 1) & 0x1) |
||
| 7042 | #define C_02882C_LINE_FILTER_DISABLE 0xFFFFFFFD |
||
| 7043 | #define S_02882C_POINT_FILTER_DISABLE(x) (((x) & 0x1) << 2) |
||
| 7044 | #define G_02882C_POINT_FILTER_DISABLE(x) (((x) >> 2) & 0x1) |
||
| 7045 | #define C_02882C_POINT_FILTER_DISABLE 0xFFFFFFFB |
||
| 7046 | #define S_02882C_RECTANGLE_FILTER_DISABLE(x) (((x) & 0x1) << 3) |
||
| 7047 | #define G_02882C_RECTANGLE_FILTER_DISABLE(x) (((x) >> 3) & 0x1) |
||
| 7048 | #define C_02882C_RECTANGLE_FILTER_DISABLE 0xFFFFFFF7 |
||
| 7049 | #define S_02882C_TRIANGLE_EXPAND_ENA(x) (((x) & 0x1) << 4) |
||
| 7050 | #define G_02882C_TRIANGLE_EXPAND_ENA(x) (((x) >> 4) & 0x1) |
||
| 7051 | #define C_02882C_TRIANGLE_EXPAND_ENA 0xFFFFFFEF |
||
| 7052 | #define S_02882C_LINE_EXPAND_ENA(x) (((x) & 0x1) << 5) |
||
| 7053 | #define G_02882C_LINE_EXPAND_ENA(x) (((x) >> 5) & 0x1) |
||
| 7054 | #define C_02882C_LINE_EXPAND_ENA 0xFFFFFFDF |
||
| 7055 | #define S_02882C_POINT_EXPAND_ENA(x) (((x) & 0x1) << 6) |
||
| 7056 | #define G_02882C_POINT_EXPAND_ENA(x) (((x) >> 6) & 0x1) |
||
| 7057 | #define C_02882C_POINT_EXPAND_ENA 0xFFFFFFBF |
||
| 7058 | #define S_02882C_RECTANGLE_EXPAND_ENA(x) (((x) & 0x1) << 7) |
||
| 7059 | #define G_02882C_RECTANGLE_EXPAND_ENA(x) (((x) >> 7) & 0x1) |
||
| 7060 | #define C_02882C_RECTANGLE_EXPAND_ENA 0xFFFFFF7F |
||
| 7061 | #define S_02882C_PRIM_EXPAND_CONSTANT(x) (((x) & 0xFF) << 8) |
||
| 7062 | #define G_02882C_PRIM_EXPAND_CONSTANT(x) (((x) >> 8) & 0xFF) |
||
| 7063 | #define C_02882C_PRIM_EXPAND_CONSTANT 0xFFFF00FF |
||
| 7064 | /* CIK */ |
||
| 7065 | #define S_02882C_XMAX_RIGHT_EXCLUSION(x) (((x) & 0x1) << 30) |
||
| 7066 | #define G_02882C_XMAX_RIGHT_EXCLUSION(x) (((x) >> 30) & 0x1) |
||
| 7067 | #define C_02882C_XMAX_RIGHT_EXCLUSION 0xBFFFFFFF |
||
| 7068 | #define S_02882C_YMAX_BOTTOM_EXCLUSION(x) (((x) & 0x1) << 31) |
||
| 7069 | #define G_02882C_YMAX_BOTTOM_EXCLUSION(x) (((x) >> 31) & 0x1) |
||
| 7070 | #define C_02882C_YMAX_BOTTOM_EXCLUSION 0x7FFFFFFF |
||
| 7071 | /* */ |
||
| 7072 | #define R_028A00_PA_SU_POINT_SIZE 0x028A00 |
||
| 7073 | #define S_028A00_HEIGHT(x) (((x) & 0xFFFF) << 0) |
||
| 7074 | #define G_028A00_HEIGHT(x) (((x) >> 0) & 0xFFFF) |
||
| 7075 | #define C_028A00_HEIGHT 0xFFFF0000 |
||
| 7076 | #define S_028A00_WIDTH(x) (((x) & 0xFFFF) << 16) |
||
| 7077 | #define G_028A00_WIDTH(x) (((x) >> 16) & 0xFFFF) |
||
| 7078 | #define C_028A00_WIDTH 0x0000FFFF |
||
| 7079 | #define R_028A04_PA_SU_POINT_MINMAX 0x028A04 |
||
| 7080 | #define S_028A04_MIN_SIZE(x) (((x) & 0xFFFF) << 0) |
||
| 7081 | #define G_028A04_MIN_SIZE(x) (((x) >> 0) & 0xFFFF) |
||
| 7082 | #define C_028A04_MIN_SIZE 0xFFFF0000 |
||
| 7083 | #define S_028A04_MAX_SIZE(x) (((x) & 0xFFFF) << 16) |
||
| 7084 | #define G_028A04_MAX_SIZE(x) (((x) >> 16) & 0xFFFF) |
||
| 7085 | #define C_028A04_MAX_SIZE 0x0000FFFF |
||
| 7086 | #define R_028A08_PA_SU_LINE_CNTL 0x028A08 |
||
| 7087 | #define S_028A08_WIDTH(x) (((x) & 0xFFFF) << 0) |
||
| 7088 | #define G_028A08_WIDTH(x) (((x) >> 0) & 0xFFFF) |
||
| 7089 | #define C_028A08_WIDTH 0xFFFF0000 |
||
| 7090 | #define R_028A0C_PA_SC_LINE_STIPPLE 0x028A0C |
||
| 7091 | #define S_028A0C_LINE_PATTERN(x) (((x) & 0xFFFF) << 0) |
||
| 7092 | #define G_028A0C_LINE_PATTERN(x) (((x) >> 0) & 0xFFFF) |
||
| 7093 | #define C_028A0C_LINE_PATTERN 0xFFFF0000 |
||
| 7094 | #define S_028A0C_REPEAT_COUNT(x) (((x) & 0xFF) << 16) |
||
| 7095 | #define G_028A0C_REPEAT_COUNT(x) (((x) >> 16) & 0xFF) |
||
| 7096 | #define C_028A0C_REPEAT_COUNT 0xFF00FFFF |
||
| 7097 | #define S_028A0C_PATTERN_BIT_ORDER(x) (((x) & 0x1) << 28) |
||
| 7098 | #define G_028A0C_PATTERN_BIT_ORDER(x) (((x) >> 28) & 0x1) |
||
| 7099 | #define C_028A0C_PATTERN_BIT_ORDER 0xEFFFFFFF |
||
| 7100 | #define S_028A0C_AUTO_RESET_CNTL(x) (((x) & 0x03) << 29) |
||
| 7101 | #define G_028A0C_AUTO_RESET_CNTL(x) (((x) >> 29) & 0x03) |
||
| 7102 | #define C_028A0C_AUTO_RESET_CNTL 0x9FFFFFFF |
||
| 7103 | #define R_028A10_VGT_OUTPUT_PATH_CNTL 0x028A10 |
||
| 7104 | #define S_028A10_PATH_SELECT(x) (((x) & 0x07) << 0) |
||
| 7105 | #define G_028A10_PATH_SELECT(x) (((x) >> 0) & 0x07) |
||
| 7106 | #define C_028A10_PATH_SELECT 0xFFFFFFF8 |
||
| 7107 | #define V_028A10_VGT_OUTPATH_VTX_REUSE 0x00 |
||
| 7108 | #define V_028A10_VGT_OUTPATH_TESS_EN 0x01 |
||
| 7109 | #define V_028A10_VGT_OUTPATH_PASSTHRU 0x02 |
||
| 7110 | #define V_028A10_VGT_OUTPATH_GS_BLOCK 0x03 |
||
| 7111 | #define V_028A10_VGT_OUTPATH_HS_BLOCK 0x04 |
||
| 7112 | #define R_028A14_VGT_HOS_CNTL 0x028A14 |
||
| 7113 | #define S_028A14_TESS_MODE(x) (((x) & 0x03) << 0) |
||
| 7114 | #define G_028A14_TESS_MODE(x) (((x) >> 0) & 0x03) |
||
| 7115 | #define C_028A14_TESS_MODE 0xFFFFFFFC |
||
| 7116 | #define R_028A18_VGT_HOS_MAX_TESS_LEVEL 0x028A18 |
||
| 7117 | #define R_028A1C_VGT_HOS_MIN_TESS_LEVEL 0x028A1C |
||
| 7118 | #define R_028A20_VGT_HOS_REUSE_DEPTH 0x028A20 |
||
| 7119 | #define S_028A20_REUSE_DEPTH(x) (((x) & 0xFF) << 0) |
||
| 7120 | #define G_028A20_REUSE_DEPTH(x) (((x) >> 0) & 0xFF) |
||
| 7121 | #define C_028A20_REUSE_DEPTH 0xFFFFFF00 |
||
| 7122 | #define R_028A24_VGT_GROUP_PRIM_TYPE 0x028A24 |
||
| 7123 | #define S_028A24_PRIM_TYPE(x) (((x) & 0x1F) << 0) |
||
| 7124 | #define G_028A24_PRIM_TYPE(x) (((x) >> 0) & 0x1F) |
||
| 7125 | #define C_028A24_PRIM_TYPE 0xFFFFFFE0 |
||
| 7126 | #define V_028A24_VGT_GRP_3D_POINT 0x00 |
||
| 7127 | #define V_028A24_VGT_GRP_3D_LINE 0x01 |
||
| 7128 | #define V_028A24_VGT_GRP_3D_TRI 0x02 |
||
| 7129 | #define V_028A24_VGT_GRP_3D_RECT 0x03 |
||
| 7130 | #define V_028A24_VGT_GRP_3D_QUAD 0x04 |
||
| 7131 | #define V_028A24_VGT_GRP_2D_COPY_RECT_V0 0x05 |
||
| 7132 | #define V_028A24_VGT_GRP_2D_COPY_RECT_V1 0x06 |
||
| 7133 | #define V_028A24_VGT_GRP_2D_COPY_RECT_V2 0x07 |
||
| 7134 | #define V_028A24_VGT_GRP_2D_COPY_RECT_V3 0x08 |
||
| 7135 | #define V_028A24_VGT_GRP_2D_FILL_RECT 0x09 |
||
| 7136 | #define V_028A24_VGT_GRP_2D_LINE 0x0A |
||
| 7137 | #define V_028A24_VGT_GRP_2D_TRI 0x0B |
||
| 7138 | #define V_028A24_VGT_GRP_PRIM_INDEX_LINE 0x0C |
||
| 7139 | #define V_028A24_VGT_GRP_PRIM_INDEX_TRI 0x0D |
||
| 7140 | #define V_028A24_VGT_GRP_PRIM_INDEX_QUAD 0x0E |
||
| 7141 | #define V_028A24_VGT_GRP_3D_LINE_ADJ 0x0F |
||
| 7142 | #define V_028A24_VGT_GRP_3D_TRI_ADJ 0x10 |
||
| 7143 | #define V_028A24_VGT_GRP_3D_PATCH 0x11 |
||
| 7144 | #define S_028A24_RETAIN_ORDER(x) (((x) & 0x1) << 14) |
||
| 7145 | #define G_028A24_RETAIN_ORDER(x) (((x) >> 14) & 0x1) |
||
| 7146 | #define C_028A24_RETAIN_ORDER 0xFFFFBFFF |
||
| 7147 | #define S_028A24_RETAIN_QUADS(x) (((x) & 0x1) << 15) |
||
| 7148 | #define G_028A24_RETAIN_QUADS(x) (((x) >> 15) & 0x1) |
||
| 7149 | #define C_028A24_RETAIN_QUADS 0xFFFF7FFF |
||
| 7150 | #define S_028A24_PRIM_ORDER(x) (((x) & 0x07) << 16) |
||
| 7151 | #define G_028A24_PRIM_ORDER(x) (((x) >> 16) & 0x07) |
||
| 7152 | #define C_028A24_PRIM_ORDER 0xFFF8FFFF |
||
| 7153 | #define V_028A24_VGT_GRP_LIST 0x00 |
||
| 7154 | #define V_028A24_VGT_GRP_STRIP 0x01 |
||
| 7155 | #define V_028A24_VGT_GRP_FAN 0x02 |
||
| 7156 | #define V_028A24_VGT_GRP_LOOP 0x03 |
||
| 7157 | #define V_028A24_VGT_GRP_POLYGON 0x04 |
||
| 7158 | #define R_028A28_VGT_GROUP_FIRST_DECR 0x028A28 |
||
| 7159 | #define S_028A28_FIRST_DECR(x) (((x) & 0x0F) << 0) |
||
| 7160 | #define G_028A28_FIRST_DECR(x) (((x) >> 0) & 0x0F) |
||
| 7161 | #define C_028A28_FIRST_DECR 0xFFFFFFF0 |
||
| 7162 | #define R_028A2C_VGT_GROUP_DECR 0x028A2C |
||
| 7163 | #define S_028A2C_DECR(x) (((x) & 0x0F) << 0) |
||
| 7164 | #define G_028A2C_DECR(x) (((x) >> 0) & 0x0F) |
||
| 7165 | #define C_028A2C_DECR 0xFFFFFFF0 |
||
| 7166 | #define R_028A30_VGT_GROUP_VECT_0_CNTL 0x028A30 |
||
| 7167 | #define S_028A30_COMP_X_EN(x) (((x) & 0x1) << 0) |
||
| 7168 | #define G_028A30_COMP_X_EN(x) (((x) >> 0) & 0x1) |
||
| 7169 | #define C_028A30_COMP_X_EN 0xFFFFFFFE |
||
| 7170 | #define S_028A30_COMP_Y_EN(x) (((x) & 0x1) << 1) |
||
| 7171 | #define G_028A30_COMP_Y_EN(x) (((x) >> 1) & 0x1) |
||
| 7172 | #define C_028A30_COMP_Y_EN 0xFFFFFFFD |
||
| 7173 | #define S_028A30_COMP_Z_EN(x) (((x) & 0x1) << 2) |
||
| 7174 | #define G_028A30_COMP_Z_EN(x) (((x) >> 2) & 0x1) |
||
| 7175 | #define C_028A30_COMP_Z_EN 0xFFFFFFFB |
||
| 7176 | #define S_028A30_COMP_W_EN(x) (((x) & 0x1) << 3) |
||
| 7177 | #define G_028A30_COMP_W_EN(x) (((x) >> 3) & 0x1) |
||
| 7178 | #define C_028A30_COMP_W_EN 0xFFFFFFF7 |
||
| 7179 | #define S_028A30_STRIDE(x) (((x) & 0xFF) << 8) |
||
| 7180 | #define G_028A30_STRIDE(x) (((x) >> 8) & 0xFF) |
||
| 7181 | #define C_028A30_STRIDE 0xFFFF00FF |
||
| 7182 | #define S_028A30_SHIFT(x) (((x) & 0xFF) << 16) |
||
| 7183 | #define G_028A30_SHIFT(x) (((x) >> 16) & 0xFF) |
||
| 7184 | #define C_028A30_SHIFT 0xFF00FFFF |
||
| 7185 | #define R_028A34_VGT_GROUP_VECT_1_CNTL 0x028A34 |
||
| 7186 | #define S_028A34_COMP_X_EN(x) (((x) & 0x1) << 0) |
||
| 7187 | #define G_028A34_COMP_X_EN(x) (((x) >> 0) & 0x1) |
||
| 7188 | #define C_028A34_COMP_X_EN 0xFFFFFFFE |
||
| 7189 | #define S_028A34_COMP_Y_EN(x) (((x) & 0x1) << 1) |
||
| 7190 | #define G_028A34_COMP_Y_EN(x) (((x) >> 1) & 0x1) |
||
| 7191 | #define C_028A34_COMP_Y_EN 0xFFFFFFFD |
||
| 7192 | #define S_028A34_COMP_Z_EN(x) (((x) & 0x1) << 2) |
||
| 7193 | #define G_028A34_COMP_Z_EN(x) (((x) >> 2) & 0x1) |
||
| 7194 | #define C_028A34_COMP_Z_EN 0xFFFFFFFB |
||
| 7195 | #define S_028A34_COMP_W_EN(x) (((x) & 0x1) << 3) |
||
| 7196 | #define G_028A34_COMP_W_EN(x) (((x) >> 3) & 0x1) |
||
| 7197 | #define C_028A34_COMP_W_EN 0xFFFFFFF7 |
||
| 7198 | #define S_028A34_STRIDE(x) (((x) & 0xFF) << 8) |
||
| 7199 | #define G_028A34_STRIDE(x) (((x) >> 8) & 0xFF) |
||
| 7200 | #define C_028A34_STRIDE 0xFFFF00FF |
||
| 7201 | #define S_028A34_SHIFT(x) (((x) & 0xFF) << 16) |
||
| 7202 | #define G_028A34_SHIFT(x) (((x) >> 16) & 0xFF) |
||
| 7203 | #define C_028A34_SHIFT 0xFF00FFFF |
||
| 7204 | #define R_028A38_VGT_GROUP_VECT_0_FMT_CNTL 0x028A38 |
||
| 7205 | #define S_028A38_X_CONV(x) (((x) & 0x0F) << 0) |
||
| 7206 | #define G_028A38_X_CONV(x) (((x) >> 0) & 0x0F) |
||
| 7207 | #define C_028A38_X_CONV 0xFFFFFFF0 |
||
| 7208 | #define V_028A38_VGT_GRP_INDEX_16 0x00 |
||
| 7209 | #define V_028A38_VGT_GRP_INDEX_32 0x01 |
||
| 7210 | #define V_028A38_VGT_GRP_UINT_16 0x02 |
||
| 7211 | #define V_028A38_VGT_GRP_UINT_32 0x03 |
||
| 7212 | #define V_028A38_VGT_GRP_SINT_16 0x04 |
||
| 7213 | #define V_028A38_VGT_GRP_SINT_32 0x05 |
||
| 7214 | #define V_028A38_VGT_GRP_FLOAT_32 0x06 |
||
| 7215 | #define V_028A38_VGT_GRP_AUTO_PRIM 0x07 |
||
| 7216 | #define V_028A38_VGT_GRP_FIX_1_23_TO_FLOAT 0x08 |
||
| 7217 | #define S_028A38_X_OFFSET(x) (((x) & 0x0F) << 4) |
||
| 7218 | #define G_028A38_X_OFFSET(x) (((x) >> 4) & 0x0F) |
||
| 7219 | #define C_028A38_X_OFFSET 0xFFFFFF0F |
||
| 7220 | #define S_028A38_Y_CONV(x) (((x) & 0x0F) << 8) |
||
| 7221 | #define G_028A38_Y_CONV(x) (((x) >> 8) & 0x0F) |
||
| 7222 | #define C_028A38_Y_CONV 0xFFFFF0FF |
||
| 7223 | #define V_028A38_VGT_GRP_INDEX_16 0x00 |
||
| 7224 | #define V_028A38_VGT_GRP_INDEX_32 0x01 |
||
| 7225 | #define V_028A38_VGT_GRP_UINT_16 0x02 |
||
| 7226 | #define V_028A38_VGT_GRP_UINT_32 0x03 |
||
| 7227 | #define V_028A38_VGT_GRP_SINT_16 0x04 |
||
| 7228 | #define V_028A38_VGT_GRP_SINT_32 0x05 |
||
| 7229 | #define V_028A38_VGT_GRP_FLOAT_32 0x06 |
||
| 7230 | #define V_028A38_VGT_GRP_AUTO_PRIM 0x07 |
||
| 7231 | #define V_028A38_VGT_GRP_FIX_1_23_TO_FLOAT 0x08 |
||
| 7232 | #define S_028A38_Y_OFFSET(x) (((x) & 0x0F) << 12) |
||
| 7233 | #define G_028A38_Y_OFFSET(x) (((x) >> 12) & 0x0F) |
||
| 7234 | #define C_028A38_Y_OFFSET 0xFFFF0FFF |
||
| 7235 | #define S_028A38_Z_CONV(x) (((x) & 0x0F) << 16) |
||
| 7236 | #define G_028A38_Z_CONV(x) (((x) >> 16) & 0x0F) |
||
| 7237 | #define C_028A38_Z_CONV 0xFFF0FFFF |
||
| 7238 | #define V_028A38_VGT_GRP_INDEX_16 0x00 |
||
| 7239 | #define V_028A38_VGT_GRP_INDEX_32 0x01 |
||
| 7240 | #define V_028A38_VGT_GRP_UINT_16 0x02 |
||
| 7241 | #define V_028A38_VGT_GRP_UINT_32 0x03 |
||
| 7242 | #define V_028A38_VGT_GRP_SINT_16 0x04 |
||
| 7243 | #define V_028A38_VGT_GRP_SINT_32 0x05 |
||
| 7244 | #define V_028A38_VGT_GRP_FLOAT_32 0x06 |
||
| 7245 | #define V_028A38_VGT_GRP_AUTO_PRIM 0x07 |
||
| 7246 | #define V_028A38_VGT_GRP_FIX_1_23_TO_FLOAT 0x08 |
||
| 7247 | #define S_028A38_Z_OFFSET(x) (((x) & 0x0F) << 20) |
||
| 7248 | #define G_028A38_Z_OFFSET(x) (((x) >> 20) & 0x0F) |
||
| 7249 | #define C_028A38_Z_OFFSET 0xFF0FFFFF |
||
| 7250 | #define S_028A38_W_CONV(x) (((x) & 0x0F) << 24) |
||
| 7251 | #define G_028A38_W_CONV(x) (((x) >> 24) & 0x0F) |
||
| 7252 | #define C_028A38_W_CONV 0xF0FFFFFF |
||
| 7253 | #define V_028A38_VGT_GRP_INDEX_16 0x00 |
||
| 7254 | #define V_028A38_VGT_GRP_INDEX_32 0x01 |
||
| 7255 | #define V_028A38_VGT_GRP_UINT_16 0x02 |
||
| 7256 | #define V_028A38_VGT_GRP_UINT_32 0x03 |
||
| 7257 | #define V_028A38_VGT_GRP_SINT_16 0x04 |
||
| 7258 | #define V_028A38_VGT_GRP_SINT_32 0x05 |
||
| 7259 | #define V_028A38_VGT_GRP_FLOAT_32 0x06 |
||
| 7260 | #define V_028A38_VGT_GRP_AUTO_PRIM 0x07 |
||
| 7261 | #define V_028A38_VGT_GRP_FIX_1_23_TO_FLOAT 0x08 |
||
| 7262 | #define S_028A38_W_OFFSET(x) (((x) & 0x0F) << 28) |
||
| 7263 | #define G_028A38_W_OFFSET(x) (((x) >> 28) & 0x0F) |
||
| 7264 | #define C_028A38_W_OFFSET 0x0FFFFFFF |
||
| 7265 | #define R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL 0x028A3C |
||
| 7266 | #define S_028A3C_X_CONV(x) (((x) & 0x0F) << 0) |
||
| 7267 | #define G_028A3C_X_CONV(x) (((x) >> 0) & 0x0F) |
||
| 7268 | #define C_028A3C_X_CONV 0xFFFFFFF0 |
||
| 7269 | #define V_028A3C_VGT_GRP_INDEX_16 0x00 |
||
| 7270 | #define V_028A3C_VGT_GRP_INDEX_32 0x01 |
||
| 7271 | #define V_028A3C_VGT_GRP_UINT_16 0x02 |
||
| 7272 | #define V_028A3C_VGT_GRP_UINT_32 0x03 |
||
| 7273 | #define V_028A3C_VGT_GRP_SINT_16 0x04 |
||
| 7274 | #define V_028A3C_VGT_GRP_SINT_32 0x05 |
||
| 7275 | #define V_028A3C_VGT_GRP_FLOAT_32 0x06 |
||
| 7276 | #define V_028A3C_VGT_GRP_AUTO_PRIM 0x07 |
||
| 7277 | #define V_028A3C_VGT_GRP_FIX_1_23_TO_FLOAT 0x08 |
||
| 7278 | #define S_028A3C_X_OFFSET(x) (((x) & 0x0F) << 4) |
||
| 7279 | #define G_028A3C_X_OFFSET(x) (((x) >> 4) & 0x0F) |
||
| 7280 | #define C_028A3C_X_OFFSET 0xFFFFFF0F |
||
| 7281 | #define S_028A3C_Y_CONV(x) (((x) & 0x0F) << 8) |
||
| 7282 | #define G_028A3C_Y_CONV(x) (((x) >> 8) & 0x0F) |
||
| 7283 | #define C_028A3C_Y_CONV 0xFFFFF0FF |
||
| 7284 | #define V_028A3C_VGT_GRP_INDEX_16 0x00 |
||
| 7285 | #define V_028A3C_VGT_GRP_INDEX_32 0x01 |
||
| 7286 | #define V_028A3C_VGT_GRP_UINT_16 0x02 |
||
| 7287 | #define V_028A3C_VGT_GRP_UINT_32 0x03 |
||
| 7288 | #define V_028A3C_VGT_GRP_SINT_16 0x04 |
||
| 7289 | #define V_028A3C_VGT_GRP_SINT_32 0x05 |
||
| 7290 | #define V_028A3C_VGT_GRP_FLOAT_32 0x06 |
||
| 7291 | #define V_028A3C_VGT_GRP_AUTO_PRIM 0x07 |
||
| 7292 | #define V_028A3C_VGT_GRP_FIX_1_23_TO_FLOAT 0x08 |
||
| 7293 | #define S_028A3C_Y_OFFSET(x) (((x) & 0x0F) << 12) |
||
| 7294 | #define G_028A3C_Y_OFFSET(x) (((x) >> 12) & 0x0F) |
||
| 7295 | #define C_028A3C_Y_OFFSET 0xFFFF0FFF |
||
| 7296 | #define S_028A3C_Z_CONV(x) (((x) & 0x0F) << 16) |
||
| 7297 | #define G_028A3C_Z_CONV(x) (((x) >> 16) & 0x0F) |
||
| 7298 | #define C_028A3C_Z_CONV 0xFFF0FFFF |
||
| 7299 | #define V_028A3C_VGT_GRP_INDEX_16 0x00 |
||
| 7300 | #define V_028A3C_VGT_GRP_INDEX_32 0x01 |
||
| 7301 | #define V_028A3C_VGT_GRP_UINT_16 0x02 |
||
| 7302 | #define V_028A3C_VGT_GRP_UINT_32 0x03 |
||
| 7303 | #define V_028A3C_VGT_GRP_SINT_16 0x04 |
||
| 7304 | #define V_028A3C_VGT_GRP_SINT_32 0x05 |
||
| 7305 | #define V_028A3C_VGT_GRP_FLOAT_32 0x06 |
||
| 7306 | #define V_028A3C_VGT_GRP_AUTO_PRIM 0x07 |
||
| 7307 | #define V_028A3C_VGT_GRP_FIX_1_23_TO_FLOAT 0x08 |
||
| 7308 | #define S_028A3C_Z_OFFSET(x) (((x) & 0x0F) << 20) |
||
| 7309 | #define G_028A3C_Z_OFFSET(x) (((x) >> 20) & 0x0F) |
||
| 7310 | #define C_028A3C_Z_OFFSET 0xFF0FFFFF |
||
| 7311 | #define S_028A3C_W_CONV(x) (((x) & 0x0F) << 24) |
||
| 7312 | #define G_028A3C_W_CONV(x) (((x) >> 24) & 0x0F) |
||
| 7313 | #define C_028A3C_W_CONV 0xF0FFFFFF |
||
| 7314 | #define V_028A3C_VGT_GRP_INDEX_16 0x00 |
||
| 7315 | #define V_028A3C_VGT_GRP_INDEX_32 0x01 |
||
| 7316 | #define V_028A3C_VGT_GRP_UINT_16 0x02 |
||
| 7317 | #define V_028A3C_VGT_GRP_UINT_32 0x03 |
||
| 7318 | #define V_028A3C_VGT_GRP_SINT_16 0x04 |
||
| 7319 | #define V_028A3C_VGT_GRP_SINT_32 0x05 |
||
| 7320 | #define V_028A3C_VGT_GRP_FLOAT_32 0x06 |
||
| 7321 | #define V_028A3C_VGT_GRP_AUTO_PRIM 0x07 |
||
| 7322 | #define V_028A3C_VGT_GRP_FIX_1_23_TO_FLOAT 0x08 |
||
| 7323 | #define S_028A3C_W_OFFSET(x) (((x) & 0x0F) << 28) |
||
| 7324 | #define G_028A3C_W_OFFSET(x) (((x) >> 28) & 0x0F) |
||
| 7325 | #define C_028A3C_W_OFFSET 0x0FFFFFFF |
||
| 7326 | #define R_028A40_VGT_GS_MODE 0x028A40 |
||
| 7327 | #define S_028A40_MODE(x) (((x) & 0x07) << 0) |
||
| 7328 | #define G_028A40_MODE(x) (((x) >> 0) & 0x07) |
||
| 7329 | #define C_028A40_MODE 0xFFFFFFF8 |
||
| 7330 | #define V_028A40_GS_OFF 0x00 |
||
| 7331 | #define V_028A40_GS_SCENARIO_A 0x01 |
||
| 7332 | #define V_028A40_GS_SCENARIO_B 0x02 |
||
| 7333 | #define V_028A40_GS_SCENARIO_G 0x03 |
||
| 7334 | #define V_028A40_GS_SCENARIO_C 0x04 |
||
| 7335 | #define V_028A40_SPRITE_EN 0x05 |
||
| 7336 | #define S_028A40_CUT_MODE(x) (((x) & 0x03) << 4) |
||
| 7337 | #define G_028A40_CUT_MODE(x) (((x) >> 4) & 0x03) |
||
| 7338 | #define C_028A40_CUT_MODE 0xFFFFFFCF |
||
| 7339 | #define V_028A40_GS_CUT_1024 0x00 |
||
| 7340 | #define V_028A40_GS_CUT_512 0x01 |
||
| 7341 | #define V_028A40_GS_CUT_256 0x02 |
||
| 7342 | #define V_028A40_GS_CUT_128 0x03 |
||
| 7343 | #define S_028A40_GS_C_PACK_EN(x) (((x) & 0x1) << 11) |
||
| 7344 | #define G_028A40_GS_C_PACK_EN(x) (((x) >> 11) & 0x1) |
||
| 7345 | #define C_028A40_GS_C_PACK_EN 0xFFFFF7FF |
||
| 7346 | #define S_028A40_ES_PASSTHRU(x) (((x) & 0x1) << 13) |
||
| 7347 | #define G_028A40_ES_PASSTHRU(x) (((x) >> 13) & 0x1) |
||
| 7348 | #define C_028A40_ES_PASSTHRU 0xFFFFDFFF |
||
| 7349 | #define S_028A40_COMPUTE_MODE(x) (((x) & 0x1) << 14) |
||
| 7350 | #define G_028A40_COMPUTE_MODE(x) (((x) >> 14) & 0x1) |
||
| 7351 | #define C_028A40_COMPUTE_MODE 0xFFFFBFFF |
||
| 7352 | #define S_028A40_FAST_COMPUTE_MODE(x) (((x) & 0x1) << 15) |
||
| 7353 | #define G_028A40_FAST_COMPUTE_MODE(x) (((x) >> 15) & 0x1) |
||
| 7354 | #define C_028A40_FAST_COMPUTE_MODE 0xFFFF7FFF |
||
| 7355 | #define S_028A40_ELEMENT_INFO_EN(x) (((x) & 0x1) << 16) |
||
| 7356 | #define G_028A40_ELEMENT_INFO_EN(x) (((x) >> 16) & 0x1) |
||
| 7357 | #define C_028A40_ELEMENT_INFO_EN 0xFFFEFFFF |
||
| 7358 | #define S_028A40_PARTIAL_THD_AT_EOI(x) (((x) & 0x1) << 17) |
||
| 7359 | #define G_028A40_PARTIAL_THD_AT_EOI(x) (((x) >> 17) & 0x1) |
||
| 7360 | #define C_028A40_PARTIAL_THD_AT_EOI 0xFFFDFFFF |
||
| 7361 | #define S_028A40_SUPPRESS_CUTS(x) (((x) & 0x1) << 18) |
||
| 7362 | #define G_028A40_SUPPRESS_CUTS(x) (((x) >> 18) & 0x1) |
||
| 7363 | #define C_028A40_SUPPRESS_CUTS 0xFFFBFFFF |
||
| 7364 | #define S_028A40_ES_WRITE_OPTIMIZE(x) (((x) & 0x1) << 19) |
||
| 7365 | #define G_028A40_ES_WRITE_OPTIMIZE(x) (((x) >> 19) & 0x1) |
||
| 7366 | #define C_028A40_ES_WRITE_OPTIMIZE 0xFFF7FFFF |
||
| 7367 | #define S_028A40_GS_WRITE_OPTIMIZE(x) (((x) & 0x1) << 20) |
||
| 7368 | #define G_028A40_GS_WRITE_OPTIMIZE(x) (((x) >> 20) & 0x1) |
||
| 7369 | #define C_028A40_GS_WRITE_OPTIMIZE 0xFFEFFFFF |
||
| 7370 | /* CIK */ |
||
| 7371 | #define S_028A40_ONCHIP(x) (((x) & 0x03) << 21) |
||
| 7372 | #define G_028A40_ONCHIP(x) (((x) >> 21) & 0x03) |
||
| 7373 | #define C_028A40_ONCHIP 0xFF9FFFFF |
||
| 7374 | #define V_028A40_X_0_OFFCHIP_GS 0x00 |
||
| 7375 | #define V_028A40_X_3_ES_AND_GS_ARE_ONCHIP 0x03 |
||
| 7376 | #define R_028A44_VGT_GS_ONCHIP_CNTL 0x028A44 |
||
| 7377 | #define S_028A44_ES_VERTS_PER_SUBGRP(x) (((x) & 0x7FF) << 0) |
||
| 7378 | #define G_028A44_ES_VERTS_PER_SUBGRP(x) (((x) >> 0) & 0x7FF) |
||
| 7379 | #define C_028A44_ES_VERTS_PER_SUBGRP 0xFFFFF800 |
||
| 7380 | #define S_028A44_GS_PRIMS_PER_SUBGRP(x) (((x) & 0x7FF) << 11) |
||
| 7381 | #define G_028A44_GS_PRIMS_PER_SUBGRP(x) (((x) >> 11) & 0x7FF) |
||
| 7382 | #define C_028A44_GS_PRIMS_PER_SUBGRP 0xFFC007FF |
||
| 7383 | /* */ |
||
| 7384 | #define R_028A48_PA_SC_MODE_CNTL_0 0x028A48 |
||
| 7385 | #define S_028A48_MSAA_ENABLE(x) (((x) & 0x1) << 0) |
||
| 7386 | #define G_028A48_MSAA_ENABLE(x) (((x) >> 0) & 0x1) |
||
| 7387 | #define C_028A48_MSAA_ENABLE 0xFFFFFFFE |
||
| 7388 | #define S_028A48_VPORT_SCISSOR_ENABLE(x) (((x) & 0x1) << 1) |
||
| 7389 | #define G_028A48_VPORT_SCISSOR_ENABLE(x) (((x) >> 1) & 0x1) |
||
| 7390 | #define C_028A48_VPORT_SCISSOR_ENABLE 0xFFFFFFFD |
||
| 7391 | #define S_028A48_LINE_STIPPLE_ENABLE(x) (((x) & 0x1) << 2) |
||
| 7392 | #define G_028A48_LINE_STIPPLE_ENABLE(x) (((x) >> 2) & 0x1) |
||
| 7393 | #define C_028A48_LINE_STIPPLE_ENABLE 0xFFFFFFFB |
||
| 7394 | #define S_028A48_SEND_UNLIT_STILES_TO_PKR(x) (((x) & 0x1) << 3) |
||
| 7395 | #define G_028A48_SEND_UNLIT_STILES_TO_PKR(x) (((x) >> 3) & 0x1) |
||
| 7396 | #define C_028A48_SEND_UNLIT_STILES_TO_PKR 0xFFFFFFF7 |
||
| 7397 | #define R_028A4C_PA_SC_MODE_CNTL_1 0x028A4C |
||
| 7398 | #define S_028A4C_WALK_SIZE(x) (((x) & 0x1) << 0) |
||
| 7399 | #define G_028A4C_WALK_SIZE(x) (((x) >> 0) & 0x1) |
||
| 7400 | #define C_028A4C_WALK_SIZE 0xFFFFFFFE |
||
| 7401 | #define S_028A4C_WALK_ALIGNMENT(x) (((x) & 0x1) << 1) |
||
| 7402 | #define G_028A4C_WALK_ALIGNMENT(x) (((x) >> 1) & 0x1) |
||
| 7403 | #define C_028A4C_WALK_ALIGNMENT 0xFFFFFFFD |
||
| 7404 | #define S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(x) (((x) & 0x1) << 2) |
||
| 7405 | #define G_028A4C_WALK_ALIGN8_PRIM_FITS_ST(x) (((x) >> 2) & 0x1) |
||
| 7406 | #define C_028A4C_WALK_ALIGN8_PRIM_FITS_ST 0xFFFFFFFB |
||
| 7407 | #define S_028A4C_WALK_FENCE_ENABLE(x) (((x) & 0x1) << 3) |
||
| 7408 | #define G_028A4C_WALK_FENCE_ENABLE(x) (((x) >> 3) & 0x1) |
||
| 7409 | #define C_028A4C_WALK_FENCE_ENABLE 0xFFFFFFF7 |
||
| 7410 | #define S_028A4C_WALK_FENCE_SIZE(x) (((x) & 0x07) << 4) |
||
| 7411 | #define G_028A4C_WALK_FENCE_SIZE(x) (((x) >> 4) & 0x07) |
||
| 7412 | #define C_028A4C_WALK_FENCE_SIZE 0xFFFFFF8F |
||
| 7413 | #define S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(x) (((x) & 0x1) << 7) |
||
| 7414 | #define G_028A4C_SUPERTILE_WALK_ORDER_ENABLE(x) (((x) >> 7) & 0x1) |
||
| 7415 | #define C_028A4C_SUPERTILE_WALK_ORDER_ENABLE 0xFFFFFF7F |
||
| 7416 | #define S_028A4C_TILE_WALK_ORDER_ENABLE(x) (((x) & 0x1) << 8) |
||
| 7417 | #define G_028A4C_TILE_WALK_ORDER_ENABLE(x) (((x) >> 8) & 0x1) |
||
| 7418 | #define C_028A4C_TILE_WALK_ORDER_ENABLE 0xFFFFFEFF |
||
| 7419 | #define S_028A4C_TILE_COVER_DISABLE(x) (((x) & 0x1) << 9) |
||
| 7420 | #define G_028A4C_TILE_COVER_DISABLE(x) (((x) >> 9) & 0x1) |
||
| 7421 | #define C_028A4C_TILE_COVER_DISABLE 0xFFFFFDFF |
||
| 7422 | #define S_028A4C_TILE_COVER_NO_SCISSOR(x) (((x) & 0x1) << 10) |
||
| 7423 | #define G_028A4C_TILE_COVER_NO_SCISSOR(x) (((x) >> 10) & 0x1) |
||
| 7424 | #define C_028A4C_TILE_COVER_NO_SCISSOR 0xFFFFFBFF |
||
| 7425 | #define S_028A4C_ZMM_LINE_EXTENT(x) (((x) & 0x1) << 11) |
||
| 7426 | #define G_028A4C_ZMM_LINE_EXTENT(x) (((x) >> 11) & 0x1) |
||
| 7427 | #define C_028A4C_ZMM_LINE_EXTENT 0xFFFFF7FF |
||
| 7428 | #define S_028A4C_ZMM_LINE_OFFSET(x) (((x) & 0x1) << 12) |
||
| 7429 | #define G_028A4C_ZMM_LINE_OFFSET(x) (((x) >> 12) & 0x1) |
||
| 7430 | #define C_028A4C_ZMM_LINE_OFFSET 0xFFFFEFFF |
||
| 7431 | #define S_028A4C_ZMM_RECT_EXTENT(x) (((x) & 0x1) << 13) |
||
| 7432 | #define G_028A4C_ZMM_RECT_EXTENT(x) (((x) >> 13) & 0x1) |
||
| 7433 | #define C_028A4C_ZMM_RECT_EXTENT 0xFFFFDFFF |
||
| 7434 | #define S_028A4C_KILL_PIX_POST_HI_Z(x) (((x) & 0x1) << 14) |
||
| 7435 | #define G_028A4C_KILL_PIX_POST_HI_Z(x) (((x) >> 14) & 0x1) |
||
| 7436 | #define C_028A4C_KILL_PIX_POST_HI_Z 0xFFFFBFFF |
||
| 7437 | #define S_028A4C_KILL_PIX_POST_DETAIL_MASK(x) (((x) & 0x1) << 15) |
||
| 7438 | #define G_028A4C_KILL_PIX_POST_DETAIL_MASK(x) (((x) >> 15) & 0x1) |
||
| 7439 | #define C_028A4C_KILL_PIX_POST_DETAIL_MASK 0xFFFF7FFF |
||
| 7440 | #define S_028A4C_PS_ITER_SAMPLE(x) (((x) & 0x1) << 16) |
||
| 7441 | #define G_028A4C_PS_ITER_SAMPLE(x) (((x) >> 16) & 0x1) |
||
| 7442 | #define C_028A4C_PS_ITER_SAMPLE 0xFFFEFFFF |
||
| 7443 | #define S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISC(x) (((x) & 0x1) << 17) |
||
| 7444 | #define G_028A4C_MULTI_SHADER_ENGINE_PRIM_DISC(x) (((x) >> 17) & 0x1) |
||
| 7445 | #define C_028A4C_MULTI_SHADER_ENGINE_PRIM_DISC 0xFFFDFFFF |
||
| 7446 | #define S_028A4C_FORCE_EOV_CNTDWN_ENABLE(x) (((x) & 0x1) << 25) |
||
| 7447 | #define G_028A4C_FORCE_EOV_CNTDWN_ENABLE(x) (((x) >> 25) & 0x1) |
||
| 7448 | #define C_028A4C_FORCE_EOV_CNTDWN_ENABLE 0xFDFFFFFF |
||
| 7449 | #define S_028A4C_FORCE_EOV_REZ_ENABLE(x) (((x) & 0x1) << 26) |
||
| 7450 | #define G_028A4C_FORCE_EOV_REZ_ENABLE(x) (((x) >> 26) & 0x1) |
||
| 7451 | #define C_028A4C_FORCE_EOV_REZ_ENABLE 0xFBFFFFFF |
||
| 7452 | #define S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(x) (((x) & 0x1) << 27) |
||
| 7453 | #define G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(x) (((x) >> 27) & 0x1) |
||
| 7454 | #define C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE 0xF7FFFFFF |
||
| 7455 | #define S_028A4C_OUT_OF_ORDER_WATER_MARK(x) (((x) & 0x07) << 28) |
||
| 7456 | #define G_028A4C_OUT_OF_ORDER_WATER_MARK(x) (((x) >> 28) & 0x07) |
||
| 7457 | #define C_028A4C_OUT_OF_ORDER_WATER_MARK 0x8FFFFFFF |
||
| 7458 | #define R_028A50_VGT_ENHANCE 0x028A50 |
||
| 7459 | #define R_028A54_VGT_GS_PER_ES 0x028A54 |
||
| 7460 | #define S_028A54_GS_PER_ES(x) (((x) & 0x7FF) << 0) |
||
| 7461 | #define G_028A54_GS_PER_ES(x) (((x) >> 0) & 0x7FF) |
||
| 7462 | #define C_028A54_GS_PER_ES 0xFFFFF800 |
||
| 7463 | #define R_028A58_VGT_ES_PER_GS 0x028A58 |
||
| 7464 | #define S_028A58_ES_PER_GS(x) (((x) & 0x7FF) << 0) |
||
| 7465 | #define G_028A58_ES_PER_GS(x) (((x) >> 0) & 0x7FF) |
||
| 7466 | #define C_028A58_ES_PER_GS 0xFFFFF800 |
||
| 7467 | #define R_028A5C_VGT_GS_PER_VS 0x028A5C |
||
| 7468 | #define S_028A5C_GS_PER_VS(x) (((x) & 0x0F) << 0) |
||
| 7469 | #define G_028A5C_GS_PER_VS(x) (((x) >> 0) & 0x0F) |
||
| 7470 | #define C_028A5C_GS_PER_VS 0xFFFFFFF0 |
||
| 7471 | #define R_028A60_VGT_GSVS_RING_OFFSET_1 0x028A60 |
||
| 7472 | #define S_028A60_OFFSET(x) (((x) & 0x7FFF) << 0) |
||
| 7473 | #define G_028A60_OFFSET(x) (((x) >> 0) & 0x7FFF) |
||
| 7474 | #define C_028A60_OFFSET 0xFFFF8000 |
||
| 7475 | #define R_028A64_VGT_GSVS_RING_OFFSET_2 0x028A64 |
||
| 7476 | #define S_028A64_OFFSET(x) (((x) & 0x7FFF) << 0) |
||
| 7477 | #define G_028A64_OFFSET(x) (((x) >> 0) & 0x7FFF) |
||
| 7478 | #define C_028A64_OFFSET 0xFFFF8000 |
||
| 7479 | #define R_028A68_VGT_GSVS_RING_OFFSET_3 0x028A68 |
||
| 7480 | #define S_028A68_OFFSET(x) (((x) & 0x7FFF) << 0) |
||
| 7481 | #define G_028A68_OFFSET(x) (((x) >> 0) & 0x7FFF) |
||
| 7482 | #define C_028A68_OFFSET 0xFFFF8000 |
||
| 7483 | #define R_028A6C_VGT_GS_OUT_PRIM_TYPE 0x028A6C |
||
| 7484 | #define S_028A6C_OUTPRIM_TYPE(x) (((x) & 0x3F) << 0) |
||
| 7485 | #define G_028A6C_OUTPRIM_TYPE(x) (((x) >> 0) & 0x3F) |
||
| 7486 | #define C_028A6C_OUTPRIM_TYPE 0xFFFFFFC0 |
||
| 7487 | #define V_028A6C_OUTPRIM_TYPE_POINTLIST 0 |
||
| 7488 | #define V_028A6C_OUTPRIM_TYPE_LINESTRIP 1 |
||
| 7489 | #define V_028A6C_OUTPRIM_TYPE_TRISTRIP 2 |
||
| 7490 | #define S_028A6C_OUTPRIM_TYPE_1(x) (((x) & 0x3F) << 8) |
||
| 7491 | #define G_028A6C_OUTPRIM_TYPE_1(x) (((x) >> 8) & 0x3F) |
||
| 7492 | #define C_028A6C_OUTPRIM_TYPE_1 0xFFFFC0FF |
||
| 7493 | #define S_028A6C_OUTPRIM_TYPE_2(x) (((x) & 0x3F) << 16) |
||
| 7494 | #define G_028A6C_OUTPRIM_TYPE_2(x) (((x) >> 16) & 0x3F) |
||
| 7495 | #define C_028A6C_OUTPRIM_TYPE_2 0xFFC0FFFF |
||
| 7496 | #define S_028A6C_OUTPRIM_TYPE_3(x) (((x) & 0x3F) << 22) |
||
| 7497 | #define G_028A6C_OUTPRIM_TYPE_3(x) (((x) >> 22) & 0x3F) |
||
| 7498 | #define C_028A6C_OUTPRIM_TYPE_3 0xF03FFFFF |
||
| 7499 | #define S_028A6C_UNIQUE_TYPE_PER_STREAM(x) (((x) & 0x1) << 31) |
||
| 7500 | #define G_028A6C_UNIQUE_TYPE_PER_STREAM(x) (((x) >> 31) & 0x1) |
||
| 7501 | #define C_028A6C_UNIQUE_TYPE_PER_STREAM 0x7FFFFFFF |
||
| 7502 | #define R_028A70_IA_ENHANCE 0x028A70 |
||
| 7503 | #define R_028A74_VGT_DMA_SIZE 0x028A74 |
||
| 7504 | #define R_028A78_VGT_DMA_MAX_SIZE 0x028A78 |
||
| 7505 | #define R_028A7C_VGT_DMA_INDEX_TYPE 0x028A7C |
||
| 7506 | #define S_028A7C_INDEX_TYPE(x) (((x) & 0x03) << 0) |
||
| 7507 | #define G_028A7C_INDEX_TYPE(x) (((x) >> 0) & 0x03) |
||
| 7508 | #define C_028A7C_INDEX_TYPE 0xFFFFFFFC |
||
| 7509 | #define V_028A7C_VGT_INDEX_16 0x00 |
||
| 7510 | #define V_028A7C_VGT_INDEX_32 0x01 |
||
| 7511 | #define S_028A7C_SWAP_MODE(x) (((x) & 0x03) << 2) |
||
| 7512 | #define G_028A7C_SWAP_MODE(x) (((x) >> 2) & 0x03) |
||
| 7513 | #define C_028A7C_SWAP_MODE 0xFFFFFFF3 |
||
| 7514 | #define V_028A7C_VGT_DMA_SWAP_NONE 0x00 |
||
| 7515 | #define V_028A7C_VGT_DMA_SWAP_16_BIT 0x01 |
||
| 7516 | #define V_028A7C_VGT_DMA_SWAP_32_BIT 0x02 |
||
| 7517 | #define V_028A7C_VGT_DMA_SWAP_WORD 0x03 |
||
| 7518 | /* CIK */ |
||
| 7519 | #define S_028A7C_BUF_TYPE(x) (((x) & 0x03) << 4) |
||
| 7520 | #define G_028A7C_BUF_TYPE(x) (((x) >> 4) & 0x03) |
||
| 7521 | #define C_028A7C_BUF_TYPE 0xFFFFFFCF |
||
| 7522 | #define V_028A7C_VGT_DMA_BUF_MEM 0x00 |
||
| 7523 | #define V_028A7C_VGT_DMA_BUF_RING 0x01 |
||
| 7524 | #define V_028A7C_VGT_DMA_BUF_SETUP 0x02 |
||
| 7525 | #define S_028A7C_RDREQ_POLICY(x) (((x) & 0x03) << 6) |
||
| 7526 | #define G_028A7C_RDREQ_POLICY(x) (((x) >> 6) & 0x03) |
||
| 7527 | #define C_028A7C_RDREQ_POLICY 0xFFFFFF3F |
||
| 7528 | #define V_028A7C_VGT_POLICY_LRU 0x00 |
||
| 7529 | #define V_028A7C_VGT_POLICY_STREAM 0x01 |
||
| 7530 | #define S_028A7C_ATC(x) (((x) & 0x1) << 8) |
||
| 7531 | #define G_028A7C_ATC(x) (((x) >> 8) & 0x1) |
||
| 7532 | #define C_028A7C_ATC 0xFFFFFEFF |
||
| 7533 | #define S_028A7C_NOT_EOP(x) (((x) & 0x1) << 9) |
||
| 7534 | #define G_028A7C_NOT_EOP(x) (((x) >> 9) & 0x1) |
||
| 7535 | #define C_028A7C_NOT_EOP 0xFFFFFDFF |
||
| 7536 | #define S_028A7C_REQ_PATH(x) (((x) & 0x1) << 10) |
||
| 7537 | #define G_028A7C_REQ_PATH(x) (((x) >> 10) & 0x1) |
||
| 7538 | #define C_028A7C_REQ_PATH 0xFFFFFBFF |
||
| 7539 | /* */ |
||
| 7540 | #define R_028A84_VGT_PRIMITIVEID_EN 0x028A84 |
||
| 7541 | #define S_028A84_PRIMITIVEID_EN(x) (((x) & 0x1) << 0) |
||
| 7542 | #define G_028A84_PRIMITIVEID_EN(x) (((x) >> 0) & 0x1) |
||
| 7543 | #define C_028A84_PRIMITIVEID_EN 0xFFFFFFFE |
||
| 7544 | #define S_028A84_DISABLE_RESET_ON_EOI(x) (((x) & 0x1) << 1) /* not on CIK */ |
||
| 7545 | #define G_028A84_DISABLE_RESET_ON_EOI(x) (((x) >> 1) & 0x1) /* not on CIK */ |
||
| 7546 | #define C_028A84_DISABLE_RESET_ON_EOI 0xFFFFFFFD /* not on CIK */ |
||
| 7547 | #define R_028A88_VGT_DMA_NUM_INSTANCES 0x028A88 |
||
| 7548 | #define R_028A8C_VGT_PRIMITIVEID_RESET 0x028A8C |
||
| 7549 | #define R_028A90_VGT_EVENT_INITIATOR 0x028A90 |
||
| 7550 | #define S_028A90_EVENT_TYPE(x) (((x) & 0x3F) << 0) |
||
| 7551 | #define G_028A90_EVENT_TYPE(x) (((x) >> 0) & 0x3F) |
||
| 7552 | #define C_028A90_EVENT_TYPE 0xFFFFFFC0 |
||
| 7553 | #define V_028A90_SAMPLE_STREAMOUTSTATS1 0x01 |
||
| 7554 | #define V_028A90_SAMPLE_STREAMOUTSTATS2 0x02 |
||
| 7555 | #define V_028A90_SAMPLE_STREAMOUTSTATS3 0x03 |
||
| 7556 | #define V_028A90_CACHE_FLUSH_TS 0x04 |
||
| 7557 | #define V_028A90_CONTEXT_DONE 0x05 |
||
| 7558 | #define V_028A90_CACHE_FLUSH 0x06 |
||
| 7559 | #define V_028A90_CS_PARTIAL_FLUSH 0x07 |
||
| 7560 | #define V_028A90_VGT_STREAMOUT_SYNC 0x08 |
||
| 7561 | #define V_028A90_VGT_STREAMOUT_RESET 0x0A |
||
| 7562 | #define V_028A90_END_OF_PIPE_INCR_DE 0x0B |
||
| 7563 | #define V_028A90_END_OF_PIPE_IB_END 0x0C |
||
| 7564 | #define V_028A90_RST_PIX_CNT 0x0D |
||
| 7565 | #define V_028A90_VS_PARTIAL_FLUSH 0x0F |
||
| 7566 | #define V_028A90_PS_PARTIAL_FLUSH 0x10 |
||
| 7567 | #define V_028A90_FLUSH_HS_OUTPUT 0x11 |
||
| 7568 | #define V_028A90_FLUSH_LS_OUTPUT 0x12 |
||
| 7569 | #define V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT 0x14 |
||
| 7570 | #define V_028A90_ZPASS_DONE 0x15 /* not on CIK */ |
||
| 7571 | #define V_028A90_CACHE_FLUSH_AND_INV_EVENT 0x16 |
||
| 7572 | #define V_028A90_PERFCOUNTER_START 0x17 |
||
| 7573 | #define V_028A90_PERFCOUNTER_STOP 0x18 |
||
| 7574 | #define V_028A90_PIPELINESTAT_START 0x19 |
||
| 7575 | #define V_028A90_PIPELINESTAT_STOP 0x1A |
||
| 7576 | #define V_028A90_PERFCOUNTER_SAMPLE 0x1B |
||
| 7577 | #define V_028A90_FLUSH_ES_OUTPUT 0x1C |
||
| 7578 | #define V_028A90_FLUSH_GS_OUTPUT 0x1D |
||
| 7579 | #define V_028A90_SAMPLE_PIPELINESTAT 0x1E |
||
| 7580 | #define V_028A90_SO_VGTSTREAMOUT_FLUSH 0x1F |
||
| 7581 | #define V_028A90_SAMPLE_STREAMOUTSTATS 0x20 |
||
| 7582 | #define V_028A90_RESET_VTX_CNT 0x21 |
||
| 7583 | #define V_028A90_BLOCK_CONTEXT_DONE 0x22 |
||
| 7584 | #define V_028A90_CS_CONTEXT_DONE 0x23 |
||
| 7585 | #define V_028A90_VGT_FLUSH 0x24 |
||
| 7586 | #define V_028A90_SC_SEND_DB_VPZ 0x27 |
||
| 7587 | #define V_028A90_BOTTOM_OF_PIPE_TS 0x28 |
||
| 7588 | #define V_028A90_DB_CACHE_FLUSH_AND_INV 0x2A |
||
| 7589 | #define V_028A90_FLUSH_AND_INV_DB_DATA_TS 0x2B |
||
| 7590 | #define V_028A90_FLUSH_AND_INV_DB_META 0x2C |
||
| 7591 | #define V_028A90_FLUSH_AND_INV_CB_DATA_TS 0x2D |
||
| 7592 | #define V_028A90_FLUSH_AND_INV_CB_META 0x2E |
||
| 7593 | #define V_028A90_CS_DONE 0x2F |
||
| 7594 | #define V_028A90_PS_DONE 0x30 |
||
| 7595 | #define V_028A90_FLUSH_AND_INV_CB_PIXEL_DATA 0x31 |
||
| 7596 | #define V_028A90_THREAD_TRACE_START 0x33 |
||
| 7597 | #define V_028A90_THREAD_TRACE_STOP 0x34 |
||
| 7598 | #define V_028A90_THREAD_TRACE_MARKER 0x35 |
||
| 7599 | #define V_028A90_THREAD_TRACE_FLUSH 0x36 |
||
| 7600 | #define V_028A90_THREAD_TRACE_FINISH 0x37 |
||
| 7601 | /* CIK */ |
||
| 7602 | #define V_028A90_PIXEL_PIPE_STAT_CONTROL 0x38 |
||
| 7603 | #define V_028A90_PIXEL_PIPE_STAT_DUMP 0x39 |
||
| 7604 | #define V_028A90_PIXEL_PIPE_STAT_RESET 0x40 |
||
| 7605 | /* */ |
||
| 7606 | #define S_028A90_ADDRESS_HI(x) (((x) & 0x1FF) << 18) |
||
| 7607 | #define G_028A90_ADDRESS_HI(x) (((x) >> 18) & 0x1FF) |
||
| 7608 | #define C_028A90_ADDRESS_HI 0xF803FFFF |
||
| 7609 | #define S_028A90_EXTENDED_EVENT(x) (((x) & 0x1) << 27) |
||
| 7610 | #define G_028A90_EXTENDED_EVENT(x) (((x) >> 27) & 0x1) |
||
| 7611 | #define C_028A90_EXTENDED_EVENT 0xF7FFFFFF |
||
| 7612 | #define R_028A94_VGT_MULTI_PRIM_IB_RESET_EN 0x028A94 |
||
| 7613 | #define S_028A94_RESET_EN(x) (((x) & 0x1) << 0) |
||
| 7614 | #define G_028A94_RESET_EN(x) (((x) >> 0) & 0x1) |
||
| 7615 | #define C_028A94_RESET_EN 0xFFFFFFFE |
||
| 7616 | #define R_028AA0_VGT_INSTANCE_STEP_RATE_0 0x028AA0 |
||
| 7617 | #define R_028AA4_VGT_INSTANCE_STEP_RATE_1 0x028AA4 |
||
| 7618 | #define R_028AA8_IA_MULTI_VGT_PARAM 0x028AA8 |
||
| 7619 | #define S_028AA8_PRIMGROUP_SIZE(x) (((x) & 0xFFFF) << 0) |
||
| 7620 | #define G_028AA8_PRIMGROUP_SIZE(x) (((x) >> 0) & 0xFFFF) |
||
| 7621 | #define C_028AA8_PRIMGROUP_SIZE 0xFFFF0000 |
||
| 7622 | #define S_028AA8_PARTIAL_VS_WAVE_ON(x) (((x) & 0x1) << 16) |
||
| 7623 | #define G_028AA8_PARTIAL_VS_WAVE_ON(x) (((x) >> 16) & 0x1) |
||
| 7624 | #define C_028AA8_PARTIAL_VS_WAVE_ON 0xFFFEFFFF |
||
| 7625 | #define S_028AA8_SWITCH_ON_EOP(x) (((x) & 0x1) << 17) |
||
| 7626 | #define G_028AA8_SWITCH_ON_EOP(x) (((x) >> 17) & 0x1) |
||
| 7627 | #define C_028AA8_SWITCH_ON_EOP 0xFFFDFFFF |
||
| 7628 | #define S_028AA8_PARTIAL_ES_WAVE_ON(x) (((x) & 0x1) << 18) |
||
| 7629 | #define G_028AA8_PARTIAL_ES_WAVE_ON(x) (((x) >> 18) & 0x1) |
||
| 7630 | #define C_028AA8_PARTIAL_ES_WAVE_ON 0xFFFBFFFF |
||
| 7631 | #define S_028AA8_SWITCH_ON_EOI(x) (((x) & 0x1) << 19) |
||
| 7632 | #define G_028AA8_SWITCH_ON_EOI(x) (((x) >> 19) & 0x1) |
||
| 7633 | #define C_028AA8_SWITCH_ON_EOI 0xFFF7FFFF |
||
| 7634 | /* CIK */ |
||
| 7635 | #define S_028AA8_WD_SWITCH_ON_EOP(x) (((x) & 0x1) << 20) |
||
| 7636 | #define G_028AA8_WD_SWITCH_ON_EOP(x) (((x) >> 20) & 0x1) |
||
| 7637 | #define C_028AA8_WD_SWITCH_ON_EOP 0xFFEFFFFF |
||
| 7638 | /* */ |
||
| 7639 | #define R_028AAC_VGT_ESGS_RING_ITEMSIZE 0x028AAC |
||
| 7640 | #define S_028AAC_ITEMSIZE(x) (((x) & 0x7FFF) << 0) |
||
| 7641 | #define G_028AAC_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) |
||
| 7642 | #define C_028AAC_ITEMSIZE 0xFFFF8000 |
||
| 7643 | #define R_028AB0_VGT_GSVS_RING_ITEMSIZE 0x028AB0 |
||
| 7644 | #define S_028AB0_ITEMSIZE(x) (((x) & 0x7FFF) << 0) |
||
| 7645 | #define G_028AB0_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) |
||
| 7646 | #define C_028AB0_ITEMSIZE 0xFFFF8000 |
||
| 7647 | #define R_028AB4_VGT_REUSE_OFF 0x028AB4 |
||
| 7648 | #define S_028AB4_REUSE_OFF(x) (((x) & 0x1) << 0) |
||
| 7649 | #define G_028AB4_REUSE_OFF(x) (((x) >> 0) & 0x1) |
||
| 7650 | #define C_028AB4_REUSE_OFF 0xFFFFFFFE |
||
| 7651 | #define R_028AB8_VGT_VTX_CNT_EN 0x028AB8 |
||
| 7652 | #define S_028AB8_VTX_CNT_EN(x) (((x) & 0x1) << 0) |
||
| 7653 | #define G_028AB8_VTX_CNT_EN(x) (((x) >> 0) & 0x1) |
||
| 7654 | #define C_028AB8_VTX_CNT_EN 0xFFFFFFFE |
||
| 7655 | #define R_028ABC_DB_HTILE_SURFACE 0x028ABC |
||
| 7656 | #define S_028ABC_LINEAR(x) (((x) & 0x1) << 0) |
||
| 7657 | #define G_028ABC_LINEAR(x) (((x) >> 0) & 0x1) |
||
| 7658 | #define C_028ABC_LINEAR 0xFFFFFFFE |
||
| 7659 | #define S_028ABC_FULL_CACHE(x) (((x) & 0x1) << 1) |
||
| 7660 | #define G_028ABC_FULL_CACHE(x) (((x) >> 1) & 0x1) |
||
| 7661 | #define C_028ABC_FULL_CACHE 0xFFFFFFFD |
||
| 7662 | #define S_028ABC_HTILE_USES_PRELOAD_WIN(x) (((x) & 0x1) << 2) |
||
| 7663 | #define G_028ABC_HTILE_USES_PRELOAD_WIN(x) (((x) >> 2) & 0x1) |
||
| 7664 | #define C_028ABC_HTILE_USES_PRELOAD_WIN 0xFFFFFFFB |
||
| 7665 | #define S_028ABC_PRELOAD(x) (((x) & 0x1) << 3) |
||
| 7666 | #define G_028ABC_PRELOAD(x) (((x) >> 3) & 0x1) |
||
| 7667 | #define C_028ABC_PRELOAD 0xFFFFFFF7 |
||
| 7668 | #define S_028ABC_PREFETCH_WIDTH(x) (((x) & 0x3F) << 4) |
||
| 7669 | #define G_028ABC_PREFETCH_WIDTH(x) (((x) >> 4) & 0x3F) |
||
| 7670 | #define C_028ABC_PREFETCH_WIDTH 0xFFFFFC0F |
||
| 7671 | #define S_028ABC_PREFETCH_HEIGHT(x) (((x) & 0x3F) << 10) |
||
| 7672 | #define G_028ABC_PREFETCH_HEIGHT(x) (((x) >> 10) & 0x3F) |
||
| 7673 | #define C_028ABC_PREFETCH_HEIGHT 0xFFFF03FF |
||
| 7674 | #define S_028ABC_DST_OUTSIDE_ZERO_TO_ONE(x) (((x) & 0x1) << 16) |
||
| 7675 | #define G_028ABC_DST_OUTSIDE_ZERO_TO_ONE(x) (((x) >> 16) & 0x1) |
||
| 7676 | #define C_028ABC_DST_OUTSIDE_ZERO_TO_ONE 0xFFFEFFFF |
||
| 7677 | #define R_028AC0_DB_SRESULTS_COMPARE_STATE0 0x028AC0 |
||
| 7678 | #define S_028AC0_COMPAREFUNC0(x) (((x) & 0x07) << 0) |
||
| 7679 | #define G_028AC0_COMPAREFUNC0(x) (((x) >> 0) & 0x07) |
||
| 7680 | #define C_028AC0_COMPAREFUNC0 0xFFFFFFF8 |
||
| 7681 | #define V_028AC0_REF_NEVER 0x00 |
||
| 7682 | #define V_028AC0_REF_LESS 0x01 |
||
| 7683 | #define V_028AC0_REF_EQUAL 0x02 |
||
| 7684 | #define V_028AC0_REF_LEQUAL 0x03 |
||
| 7685 | #define V_028AC0_REF_GREATER 0x04 |
||
| 7686 | #define V_028AC0_REF_NOTEQUAL 0x05 |
||
| 7687 | #define V_028AC0_REF_GEQUAL 0x06 |
||
| 7688 | #define V_028AC0_REF_ALWAYS 0x07 |
||
| 7689 | #define S_028AC0_COMPAREVALUE0(x) (((x) & 0xFF) << 4) |
||
| 7690 | #define G_028AC0_COMPAREVALUE0(x) (((x) >> 4) & 0xFF) |
||
| 7691 | #define C_028AC0_COMPAREVALUE0 0xFFFFF00F |
||
| 7692 | #define S_028AC0_COMPAREMASK0(x) (((x) & 0xFF) << 12) |
||
| 7693 | #define G_028AC0_COMPAREMASK0(x) (((x) >> 12) & 0xFF) |
||
| 7694 | #define C_028AC0_COMPAREMASK0 0xFFF00FFF |
||
| 7695 | #define S_028AC0_ENABLE0(x) (((x) & 0x1) << 24) |
||
| 7696 | #define G_028AC0_ENABLE0(x) (((x) >> 24) & 0x1) |
||
| 7697 | #define C_028AC0_ENABLE0 0xFEFFFFFF |
||
| 7698 | #define R_028AC4_DB_SRESULTS_COMPARE_STATE1 0x028AC4 |
||
| 7699 | #define S_028AC4_COMPAREFUNC1(x) (((x) & 0x07) << 0) |
||
| 7700 | #define G_028AC4_COMPAREFUNC1(x) (((x) >> 0) & 0x07) |
||
| 7701 | #define C_028AC4_COMPAREFUNC1 0xFFFFFFF8 |
||
| 7702 | #define V_028AC4_REF_NEVER 0x00 |
||
| 7703 | #define V_028AC4_REF_LESS 0x01 |
||
| 7704 | #define V_028AC4_REF_EQUAL 0x02 |
||
| 7705 | #define V_028AC4_REF_LEQUAL 0x03 |
||
| 7706 | #define V_028AC4_REF_GREATER 0x04 |
||
| 7707 | #define V_028AC4_REF_NOTEQUAL 0x05 |
||
| 7708 | #define V_028AC4_REF_GEQUAL 0x06 |
||
| 7709 | #define V_028AC4_REF_ALWAYS 0x07 |
||
| 7710 | #define S_028AC4_COMPAREVALUE1(x) (((x) & 0xFF) << 4) |
||
| 7711 | #define G_028AC4_COMPAREVALUE1(x) (((x) >> 4) & 0xFF) |
||
| 7712 | #define C_028AC4_COMPAREVALUE1 0xFFFFF00F |
||
| 7713 | #define S_028AC4_COMPAREMASK1(x) (((x) & 0xFF) << 12) |
||
| 7714 | #define G_028AC4_COMPAREMASK1(x) (((x) >> 12) & 0xFF) |
||
| 7715 | #define C_028AC4_COMPAREMASK1 0xFFF00FFF |
||
| 7716 | #define S_028AC4_ENABLE1(x) (((x) & 0x1) << 24) |
||
| 7717 | #define G_028AC4_ENABLE1(x) (((x) >> 24) & 0x1) |
||
| 7718 | #define C_028AC4_ENABLE1 0xFEFFFFFF |
||
| 7719 | #define R_028AC8_DB_PRELOAD_CONTROL 0x028AC8 |
||
| 7720 | #define S_028AC8_START_X(x) (((x) & 0xFF) << 0) |
||
| 7721 | #define G_028AC8_START_X(x) (((x) >> 0) & 0xFF) |
||
| 7722 | #define C_028AC8_START_X 0xFFFFFF00 |
||
| 7723 | #define S_028AC8_START_Y(x) (((x) & 0xFF) << 8) |
||
| 7724 | #define G_028AC8_START_Y(x) (((x) >> 8) & 0xFF) |
||
| 7725 | #define C_028AC8_START_Y 0xFFFF00FF |
||
| 7726 | #define S_028AC8_MAX_X(x) (((x) & 0xFF) << 16) |
||
| 7727 | #define G_028AC8_MAX_X(x) (((x) >> 16) & 0xFF) |
||
| 7728 | #define C_028AC8_MAX_X 0xFF00FFFF |
||
| 7729 | #define S_028AC8_MAX_Y(x) (((x) & 0xFF) << 24) |
||
| 7730 | #define G_028AC8_MAX_Y(x) (((x) >> 24) & 0xFF) |
||
| 7731 | #define C_028AC8_MAX_Y 0x00FFFFFF |
||
| 7732 | #define R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 0x028AD0 |
||
| 7733 | #define R_028AD4_VGT_STRMOUT_VTX_STRIDE_0 0x028AD4 |
||
| 7734 | #define S_028AD4_STRIDE(x) (((x) & 0x3FF) << 0) |
||
| 7735 | #define G_028AD4_STRIDE(x) (((x) >> 0) & 0x3FF) |
||
| 7736 | #define C_028AD4_STRIDE 0xFFFFFC00 |
||
| 7737 | #define R_028ADC_VGT_STRMOUT_BUFFER_OFFSET_0 0x028ADC |
||
| 7738 | #define R_028AE0_VGT_STRMOUT_BUFFER_SIZE_1 0x028AE0 |
||
| 7739 | #define R_028AE4_VGT_STRMOUT_VTX_STRIDE_1 0x028AE4 |
||
| 7740 | #define S_028AE4_STRIDE(x) (((x) & 0x3FF) << 0) |
||
| 7741 | #define G_028AE4_STRIDE(x) (((x) >> 0) & 0x3FF) |
||
| 7742 | #define C_028AE4_STRIDE 0xFFFFFC00 |
||
| 7743 | #define R_028AEC_VGT_STRMOUT_BUFFER_OFFSET_1 0x028AEC |
||
| 7744 | #define R_028AF0_VGT_STRMOUT_BUFFER_SIZE_2 0x028AF0 |
||
| 7745 | #define R_028AF4_VGT_STRMOUT_VTX_STRIDE_2 0x028AF4 |
||
| 7746 | #define S_028AF4_STRIDE(x) (((x) & 0x3FF) << 0) |
||
| 7747 | #define G_028AF4_STRIDE(x) (((x) >> 0) & 0x3FF) |
||
| 7748 | #define C_028AF4_STRIDE 0xFFFFFC00 |
||
| 7749 | #define R_028AFC_VGT_STRMOUT_BUFFER_OFFSET_2 0x028AFC |
||
| 7750 | #define R_028B00_VGT_STRMOUT_BUFFER_SIZE_3 0x028B00 |
||
| 7751 | #define R_028B04_VGT_STRMOUT_VTX_STRIDE_3 0x028B04 |
||
| 7752 | #define S_028B04_STRIDE(x) (((x) & 0x3FF) << 0) |
||
| 7753 | #define G_028B04_STRIDE(x) (((x) >> 0) & 0x3FF) |
||
| 7754 | #define C_028B04_STRIDE 0xFFFFFC00 |
||
| 7755 | #define R_028B0C_VGT_STRMOUT_BUFFER_OFFSET_3 0x028B0C |
||
| 7756 | #define R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET 0x028B28 |
||
| 7757 | #define R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE 0x028B2C |
||
| 7758 | #define R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE 0x028B30 |
||
| 7759 | #define S_028B30_VERTEX_STRIDE(x) (((x) & 0x1FF) << 0) |
||
| 7760 | #define G_028B30_VERTEX_STRIDE(x) (((x) >> 0) & 0x1FF) |
||
| 7761 | #define C_028B30_VERTEX_STRIDE 0xFFFFFE00 |
||
| 7762 | #define R_028B38_VGT_GS_MAX_VERT_OUT 0x028B38 |
||
| 7763 | #define S_028B38_MAX_VERT_OUT(x) (((x) & 0x7FF) << 0) |
||
| 7764 | #define G_028B38_MAX_VERT_OUT(x) (((x) >> 0) & 0x7FF) |
||
| 7765 | #define C_028B38_MAX_VERT_OUT 0xFFFFF800 |
||
| 7766 | #define R_028B54_VGT_SHADER_STAGES_EN 0x028B54 |
||
| 7767 | #define S_028B54_LS_EN(x) (((x) & 0x03) << 0) |
||
| 7768 | #define G_028B54_LS_EN(x) (((x) >> 0) & 0x03) |
||
| 7769 | #define C_028B54_LS_EN 0xFFFFFFFC |
||
| 7770 | #define V_028B54_LS_STAGE_OFF 0x00 |
||
| 7771 | #define V_028B54_LS_STAGE_ON 0x01 |
||
| 7772 | #define V_028B54_CS_STAGE_ON 0x02 |
||
| 7773 | #define S_028B54_HS_EN(x) (((x) & 0x1) << 2) |
||
| 7774 | #define G_028B54_HS_EN(x) (((x) >> 2) & 0x1) |
||
| 7775 | #define C_028B54_HS_EN 0xFFFFFFFB |
||
| 7776 | #define S_028B54_ES_EN(x) (((x) & 0x03) << 3) |
||
| 7777 | #define G_028B54_ES_EN(x) (((x) >> 3) & 0x03) |
||
| 7778 | #define C_028B54_ES_EN 0xFFFFFFE7 |
||
| 7779 | #define V_028B54_ES_STAGE_OFF 0x00 |
||
| 7780 | #define V_028B54_ES_STAGE_DS 0x01 |
||
| 7781 | #define V_028B54_ES_STAGE_REAL 0x02 |
||
| 7782 | #define S_028B54_GS_EN(x) (((x) & 0x1) << 5) |
||
| 7783 | #define G_028B54_GS_EN(x) (((x) >> 5) & 0x1) |
||
| 7784 | #define C_028B54_GS_EN 0xFFFFFFDF |
||
| 7785 | #define S_028B54_VS_EN(x) (((x) & 0x03) << 6) |
||
| 7786 | #define G_028B54_VS_EN(x) (((x) >> 6) & 0x03) |
||
| 7787 | #define C_028B54_VS_EN 0xFFFFFF3F |
||
| 7788 | #define V_028B54_VS_STAGE_REAL 0x00 |
||
| 7789 | #define V_028B54_VS_STAGE_DS 0x01 |
||
| 7790 | #define V_028B54_VS_STAGE_COPY_SHADER 0x02 |
||
| 7791 | #define S_028B54_DYNAMIC_HS(x) (((x) & 0x1) << 8) |
||
| 7792 | #define G_028B54_DYNAMIC_HS(x) (((x) >> 8) & 0x1) |
||
| 7793 | #define C_028B54_DYNAMIC_HS 0xFFFFFEFF |
||
| 7794 | #define R_028B58_VGT_LS_HS_CONFIG 0x028B58 |
||
| 7795 | #define S_028B58_NUM_PATCHES(x) (((x) & 0xFF) << 0) |
||
| 7796 | #define G_028B58_NUM_PATCHES(x) (((x) >> 0) & 0xFF) |
||
| 7797 | #define C_028B58_NUM_PATCHES 0xFFFFFF00 |
||
| 7798 | #define S_028B58_HS_NUM_INPUT_CP(x) (((x) & 0x3F) << 8) |
||
| 7799 | #define G_028B58_HS_NUM_INPUT_CP(x) (((x) >> 8) & 0x3F) |
||
| 7800 | #define C_028B58_HS_NUM_INPUT_CP 0xFFFFC0FF |
||
| 7801 | #define S_028B58_HS_NUM_OUTPUT_CP(x) (((x) & 0x3F) << 14) |
||
| 7802 | #define G_028B58_HS_NUM_OUTPUT_CP(x) (((x) >> 14) & 0x3F) |
||
| 7803 | #define C_028B58_HS_NUM_OUTPUT_CP 0xFFF03FFF |
||
| 7804 | #define R_028B5C_VGT_GS_VERT_ITEMSIZE 0x028B5C |
||
| 7805 | #define S_028B5C_ITEMSIZE(x) (((x) & 0x7FFF) << 0) |
||
| 7806 | #define G_028B5C_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) |
||
| 7807 | #define C_028B5C_ITEMSIZE 0xFFFF8000 |
||
| 7808 | #define R_028B60_VGT_GS_VERT_ITEMSIZE_1 0x028B60 |
||
| 7809 | #define S_028B60_ITEMSIZE(x) (((x) & 0x7FFF) << 0) |
||
| 7810 | #define G_028B60_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) |
||
| 7811 | #define C_028B60_ITEMSIZE 0xFFFF8000 |
||
| 7812 | #define R_028B64_VGT_GS_VERT_ITEMSIZE_2 0x028B64 |
||
| 7813 | #define S_028B64_ITEMSIZE(x) (((x) & 0x7FFF) << 0) |
||
| 7814 | #define G_028B64_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) |
||
| 7815 | #define C_028B64_ITEMSIZE 0xFFFF8000 |
||
| 7816 | #define R_028B68_VGT_GS_VERT_ITEMSIZE_3 0x028B68 |
||
| 7817 | #define S_028B68_ITEMSIZE(x) (((x) & 0x7FFF) << 0) |
||
| 7818 | #define G_028B68_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) |
||
| 7819 | #define C_028B68_ITEMSIZE 0xFFFF8000 |
||
| 7820 | #define R_028B6C_VGT_TF_PARAM 0x028B6C |
||
| 7821 | #define S_028B6C_TYPE(x) (((x) & 0x03) << 0) |
||
| 7822 | #define G_028B6C_TYPE(x) (((x) >> 0) & 0x03) |
||
| 7823 | #define C_028B6C_TYPE 0xFFFFFFFC |
||
| 7824 | #define V_028B6C_TESS_ISOLINE 0x00 |
||
| 7825 | #define V_028B6C_TESS_TRIANGLE 0x01 |
||
| 7826 | #define V_028B6C_TESS_QUAD 0x02 |
||
| 7827 | #define S_028B6C_PARTITIONING(x) (((x) & 0x07) << 2) |
||
| 7828 | #define G_028B6C_PARTITIONING(x) (((x) >> 2) & 0x07) |
||
| 7829 | #define C_028B6C_PARTITIONING 0xFFFFFFE3 |
||
| 7830 | #define V_028B6C_PART_INTEGER 0x00 |
||
| 7831 | #define V_028B6C_PART_POW2 0x01 |
||
| 7832 | #define V_028B6C_PART_FRAC_ODD 0x02 |
||
| 7833 | #define V_028B6C_PART_FRAC_EVEN 0x03 |
||
| 7834 | #define S_028B6C_TOPOLOGY(x) (((x) & 0x07) << 5) |
||
| 7835 | #define G_028B6C_TOPOLOGY(x) (((x) >> 5) & 0x07) |
||
| 7836 | #define C_028B6C_TOPOLOGY 0xFFFFFF1F |
||
| 7837 | #define V_028B6C_OUTPUT_POINT 0x00 |
||
| 7838 | #define V_028B6C_OUTPUT_LINE 0x01 |
||
| 7839 | #define V_028B6C_OUTPUT_TRIANGLE_CW 0x02 |
||
| 7840 | #define V_028B6C_OUTPUT_TRIANGLE_CCW 0x03 |
||
| 7841 | #define S_028B6C_RESERVED_REDUC_AXIS(x) (((x) & 0x1) << 8) /* not on CIK */ |
||
| 7842 | #define G_028B6C_RESERVED_REDUC_AXIS(x) (((x) >> 8) & 0x1) /* not on CIK */ |
||
| 7843 | #define C_028B6C_RESERVED_REDUC_AXIS 0xFFFFFEFF /* not on CIK */ |
||
| 7844 | #define S_028B6C_NUM_DS_WAVES_PER_SIMD(x) (((x) & 0x0F) << 10) |
||
| 7845 | #define G_028B6C_NUM_DS_WAVES_PER_SIMD(x) (((x) >> 10) & 0x0F) |
||
| 7846 | #define C_028B6C_NUM_DS_WAVES_PER_SIMD 0xFFFFC3FF |
||
| 7847 | #define S_028B6C_DISABLE_DONUTS(x) (((x) & 0x1) << 14) |
||
| 7848 | #define G_028B6C_DISABLE_DONUTS(x) (((x) >> 14) & 0x1) |
||
| 7849 | #define C_028B6C_DISABLE_DONUTS 0xFFFFBFFF |
||
| 7850 | /* CIK */ |
||
| 7851 | #define S_028B6C_RDREQ_POLICY(x) (((x) & 0x03) << 15) |
||
| 7852 | #define G_028B6C_RDREQ_POLICY(x) (((x) >> 15) & 0x03) |
||
| 7853 | #define C_028B6C_RDREQ_POLICY 0xFFFE7FFF |
||
| 7854 | #define V_028B6C_VGT_POLICY_LRU 0x00 |
||
| 7855 | #define V_028B6C_VGT_POLICY_STREAM 0x01 |
||
| 7856 | #define V_028B6C_VGT_POLICY_BYPASS 0x02 |
||
| 7857 | /* */ |
||
| 7858 | #define R_028B70_DB_ALPHA_TO_MASK 0x028B70 |
||
| 7859 | #define S_028B70_ALPHA_TO_MASK_ENABLE(x) (((x) & 0x1) << 0) |
||
| 7860 | #define G_028B70_ALPHA_TO_MASK_ENABLE(x) (((x) >> 0) & 0x1) |
||
| 7861 | #define C_028B70_ALPHA_TO_MASK_ENABLE 0xFFFFFFFE |
||
| 7862 | #define S_028B70_ALPHA_TO_MASK_OFFSET0(x) (((x) & 0x03) << 8) |
||
| 7863 | #define G_028B70_ALPHA_TO_MASK_OFFSET0(x) (((x) >> 8) & 0x03) |
||
| 7864 | #define C_028B70_ALPHA_TO_MASK_OFFSET0 0xFFFFFCFF |
||
| 7865 | #define S_028B70_ALPHA_TO_MASK_OFFSET1(x) (((x) & 0x03) << 10) |
||
| 7866 | #define G_028B70_ALPHA_TO_MASK_OFFSET1(x) (((x) >> 10) & 0x03) |
||
| 7867 | #define C_028B70_ALPHA_TO_MASK_OFFSET1 0xFFFFF3FF |
||
| 7868 | #define S_028B70_ALPHA_TO_MASK_OFFSET2(x) (((x) & 0x03) << 12) |
||
| 7869 | #define G_028B70_ALPHA_TO_MASK_OFFSET2(x) (((x) >> 12) & 0x03) |
||
| 7870 | #define C_028B70_ALPHA_TO_MASK_OFFSET2 0xFFFFCFFF |
||
| 7871 | #define S_028B70_ALPHA_TO_MASK_OFFSET3(x) (((x) & 0x03) << 14) |
||
| 7872 | #define G_028B70_ALPHA_TO_MASK_OFFSET3(x) (((x) >> 14) & 0x03) |
||
| 7873 | #define C_028B70_ALPHA_TO_MASK_OFFSET3 0xFFFF3FFF |
||
| 7874 | #define S_028B70_OFFSET_ROUND(x) (((x) & 0x1) << 16) |
||
| 7875 | #define G_028B70_OFFSET_ROUND(x) (((x) >> 16) & 0x1) |
||
| 7876 | #define C_028B70_OFFSET_ROUND 0xFFFEFFFF |
||
| 7877 | /* CIK */ |
||
| 7878 | #define R_028B74_VGT_DISPATCH_DRAW_INDEX 0x028B74 |
||
| 7879 | /* */ |
||
| 7880 | #define R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL 0x028B78 |
||
| 7881 | #define S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(x) (((x) & 0xFF) << 0) |
||
| 7882 | #define G_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(x) (((x) >> 0) & 0xFF) |
||
| 7883 | #define C_028B78_POLY_OFFSET_NEG_NUM_DB_BITS 0xFFFFFF00 |
||
| 7884 | #define S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(x) (((x) & 0x1) << 8) |
||
| 7885 | #define G_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(x) (((x) >> 8) & 0x1) |
||
| 7886 | #define C_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT 0xFFFFFEFF |
||
| 7887 | #define R_028B7C_PA_SU_POLY_OFFSET_CLAMP 0x028B7C |
||
| 7888 | #define R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE 0x028B80 |
||
| 7889 | #define R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET 0x028B84 |
||
| 7890 | #define R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE 0x028B88 |
||
| 7891 | #define R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET 0x028B8C |
||
| 7892 | #define R_028B90_VGT_GS_INSTANCE_CNT 0x028B90 |
||
| 7893 | #define S_028B90_ENABLE(x) (((x) & 0x1) << 0) |
||
| 7894 | #define G_028B90_ENABLE(x) (((x) >> 0) & 0x1) |
||
| 7895 | #define C_028B90_ENABLE 0xFFFFFFFE |
||
| 7896 | #define S_028B90_CNT(x) (((x) & 0x7F) << 2) |
||
| 7897 | #define G_028B90_CNT(x) (((x) >> 2) & 0x7F) |
||
| 7898 | #define C_028B90_CNT 0xFFFFFE03 |
||
| 7899 | #define R_028B94_VGT_STRMOUT_CONFIG 0x028B94 |
||
| 7900 | #define S_028B94_STREAMOUT_0_EN(x) (((x) & 0x1) << 0) |
||
| 7901 | #define G_028B94_STREAMOUT_0_EN(x) (((x) >> 0) & 0x1) |
||
| 7902 | #define C_028B94_STREAMOUT_0_EN 0xFFFFFFFE |
||
| 7903 | #define S_028B94_STREAMOUT_1_EN(x) (((x) & 0x1) << 1) |
||
| 7904 | #define G_028B94_STREAMOUT_1_EN(x) (((x) >> 1) & 0x1) |
||
| 7905 | #define C_028B94_STREAMOUT_1_EN 0xFFFFFFFD |
||
| 7906 | #define S_028B94_STREAMOUT_2_EN(x) (((x) & 0x1) << 2) |
||
| 7907 | #define G_028B94_STREAMOUT_2_EN(x) (((x) >> 2) & 0x1) |
||
| 7908 | #define C_028B94_STREAMOUT_2_EN 0xFFFFFFFB |
||
| 7909 | #define S_028B94_STREAMOUT_3_EN(x) (((x) & 0x1) << 3) |
||
| 7910 | #define G_028B94_STREAMOUT_3_EN(x) (((x) >> 3) & 0x1) |
||
| 7911 | #define C_028B94_STREAMOUT_3_EN 0xFFFFFFF7 |
||
| 7912 | #define S_028B94_RAST_STREAM(x) (((x) & 0x07) << 4) |
||
| 7913 | #define G_028B94_RAST_STREAM(x) (((x) >> 4) & 0x07) |
||
| 7914 | #define C_028B94_RAST_STREAM 0xFFFFFF8F |
||
| 7915 | #define S_028B94_RAST_STREAM_MASK(x) (((x) & 0x0F) << 8) |
||
| 7916 | #define G_028B94_RAST_STREAM_MASK(x) (((x) >> 8) & 0x0F) |
||
| 7917 | #define C_028B94_RAST_STREAM_MASK 0xFFFFF0FF |
||
| 7918 | #define S_028B94_USE_RAST_STREAM_MASK(x) (((x) & 0x1) << 31) |
||
| 7919 | #define G_028B94_USE_RAST_STREAM_MASK(x) (((x) >> 31) & 0x1) |
||
| 7920 | #define C_028B94_USE_RAST_STREAM_MASK 0x7FFFFFFF |
||
| 7921 | #define R_028B98_VGT_STRMOUT_BUFFER_CONFIG 0x028B98 |
||
| 7922 | #define S_028B98_STREAM_0_BUFFER_EN(x) (((x) & 0x0F) << 0) |
||
| 7923 | #define G_028B98_STREAM_0_BUFFER_EN(x) (((x) >> 0) & 0x0F) |
||
| 7924 | #define C_028B98_STREAM_0_BUFFER_EN 0xFFFFFFF0 |
||
| 7925 | #define S_028B98_STREAM_1_BUFFER_EN(x) (((x) & 0x0F) << 4) |
||
| 7926 | #define G_028B98_STREAM_1_BUFFER_EN(x) (((x) >> 4) & 0x0F) |
||
| 7927 | #define C_028B98_STREAM_1_BUFFER_EN 0xFFFFFF0F |
||
| 7928 | #define S_028B98_STREAM_2_BUFFER_EN(x) (((x) & 0x0F) << 8) |
||
| 7929 | #define G_028B98_STREAM_2_BUFFER_EN(x) (((x) >> 8) & 0x0F) |
||
| 7930 | #define C_028B98_STREAM_2_BUFFER_EN 0xFFFFF0FF |
||
| 7931 | #define S_028B98_STREAM_3_BUFFER_EN(x) (((x) & 0x0F) << 12) |
||
| 7932 | #define G_028B98_STREAM_3_BUFFER_EN(x) (((x) >> 12) & 0x0F) |
||
| 7933 | #define C_028B98_STREAM_3_BUFFER_EN 0xFFFF0FFF |
||
| 7934 | #define R_028BD4_PA_SC_CENTROID_PRIORITY_0 0x028BD4 |
||
| 7935 | #define S_028BD4_DISTANCE_0(x) (((x) & 0x0F) << 0) |
||
| 7936 | #define G_028BD4_DISTANCE_0(x) (((x) >> 0) & 0x0F) |
||
| 7937 | #define C_028BD4_DISTANCE_0 0xFFFFFFF0 |
||
| 7938 | #define S_028BD4_DISTANCE_1(x) (((x) & 0x0F) << 4) |
||
| 7939 | #define G_028BD4_DISTANCE_1(x) (((x) >> 4) & 0x0F) |
||
| 7940 | #define C_028BD4_DISTANCE_1 0xFFFFFF0F |
||
| 7941 | #define S_028BD4_DISTANCE_2(x) (((x) & 0x0F) << 8) |
||
| 7942 | #define G_028BD4_DISTANCE_2(x) (((x) >> 8) & 0x0F) |
||
| 7943 | #define C_028BD4_DISTANCE_2 0xFFFFF0FF |
||
| 7944 | #define S_028BD4_DISTANCE_3(x) (((x) & 0x0F) << 12) |
||
| 7945 | #define G_028BD4_DISTANCE_3(x) (((x) >> 12) & 0x0F) |
||
| 7946 | #define C_028BD4_DISTANCE_3 0xFFFF0FFF |
||
| 7947 | #define S_028BD4_DISTANCE_4(x) (((x) & 0x0F) << 16) |
||
| 7948 | #define G_028BD4_DISTANCE_4(x) (((x) >> 16) & 0x0F) |
||
| 7949 | #define C_028BD4_DISTANCE_4 0xFFF0FFFF |
||
| 7950 | #define S_028BD4_DISTANCE_5(x) (((x) & 0x0F) << 20) |
||
| 7951 | #define G_028BD4_DISTANCE_5(x) (((x) >> 20) & 0x0F) |
||
| 7952 | #define C_028BD4_DISTANCE_5 0xFF0FFFFF |
||
| 7953 | #define S_028BD4_DISTANCE_6(x) (((x) & 0x0F) << 24) |
||
| 7954 | #define G_028BD4_DISTANCE_6(x) (((x) >> 24) & 0x0F) |
||
| 7955 | #define C_028BD4_DISTANCE_6 0xF0FFFFFF |
||
| 7956 | #define S_028BD4_DISTANCE_7(x) (((x) & 0x0F) << 28) |
||
| 7957 | #define G_028BD4_DISTANCE_7(x) (((x) >> 28) & 0x0F) |
||
| 7958 | #define C_028BD4_DISTANCE_7 0x0FFFFFFF |
||
| 7959 | #define R_028BD8_PA_SC_CENTROID_PRIORITY_1 0x028BD8 |
||
| 7960 | #define S_028BD8_DISTANCE_8(x) (((x) & 0x0F) << 0) |
||
| 7961 | #define G_028BD8_DISTANCE_8(x) (((x) >> 0) & 0x0F) |
||
| 7962 | #define C_028BD8_DISTANCE_8 0xFFFFFFF0 |
||
| 7963 | #define S_028BD8_DISTANCE_9(x) (((x) & 0x0F) << 4) |
||
| 7964 | #define G_028BD8_DISTANCE_9(x) (((x) >> 4) & 0x0F) |
||
| 7965 | #define C_028BD8_DISTANCE_9 0xFFFFFF0F |
||
| 7966 | #define S_028BD8_DISTANCE_10(x) (((x) & 0x0F) << 8) |
||
| 7967 | #define G_028BD8_DISTANCE_10(x) (((x) >> 8) & 0x0F) |
||
| 7968 | #define C_028BD8_DISTANCE_10 0xFFFFF0FF |
||
| 7969 | #define S_028BD8_DISTANCE_11(x) (((x) & 0x0F) << 12) |
||
| 7970 | #define G_028BD8_DISTANCE_11(x) (((x) >> 12) & 0x0F) |
||
| 7971 | #define C_028BD8_DISTANCE_11 0xFFFF0FFF |
||
| 7972 | #define S_028BD8_DISTANCE_12(x) (((x) & 0x0F) << 16) |
||
| 7973 | #define G_028BD8_DISTANCE_12(x) (((x) >> 16) & 0x0F) |
||
| 7974 | #define C_028BD8_DISTANCE_12 0xFFF0FFFF |
||
| 7975 | #define S_028BD8_DISTANCE_13(x) (((x) & 0x0F) << 20) |
||
| 7976 | #define G_028BD8_DISTANCE_13(x) (((x) >> 20) & 0x0F) |
||
| 7977 | #define C_028BD8_DISTANCE_13 0xFF0FFFFF |
||
| 7978 | #define S_028BD8_DISTANCE_14(x) (((x) & 0x0F) << 24) |
||
| 7979 | #define G_028BD8_DISTANCE_14(x) (((x) >> 24) & 0x0F) |
||
| 7980 | #define C_028BD8_DISTANCE_14 0xF0FFFFFF |
||
| 7981 | #define S_028BD8_DISTANCE_15(x) (((x) & 0x0F) << 28) |
||
| 7982 | #define G_028BD8_DISTANCE_15(x) (((x) >> 28) & 0x0F) |
||
| 7983 | #define C_028BD8_DISTANCE_15 0x0FFFFFFF |
||
| 7984 | #define R_028BDC_PA_SC_LINE_CNTL 0x028BDC |
||
| 7985 | #define S_028BDC_EXPAND_LINE_WIDTH(x) (((x) & 0x1) << 9) |
||
| 7986 | #define G_028BDC_EXPAND_LINE_WIDTH(x) (((x) >> 9) & 0x1) |
||
| 7987 | #define C_028BDC_EXPAND_LINE_WIDTH 0xFFFFFDFF |
||
| 7988 | #define S_028BDC_LAST_PIXEL(x) (((x) & 0x1) << 10) |
||
| 7989 | #define G_028BDC_LAST_PIXEL(x) (((x) >> 10) & 0x1) |
||
| 7990 | #define C_028BDC_LAST_PIXEL 0xFFFFFBFF |
||
| 7991 | #define S_028BDC_PERPENDICULAR_ENDCAP_ENA(x) (((x) & 0x1) << 11) |
||
| 7992 | #define G_028BDC_PERPENDICULAR_ENDCAP_ENA(x) (((x) >> 11) & 0x1) |
||
| 7993 | #define C_028BDC_PERPENDICULAR_ENDCAP_ENA 0xFFFFF7FF |
||
| 7994 | #define S_028BDC_DX10_DIAMOND_TEST_ENA(x) (((x) & 0x1) << 12) |
||
| 7995 | #define G_028BDC_DX10_DIAMOND_TEST_ENA(x) (((x) >> 12) & 0x1) |
||
| 7996 | #define C_028BDC_DX10_DIAMOND_TEST_ENA 0xFFFFEFFF |
||
| 7997 | #define R_028BE4_PA_SU_VTX_CNTL 0x028BE4 |
||
| 7998 | #define S_028BE4_PIX_CENTER(x) (((x) & 0x1) << 0) |
||
| 7999 | #define G_028BE4_PIX_CENTER(x) (((x) >> 0) & 0x1) |
||
| 8000 | #define C_028BE4_PIX_CENTER 0xFFFFFFFE |
||
| 8001 | #define S_028BE4_ROUND_MODE(x) (((x) & 0x03) << 1) |
||
| 8002 | #define G_028BE4_ROUND_MODE(x) (((x) >> 1) & 0x03) |
||
| 8003 | #define C_028BE4_ROUND_MODE 0xFFFFFFF9 |
||
| 8004 | #define V_028BE4_X_TRUNCATE 0x00 |
||
| 8005 | #define V_028BE4_X_ROUND 0x01 |
||
| 8006 | #define V_028BE4_X_ROUND_TO_EVEN 0x02 |
||
| 8007 | #define V_028BE4_X_ROUND_TO_ODD 0x03 |
||
| 8008 | #define S_028BE4_QUANT_MODE(x) (((x) & 0x07) << 3) |
||
| 8009 | #define G_028BE4_QUANT_MODE(x) (((x) >> 3) & 0x07) |
||
| 8010 | #define C_028BE4_QUANT_MODE 0xFFFFFFC7 |
||
| 8011 | #define V_028BE4_X_16_8_FIXED_POINT_1_16TH 0x00 |
||
| 8012 | #define V_028BE4_X_16_8_FIXED_POINT_1_8TH 0x01 |
||
| 8013 | #define V_028BE4_X_16_8_FIXED_POINT_1_4TH 0x02 |
||
| 8014 | #define V_028BE4_X_16_8_FIXED_POINT_1_2 0x03 |
||
| 8015 | #define V_028BE4_X_16_8_FIXED_POINT_1 0x04 |
||
| 8016 | #define V_028BE4_X_16_8_FIXED_POINT_1_256TH 0x05 |
||
| 8017 | #define V_028BE4_X_14_10_FIXED_POINT_1_1024TH 0x06 |
||
| 8018 | #define V_028BE4_X_12_12_FIXED_POINT_1_4096TH 0x07 |
||
| 8019 | #define R_028BE8_PA_CL_GB_VERT_CLIP_ADJ 0x028BE8 |
||
| 8020 | #define R_028BEC_PA_CL_GB_VERT_DISC_ADJ 0x028BEC |
||
| 8021 | #define R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ 0x028BF0 |
||
| 8022 | #define R_028BF4_PA_CL_GB_HORZ_DISC_ADJ 0x028BF4 |
||
| 8023 | #define R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 0x028BF8 |
||
| 8024 | #define S_028BF8_S0_X(x) (((x) & 0x0F) << 0) |
||
| 8025 | #define G_028BF8_S0_X(x) (((x) >> 0) & 0x0F) |
||
| 8026 | #define C_028BF8_S0_X 0xFFFFFFF0 |
||
| 8027 | #define S_028BF8_S0_Y(x) (((x) & 0x0F) << 4) |
||
| 8028 | #define G_028BF8_S0_Y(x) (((x) >> 4) & 0x0F) |
||
| 8029 | #define C_028BF8_S0_Y 0xFFFFFF0F |
||
| 8030 | #define S_028BF8_S1_X(x) (((x) & 0x0F) << 8) |
||
| 8031 | #define G_028BF8_S1_X(x) (((x) >> 8) & 0x0F) |
||
| 8032 | #define C_028BF8_S1_X 0xFFFFF0FF |
||
| 8033 | #define S_028BF8_S1_Y(x) (((x) & 0x0F) << 12) |
||
| 8034 | #define G_028BF8_S1_Y(x) (((x) >> 12) & 0x0F) |
||
| 8035 | #define C_028BF8_S1_Y 0xFFFF0FFF |
||
| 8036 | #define S_028BF8_S2_X(x) (((x) & 0x0F) << 16) |
||
| 8037 | #define G_028BF8_S2_X(x) (((x) >> 16) & 0x0F) |
||
| 8038 | #define C_028BF8_S2_X 0xFFF0FFFF |
||
| 8039 | #define S_028BF8_S2_Y(x) (((x) & 0x0F) << 20) |
||
| 8040 | #define G_028BF8_S2_Y(x) (((x) >> 20) & 0x0F) |
||
| 8041 | #define C_028BF8_S2_Y 0xFF0FFFFF |
||
| 8042 | #define S_028BF8_S3_X(x) (((x) & 0x0F) << 24) |
||
| 8043 | #define G_028BF8_S3_X(x) (((x) >> 24) & 0x0F) |
||
| 8044 | #define C_028BF8_S3_X 0xF0FFFFFF |
||
| 8045 | #define S_028BF8_S3_Y(x) (((x) & 0x0F) << 28) |
||
| 8046 | #define G_028BF8_S3_Y(x) (((x) >> 28) & 0x0F) |
||
| 8047 | #define C_028BF8_S3_Y 0x0FFFFFFF |
||
| 8048 | #define R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1 0x028BFC |
||
| 8049 | #define S_028BFC_S4_X(x) (((x) & 0x0F) << 0) |
||
| 8050 | #define G_028BFC_S4_X(x) (((x) >> 0) & 0x0F) |
||
| 8051 | #define C_028BFC_S4_X 0xFFFFFFF0 |
||
| 8052 | #define S_028BFC_S4_Y(x) (((x) & 0x0F) << 4) |
||
| 8053 | #define G_028BFC_S4_Y(x) (((x) >> 4) & 0x0F) |
||
| 8054 | #define C_028BFC_S4_Y 0xFFFFFF0F |
||
| 8055 | #define S_028BFC_S5_X(x) (((x) & 0x0F) << 8) |
||
| 8056 | #define G_028BFC_S5_X(x) (((x) >> 8) & 0x0F) |
||
| 8057 | #define C_028BFC_S5_X 0xFFFFF0FF |
||
| 8058 | #define S_028BFC_S5_Y(x) (((x) & 0x0F) << 12) |
||
| 8059 | #define G_028BFC_S5_Y(x) (((x) >> 12) & 0x0F) |
||
| 8060 | #define C_028BFC_S5_Y 0xFFFF0FFF |
||
| 8061 | #define S_028BFC_S6_X(x) (((x) & 0x0F) << 16) |
||
| 8062 | #define G_028BFC_S6_X(x) (((x) >> 16) & 0x0F) |
||
| 8063 | #define C_028BFC_S6_X 0xFFF0FFFF |
||
| 8064 | #define S_028BFC_S6_Y(x) (((x) & 0x0F) << 20) |
||
| 8065 | #define G_028BFC_S6_Y(x) (((x) >> 20) & 0x0F) |
||
| 8066 | #define C_028BFC_S6_Y 0xFF0FFFFF |
||
| 8067 | #define S_028BFC_S7_X(x) (((x) & 0x0F) << 24) |
||
| 8068 | #define G_028BFC_S7_X(x) (((x) >> 24) & 0x0F) |
||
| 8069 | #define C_028BFC_S7_X 0xF0FFFFFF |
||
| 8070 | #define S_028BFC_S7_Y(x) (((x) & 0x0F) << 28) |
||
| 8071 | #define G_028BFC_S7_Y(x) (((x) >> 28) & 0x0F) |
||
| 8072 | #define C_028BFC_S7_Y 0x0FFFFFFF |
||
| 8073 | #define R_028C00_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2 0x028C00 |
||
| 8074 | #define S_028C00_S8_X(x) (((x) & 0x0F) << 0) |
||
| 8075 | #define G_028C00_S8_X(x) (((x) >> 0) & 0x0F) |
||
| 8076 | #define C_028C00_S8_X 0xFFFFFFF0 |
||
| 8077 | #define S_028C00_S8_Y(x) (((x) & 0x0F) << 4) |
||
| 8078 | #define G_028C00_S8_Y(x) (((x) >> 4) & 0x0F) |
||
| 8079 | #define C_028C00_S8_Y 0xFFFFFF0F |
||
| 8080 | #define S_028C00_S9_X(x) (((x) & 0x0F) << 8) |
||
| 8081 | #define G_028C00_S9_X(x) (((x) >> 8) & 0x0F) |
||
| 8082 | #define C_028C00_S9_X 0xFFFFF0FF |
||
| 8083 | #define S_028C00_S9_Y(x) (((x) & 0x0F) << 12) |
||
| 8084 | #define G_028C00_S9_Y(x) (((x) >> 12) & 0x0F) |
||
| 8085 | #define C_028C00_S9_Y 0xFFFF0FFF |
||
| 8086 | #define S_028C00_S10_X(x) (((x) & 0x0F) << 16) |
||
| 8087 | #define G_028C00_S10_X(x) (((x) >> 16) & 0x0F) |
||
| 8088 | #define C_028C00_S10_X 0xFFF0FFFF |
||
| 8089 | #define S_028C00_S10_Y(x) (((x) & 0x0F) << 20) |
||
| 8090 | #define G_028C00_S10_Y(x) (((x) >> 20) & 0x0F) |
||
| 8091 | #define C_028C00_S10_Y 0xFF0FFFFF |
||
| 8092 | #define S_028C00_S11_X(x) (((x) & 0x0F) << 24) |
||
| 8093 | #define G_028C00_S11_X(x) (((x) >> 24) & 0x0F) |
||
| 8094 | #define C_028C00_S11_X 0xF0FFFFFF |
||
| 8095 | #define S_028C00_S11_Y(x) (((x) & 0x0F) << 28) |
||
| 8096 | #define G_028C00_S11_Y(x) (((x) >> 28) & 0x0F) |
||
| 8097 | #define C_028C00_S11_Y 0x0FFFFFFF |
||
| 8098 | #define R_028C04_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3 0x028C04 |
||
| 8099 | #define S_028C04_S12_X(x) (((x) & 0x0F) << 0) |
||
| 8100 | #define G_028C04_S12_X(x) (((x) >> 0) & 0x0F) |
||
| 8101 | #define C_028C04_S12_X 0xFFFFFFF0 |
||
| 8102 | #define S_028C04_S12_Y(x) (((x) & 0x0F) << 4) |
||
| 8103 | #define G_028C04_S12_Y(x) (((x) >> 4) & 0x0F) |
||
| 8104 | #define C_028C04_S12_Y 0xFFFFFF0F |
||
| 8105 | #define S_028C04_S13_X(x) (((x) & 0x0F) << 8) |
||
| 8106 | #define G_028C04_S13_X(x) (((x) >> 8) & 0x0F) |
||
| 8107 | #define C_028C04_S13_X 0xFFFFF0FF |
||
| 8108 | #define S_028C04_S13_Y(x) (((x) & 0x0F) << 12) |
||
| 8109 | #define G_028C04_S13_Y(x) (((x) >> 12) & 0x0F) |
||
| 8110 | #define C_028C04_S13_Y 0xFFFF0FFF |
||
| 8111 | #define S_028C04_S14_X(x) (((x) & 0x0F) << 16) |
||
| 8112 | #define G_028C04_S14_X(x) (((x) >> 16) & 0x0F) |
||
| 8113 | #define C_028C04_S14_X 0xFFF0FFFF |
||
| 8114 | #define S_028C04_S14_Y(x) (((x) & 0x0F) << 20) |
||
| 8115 | #define G_028C04_S14_Y(x) (((x) >> 20) & 0x0F) |
||
| 8116 | #define C_028C04_S14_Y 0xFF0FFFFF |
||
| 8117 | #define S_028C04_S15_X(x) (((x) & 0x0F) << 24) |
||
| 8118 | #define G_028C04_S15_X(x) (((x) >> 24) & 0x0F) |
||
| 8119 | #define C_028C04_S15_X 0xF0FFFFFF |
||
| 8120 | #define S_028C04_S15_Y(x) (((x) & 0x0F) << 28) |
||
| 8121 | #define G_028C04_S15_Y(x) (((x) >> 28) & 0x0F) |
||
| 8122 | #define C_028C04_S15_Y 0x0FFFFFFF |
||
| 8123 | #define R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 0x028C08 |
||
| 8124 | #define S_028C08_S0_X(x) (((x) & 0x0F) << 0) |
||
| 8125 | #define G_028C08_S0_X(x) (((x) >> 0) & 0x0F) |
||
| 8126 | #define C_028C08_S0_X 0xFFFFFFF0 |
||
| 8127 | #define S_028C08_S0_Y(x) (((x) & 0x0F) << 4) |
||
| 8128 | #define G_028C08_S0_Y(x) (((x) >> 4) & 0x0F) |
||
| 8129 | #define C_028C08_S0_Y 0xFFFFFF0F |
||
| 8130 | #define S_028C08_S1_X(x) (((x) & 0x0F) << 8) |
||
| 8131 | #define G_028C08_S1_X(x) (((x) >> 8) & 0x0F) |
||
| 8132 | #define C_028C08_S1_X 0xFFFFF0FF |
||
| 8133 | #define S_028C08_S1_Y(x) (((x) & 0x0F) << 12) |
||
| 8134 | #define G_028C08_S1_Y(x) (((x) >> 12) & 0x0F) |
||
| 8135 | #define C_028C08_S1_Y 0xFFFF0FFF |
||
| 8136 | #define S_028C08_S2_X(x) (((x) & 0x0F) << 16) |
||
| 8137 | #define G_028C08_S2_X(x) (((x) >> 16) & 0x0F) |
||
| 8138 | #define C_028C08_S2_X 0xFFF0FFFF |
||
| 8139 | #define S_028C08_S2_Y(x) (((x) & 0x0F) << 20) |
||
| 8140 | #define G_028C08_S2_Y(x) (((x) >> 20) & 0x0F) |
||
| 8141 | #define C_028C08_S2_Y 0xFF0FFFFF |
||
| 8142 | #define S_028C08_S3_X(x) (((x) & 0x0F) << 24) |
||
| 8143 | #define G_028C08_S3_X(x) (((x) >> 24) & 0x0F) |
||
| 8144 | #define C_028C08_S3_X 0xF0FFFFFF |
||
| 8145 | #define S_028C08_S3_Y(x) (((x) & 0x0F) << 28) |
||
| 8146 | #define G_028C08_S3_Y(x) (((x) >> 28) & 0x0F) |
||
| 8147 | #define C_028C08_S3_Y 0x0FFFFFFF |
||
| 8148 | #define R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1 0x028C0C |
||
| 8149 | #define S_028C0C_S4_X(x) (((x) & 0x0F) << 0) |
||
| 8150 | #define G_028C0C_S4_X(x) (((x) >> 0) & 0x0F) |
||
| 8151 | #define C_028C0C_S4_X 0xFFFFFFF0 |
||
| 8152 | #define S_028C0C_S4_Y(x) (((x) & 0x0F) << 4) |
||
| 8153 | #define G_028C0C_S4_Y(x) (((x) >> 4) & 0x0F) |
||
| 8154 | #define C_028C0C_S4_Y 0xFFFFFF0F |
||
| 8155 | #define S_028C0C_S5_X(x) (((x) & 0x0F) << 8) |
||
| 8156 | #define G_028C0C_S5_X(x) (((x) >> 8) & 0x0F) |
||
| 8157 | #define C_028C0C_S5_X 0xFFFFF0FF |
||
| 8158 | #define S_028C0C_S5_Y(x) (((x) & 0x0F) << 12) |
||
| 8159 | #define G_028C0C_S5_Y(x) (((x) >> 12) & 0x0F) |
||
| 8160 | #define C_028C0C_S5_Y 0xFFFF0FFF |
||
| 8161 | #define S_028C0C_S6_X(x) (((x) & 0x0F) << 16) |
||
| 8162 | #define G_028C0C_S6_X(x) (((x) >> 16) & 0x0F) |
||
| 8163 | #define C_028C0C_S6_X 0xFFF0FFFF |
||
| 8164 | #define S_028C0C_S6_Y(x) (((x) & 0x0F) << 20) |
||
| 8165 | #define G_028C0C_S6_Y(x) (((x) >> 20) & 0x0F) |
||
| 8166 | #define C_028C0C_S6_Y 0xFF0FFFFF |
||
| 8167 | #define S_028C0C_S7_X(x) (((x) & 0x0F) << 24) |
||
| 8168 | #define G_028C0C_S7_X(x) (((x) >> 24) & 0x0F) |
||
| 8169 | #define C_028C0C_S7_X 0xF0FFFFFF |
||
| 8170 | #define S_028C0C_S7_Y(x) (((x) & 0x0F) << 28) |
||
| 8171 | #define G_028C0C_S7_Y(x) (((x) >> 28) & 0x0F) |
||
| 8172 | #define C_028C0C_S7_Y 0x0FFFFFFF |
||
| 8173 | #define R_028C10_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2 0x028C10 |
||
| 8174 | #define S_028C10_S8_X(x) (((x) & 0x0F) << 0) |
||
| 8175 | #define G_028C10_S8_X(x) (((x) >> 0) & 0x0F) |
||
| 8176 | #define C_028C10_S8_X 0xFFFFFFF0 |
||
| 8177 | #define S_028C10_S8_Y(x) (((x) & 0x0F) << 4) |
||
| 8178 | #define G_028C10_S8_Y(x) (((x) >> 4) & 0x0F) |
||
| 8179 | #define C_028C10_S8_Y 0xFFFFFF0F |
||
| 8180 | #define S_028C10_S9_X(x) (((x) & 0x0F) << 8) |
||
| 8181 | #define G_028C10_S9_X(x) (((x) >> 8) & 0x0F) |
||
| 8182 | #define C_028C10_S9_X 0xFFFFF0FF |
||
| 8183 | #define S_028C10_S9_Y(x) (((x) & 0x0F) << 12) |
||
| 8184 | #define G_028C10_S9_Y(x) (((x) >> 12) & 0x0F) |
||
| 8185 | #define C_028C10_S9_Y 0xFFFF0FFF |
||
| 8186 | #define S_028C10_S10_X(x) (((x) & 0x0F) << 16) |
||
| 8187 | #define G_028C10_S10_X(x) (((x) >> 16) & 0x0F) |
||
| 8188 | #define C_028C10_S10_X 0xFFF0FFFF |
||
| 8189 | #define S_028C10_S10_Y(x) (((x) & 0x0F) << 20) |
||
| 8190 | #define G_028C10_S10_Y(x) (((x) >> 20) & 0x0F) |
||
| 8191 | #define C_028C10_S10_Y 0xFF0FFFFF |
||
| 8192 | #define S_028C10_S11_X(x) (((x) & 0x0F) << 24) |
||
| 8193 | #define G_028C10_S11_X(x) (((x) >> 24) & 0x0F) |
||
| 8194 | #define C_028C10_S11_X 0xF0FFFFFF |
||
| 8195 | #define S_028C10_S11_Y(x) (((x) & 0x0F) << 28) |
||
| 8196 | #define G_028C10_S11_Y(x) (((x) >> 28) & 0x0F) |
||
| 8197 | #define C_028C10_S11_Y 0x0FFFFFFF |
||
| 8198 | #define R_028C14_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3 0x028C14 |
||
| 8199 | #define S_028C14_S12_X(x) (((x) & 0x0F) << 0) |
||
| 8200 | #define G_028C14_S12_X(x) (((x) >> 0) & 0x0F) |
||
| 8201 | #define C_028C14_S12_X 0xFFFFFFF0 |
||
| 8202 | #define S_028C14_S12_Y(x) (((x) & 0x0F) << 4) |
||
| 8203 | #define G_028C14_S12_Y(x) (((x) >> 4) & 0x0F) |
||
| 8204 | #define C_028C14_S12_Y 0xFFFFFF0F |
||
| 8205 | #define S_028C14_S13_X(x) (((x) & 0x0F) << 8) |
||
| 8206 | #define G_028C14_S13_X(x) (((x) >> 8) & 0x0F) |
||
| 8207 | #define C_028C14_S13_X 0xFFFFF0FF |
||
| 8208 | #define S_028C14_S13_Y(x) (((x) & 0x0F) << 12) |
||
| 8209 | #define G_028C14_S13_Y(x) (((x) >> 12) & 0x0F) |
||
| 8210 | #define C_028C14_S13_Y 0xFFFF0FFF |
||
| 8211 | #define S_028C14_S14_X(x) (((x) & 0x0F) << 16) |
||
| 8212 | #define G_028C14_S14_X(x) (((x) >> 16) & 0x0F) |
||
| 8213 | #define C_028C14_S14_X 0xFFF0FFFF |
||
| 8214 | #define S_028C14_S14_Y(x) (((x) & 0x0F) << 20) |
||
| 8215 | #define G_028C14_S14_Y(x) (((x) >> 20) & 0x0F) |
||
| 8216 | #define C_028C14_S14_Y 0xFF0FFFFF |
||
| 8217 | #define S_028C14_S15_X(x) (((x) & 0x0F) << 24) |
||
| 8218 | #define G_028C14_S15_X(x) (((x) >> 24) & 0x0F) |
||
| 8219 | #define C_028C14_S15_X 0xF0FFFFFF |
||
| 8220 | #define S_028C14_S15_Y(x) (((x) & 0x0F) << 28) |
||
| 8221 | #define G_028C14_S15_Y(x) (((x) >> 28) & 0x0F) |
||
| 8222 | #define C_028C14_S15_Y 0x0FFFFFFF |
||
| 8223 | #define R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 0x028C18 |
||
| 8224 | #define S_028C18_S0_X(x) (((x) & 0x0F) << 0) |
||
| 8225 | #define G_028C18_S0_X(x) (((x) >> 0) & 0x0F) |
||
| 8226 | #define C_028C18_S0_X 0xFFFFFFF0 |
||
| 8227 | #define S_028C18_S0_Y(x) (((x) & 0x0F) << 4) |
||
| 8228 | #define G_028C18_S0_Y(x) (((x) >> 4) & 0x0F) |
||
| 8229 | #define C_028C18_S0_Y 0xFFFFFF0F |
||
| 8230 | #define S_028C18_S1_X(x) (((x) & 0x0F) << 8) |
||
| 8231 | #define G_028C18_S1_X(x) (((x) >> 8) & 0x0F) |
||
| 8232 | #define C_028C18_S1_X 0xFFFFF0FF |
||
| 8233 | #define S_028C18_S1_Y(x) (((x) & 0x0F) << 12) |
||
| 8234 | #define G_028C18_S1_Y(x) (((x) >> 12) & 0x0F) |
||
| 8235 | #define C_028C18_S1_Y 0xFFFF0FFF |
||
| 8236 | #define S_028C18_S2_X(x) (((x) & 0x0F) << 16) |
||
| 8237 | #define G_028C18_S2_X(x) (((x) >> 16) & 0x0F) |
||
| 8238 | #define C_028C18_S2_X 0xFFF0FFFF |
||
| 8239 | #define S_028C18_S2_Y(x) (((x) & 0x0F) << 20) |
||
| 8240 | #define G_028C18_S2_Y(x) (((x) >> 20) & 0x0F) |
||
| 8241 | #define C_028C18_S2_Y 0xFF0FFFFF |
||
| 8242 | #define S_028C18_S3_X(x) (((x) & 0x0F) << 24) |
||
| 8243 | #define G_028C18_S3_X(x) (((x) >> 24) & 0x0F) |
||
| 8244 | #define C_028C18_S3_X 0xF0FFFFFF |
||
| 8245 | #define S_028C18_S3_Y(x) (((x) & 0x0F) << 28) |
||
| 8246 | #define G_028C18_S3_Y(x) (((x) >> 28) & 0x0F) |
||
| 8247 | #define C_028C18_S3_Y 0x0FFFFFFF |
||
| 8248 | #define R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1 0x028C1C |
||
| 8249 | #define S_028C1C_S4_X(x) (((x) & 0x0F) << 0) |
||
| 8250 | #define G_028C1C_S4_X(x) (((x) >> 0) & 0x0F) |
||
| 8251 | #define C_028C1C_S4_X 0xFFFFFFF0 |
||
| 8252 | #define S_028C1C_S4_Y(x) (((x) & 0x0F) << 4) |
||
| 8253 | #define G_028C1C_S4_Y(x) (((x) >> 4) & 0x0F) |
||
| 8254 | #define C_028C1C_S4_Y 0xFFFFFF0F |
||
| 8255 | #define S_028C1C_S5_X(x) (((x) & 0x0F) << 8) |
||
| 8256 | #define G_028C1C_S5_X(x) (((x) >> 8) & 0x0F) |
||
| 8257 | #define C_028C1C_S5_X 0xFFFFF0FF |
||
| 8258 | #define S_028C1C_S5_Y(x) (((x) & 0x0F) << 12) |
||
| 8259 | #define G_028C1C_S5_Y(x) (((x) >> 12) & 0x0F) |
||
| 8260 | #define C_028C1C_S5_Y 0xFFFF0FFF |
||
| 8261 | #define S_028C1C_S6_X(x) (((x) & 0x0F) << 16) |
||
| 8262 | #define G_028C1C_S6_X(x) (((x) >> 16) & 0x0F) |
||
| 8263 | #define C_028C1C_S6_X 0xFFF0FFFF |
||
| 8264 | #define S_028C1C_S6_Y(x) (((x) & 0x0F) << 20) |
||
| 8265 | #define G_028C1C_S6_Y(x) (((x) >> 20) & 0x0F) |
||
| 8266 | #define C_028C1C_S6_Y 0xFF0FFFFF |
||
| 8267 | #define S_028C1C_S7_X(x) (((x) & 0x0F) << 24) |
||
| 8268 | #define G_028C1C_S7_X(x) (((x) >> 24) & 0x0F) |
||
| 8269 | #define C_028C1C_S7_X 0xF0FFFFFF |
||
| 8270 | #define S_028C1C_S7_Y(x) (((x) & 0x0F) << 28) |
||
| 8271 | #define G_028C1C_S7_Y(x) (((x) >> 28) & 0x0F) |
||
| 8272 | #define C_028C1C_S7_Y 0x0FFFFFFF |
||
| 8273 | #define R_028C20_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2 0x028C20 |
||
| 8274 | #define S_028C20_S8_X(x) (((x) & 0x0F) << 0) |
||
| 8275 | #define G_028C20_S8_X(x) (((x) >> 0) & 0x0F) |
||
| 8276 | #define C_028C20_S8_X 0xFFFFFFF0 |
||
| 8277 | #define S_028C20_S8_Y(x) (((x) & 0x0F) << 4) |
||
| 8278 | #define G_028C20_S8_Y(x) (((x) >> 4) & 0x0F) |
||
| 8279 | #define C_028C20_S8_Y 0xFFFFFF0F |
||
| 8280 | #define S_028C20_S9_X(x) (((x) & 0x0F) << 8) |
||
| 8281 | #define G_028C20_S9_X(x) (((x) >> 8) & 0x0F) |
||
| 8282 | #define C_028C20_S9_X 0xFFFFF0FF |
||
| 8283 | #define S_028C20_S9_Y(x) (((x) & 0x0F) << 12) |
||
| 8284 | #define G_028C20_S9_Y(x) (((x) >> 12) & 0x0F) |
||
| 8285 | #define C_028C20_S9_Y 0xFFFF0FFF |
||
| 8286 | #define S_028C20_S10_X(x) (((x) & 0x0F) << 16) |
||
| 8287 | #define G_028C20_S10_X(x) (((x) >> 16) & 0x0F) |
||
| 8288 | #define C_028C20_S10_X 0xFFF0FFFF |
||
| 8289 | #define S_028C20_S10_Y(x) (((x) & 0x0F) << 20) |
||
| 8290 | #define G_028C20_S10_Y(x) (((x) >> 20) & 0x0F) |
||
| 8291 | #define C_028C20_S10_Y 0xFF0FFFFF |
||
| 8292 | #define S_028C20_S11_X(x) (((x) & 0x0F) << 24) |
||
| 8293 | #define G_028C20_S11_X(x) (((x) >> 24) & 0x0F) |
||
| 8294 | #define C_028C20_S11_X 0xF0FFFFFF |
||
| 8295 | #define S_028C20_S11_Y(x) (((x) & 0x0F) << 28) |
||
| 8296 | #define G_028C20_S11_Y(x) (((x) >> 28) & 0x0F) |
||
| 8297 | #define C_028C20_S11_Y 0x0FFFFFFF |
||
| 8298 | #define R_028C24_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3 0x028C24 |
||
| 8299 | #define S_028C24_S12_X(x) (((x) & 0x0F) << 0) |
||
| 8300 | #define G_028C24_S12_X(x) (((x) >> 0) & 0x0F) |
||
| 8301 | #define C_028C24_S12_X 0xFFFFFFF0 |
||
| 8302 | #define S_028C24_S12_Y(x) (((x) & 0x0F) << 4) |
||
| 8303 | #define G_028C24_S12_Y(x) (((x) >> 4) & 0x0F) |
||
| 8304 | #define C_028C24_S12_Y 0xFFFFFF0F |
||
| 8305 | #define S_028C24_S13_X(x) (((x) & 0x0F) << 8) |
||
| 8306 | #define G_028C24_S13_X(x) (((x) >> 8) & 0x0F) |
||
| 8307 | #define C_028C24_S13_X 0xFFFFF0FF |
||
| 8308 | #define S_028C24_S13_Y(x) (((x) & 0x0F) << 12) |
||
| 8309 | #define G_028C24_S13_Y(x) (((x) >> 12) & 0x0F) |
||
| 8310 | #define C_028C24_S13_Y 0xFFFF0FFF |
||
| 8311 | #define S_028C24_S14_X(x) (((x) & 0x0F) << 16) |
||
| 8312 | #define G_028C24_S14_X(x) (((x) >> 16) & 0x0F) |
||
| 8313 | #define C_028C24_S14_X 0xFFF0FFFF |
||
| 8314 | #define S_028C24_S14_Y(x) (((x) & 0x0F) << 20) |
||
| 8315 | #define G_028C24_S14_Y(x) (((x) >> 20) & 0x0F) |
||
| 8316 | #define C_028C24_S14_Y 0xFF0FFFFF |
||
| 8317 | #define S_028C24_S15_X(x) (((x) & 0x0F) << 24) |
||
| 8318 | #define G_028C24_S15_X(x) (((x) >> 24) & 0x0F) |
||
| 8319 | #define C_028C24_S15_X 0xF0FFFFFF |
||
| 8320 | #define S_028C24_S15_Y(x) (((x) & 0x0F) << 28) |
||
| 8321 | #define G_028C24_S15_Y(x) (((x) >> 28) & 0x0F) |
||
| 8322 | #define C_028C24_S15_Y 0x0FFFFFFF |
||
| 8323 | #define R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 0x028C28 |
||
| 8324 | #define S_028C28_S0_X(x) (((x) & 0x0F) << 0) |
||
| 8325 | #define G_028C28_S0_X(x) (((x) >> 0) & 0x0F) |
||
| 8326 | #define C_028C28_S0_X 0xFFFFFFF0 |
||
| 8327 | #define S_028C28_S0_Y(x) (((x) & 0x0F) << 4) |
||
| 8328 | #define G_028C28_S0_Y(x) (((x) >> 4) & 0x0F) |
||
| 8329 | #define C_028C28_S0_Y 0xFFFFFF0F |
||
| 8330 | #define S_028C28_S1_X(x) (((x) & 0x0F) << 8) |
||
| 8331 | #define G_028C28_S1_X(x) (((x) >> 8) & 0x0F) |
||
| 8332 | #define C_028C28_S1_X 0xFFFFF0FF |
||
| 8333 | #define S_028C28_S1_Y(x) (((x) & 0x0F) << 12) |
||
| 8334 | #define G_028C28_S1_Y(x) (((x) >> 12) & 0x0F) |
||
| 8335 | #define C_028C28_S1_Y 0xFFFF0FFF |
||
| 8336 | #define S_028C28_S2_X(x) (((x) & 0x0F) << 16) |
||
| 8337 | #define G_028C28_S2_X(x) (((x) >> 16) & 0x0F) |
||
| 8338 | #define C_028C28_S2_X 0xFFF0FFFF |
||
| 8339 | #define S_028C28_S2_Y(x) (((x) & 0x0F) << 20) |
||
| 8340 | #define G_028C28_S2_Y(x) (((x) >> 20) & 0x0F) |
||
| 8341 | #define C_028C28_S2_Y 0xFF0FFFFF |
||
| 8342 | #define S_028C28_S3_X(x) (((x) & 0x0F) << 24) |
||
| 8343 | #define G_028C28_S3_X(x) (((x) >> 24) & 0x0F) |
||
| 8344 | #define C_028C28_S3_X 0xF0FFFFFF |
||
| 8345 | #define S_028C28_S3_Y(x) (((x) & 0x0F) << 28) |
||
| 8346 | #define G_028C28_S3_Y(x) (((x) >> 28) & 0x0F) |
||
| 8347 | #define C_028C28_S3_Y 0x0FFFFFFF |
||
| 8348 | #define R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1 0x028C2C |
||
| 8349 | #define S_028C2C_S4_X(x) (((x) & 0x0F) << 0) |
||
| 8350 | #define G_028C2C_S4_X(x) (((x) >> 0) & 0x0F) |
||
| 8351 | #define C_028C2C_S4_X 0xFFFFFFF0 |
||
| 8352 | #define S_028C2C_S4_Y(x) (((x) & 0x0F) << 4) |
||
| 8353 | #define G_028C2C_S4_Y(x) (((x) >> 4) & 0x0F) |
||
| 8354 | #define C_028C2C_S4_Y 0xFFFFFF0F |
||
| 8355 | #define S_028C2C_S5_X(x) (((x) & 0x0F) << 8) |
||
| 8356 | #define G_028C2C_S5_X(x) (((x) >> 8) & 0x0F) |
||
| 8357 | #define C_028C2C_S5_X 0xFFFFF0FF |
||
| 8358 | #define S_028C2C_S5_Y(x) (((x) & 0x0F) << 12) |
||
| 8359 | #define G_028C2C_S5_Y(x) (((x) >> 12) & 0x0F) |
||
| 8360 | #define C_028C2C_S5_Y 0xFFFF0FFF |
||
| 8361 | #define S_028C2C_S6_X(x) (((x) & 0x0F) << 16) |
||
| 8362 | #define G_028C2C_S6_X(x) (((x) >> 16) & 0x0F) |
||
| 8363 | #define C_028C2C_S6_X 0xFFF0FFFF |
||
| 8364 | #define S_028C2C_S6_Y(x) (((x) & 0x0F) << 20) |
||
| 8365 | #define G_028C2C_S6_Y(x) (((x) >> 20) & 0x0F) |
||
| 8366 | #define C_028C2C_S6_Y 0xFF0FFFFF |
||
| 8367 | #define S_028C2C_S7_X(x) (((x) & 0x0F) << 24) |
||
| 8368 | #define G_028C2C_S7_X(x) (((x) >> 24) & 0x0F) |
||
| 8369 | #define C_028C2C_S7_X 0xF0FFFFFF |
||
| 8370 | #define S_028C2C_S7_Y(x) (((x) & 0x0F) << 28) |
||
| 8371 | #define G_028C2C_S7_Y(x) (((x) >> 28) & 0x0F) |
||
| 8372 | #define C_028C2C_S7_Y 0x0FFFFFFF |
||
| 8373 | #define R_028C30_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2 0x028C30 |
||
| 8374 | #define S_028C30_S8_X(x) (((x) & 0x0F) << 0) |
||
| 8375 | #define G_028C30_S8_X(x) (((x) >> 0) & 0x0F) |
||
| 8376 | #define C_028C30_S8_X 0xFFFFFFF0 |
||
| 8377 | #define S_028C30_S8_Y(x) (((x) & 0x0F) << 4) |
||
| 8378 | #define G_028C30_S8_Y(x) (((x) >> 4) & 0x0F) |
||
| 8379 | #define C_028C30_S8_Y 0xFFFFFF0F |
||
| 8380 | #define S_028C30_S9_X(x) (((x) & 0x0F) << 8) |
||
| 8381 | #define G_028C30_S9_X(x) (((x) >> 8) & 0x0F) |
||
| 8382 | #define C_028C30_S9_X 0xFFFFF0FF |
||
| 8383 | #define S_028C30_S9_Y(x) (((x) & 0x0F) << 12) |
||
| 8384 | #define G_028C30_S9_Y(x) (((x) >> 12) & 0x0F) |
||
| 8385 | #define C_028C30_S9_Y 0xFFFF0FFF |
||
| 8386 | #define S_028C30_S10_X(x) (((x) & 0x0F) << 16) |
||
| 8387 | #define G_028C30_S10_X(x) (((x) >> 16) & 0x0F) |
||
| 8388 | #define C_028C30_S10_X 0xFFF0FFFF |
||
| 8389 | #define S_028C30_S10_Y(x) (((x) & 0x0F) << 20) |
||
| 8390 | #define G_028C30_S10_Y(x) (((x) >> 20) & 0x0F) |
||
| 8391 | #define C_028C30_S10_Y 0xFF0FFFFF |
||
| 8392 | #define S_028C30_S11_X(x) (((x) & 0x0F) << 24) |
||
| 8393 | #define G_028C30_S11_X(x) (((x) >> 24) & 0x0F) |
||
| 8394 | #define C_028C30_S11_X 0xF0FFFFFF |
||
| 8395 | #define S_028C30_S11_Y(x) (((x) & 0x0F) << 28) |
||
| 8396 | #define G_028C30_S11_Y(x) (((x) >> 28) & 0x0F) |
||
| 8397 | #define C_028C30_S11_Y 0x0FFFFFFF |
||
| 8398 | #define R_028C34_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3 0x028C34 |
||
| 8399 | #define S_028C34_S12_X(x) (((x) & 0x0F) << 0) |
||
| 8400 | #define G_028C34_S12_X(x) (((x) >> 0) & 0x0F) |
||
| 8401 | #define C_028C34_S12_X 0xFFFFFFF0 |
||
| 8402 | #define S_028C34_S12_Y(x) (((x) & 0x0F) << 4) |
||
| 8403 | #define G_028C34_S12_Y(x) (((x) >> 4) & 0x0F) |
||
| 8404 | #define C_028C34_S12_Y 0xFFFFFF0F |
||
| 8405 | #define S_028C34_S13_X(x) (((x) & 0x0F) << 8) |
||
| 8406 | #define G_028C34_S13_X(x) (((x) >> 8) & 0x0F) |
||
| 8407 | #define C_028C34_S13_X 0xFFFFF0FF |
||
| 8408 | #define S_028C34_S13_Y(x) (((x) & 0x0F) << 12) |
||
| 8409 | #define G_028C34_S13_Y(x) (((x) >> 12) & 0x0F) |
||
| 8410 | #define C_028C34_S13_Y 0xFFFF0FFF |
||
| 8411 | #define S_028C34_S14_X(x) (((x) & 0x0F) << 16) |
||
| 8412 | #define G_028C34_S14_X(x) (((x) >> 16) & 0x0F) |
||
| 8413 | #define C_028C34_S14_X 0xFFF0FFFF |
||
| 8414 | #define S_028C34_S14_Y(x) (((x) & 0x0F) << 20) |
||
| 8415 | #define G_028C34_S14_Y(x) (((x) >> 20) & 0x0F) |
||
| 8416 | #define C_028C34_S14_Y 0xFF0FFFFF |
||
| 8417 | #define S_028C34_S15_X(x) (((x) & 0x0F) << 24) |
||
| 8418 | #define G_028C34_S15_X(x) (((x) >> 24) & 0x0F) |
||
| 8419 | #define C_028C34_S15_X 0xF0FFFFFF |
||
| 8420 | #define S_028C34_S15_Y(x) (((x) & 0x0F) << 28) |
||
| 8421 | #define G_028C34_S15_Y(x) (((x) >> 28) & 0x0F) |
||
| 8422 | #define C_028C34_S15_Y 0x0FFFFFFF |
||
| 8423 | #define R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0 0x028C38 |
||
| 8424 | #define S_028C38_AA_MASK_X0Y0(x) (((x) & 0xFFFF) << 0) |
||
| 8425 | #define G_028C38_AA_MASK_X0Y0(x) (((x) >> 0) & 0xFFFF) |
||
| 8426 | #define C_028C38_AA_MASK_X0Y0 0xFFFF0000 |
||
| 8427 | #define S_028C38_AA_MASK_X1Y0(x) (((x) & 0xFFFF) << 16) |
||
| 8428 | #define G_028C38_AA_MASK_X1Y0(x) (((x) >> 16) & 0xFFFF) |
||
| 8429 | #define C_028C38_AA_MASK_X1Y0 0x0000FFFF |
||
| 8430 | #define R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1 0x028C3C |
||
| 8431 | #define S_028C3C_AA_MASK_X0Y1(x) (((x) & 0xFFFF) << 0) |
||
| 8432 | #define G_028C3C_AA_MASK_X0Y1(x) (((x) >> 0) & 0xFFFF) |
||
| 8433 | #define C_028C3C_AA_MASK_X0Y1 0xFFFF0000 |
||
| 8434 | #define S_028C3C_AA_MASK_X1Y1(x) (((x) & 0xFFFF) << 16) |
||
| 8435 | #define G_028C3C_AA_MASK_X1Y1(x) (((x) >> 16) & 0xFFFF) |
||
| 8436 | #define C_028C3C_AA_MASK_X1Y1 0x0000FFFF |
||
| 8437 | #define R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL 0x028C58 |
||
| 8438 | #define S_028C58_VTX_REUSE_DEPTH(x) (((x) & 0xFF) << 0) |
||
| 8439 | #define G_028C58_VTX_REUSE_DEPTH(x) (((x) >> 0) & 0xFF) |
||
| 8440 | #define C_028C58_VTX_REUSE_DEPTH 0xFFFFFF00 |
||
| 8441 | #define R_028C5C_VGT_OUT_DEALLOC_CNTL 0x028C5C |
||
| 8442 | #define S_028C5C_DEALLOC_DIST(x) (((x) & 0x7F) << 0) |
||
| 8443 | #define G_028C5C_DEALLOC_DIST(x) (((x) >> 0) & 0x7F) |
||
| 8444 | #define C_028C5C_DEALLOC_DIST 0xFFFFFF80 |
||
| 8445 | #define R_028C60_CB_COLOR0_BASE 0x028C60 |
||
| 8446 | #define R_028C64_CB_COLOR0_PITCH 0x028C64 |
||
| 8447 | #define S_028C64_TILE_MAX(x) (((x) & 0x7FF) << 0) |
||
| 8448 | #define G_028C64_TILE_MAX(x) (((x) >> 0) & 0x7FF) |
||
| 8449 | #define C_028C64_TILE_MAX 0xFFFFF800 |
||
| 8450 | /* CIK */ |
||
| 8451 | #define S_028C64_FMASK_TILE_MAX(x) (((x) & 0x7FF) << 20) |
||
| 8452 | #define G_028C64_FMASK_TILE_MAX(x) (((x) >> 20) & 0x7FF) |
||
| 8453 | #define C_028C64_FMASK_TILE_MAX 0x800FFFFF |
||
| 8454 | /* */ |
||
| 8455 | #define R_028C68_CB_COLOR0_SLICE 0x028C68 |
||
| 8456 | #define S_028C68_TILE_MAX(x) (((x) & 0x3FFFFF) << 0) |
||
| 8457 | #define G_028C68_TILE_MAX(x) (((x) >> 0) & 0x3FFFFF) |
||
| 8458 | #define C_028C68_TILE_MAX 0xFFC00000 |
||
| 8459 | #define R_028C6C_CB_COLOR0_VIEW 0x028C6C |
||
| 8460 | #define S_028C6C_SLICE_START(x) (((x) & 0x7FF) << 0) |
||
| 8461 | #define G_028C6C_SLICE_START(x) (((x) >> 0) & 0x7FF) |
||
| 8462 | #define C_028C6C_SLICE_START 0xFFFFF800 |
||
| 8463 | #define S_028C6C_SLICE_MAX(x) (((x) & 0x7FF) << 13) |
||
| 8464 | #define G_028C6C_SLICE_MAX(x) (((x) >> 13) & 0x7FF) |
||
| 8465 | #define C_028C6C_SLICE_MAX 0xFF001FFF |
||
| 8466 | #define R_028C70_CB_COLOR0_INFO 0x028C70 |
||
| 8467 | #define S_028C70_ENDIAN(x) (((x) & 0x03) << 0) |
||
| 8468 | #define G_028C70_ENDIAN(x) (((x) >> 0) & 0x03) |
||
| 8469 | #define C_028C70_ENDIAN 0xFFFFFFFC |
||
| 8470 | #define V_028C70_ENDIAN_NONE 0x00 |
||
| 8471 | #define V_028C70_ENDIAN_8IN16 0x01 |
||
| 8472 | #define V_028C70_ENDIAN_8IN32 0x02 |
||
| 8473 | #define V_028C70_ENDIAN_8IN64 0x03 |
||
| 8474 | #define S_028C70_FORMAT(x) (((x) & 0x1F) << 2) |
||
| 8475 | #define G_028C70_FORMAT(x) (((x) >> 2) & 0x1F) |
||
| 8476 | #define C_028C70_FORMAT 0xFFFFFF83 |
||
| 8477 | #define V_028C70_COLOR_INVALID 0x00 |
||
| 8478 | #define V_028C70_COLOR_8 0x01 |
||
| 8479 | #define V_028C70_COLOR_16 0x02 |
||
| 8480 | #define V_028C70_COLOR_8_8 0x03 |
||
| 8481 | #define V_028C70_COLOR_32 0x04 |
||
| 8482 | #define V_028C70_COLOR_16_16 0x05 |
||
| 8483 | #define V_028C70_COLOR_10_11_11 0x06 |
||
| 8484 | #define V_028C70_COLOR_11_11_10 0x07 |
||
| 8485 | #define V_028C70_COLOR_10_10_10_2 0x08 |
||
| 8486 | #define V_028C70_COLOR_2_10_10_10 0x09 |
||
| 8487 | #define V_028C70_COLOR_8_8_8_8 0x0A |
||
| 8488 | #define V_028C70_COLOR_32_32 0x0B |
||
| 8489 | #define V_028C70_COLOR_16_16_16_16 0x0C |
||
| 8490 | #define V_028C70_COLOR_32_32_32_32 0x0E |
||
| 8491 | #define V_028C70_COLOR_5_6_5 0x10 |
||
| 8492 | #define V_028C70_COLOR_1_5_5_5 0x11 |
||
| 8493 | #define V_028C70_COLOR_5_5_5_1 0x12 |
||
| 8494 | #define V_028C70_COLOR_4_4_4_4 0x13 |
||
| 8495 | #define V_028C70_COLOR_8_24 0x14 |
||
| 8496 | #define V_028C70_COLOR_24_8 0x15 |
||
| 8497 | #define V_028C70_COLOR_X24_8_32_FLOAT 0x16 |
||
| 8498 | #define S_028C70_LINEAR_GENERAL(x) (((x) & 0x1) << 7) |
||
| 8499 | #define G_028C70_LINEAR_GENERAL(x) (((x) >> 7) & 0x1) |
||
| 8500 | #define C_028C70_LINEAR_GENERAL 0xFFFFFF7F |
||
| 8501 | #define S_028C70_NUMBER_TYPE(x) (((x) & 0x07) << 8) |
||
| 8502 | #define G_028C70_NUMBER_TYPE(x) (((x) >> 8) & 0x07) |
||
| 8503 | #define C_028C70_NUMBER_TYPE 0xFFFFF8FF |
||
| 8504 | #define V_028C70_NUMBER_UNORM 0x00 |
||
| 8505 | #define V_028C70_NUMBER_SNORM 0x01 |
||
| 8506 | #define V_028C70_NUMBER_UINT 0x04 |
||
| 8507 | #define V_028C70_NUMBER_SINT 0x05 |
||
| 8508 | #define V_028C70_NUMBER_SRGB 0x06 |
||
| 8509 | #define V_028C70_NUMBER_FLOAT 0x07 |
||
| 8510 | #define S_028C70_COMP_SWAP(x) (((x) & 0x03) << 11) |
||
| 8511 | #define G_028C70_COMP_SWAP(x) (((x) >> 11) & 0x03) |
||
| 8512 | #define C_028C70_COMP_SWAP 0xFFFFE7FF |
||
| 8513 | #define V_028C70_SWAP_STD 0x00 |
||
| 8514 | #define V_028C70_SWAP_ALT 0x01 |
||
| 8515 | #define V_028C70_SWAP_STD_REV 0x02 |
||
| 8516 | #define V_028C70_SWAP_ALT_REV 0x03 |
||
| 8517 | #define S_028C70_FAST_CLEAR(x) (((x) & 0x1) << 13) |
||
| 8518 | #define G_028C70_FAST_CLEAR(x) (((x) >> 13) & 0x1) |
||
| 8519 | #define C_028C70_FAST_CLEAR 0xFFFFDFFF |
||
| 8520 | #define S_028C70_COMPRESSION(x) (((x) & 0x1) << 14) |
||
| 8521 | #define G_028C70_COMPRESSION(x) (((x) >> 14) & 0x1) |
||
| 8522 | #define C_028C70_COMPRESSION 0xFFFFBFFF |
||
| 8523 | #define S_028C70_BLEND_CLAMP(x) (((x) & 0x1) << 15) |
||
| 8524 | #define G_028C70_BLEND_CLAMP(x) (((x) >> 15) & 0x1) |
||
| 8525 | #define C_028C70_BLEND_CLAMP 0xFFFF7FFF |
||
| 8526 | #define S_028C70_BLEND_BYPASS(x) (((x) & 0x1) << 16) |
||
| 8527 | #define G_028C70_BLEND_BYPASS(x) (((x) >> 16) & 0x1) |
||
| 8528 | #define C_028C70_BLEND_BYPASS 0xFFFEFFFF |
||
| 8529 | #define S_028C70_SIMPLE_FLOAT(x) (((x) & 0x1) << 17) |
||
| 8530 | #define G_028C70_SIMPLE_FLOAT(x) (((x) >> 17) & 0x1) |
||
| 8531 | #define C_028C70_SIMPLE_FLOAT 0xFFFDFFFF |
||
| 8532 | #define S_028C70_ROUND_MODE(x) (((x) & 0x1) << 18) |
||
| 8533 | #define G_028C70_ROUND_MODE(x) (((x) >> 18) & 0x1) |
||
| 8534 | #define C_028C70_ROUND_MODE 0xFFFBFFFF |
||
| 8535 | #define S_028C70_CMASK_IS_LINEAR(x) (((x) & 0x1) << 19) |
||
| 8536 | #define G_028C70_CMASK_IS_LINEAR(x) (((x) >> 19) & 0x1) |
||
| 8537 | #define C_028C70_CMASK_IS_LINEAR 0xFFF7FFFF |
||
| 8538 | #define S_028C70_BLEND_OPT_DONT_RD_DST(x) (((x) & 0x07) << 20) |
||
| 8539 | #define G_028C70_BLEND_OPT_DONT_RD_DST(x) (((x) >> 20) & 0x07) |
||
| 8540 | #define C_028C70_BLEND_OPT_DONT_RD_DST 0xFF8FFFFF |
||
| 8541 | #define V_028C70_FORCE_OPT_AUTO 0x00 |
||
| 8542 | #define V_028C70_FORCE_OPT_DISABLE 0x01 |
||
| 8543 | #define V_028C70_FORCE_OPT_ENABLE_IF_SRC_A_0 0x02 |
||
| 8544 | #define V_028C70_FORCE_OPT_ENABLE_IF_SRC_RGB_0 0x03 |
||
| 8545 | #define V_028C70_FORCE_OPT_ENABLE_IF_SRC_ARGB_0 0x04 |
||
| 8546 | #define V_028C70_FORCE_OPT_ENABLE_IF_SRC_A_1 0x05 |
||
| 8547 | #define V_028C70_FORCE_OPT_ENABLE_IF_SRC_RGB_1 0x06 |
||
| 8548 | #define V_028C70_FORCE_OPT_ENABLE_IF_SRC_ARGB_1 0x07 |
||
| 8549 | #define S_028C70_BLEND_OPT_DISCARD_PIXEL(x) (((x) & 0x07) << 23) |
||
| 8550 | #define G_028C70_BLEND_OPT_DISCARD_PIXEL(x) (((x) >> 23) & 0x07) |
||
| 8551 | #define C_028C70_BLEND_OPT_DISCARD_PIXEL 0xFC7FFFFF |
||
| 8552 | #define V_028C70_FORCE_OPT_AUTO 0x00 |
||
| 8553 | #define V_028C70_FORCE_OPT_DISABLE 0x01 |
||
| 8554 | #define V_028C70_FORCE_OPT_ENABLE_IF_SRC_A_0 0x02 |
||
| 8555 | #define V_028C70_FORCE_OPT_ENABLE_IF_SRC_RGB_0 0x03 |
||
| 8556 | #define V_028C70_FORCE_OPT_ENABLE_IF_SRC_ARGB_0 0x04 |
||
| 8557 | #define V_028C70_FORCE_OPT_ENABLE_IF_SRC_A_1 0x05 |
||
| 8558 | #define V_028C70_FORCE_OPT_ENABLE_IF_SRC_RGB_1 0x06 |
||
| 8559 | #define V_028C70_FORCE_OPT_ENABLE_IF_SRC_ARGB_1 0x07 |
||
| 8560 | /* CIK */ |
||
| 8561 | #define S_028C70_FMASK_COMPRESSION_DISABLE(x) (((x) & 0x1) << 26) |
||
| 8562 | #define G_028C70_FMASK_COMPRESSION_DISABLE(x) (((x) >> 26) & 0x1) |
||
| 8563 | #define C_028C70_FMASK_COMPRESSION_DISABLE 0xFBFFFFFF |
||
| 8564 | /* */ |
||
| 8565 | #define R_028C74_CB_COLOR0_ATTRIB 0x028C74 |
||
| 8566 | #define S_028C74_TILE_MODE_INDEX(x) (((x) & 0x1F) << 0) |
||
| 8567 | #define G_028C74_TILE_MODE_INDEX(x) (((x) >> 0) & 0x1F) |
||
| 8568 | #define C_028C74_TILE_MODE_INDEX 0xFFFFFFE0 |
||
| 8569 | #define S_028C74_FMASK_TILE_MODE_INDEX(x) (((x) & 0x1F) << 5) |
||
| 8570 | #define G_028C74_FMASK_TILE_MODE_INDEX(x) (((x) >> 5) & 0x1F) |
||
| 8571 | #define C_028C74_FMASK_TILE_MODE_INDEX 0xFFFFFC1F |
||
| 8572 | #define S_028C74_FMASK_BANK_HEIGHT(x) (((x) & 0x3) << 10) /* SI errata */ |
||
| 8573 | #define S_028C74_NUM_SAMPLES(x) (((x) & 0x07) << 12) |
||
| 8574 | #define G_028C74_NUM_SAMPLES(x) (((x) >> 12) & 0x07) |
||
| 8575 | #define C_028C74_NUM_SAMPLES 0xFFFF8FFF |
||
| 8576 | #define S_028C74_NUM_FRAGMENTS(x) (((x) & 0x03) << 15) |
||
| 8577 | #define G_028C74_NUM_FRAGMENTS(x) (((x) >> 15) & 0x03) |
||
| 8578 | #define C_028C74_NUM_FRAGMENTS 0xFFFE7FFF |
||
| 8579 | #define S_028C74_FORCE_DST_ALPHA_1(x) (((x) & 0x1) << 17) |
||
| 8580 | #define G_028C74_FORCE_DST_ALPHA_1(x) (((x) >> 17) & 0x1) |
||
| 8581 | #define C_028C74_FORCE_DST_ALPHA_1 0xFFFDFFFF |
||
| 8582 | #define R_028C7C_CB_COLOR0_CMASK 0x028C7C |
||
| 8583 | #define R_028C80_CB_COLOR0_CMASK_SLICE 0x028C80 |
||
| 8584 | #define S_028C80_TILE_MAX(x) (((x) & 0x3FFF) << 0) |
||
| 8585 | #define G_028C80_TILE_MAX(x) (((x) >> 0) & 0x3FFF) |
||
| 8586 | #define C_028C80_TILE_MAX 0xFFFFC000 |
||
| 8587 | #define R_028C84_CB_COLOR0_FMASK 0x028C84 |
||
| 8588 | #define R_028C88_CB_COLOR0_FMASK_SLICE 0x028C88 |
||
| 8589 | #define S_028C88_TILE_MAX(x) (((x) & 0x3FFFFF) << 0) |
||
| 8590 | #define G_028C88_TILE_MAX(x) (((x) >> 0) & 0x3FFFFF) |
||
| 8591 | #define C_028C88_TILE_MAX 0xFFC00000 |
||
| 8592 | #define R_028C8C_CB_COLOR0_CLEAR_WORD0 0x028C8C |
||
| 8593 | #define R_028C90_CB_COLOR0_CLEAR_WORD1 0x028C90 |
||
| 8594 | #define R_028C9C_CB_COLOR1_BASE 0x028C9C |
||
| 8595 | #define R_028CA0_CB_COLOR1_PITCH 0x028CA0 |
||
| 8596 | #define R_028CA4_CB_COLOR1_SLICE 0x028CA4 |
||
| 8597 | #define R_028CA8_CB_COLOR1_VIEW 0x028CA8 |
||
| 8598 | #define R_028CAC_CB_COLOR1_INFO 0x028CAC |
||
| 8599 | #define R_028CB0_CB_COLOR1_ATTRIB 0x028CB0 |
||
| 8600 | #define R_028CD4_CB_COLOR1_CMASK 0x028CB8 |
||
| 8601 | #define R_028CBC_CB_COLOR1_CMASK_SLICE 0x028CBC |
||
| 8602 | #define R_028CC0_CB_COLOR1_FMASK 0x028CC0 |
||
| 8603 | #define R_028CC4_CB_COLOR1_FMASK_SLICE 0x028CC4 |
||
| 8604 | #define R_028CC8_CB_COLOR1_CLEAR_WORD0 0x028CC8 |
||
| 8605 | #define R_028CCC_CB_COLOR1_CLEAR_WORD1 0x028CCC |
||
| 8606 | #define R_028CD8_CB_COLOR2_BASE 0x028CD8 |
||
| 8607 | #define R_028CDC_CB_COLOR2_PITCH 0x028CDC |
||
| 8608 | #define R_028CE0_CB_COLOR2_SLICE 0x028CE0 |
||
| 8609 | #define R_028CE4_CB_COLOR2_VIEW 0x028CE4 |
||
| 8610 | #define R_028CE8_CB_COLOR2_INFO 0x028CE8 |
||
| 8611 | #define R_028CEC_CB_COLOR2_ATTRIB 0x028CEC |
||
| 8612 | #define R_028CF4_CB_COLOR2_CMASK 0x028CF4 |
||
| 8613 | #define R_028CF8_CB_COLOR2_CMASK_SLICE 0x028CF8 |
||
| 8614 | #define R_028CFC_CB_COLOR2_FMASK 0x028CFC |
||
| 8615 | #define R_028D00_CB_COLOR2_FMASK_SLICE 0x028D00 |
||
| 8616 | #define R_028D04_CB_COLOR2_CLEAR_WORD0 0x028D04 |
||
| 8617 | #define R_028D08_CB_COLOR2_CLEAR_WORD1 0x028D08 |
||
| 8618 | #define R_028D14_CB_COLOR3_BASE 0x028D14 |
||
| 8619 | #define R_028D18_CB_COLOR3_PITCH 0x028D18 |
||
| 8620 | #define R_028D1C_CB_COLOR3_SLICE 0x028D1C |
||
| 8621 | #define R_028D20_CB_COLOR3_VIEW 0x028D20 |
||
| 8622 | #define R_028D24_CB_COLOR3_INFO 0x028D24 |
||
| 8623 | #define R_028D28_CB_COLOR3_ATTRIB 0x028D28 |
||
| 8624 | #define R_028D30_CB_COLOR3_CMASK 0x028D30 |
||
| 8625 | #define R_028D34_CB_COLOR3_CMASK_SLICE 0x028D34 |
||
| 8626 | #define R_028D38_CB_COLOR3_FMASK 0x028D38 |
||
| 8627 | #define R_028D3C_CB_COLOR3_FMASK_SLICE 0x028D3C |
||
| 8628 | #define R_028D40_CB_COLOR3_CLEAR_WORD0 0x028D40 |
||
| 8629 | #define R_028D44_CB_COLOR3_CLEAR_WORD1 0x028D44 |
||
| 8630 | #define R_028D50_CB_COLOR4_BASE 0x028D50 |
||
| 8631 | #define R_028D54_CB_COLOR4_PITCH 0x028D54 |
||
| 8632 | #define R_028D58_CB_COLOR4_SLICE 0x028D58 |
||
| 8633 | #define R_028D5C_CB_COLOR4_VIEW 0x028D5C |
||
| 8634 | #define R_028D60_CB_COLOR4_INFO 0x028D60 |
||
| 8635 | #define R_028D64_CB_COLOR4_ATTRIB 0x028D64 |
||
| 8636 | #define R_028D6C_CB_COLOR4_CMASK 0x028D6C |
||
| 8637 | #define R_028D70_CB_COLOR4_CMASK_SLICE 0x028D70 |
||
| 8638 | #define R_028D74_CB_COLOR4_FMASK 0x028D74 |
||
| 8639 | #define R_028D78_CB_COLOR4_FMASK_SLICE 0x028D78 |
||
| 8640 | #define R_028D7C_CB_COLOR4_CLEAR_WORD0 0x028D7C |
||
| 8641 | #define R_028D80_CB_COLOR4_CLEAR_WORD1 0x028D80 |
||
| 8642 | #define R_028D8C_CB_COLOR5_BASE 0x028D8C |
||
| 8643 | #define R_028D90_CB_COLOR5_PITCH 0x028D90 |
||
| 8644 | #define R_028D94_CB_COLOR5_SLICE 0x028D94 |
||
| 8645 | #define R_028D98_CB_COLOR5_VIEW 0x028D98 |
||
| 8646 | #define R_028D9C_CB_COLOR5_INFO 0x028D9C |
||
| 8647 | #define R_028DA0_CB_COLOR5_ATTRIB 0x028DA0 |
||
| 8648 | #define R_028DA8_CB_COLOR5_CMASK 0x028DA8 |
||
| 8649 | #define R_028DAC_CB_COLOR5_CMASK_SLICE 0x028DAC |
||
| 8650 | #define R_028DB0_CB_COLOR5_FMASK 0x028DB0 |
||
| 8651 | #define R_028DB4_CB_COLOR5_FMASK_SLICE 0x028DB4 |
||
| 8652 | #define R_028DB8_CB_COLOR5_CLEAR_WORD0 0x028DB8 |
||
| 8653 | #define R_028DBC_CB_COLOR5_CLEAR_WORD1 0x028DBC |
||
| 8654 | #define R_028DC8_CB_COLOR6_BASE 0x028DC8 |
||
| 8655 | #define R_028DCC_CB_COLOR6_PITCH 0x028DCC |
||
| 8656 | #define R_028DD0_CB_COLOR6_SLICE 0x028DD0 |
||
| 8657 | #define R_028DD4_CB_COLOR6_VIEW 0x028DD4 |
||
| 8658 | #define R_028DD8_CB_COLOR6_INFO 0x028DD8 |
||
| 8659 | #define R_028DDC_CB_COLOR6_ATTRIB 0x028DDC |
||
| 8660 | #define R_028DE4_CB_COLOR6_CMASK 0x028DE4 |
||
| 8661 | #define R_028DE8_CB_COLOR6_CMASK_SLICE 0x028DE8 |
||
| 8662 | #define R_028DEC_CB_COLOR6_FMASK 0x028DEC |
||
| 8663 | #define R_028DF0_CB_COLOR6_FMASK_SLICE 0x028DF0 |
||
| 8664 | #define R_028DF4_CB_COLOR6_CLEAR_WORD0 0x028DF4 |
||
| 8665 | #define R_028DF8_CB_COLOR6_CLEAR_WORD1 0x028DF8 |
||
| 8666 | #define R_028E04_CB_COLOR7_BASE 0x028E04 |
||
| 8667 | #define R_028E08_CB_COLOR7_PITCH 0x028E08 |
||
| 8668 | #define R_028E0C_CB_COLOR7_SLICE 0x028E0C |
||
| 8669 | #define R_028E10_CB_COLOR7_VIEW 0x028E10 |
||
| 8670 | #define R_028E14_CB_COLOR7_INFO 0x028E14 |
||
| 8671 | #define R_028E18_CB_COLOR7_ATTRIB 0x028E18 |
||
| 8672 | #define R_028E20_CB_COLOR7_CMASK 0x028E20 |
||
| 8673 | #define R_028E24_CB_COLOR7_CMASK_SLICE 0x028E24 |
||
| 8674 | #define R_028E28_CB_COLOR7_FMASK 0x028E28 |
||
| 8675 | #define R_028E2C_CB_COLOR7_FMASK_SLICE 0x028E2C |
||
| 8676 | #define R_028E30_CB_COLOR7_CLEAR_WORD0 0x028E30 |
||
| 8677 | #define R_028E34_CB_COLOR7_CLEAR_WORD1 0x028E34 |
||
| 8678 | |||
| 8679 | /* SI async DMA packets */ |
||
| 8680 | #define SI_DMA_PACKET(cmd, sub_cmd, n) ((((cmd) & 0xF) << 28) | \ |
||
| 8681 | (((sub_cmd) & 0xFF) << 20) |\ |
||
| 8682 | (((n) & 0xFFFFF) << 0)) |
||
| 8683 | /* SI async DMA Packet types */ |
||
| 8684 | #define SI_DMA_PACKET_WRITE 0x2 |
||
| 8685 | #define SI_DMA_PACKET_COPY 0x3 |
||
| 8686 | #define SI_DMA_COPY_MAX_SIZE 0xfffe0 |
||
| 8687 | #define SI_DMA_COPY_MAX_SIZE_DW 0xffff8 |
||
| 8688 | #define SI_DMA_COPY_DWORD_ALIGNED 0x00 |
||
| 8689 | #define SI_DMA_COPY_BYTE_ALIGNED 0x40 |
||
| 8690 | #define SI_DMA_COPY_TILED 0x8 |
||
| 8691 | #define SI_DMA_PACKET_INDIRECT_BUFFER 0x4 |
||
| 8692 | #define SI_DMA_PACKET_SEMAPHORE 0x5 |
||
| 8693 | #define SI_DMA_PACKET_FENCE 0x6 |
||
| 8694 | #define SI_DMA_PACKET_TRAP 0x7 |
||
| 8695 | #define SI_DMA_PACKET_SRBM_WRITE 0x9 |
||
| 8696 | #define SI_DMA_PACKET_CONSTANT_FILL 0xd |
||
| 8697 | #define SI_DMA_PACKET_NOP 0xf |
||
| 8698 | |||
| 8699 | #endif /* _SID_H */ |
||
| 8700 |