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5564 serge 1
/**************************************************************************
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 *
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 * Copyright 2011 Advanced Micro Devices, Inc.
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 * All Rights Reserved.
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a
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 * copy of this software and associated documentation files (the
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 * "Software"), to deal in the Software without restriction, including
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 * without limitation the rights to use, copy, modify, merge, publish,
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 * distribute, sub license, and/or sell copies of the Software, and to
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 * permit persons to whom the Software is furnished to do so, subject to
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 * the following conditions:
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 *
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 * The above copyright notice and this permission notice (including the
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 * next paragraph) shall be included in all copies or substantial portions
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 * of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
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 * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
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 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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 *
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 **************************************************************************/
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/*
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 * Authors:
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 *      Christian König 
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 *
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 */
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#include "si_pipe.h"
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#include "radeon/radeon_video.h"
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#include "radeon/radeon_uvd.h"
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#include "radeon/radeon_vce.h"
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/**
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 * creates an video buffer with an UVD compatible memory layout
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 */
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struct pipe_video_buffer *si_video_buffer_create(struct pipe_context *pipe,
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						 const struct pipe_video_buffer *tmpl)
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{
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	struct si_context *ctx = (struct si_context *)pipe;
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	struct r600_texture *resources[VL_NUM_COMPONENTS] = {};
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	struct radeon_surf *surfaces[VL_NUM_COMPONENTS] = {};
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	struct pb_buffer **pbs[VL_NUM_COMPONENTS] = {};
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	const enum pipe_format *resource_formats;
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	struct pipe_video_buffer template;
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	struct pipe_resource templ;
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	unsigned i, array_size;
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	assert(pipe);
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	/* first create the needed resources as "normal" textures */
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	resource_formats = vl_video_buffer_formats(pipe->screen, tmpl->buffer_format);
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	if (!resource_formats)
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		return NULL;
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	array_size = tmpl->interlaced ? 2 : 1;
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	template = *tmpl;
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	template.width = align(tmpl->width, VL_MACROBLOCK_WIDTH);
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	template.height = align(tmpl->height / array_size, VL_MACROBLOCK_HEIGHT);
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	vl_video_buffer_template(&templ, &template, resource_formats[0], 1, array_size, PIPE_USAGE_DEFAULT, 0);
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	/* TODO: get tiling working */
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	templ.bind = PIPE_BIND_LINEAR;
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	resources[0] = (struct r600_texture *)
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		pipe->screen->resource_create(pipe->screen, &templ);
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	if (!resources[0])
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		goto error;
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	if (resource_formats[1] != PIPE_FORMAT_NONE) {
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		vl_video_buffer_template(&templ, &template, resource_formats[1], 1, array_size, PIPE_USAGE_DEFAULT, 1);
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		templ.bind = PIPE_BIND_LINEAR;
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		resources[1] = (struct r600_texture *)
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			pipe->screen->resource_create(pipe->screen, &templ);
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		if (!resources[1])
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			goto error;
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	}
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	if (resource_formats[2] != PIPE_FORMAT_NONE) {
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		vl_video_buffer_template(&templ, &template, resource_formats[2], 1, array_size, PIPE_USAGE_DEFAULT, 2);
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		templ.bind = PIPE_BIND_LINEAR;
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		resources[2] = (struct r600_texture *)
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			pipe->screen->resource_create(pipe->screen, &templ);
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		if (!resources[2])
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			goto error;
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	}
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	for (i = 0; i < VL_NUM_COMPONENTS; ++i) {
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		if (!resources[i])
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			continue;
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		surfaces[i] = & resources[i]->surface;
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		pbs[i] = &resources[i]->resource.buf;
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	}
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	rvid_join_surfaces(ctx->b.ws, templ.bind, pbs, surfaces);
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	for (i = 0; i < VL_NUM_COMPONENTS; ++i) {
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		if (!resources[i])
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			continue;
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		/* recreate the CS handle */
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		resources[i]->resource.cs_buf = ctx->b.ws->buffer_get_cs_handle(
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			resources[i]->resource.buf);
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		resources[i]->resource.gpu_address = ctx->b.ws->buffer_get_virtual_address(
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			resources[i]->resource.cs_buf);
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	}
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	template.height *= array_size;
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	return vl_video_buffer_create_ex2(pipe, &template, (struct pipe_resource **)resources);
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error:
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	for (i = 0; i < VL_NUM_COMPONENTS; ++i)
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		pipe_resource_reference((struct pipe_resource **)&resources[i], NULL);
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	return NULL;
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}
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/* set the decoding target buffer offsets */
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static struct radeon_winsys_cs_handle* si_uvd_set_dtb(struct ruvd_msg *msg, struct vl_video_buffer *buf)
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{
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	struct r600_texture *luma = (struct r600_texture *)buf->resources[0];
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	struct r600_texture *chroma = (struct r600_texture *)buf->resources[1];
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	msg->body.decode.dt_field_mode = buf->base.interlaced;
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	ruvd_set_dt_surfaces(msg, &luma->surface, &chroma->surface);
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	return luma->resource.cs_buf;
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}
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/* get the radeon resources for VCE */
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static void si_vce_get_buffer(struct pipe_resource *resource,
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			      struct radeon_winsys_cs_handle **handle,
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			      struct radeon_surf **surface)
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{
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	struct r600_texture *res = (struct r600_texture *)resource;
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	if (handle)
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		*handle = res->resource.cs_buf;
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	if (surface)
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		*surface = &res->surface;
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}
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/**
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 * creates an UVD compatible decoder
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 */
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struct pipe_video_codec *si_uvd_create_decoder(struct pipe_context *context,
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					       const struct pipe_video_codec *templ)
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{
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	struct si_context *ctx = (struct si_context *)context;
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158
        if (templ->entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE)
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                return rvce_create_encoder(context, templ, ctx->b.ws, si_vce_get_buffer);
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	return ruvd_create_decoder(context, templ, si_uvd_set_dtb);
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}