WebSVN – Kolibri OS – Blame – /contrib/sdk/sources/Mesa/mesa-10.6.0/src/gallium/drivers/radeon/radeon_winsys.h

Rev	Author	Line No.	Line
5564	serge	1	/*
		2	* Copyright 2008 Corbin Simpson
		3	* Copyright 2010 Marek Olšák
		4	*
		5	* Permission is hereby granted, free of charge, to any person obtaining a
		6	* copy of this software and associated documentation files (the "Software"),
		7	* to deal in the Software without restriction, including without limitation
		8	* on the rights to use, copy, modify, merge, publish, distribute, sub
		9	* license, and/or sell copies of the Software, and to permit persons to whom
		10	* the Software is furnished to do so, subject to the following conditions:
		11	*
		12	* The above copyright notice and this permission notice (including the next
		13	* paragraph) shall be included in all copies or substantial portions of the
		14	* Software.
		15	*
		16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		18	* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
		19	* THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
		20	* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
		21	* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
		22	* USE OR OTHER DEALINGS IN THE SOFTWARE. */
		23
		24	#ifndef RADEON_WINSYS_H
		25	#define RADEON_WINSYS_H
		26
		27	/* The public winsys interface header for the radeon driver. */
		28
		29	/* R300 features in DRM.
		30	*
		31	* 2.6.0:
		32	* - Hyper-Z
		33	* - GB_Z_PEQ_CONFIG on rv350->r4xx
		34	* - R500 FG_ALPHA_VALUE
		35	*
		36	* 2.8.0:
		37	* - R500 US_FORMAT regs
		38	* - R500 ARGB2101010 colorbuffer
		39	* - CMask and AA regs
		40	* - R16F/RG16F
		41	*/
		42
		43	#include "pipebuffer/pb_buffer.h"
		44
		45	#define RADEON_MAX_CMDBUF_DWORDS (16 * 1024)
		46
		47	#define RADEON_FLUSH_ASYNC (1 << 0)
		48	#define RADEON_FLUSH_KEEP_TILING_FLAGS (1 << 1) /* needs DRM 2.12.0 */
		49	#define RADEON_FLUSH_COMPUTE (1 << 2)
		50	#define RADEON_FLUSH_END_OF_FRAME (1 << 3)
		51
		52	/* Tiling flags. */
		53	enum radeon_bo_layout {
		54	RADEON_LAYOUT_LINEAR = 0,
		55	RADEON_LAYOUT_TILED,
		56	RADEON_LAYOUT_SQUARETILED,
		57
		58	RADEON_LAYOUT_UNKNOWN
		59	};
		60
		61	enum radeon_bo_domain { /* bitfield */
		62	RADEON_DOMAIN_GTT = 2,
		63	RADEON_DOMAIN_VRAM = 4,
		64	RADEON_DOMAIN_VRAM_GTT = RADEON_DOMAIN_VRAM \| RADEON_DOMAIN_GTT
		65	};
		66
		67	enum radeon_bo_flag { /* bitfield */
		68	RADEON_FLAG_GTT_WC = (1 << 0),
		69	RADEON_FLAG_CPU_ACCESS = (1 << 1),
		70	RADEON_FLAG_NO_CPU_ACCESS = (1 << 2),
		71	};
		72
		73	enum radeon_bo_usage { /* bitfield */
		74	RADEON_USAGE_READ = 2,
		75	RADEON_USAGE_WRITE = 4,
		76	RADEON_USAGE_READWRITE = RADEON_USAGE_READ \| RADEON_USAGE_WRITE
		77	};
		78
		79	enum radeon_family {
		80	CHIP_UNKNOWN = 0,
		81	CHIP_R300, /* R3xx-based cores. */
		82	CHIP_R350,
		83	CHIP_RV350,
		84	CHIP_RV370,
		85	CHIP_RV380,
		86	CHIP_RS400,
		87	CHIP_RC410,
		88	CHIP_RS480,
		89	CHIP_R420, /* R4xx-based cores. */
		90	CHIP_R423,
		91	CHIP_R430,
		92	CHIP_R480,
		93	CHIP_R481,
		94	CHIP_RV410,
		95	CHIP_RS600,
		96	CHIP_RS690,
		97	CHIP_RS740,
		98	CHIP_RV515, /* R5xx-based cores. */
		99	CHIP_R520,
		100	CHIP_RV530,
		101	CHIP_R580,
		102	CHIP_RV560,
		103	CHIP_RV570,
		104	CHIP_R600,
		105	CHIP_RV610,
		106	CHIP_RV630,
		107	CHIP_RV670,
		108	CHIP_RV620,
		109	CHIP_RV635,
		110	CHIP_RS780,
		111	CHIP_RS880,
		112	CHIP_RV770,
		113	CHIP_RV730,
		114	CHIP_RV710,
		115	CHIP_RV740,
		116	CHIP_CEDAR,
		117	CHIP_REDWOOD,
		118	CHIP_JUNIPER,
		119	CHIP_CYPRESS,
		120	CHIP_HEMLOCK,
		121	CHIP_PALM,
		122	CHIP_SUMO,
		123	CHIP_SUMO2,
		124	CHIP_BARTS,
		125	CHIP_TURKS,
		126	CHIP_CAICOS,
		127	CHIP_CAYMAN,
		128	CHIP_ARUBA,
		129	CHIP_TAHITI,
		130	CHIP_PITCAIRN,
		131	CHIP_VERDE,
		132	CHIP_OLAND,
		133	CHIP_HAINAN,
		134	CHIP_BONAIRE,
		135	CHIP_KAVERI,
		136	CHIP_KABINI,
		137	CHIP_HAWAII,
		138	CHIP_MULLINS,
		139	CHIP_LAST,
		140	};
		141
		142	enum chip_class {
		143	CLASS_UNKNOWN = 0,
		144	R300,
		145	R400,
		146	R500,
		147	R600,
		148	R700,
		149	EVERGREEN,
		150	CAYMAN,
		151	SI,
		152	CIK,
		153	};
		154
		155	enum ring_type {
		156	RING_GFX = 0,
		157	RING_DMA,
		158	RING_UVD,
		159	RING_VCE,
		160	RING_LAST,
		161	};
		162
		163	enum radeon_value_id {
		164	RADEON_REQUESTED_VRAM_MEMORY,
		165	RADEON_REQUESTED_GTT_MEMORY,
		166	RADEON_BUFFER_WAIT_TIME_NS,
		167	RADEON_TIMESTAMP,
		168	RADEON_NUM_CS_FLUSHES,
		169	RADEON_NUM_BYTES_MOVED,
		170	RADEON_VRAM_USAGE,
		171	RADEON_GTT_USAGE,
		172	RADEON_GPU_TEMPERATURE,
		173	RADEON_CURRENT_SCLK,
		174	RADEON_CURRENT_MCLK
		175	};
		176
		177	enum radeon_bo_priority {
		178	RADEON_PRIO_MIN,
		179	RADEON_PRIO_SHADER_DATA, /* shader code, resource descriptors */
		180	RADEON_PRIO_SHADER_BUFFER_RO, /* read-only */
		181	RADEON_PRIO_SHADER_TEXTURE_RO, /* read-only */
		182	RADEON_PRIO_SHADER_RESOURCE_RW, /* buffers, textures, streamout, GS rings, RATs; read/write */
		183	RADEON_PRIO_COLOR_BUFFER,
		184	RADEON_PRIO_DEPTH_BUFFER,
		185	RADEON_PRIO_SHADER_TEXTURE_MSAA,
		186	RADEON_PRIO_COLOR_BUFFER_MSAA,
		187	RADEON_PRIO_DEPTH_BUFFER_MSAA,
		188	RADEON_PRIO_COLOR_META,
		189	RADEON_PRIO_DEPTH_META,
		190	RADEON_PRIO_MAX /* must be <= 15 */
		191	};
		192
		193	struct winsys_handle;
		194	struct radeon_winsys_cs_handle;
		195
		196	struct radeon_winsys_cs {
		197	unsigned cdw; /* Number of used dwords. */
		198	uint32_t buf; / The command buffer. */
		199	enum ring_type ring_type;
		200	};
		201
		202	struct radeon_info {
		203	uint32_t pci_id;
		204	enum radeon_family family;
		205	enum chip_class chip_class;
		206	uint64_t gart_size;
		207	uint64_t vram_size;
		208	uint32_t max_sclk;
		209	uint32_t max_compute_units;
		210	uint32_t max_se;
		211	uint32_t max_sh_per_se;
		212
		213	uint32_t drm_major; /* version */
		214	uint32_t drm_minor;
		215	uint32_t drm_patchlevel;
		216
		217	boolean has_uvd;
		218	uint32_t vce_fw_version;
		219	boolean has_userptr;
		220
		221	uint32_t r300_num_gb_pipes;
		222	uint32_t r300_num_z_pipes;
		223
		224	uint32_t r600_num_backends;
		225	uint32_t r600_clock_crystal_freq;
		226	uint32_t r600_tiling_config;
		227	uint32_t r600_num_tile_pipes;
		228	uint32_t r600_max_pipes;
		229	boolean r600_virtual_address;
		230	boolean r600_has_dma;
		231
		232	uint32_t r600_backend_map;
		233	boolean r600_backend_map_valid;
		234
		235	boolean si_tile_mode_array_valid;
		236	uint32_t si_tile_mode_array[32];
		237	uint32_t si_backend_enabled_mask;
		238
		239	boolean cik_macrotile_mode_array_valid;
		240	uint32_t cik_macrotile_mode_array[16];
		241	};
		242
		243	enum radeon_feature_id {
		244	RADEON_FID_R300_HYPERZ_ACCESS, /* ZMask + HiZ */
		245	RADEON_FID_R300_CMASK_ACCESS,
		246	};
		247
		248	#define RADEON_SURF_MAX_LEVEL 32
		249
		250	#define RADEON_SURF_TYPE_MASK 0xFF
		251	#define RADEON_SURF_TYPE_SHIFT 0
		252	#define RADEON_SURF_TYPE_1D 0
		253	#define RADEON_SURF_TYPE_2D 1
		254	#define RADEON_SURF_TYPE_3D 2
		255	#define RADEON_SURF_TYPE_CUBEMAP 3
		256	#define RADEON_SURF_TYPE_1D_ARRAY 4
		257	#define RADEON_SURF_TYPE_2D_ARRAY 5
		258	#define RADEON_SURF_MODE_MASK 0xFF
		259	#define RADEON_SURF_MODE_SHIFT 8
		260	#define RADEON_SURF_MODE_LINEAR 0
		261	#define RADEON_SURF_MODE_LINEAR_ALIGNED 1
		262	#define RADEON_SURF_MODE_1D 2
		263	#define RADEON_SURF_MODE_2D 3
		264	#define RADEON_SURF_SCANOUT (1 << 16)
		265	#define RADEON_SURF_ZBUFFER (1 << 17)
		266	#define RADEON_SURF_SBUFFER (1 << 18)
		267	#define RADEON_SURF_Z_OR_SBUFFER (RADEON_SURF_ZBUFFER \| RADEON_SURF_SBUFFER)
		268	#define RADEON_SURF_HAS_SBUFFER_MIPTREE (1 << 19)
		269	#define RADEON_SURF_HAS_TILE_MODE_INDEX (1 << 20)
		270	#define RADEON_SURF_FMASK (1 << 21)
		271
		272	#define RADEON_SURF_GET(v, field) (((v) >> RADEON_SURF_ ## field ## _SHIFT) & RADEON_SURF_ ## field ## _MASK)
		273	#define RADEON_SURF_SET(v, field) (((v) & RADEON_SURF_ ## field ## _MASK) << RADEON_SURF_ ## field ## _SHIFT)
		274	#define RADEON_SURF_CLR(v, field) ((v) & ~(RADEON_SURF_ ## field ## _MASK << RADEON_SURF_ ## field ## _SHIFT))
		275
		276	struct radeon_surf_level {
		277	uint64_t offset;
		278	uint64_t slice_size;
		279	uint32_t npix_x;
		280	uint32_t npix_y;
		281	uint32_t npix_z;
		282	uint32_t nblk_x;
		283	uint32_t nblk_y;
		284	uint32_t nblk_z;
		285	uint32_t pitch_bytes;
		286	uint32_t mode;
		287	};
		288
		289	struct radeon_surf {
		290	/* These are inputs to the calculator. */
		291	uint32_t npix_x;
		292	uint32_t npix_y;
		293	uint32_t npix_z;
		294	uint32_t blk_w;
		295	uint32_t blk_h;
		296	uint32_t blk_d;
		297	uint32_t array_size;
		298	uint32_t last_level;
		299	uint32_t bpe;
		300	uint32_t nsamples;
		301	uint32_t flags;
		302
		303	/* These are return values. Some of them can be set by the caller, but
		304	* they will be treated as hints (e.g. bankw, bankh) and might be
		305	* changed by the calculator.
		306	*/
		307	uint64_t bo_size;
		308	uint64_t bo_alignment;
		309	/* This applies to EG and later. */
		310	uint32_t bankw;
		311	uint32_t bankh;
		312	uint32_t mtilea;
		313	uint32_t tile_split;
		314	uint32_t stencil_tile_split;
		315	uint64_t stencil_offset;
		316	struct radeon_surf_level level[RADEON_SURF_MAX_LEVEL];
		317	struct radeon_surf_level stencil_level[RADEON_SURF_MAX_LEVEL];
		318	uint32_t tiling_index[RADEON_SURF_MAX_LEVEL];
		319	uint32_t stencil_tiling_index[RADEON_SURF_MAX_LEVEL];
		320	};
		321
		322	struct radeon_winsys {
		323	/**
		324	* The screen object this winsys was created for
		325	*/
		326	struct pipe_screen *screen;
		327
		328	/**
		329	* Decrement the winsys reference count.
		330	*
		331	* \param ws The winsys this function is called for.
		332	* \return True if the winsys and screen should be destroyed.
		333	*/
		334	bool (unref)(struct radeon_winsys ws);
		335
		336	/**
		337	* Destroy this winsys.
		338	*
		339	* \param ws The winsys this function is called from.
		340	*/
		341	void (destroy)(struct radeon_winsys ws);
		342
		343	/**
		344	* Query an info structure from winsys.
		345	*
		346	* \param ws The winsys this function is called from.
		347	* \param info Return structure
		348	*/
		349	void (query_info)(struct radeon_winsys ws,
		350	struct radeon_info *info);
		351
		352	/**************************************************************************
		353	* Buffer management. Buffer attributes are mostly fixed over its lifetime.
		354	*
		355	* Remember that gallium gets to choose the interface it needs, and the
		356	* window systems must then implement that interface (rather than the
		357	* other way around...).
		358	*************************************************************************/
		359
		360	/**
		361	* Create a buffer object.
		362	*
		363	* \param ws The winsys this function is called from.
		364	* \param size The size to allocate.
		365	* \param alignment An alignment of the buffer in memory.
		366	* \param use_reusable_pool Whether the cache buffer manager should be used.
		367	* \param domain A bitmask of the RADEON_DOMAIN_* flags.
		368	* \return The created buffer object.
		369	*/
		370	struct pb_buffer (buffer_create)(struct radeon_winsys *ws,
		371	unsigned size,
		372	unsigned alignment,
		373	boolean use_reusable_pool,
		374	enum radeon_bo_domain domain,
		375	enum radeon_bo_flag flags);
		376
		377	struct radeon_winsys_cs_handle (buffer_get_cs_handle)(
		378	struct pb_buffer *buf);
		379
		380	/**
		381	* Map the entire data store of a buffer object into the client's address
		382	* space.
		383	*
		384	* \param buf A winsys buffer object to map.
		385	* \param cs A command stream to flush if the buffer is referenced by it.
		386	* \param usage A bitmask of the PIPE_TRANSFER_* flags.
		387	* \return The pointer at the beginning of the buffer.
		388	*/
		389	void (buffer_map)(struct radeon_winsys_cs_handle *buf,
		390	struct radeon_winsys_cs *cs,
		391	enum pipe_transfer_usage usage);
		392
		393	/**
		394	* Unmap a buffer object from the client's address space.
		395	*
		396	* \param buf A winsys buffer object to unmap.
		397	*/
		398	void (buffer_unmap)(struct radeon_winsys_cs_handle buf);
		399
		400	/**
		401	* Return TRUE if a buffer object is being used by the GPU.
		402	*
		403	* \param buf A winsys buffer object.
		404	* \param usage Only check whether the buffer is busy for the given usage.
		405	*/
		406	boolean (buffer_is_busy)(struct pb_buffer buf,
		407	enum radeon_bo_usage usage);
		408
		409	/**
		410	* Wait for a buffer object until it is not used by a GPU. This is
		411	* equivalent to a fence placed after the last command using the buffer,
		412	* and synchronizing to the fence.
		413	*
		414	* \param buf A winsys buffer object to wait for.
		415	* \param usage Only wait until the buffer is idle for the given usage,
		416	* but may still be busy for some other usage.
		417	*/
		418	void (buffer_wait)(struct pb_buffer buf, enum radeon_bo_usage usage);
		419
		420	/**
		421	* Return tiling flags describing a memory layout of a buffer object.
		422	*
		423	* \param buf A winsys buffer object to get the flags from.
		424	* \param macrotile A pointer to the return value of the microtile flag.
		425	* \param microtile A pointer to the return value of the macrotile flag.
		426	*
		427	* \note microtile and macrotile are not bitmasks!
		428	*/
		429	void (buffer_get_tiling)(struct pb_buffer buf,
		430	enum radeon_bo_layout *microtile,
		431	enum radeon_bo_layout *macrotile,
		432	unsigned bankw, unsigned bankh,
		433	unsigned *tile_split,
		434	unsigned *stencil_tile_split,
		435	unsigned *mtilea,
		436	bool *scanout);
		437
		438	/**
		439	* Set tiling flags describing a memory layout of a buffer object.
		440	*
		441	* \param buf A winsys buffer object to set the flags for.
		442	* \param cs A command stream to flush if the buffer is referenced by it.
		443	* \param macrotile A macrotile flag.
		444	* \param microtile A microtile flag.
		445	* \param stride A stride of the buffer in bytes, for texturing.
		446	*
		447	* \note microtile and macrotile are not bitmasks!
		448	*/
		449	void (buffer_set_tiling)(struct pb_buffer buf,
		450	struct radeon_winsys_cs *rcs,
		451	enum radeon_bo_layout microtile,
		452	enum radeon_bo_layout macrotile,
		453	unsigned bankw, unsigned bankh,
		454	unsigned tile_split,
		455	unsigned stencil_tile_split,
		456	unsigned mtilea,
		457	unsigned stride,
		458	bool scanout);
		459
		460	/**
		461	* Get a winsys buffer from a winsys handle. The internal structure
		462	* of the handle is platform-specific and only a winsys should access it.
		463	*
		464	* \param ws The winsys this function is called from.
		465	* \param whandle A winsys handle pointer as was received from a state
		466	* tracker.
		467	* \param stride The returned buffer stride in bytes.
		468	*/
		469	struct pb_buffer (buffer_from_handle)(struct radeon_winsys *ws,
		470	struct winsys_handle *whandle,
		471	unsigned *stride);
		472
		473	/**
		474	* Get a winsys buffer from a user pointer. The resulting buffer can't
		475	* be exported. Both pointer and size must be page aligned.
		476	*
		477	* \param ws The winsys this function is called from.
		478	* \param pointer User pointer to turn into a buffer object.
		479	* \param Size Size in bytes for the new buffer.
		480	*/
		481	struct pb_buffer (buffer_from_ptr)(struct radeon_winsys *ws,
		482	void *pointer, unsigned size);
		483
		484	/**
		485	* Get a winsys handle from a winsys buffer. The internal structure
		486	* of the handle is platform-specific and only a winsys should access it.
		487	*
		488	* \param buf A winsys buffer object to get the handle from.
		489	* \param whandle A winsys handle pointer.
		490	* \param stride A stride of the buffer in bytes, for texturing.
		491	* \return TRUE on success.
		492	*/
		493	boolean (buffer_get_handle)(struct pb_buffer buf,
		494	unsigned stride,
		495	struct winsys_handle *whandle);
		496
		497	/**
		498	* Return the virtual address of a buffer.
		499	*
		500	* \param buf A winsys buffer object
		501	* \return virtual address
		502	*/
		503	uint64_t (buffer_get_virtual_address)(struct radeon_winsys_cs_handle buf);
		504
		505	/**
		506	* Query the initial placement of the buffer from the kernel driver.
		507	*/
		508	enum radeon_bo_domain (buffer_get_initial_domain)(struct radeon_winsys_cs_handle buf);
		509
		510	/**************************************************************************
		511	* Command submission.
		512	*
		513	* Each pipe context should create its own command stream and submit
		514	* commands independently of other contexts.
		515	*************************************************************************/
		516
		517	/**
		518	* Create a command stream.
		519	*
		520	* \param ws The winsys this function is called from.
		521	* \param ring_type The ring type (GFX, DMA, UVD)
		522	* \param flush Flush callback function associated with the command stream.
		523	* \param user User pointer that will be passed to the flush callback.
		524	* \param trace_buf Trace buffer when tracing is enabled
		525	*/
		526	struct radeon_winsys_cs (cs_create)(struct radeon_winsys *ws,
		527	enum ring_type ring_type,
		528	void (flush)(void ctx, unsigned flags,
		529	struct pipe_fence_handle **fence),
		530	void *flush_ctx,
		531	struct radeon_winsys_cs_handle *trace_buf);
		532
		533	/**
		534	* Destroy a command stream.
		535	*
		536	* \param cs A command stream to destroy.
		537	*/
		538	void (cs_destroy)(struct radeon_winsys_cs cs);
		539
		540	/**
		541	* Add a new buffer relocation. Every relocation must first be added
		542	* before it can be written.
		543	*
		544	* \param cs A command stream to add buffer for validation against.
		545	* \param buf A winsys buffer to validate.
		546	* \param usage Whether the buffer is used for read and/or write.
		547	* \param domain Bitmask of the RADEON_DOMAIN_* flags.
		548	* \param priority A higher number means a greater chance of being
		549	* placed in the requested domain. 15 is the maximum.
		550	* \return Relocation index.
		551	*/
		552	unsigned (cs_add_reloc)(struct radeon_winsys_cs cs,
		553	struct radeon_winsys_cs_handle *buf,
		554	enum radeon_bo_usage usage,
		555	enum radeon_bo_domain domain,
		556	enum radeon_bo_priority priority);
		557
		558	/**
		559	* Return the index of an already-added buffer.
		560	*
		561	* \param cs Command stream
		562	* \param buf Buffer
		563	* \return The buffer index, or -1 if the buffer has not been added.
		564	*/
		565	int (cs_get_reloc)(struct radeon_winsys_cs cs,
		566	struct radeon_winsys_cs_handle *buf);
		567
		568	/**
		569	* Return TRUE if there is enough memory in VRAM and GTT for the relocs
		570	* added so far. If the validation fails, all the relocations which have
		571	* been added since the last call of cs_validate will be removed and
		572	* the CS will be flushed (provided there are still any relocations).
		573	*
		574	* \param cs A command stream to validate.
		575	*/
		576	boolean (cs_validate)(struct radeon_winsys_cs cs);
		577
		578	/**
		579	* Return TRUE if there is enough memory in VRAM and GTT for the relocs
		580	* added so far.
		581	*
		582	* \param cs A command stream to validate.
		583	* \param vram VRAM memory size pending to be use
		584	* \param gtt GTT memory size pending to be use
		585	*/
		586	boolean (cs_memory_below_limit)(struct radeon_winsys_cs cs, uint64_t vram, uint64_t gtt);
		587
		588	/**
		589	* Flush a command stream.
		590	*
		591	* \param cs A command stream to flush.
		592	* \param flags, RADEON_FLUSH_ASYNC or 0.
		593	* \param fence Pointer to a fence. If non-NULL, a fence is inserted
		594	* after the CS and is returned through this parameter.
		595	* \param cs_trace_id A unique identifier of the cs, used for tracing.
		596	*/
		597	void (cs_flush)(struct radeon_winsys_cs cs,
		598	unsigned flags,
		599	struct pipe_fence_handle **fence,
		600	uint32_t cs_trace_id);
		601
		602	/**
		603	* Return TRUE if a buffer is referenced by a command stream.
		604	*
		605	* \param cs A command stream.
		606	* \param buf A winsys buffer.
		607	*/
		608	boolean (cs_is_buffer_referenced)(struct radeon_winsys_cs cs,
		609	struct radeon_winsys_cs_handle *buf,
		610	enum radeon_bo_usage usage);
		611
		612	/**
		613	* Request access to a feature for a command stream.
		614	*
		615	* \param cs A command stream.
		616	* \param fid Feature ID, one of RADEON_FID_*
		617	* \param enable Whether to enable or disable the feature.
		618	*/
		619	boolean (cs_request_feature)(struct radeon_winsys_cs cs,
		620	enum radeon_feature_id fid,
		621	boolean enable);
		622	/**
		623	* Make sure all asynchronous flush of the cs have completed
		624	*
		625	* \param cs A command stream.
		626	*/
		627	void (cs_sync_flush)(struct radeon_winsys_cs cs);
		628
		629	/**
		630	* Wait for the fence and return true if the fence has been signalled.
		631	* The timeout of 0 will only return the status.
		632	* The timeout of PIPE_TIMEOUT_INFINITE will always wait until the fence
		633	* is signalled.
		634	*/
		635	bool (fence_wait)(struct radeon_winsys ws,
		636	struct pipe_fence_handle *fence,
		637	uint64_t timeout);
		638
		639	/**
		640	* Reference counting for fences.
		641	*/
		642	void (fence_reference)(struct pipe_fence_handle *dst,
		643	struct pipe_fence_handle *src);
		644
		645	/**
		646	* Initialize surface
		647	*
		648	* \param ws The winsys this function is called from.
		649	* \param surf Surface structure ptr
		650	*/
		651	int (surface_init)(struct radeon_winsys ws,
		652	struct radeon_surf *surf);
		653
		654	/**
		655	* Find best values for a surface
		656	*
		657	* \param ws The winsys this function is called from.
		658	* \param surf Surface structure ptr
		659	*/
		660	int (surface_best)(struct radeon_winsys ws,
		661	struct radeon_surf *surf);
		662
		663	uint64_t (query_value)(struct radeon_winsys ws,
		664	enum radeon_value_id value);
		665
		666	void (read_registers)(struct radeon_winsys ws, unsigned reg_offset,
		667	unsigned num_registers, uint32_t *out);
		668	};
		669
		670
		671	static INLINE void radeon_emit(struct radeon_winsys_cs *cs, uint32_t value)
		672	{
		673	cs->buf[cs->cdw++] = value;
		674	}
		675
		676	static INLINE void radeon_emit_array(struct radeon_winsys_cs *cs,
		677	const uint32_t *values, unsigned count)
		678	{
		679	memcpy(cs->buf+cs->cdw, values, count * 4);
		680	cs->cdw += count;
		681	}
		682
		683	#endif

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(root)/contrib/sdk/sources/Mesa/mesa-10.6.0/src/gallium/drivers/radeon/radeon_winsys.h – Rev 5568