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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 5564 | serge | 1 | /* |
| 2 | * Copyright 2013 Advanced Micro Devices, Inc. |
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| 3 | * |
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| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 5 | * copy of this software and associated documentation files (the "Software"), |
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| 6 | * to deal in the Software without restriction, including without limitation |
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| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 9 | * Software is furnished to do so, subject to the following conditions: |
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| 10 | * |
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| 11 | * The above copyright notice and this permission notice (including the next |
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| 12 | * paragraph) shall be included in all copies or substantial portions of the |
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| 13 | * Software. |
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| 14 | * |
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| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
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| 20 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
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| 21 | * SOFTWARE. |
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| 22 | * |
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| 23 | * Authors: Marek Olšák |
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| 24 | * |
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| 25 | */ |
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| 26 | |||
| 27 | #include "r600_pipe_common.h" |
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| 28 | #include "r600_cs.h" |
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| 29 | #include "tgsi/tgsi_parse.h" |
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| 30 | #include "util/u_draw_quad.h" |
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| 31 | #include "util/u_memory.h" |
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| 32 | #include "util/u_format_s3tc.h" |
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| 33 | #include "util/u_upload_mgr.h" |
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| 34 | #include "vl/vl_decoder.h" |
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| 35 | #include "vl/vl_video_buffer.h" |
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| 36 | #include "radeon/radeon_video.h" |
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| 37 | #include |
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| 38 | |||
| 39 | #ifndef HAVE_LLVM |
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| 40 | #define HAVE_LLVM 0 |
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| 41 | #endif |
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| 42 | |||
| 43 | /* |
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| 44 | * pipe_context |
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| 45 | */ |
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| 46 | |||
| 47 | void r600_draw_rectangle(struct blitter_context *blitter, |
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| 48 | int x1, int y1, int x2, int y2, float depth, |
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| 49 | enum blitter_attrib_type type, |
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| 50 | const union pipe_color_union *attrib) |
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| 51 | { |
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| 52 | struct r600_common_context *rctx = |
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| 53 | (struct r600_common_context*)util_blitter_get_pipe(blitter); |
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| 54 | struct pipe_viewport_state viewport; |
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| 55 | struct pipe_resource *buf = NULL; |
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| 56 | unsigned offset = 0; |
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| 57 | float *vb; |
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| 58 | |||
| 59 | if (type == UTIL_BLITTER_ATTRIB_TEXCOORD) { |
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| 60 | util_blitter_draw_rectangle(blitter, x1, y1, x2, y2, depth, type, attrib); |
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| 61 | return; |
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| 62 | } |
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| 63 | |||
| 64 | /* Some operations (like color resolve on r6xx) don't work |
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| 65 | * with the conventional primitive types. |
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| 66 | * One that works is PT_RECTLIST, which we use here. */ |
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| 67 | |||
| 68 | /* setup viewport */ |
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| 69 | viewport.scale[0] = 1.0f; |
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| 70 | viewport.scale[1] = 1.0f; |
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| 71 | viewport.scale[2] = 1.0f; |
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| 72 | viewport.translate[0] = 0.0f; |
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| 73 | viewport.translate[1] = 0.0f; |
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| 74 | viewport.translate[2] = 0.0f; |
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| 75 | rctx->b.set_viewport_states(&rctx->b, 0, 1, &viewport); |
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| 76 | |||
| 77 | /* Upload vertices. The hw rectangle has only 3 vertices, |
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| 78 | * I guess the 4th one is derived from the first 3. |
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| 79 | * The vertex specification should match u_blitter's vertex element state. */ |
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| 80 | u_upload_alloc(rctx->uploader, 0, sizeof(float) * 24, &offset, &buf, (void**)&vb); |
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| 81 | vb[0] = x1; |
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| 82 | vb[1] = y1; |
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| 83 | vb[2] = depth; |
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| 84 | vb[3] = 1; |
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| 85 | |||
| 86 | vb[8] = x1; |
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| 87 | vb[9] = y2; |
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| 88 | vb[10] = depth; |
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| 89 | vb[11] = 1; |
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| 90 | |||
| 91 | vb[16] = x2; |
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| 92 | vb[17] = y1; |
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| 93 | vb[18] = depth; |
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| 94 | vb[19] = 1; |
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| 95 | |||
| 96 | if (attrib) { |
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| 97 | memcpy(vb+4, attrib->f, sizeof(float)*4); |
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| 98 | memcpy(vb+12, attrib->f, sizeof(float)*4); |
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| 99 | memcpy(vb+20, attrib->f, sizeof(float)*4); |
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| 100 | } |
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| 101 | |||
| 102 | /* draw */ |
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| 103 | util_draw_vertex_buffer(&rctx->b, NULL, buf, blitter->vb_slot, offset, |
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| 104 | R600_PRIM_RECTANGLE_LIST, 3, 2); |
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| 105 | pipe_resource_reference(&buf, NULL); |
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| 106 | } |
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| 107 | |||
| 108 | void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw) |
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| 109 | { |
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| 110 | /* The number of dwords we already used in the DMA so far. */ |
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| 111 | num_dw += ctx->rings.dma.cs->cdw; |
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| 112 | /* Flush if there's not enough space. */ |
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| 113 | if (num_dw > RADEON_MAX_CMDBUF_DWORDS) { |
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| 114 | ctx->rings.dma.flush(ctx, RADEON_FLUSH_ASYNC, NULL); |
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| 115 | } |
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| 116 | } |
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| 117 | |||
| 118 | static void r600_memory_barrier(struct pipe_context *ctx, unsigned flags) |
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| 119 | { |
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| 120 | } |
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| 121 | |||
| 122 | void r600_preflush_suspend_features(struct r600_common_context *ctx) |
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| 123 | { |
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| 124 | /* Disable render condition. */ |
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| 125 | ctx->saved_render_cond = NULL; |
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| 126 | ctx->saved_render_cond_cond = FALSE; |
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| 127 | ctx->saved_render_cond_mode = 0; |
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| 128 | if (ctx->current_render_cond) { |
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| 129 | ctx->saved_render_cond = ctx->current_render_cond; |
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| 130 | ctx->saved_render_cond_cond = ctx->current_render_cond_cond; |
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| 131 | ctx->saved_render_cond_mode = ctx->current_render_cond_mode; |
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| 132 | ctx->b.render_condition(&ctx->b, NULL, FALSE, 0); |
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| 133 | } |
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| 134 | |||
| 135 | /* suspend queries */ |
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| 136 | ctx->nontimer_queries_suspended = false; |
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| 137 | if (ctx->num_cs_dw_nontimer_queries_suspend) { |
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| 138 | r600_suspend_nontimer_queries(ctx); |
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| 139 | ctx->nontimer_queries_suspended = true; |
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| 140 | } |
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| 141 | |||
| 142 | ctx->streamout.suspended = false; |
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| 143 | if (ctx->streamout.begin_emitted) { |
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| 144 | r600_emit_streamout_end(ctx); |
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| 145 | ctx->streamout.suspended = true; |
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| 146 | } |
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| 147 | } |
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| 148 | |||
| 149 | void r600_postflush_resume_features(struct r600_common_context *ctx) |
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| 150 | { |
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| 151 | if (ctx->streamout.suspended) { |
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| 152 | ctx->streamout.append_bitmask = ctx->streamout.enabled_mask; |
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| 153 | r600_streamout_buffers_dirty(ctx); |
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| 154 | } |
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| 155 | |||
| 156 | /* resume queries */ |
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| 157 | if (ctx->nontimer_queries_suspended) { |
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| 158 | r600_resume_nontimer_queries(ctx); |
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| 159 | } |
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| 160 | |||
| 161 | /* Re-enable render condition. */ |
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| 162 | if (ctx->saved_render_cond) { |
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| 163 | ctx->b.render_condition(&ctx->b, ctx->saved_render_cond, |
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| 164 | ctx->saved_render_cond_cond, |
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| 165 | ctx->saved_render_cond_mode); |
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| 166 | } |
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| 167 | } |
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| 168 | |||
| 169 | static void r600_flush_from_st(struct pipe_context *ctx, |
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| 170 | struct pipe_fence_handle **fence, |
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| 171 | unsigned flags) |
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| 172 | { |
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| 173 | struct r600_common_context *rctx = (struct r600_common_context *)ctx; |
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| 174 | unsigned rflags = 0; |
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| 175 | |||
| 176 | if (flags & PIPE_FLUSH_END_OF_FRAME) |
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| 177 | rflags |= RADEON_FLUSH_END_OF_FRAME; |
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| 178 | |||
| 179 | if (rctx->rings.dma.cs) { |
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| 180 | rctx->rings.dma.flush(rctx, rflags, NULL); |
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| 181 | } |
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| 182 | rctx->rings.gfx.flush(rctx, rflags, fence); |
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| 183 | } |
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| 184 | |||
| 185 | static void r600_flush_dma_ring(void *ctx, unsigned flags, |
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| 186 | struct pipe_fence_handle **fence) |
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| 187 | { |
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| 188 | struct r600_common_context *rctx = (struct r600_common_context *)ctx; |
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| 189 | struct radeon_winsys_cs *cs = rctx->rings.dma.cs; |
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| 190 | |||
| 191 | if (!cs->cdw) { |
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| 192 | return; |
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| 193 | } |
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| 194 | |||
| 195 | rctx->rings.dma.flushing = true; |
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| 196 | rctx->ws->cs_flush(cs, flags, fence, 0); |
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| 197 | rctx->rings.dma.flushing = false; |
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| 198 | } |
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| 199 | |||
| 200 | bool r600_common_context_init(struct r600_common_context *rctx, |
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| 201 | struct r600_common_screen *rscreen) |
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| 202 | { |
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| 203 | util_slab_create(&rctx->pool_transfers, |
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| 204 | sizeof(struct r600_transfer), 64, |
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| 205 | UTIL_SLAB_SINGLETHREADED); |
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| 206 | |||
| 207 | rctx->screen = rscreen; |
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| 208 | rctx->ws = rscreen->ws; |
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| 209 | rctx->family = rscreen->family; |
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| 210 | rctx->chip_class = rscreen->chip_class; |
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| 211 | |||
| 212 | if (rscreen->family == CHIP_HAWAII) |
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| 213 | rctx->max_db = 16; |
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| 214 | else if (rscreen->chip_class >= EVERGREEN) |
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| 215 | rctx->max_db = 8; |
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| 216 | else |
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| 217 | rctx->max_db = 4; |
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| 218 | |||
| 219 | rctx->b.transfer_map = u_transfer_map_vtbl; |
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| 220 | rctx->b.transfer_flush_region = u_default_transfer_flush_region; |
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| 221 | rctx->b.transfer_unmap = u_transfer_unmap_vtbl; |
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| 222 | rctx->b.transfer_inline_write = u_default_transfer_inline_write; |
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| 223 | rctx->b.memory_barrier = r600_memory_barrier; |
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| 224 | rctx->b.flush = r600_flush_from_st; |
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| 225 | |||
| 226 | LIST_INITHEAD(&rctx->texture_buffers); |
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| 227 | |||
| 228 | r600_init_context_texture_functions(rctx); |
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| 229 | r600_streamout_init(rctx); |
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| 230 | r600_query_init(rctx); |
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| 231 | cayman_init_msaa(&rctx->b); |
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| 232 | |||
| 233 | rctx->allocator_so_filled_size = u_suballocator_create(&rctx->b, 4096, 4, |
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| 234 | 0, PIPE_USAGE_DEFAULT, TRUE); |
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| 235 | if (!rctx->allocator_so_filled_size) |
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| 236 | return false; |
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| 237 | |||
| 238 | rctx->uploader = u_upload_create(&rctx->b, 1024 * 1024, 256, |
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| 239 | PIPE_BIND_INDEX_BUFFER | |
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| 240 | PIPE_BIND_CONSTANT_BUFFER); |
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| 241 | if (!rctx->uploader) |
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| 242 | return false; |
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| 243 | |||
| 244 | if (rscreen->info.r600_has_dma && !(rscreen->debug_flags & DBG_NO_ASYNC_DMA)) { |
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| 245 | rctx->rings.dma.cs = rctx->ws->cs_create(rctx->ws, RING_DMA, |
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| 246 | r600_flush_dma_ring, |
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| 247 | rctx, NULL); |
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| 248 | rctx->rings.dma.flush = r600_flush_dma_ring; |
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| 249 | } |
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| 250 | |||
| 251 | return true; |
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| 252 | } |
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| 253 | |||
| 254 | void r600_common_context_cleanup(struct r600_common_context *rctx) |
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| 255 | { |
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| 256 | if (rctx->rings.gfx.cs) { |
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| 257 | rctx->ws->cs_destroy(rctx->rings.gfx.cs); |
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| 258 | } |
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| 259 | if (rctx->rings.dma.cs) { |
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| 260 | rctx->ws->cs_destroy(rctx->rings.dma.cs); |
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| 261 | } |
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| 262 | |||
| 263 | if (rctx->uploader) { |
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| 264 | u_upload_destroy(rctx->uploader); |
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| 265 | } |
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| 266 | |||
| 267 | util_slab_destroy(&rctx->pool_transfers); |
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| 268 | |||
| 269 | if (rctx->allocator_so_filled_size) { |
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| 270 | u_suballocator_destroy(rctx->allocator_so_filled_size); |
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| 271 | } |
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| 272 | } |
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| 273 | |||
| 274 | void r600_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r) |
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| 275 | { |
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| 276 | struct r600_common_context *rctx = (struct r600_common_context *)ctx; |
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| 277 | struct r600_resource *rr = (struct r600_resource *)r; |
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| 278 | |||
| 279 | if (r == NULL) { |
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| 280 | return; |
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| 281 | } |
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| 282 | |||
| 283 | /* |
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| 284 | * The idea is to compute a gross estimate of memory requirement of |
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| 285 | * each draw call. After each draw call, memory will be precisely |
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| 286 | * accounted. So the uncertainty is only on the current draw call. |
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| 287 | * In practice this gave very good estimate (+/- 10% of the target |
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| 288 | * memory limit). |
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| 289 | */ |
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| 290 | if (rr->domains & RADEON_DOMAIN_GTT) { |
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| 291 | rctx->gtt += rr->buf->size; |
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| 292 | } |
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| 293 | if (rr->domains & RADEON_DOMAIN_VRAM) { |
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| 294 | rctx->vram += rr->buf->size; |
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| 295 | } |
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| 296 | } |
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| 297 | |||
| 298 | /* |
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| 299 | * pipe_screen |
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| 300 | */ |
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| 301 | |||
| 302 | static const struct debug_named_value common_debug_options[] = { |
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| 303 | /* logging */ |
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| 304 | { "tex", DBG_TEX, "Print texture info" }, |
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| 305 | { "texmip", DBG_TEXMIP, "Print texture info (mipmapped only)" }, |
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| 306 | { "compute", DBG_COMPUTE, "Print compute info" }, |
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| 307 | { "vm", DBG_VM, "Print virtual addresses when creating resources" }, |
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| 308 | { "trace_cs", DBG_TRACE_CS, "Trace cs and write rlockup_ |
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| 309 | { "info", DBG_INFO, "Print driver information" }, |
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| 310 | |||
| 311 | /* shaders */ |
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| 312 | { "fs", DBG_FS, "Print fetch shaders" }, |
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| 313 | { "vs", DBG_VS, "Print vertex shaders" }, |
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| 314 | { "gs", DBG_GS, "Print geometry shaders" }, |
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| 315 | { "ps", DBG_PS, "Print pixel shaders" }, |
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| 316 | { "cs", DBG_CS, "Print compute shaders" }, |
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| 317 | |||
| 318 | /* features */ |
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| 319 | { "nodma", DBG_NO_ASYNC_DMA, "Disable asynchronous DMA" }, |
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| 320 | { "nohyperz", DBG_NO_HYPERZ, "Disable Hyper-Z" }, |
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| 321 | /* GL uses the word INVALIDATE, gallium uses the word DISCARD */ |
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| 322 | { "noinvalrange", DBG_NO_DISCARD_RANGE, "Disable handling of INVALIDATE_RANGE map flags" }, |
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| 323 | { "no2d", DBG_NO_2D_TILING, "Disable 2D tiling" }, |
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| 324 | { "notiling", DBG_NO_TILING, "Disable tiling" }, |
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| 325 | { "switch_on_eop", DBG_SWITCH_ON_EOP, "Program WD/IA to switch on end-of-packet." }, |
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| 326 | { "forcedma", DBG_FORCE_DMA, "Use asynchronous DMA for all operations when possible." }, |
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| 327 | { "precompile", DBG_PRECOMPILE, "Compile one shader variant at shader creation." }, |
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| 328 | |||
| 329 | DEBUG_NAMED_VALUE_END /* must be last */ |
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| 330 | }; |
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| 331 | |||
| 332 | static const char* r600_get_vendor(struct pipe_screen* pscreen) |
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| 333 | { |
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| 334 | return "X.Org"; |
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| 335 | } |
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| 336 | |||
| 337 | static const char* r600_get_device_vendor(struct pipe_screen* pscreen) |
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| 338 | { |
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| 339 | return "AMD"; |
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| 340 | } |
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| 341 | |||
| 342 | static const char* r600_get_name(struct pipe_screen* pscreen) |
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| 343 | { |
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| 344 | struct r600_common_screen *rscreen = (struct r600_common_screen*)pscreen; |
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| 345 | |||
| 346 | switch (rscreen->family) { |
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| 347 | case CHIP_R600: return "AMD R600"; |
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| 348 | case CHIP_RV610: return "AMD RV610"; |
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| 349 | case CHIP_RV630: return "AMD RV630"; |
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| 350 | case CHIP_RV670: return "AMD RV670"; |
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| 351 | case CHIP_RV620: return "AMD RV620"; |
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| 352 | case CHIP_RV635: return "AMD RV635"; |
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| 353 | case CHIP_RS780: return "AMD RS780"; |
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| 354 | case CHIP_RS880: return "AMD RS880"; |
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| 355 | case CHIP_RV770: return "AMD RV770"; |
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| 356 | case CHIP_RV730: return "AMD RV730"; |
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| 357 | case CHIP_RV710: return "AMD RV710"; |
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| 358 | case CHIP_RV740: return "AMD RV740"; |
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| 359 | case CHIP_CEDAR: return "AMD CEDAR"; |
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| 360 | case CHIP_REDWOOD: return "AMD REDWOOD"; |
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| 361 | case CHIP_JUNIPER: return "AMD JUNIPER"; |
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| 362 | case CHIP_CYPRESS: return "AMD CYPRESS"; |
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| 363 | case CHIP_HEMLOCK: return "AMD HEMLOCK"; |
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| 364 | case CHIP_PALM: return "AMD PALM"; |
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| 365 | case CHIP_SUMO: return "AMD SUMO"; |
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| 366 | case CHIP_SUMO2: return "AMD SUMO2"; |
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| 367 | case CHIP_BARTS: return "AMD BARTS"; |
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| 368 | case CHIP_TURKS: return "AMD TURKS"; |
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| 369 | case CHIP_CAICOS: return "AMD CAICOS"; |
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| 370 | case CHIP_CAYMAN: return "AMD CAYMAN"; |
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| 371 | case CHIP_ARUBA: return "AMD ARUBA"; |
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| 372 | case CHIP_TAHITI: return "AMD TAHITI"; |
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| 373 | case CHIP_PITCAIRN: return "AMD PITCAIRN"; |
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| 374 | case CHIP_VERDE: return "AMD CAPE VERDE"; |
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| 375 | case CHIP_OLAND: return "AMD OLAND"; |
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| 376 | case CHIP_HAINAN: return "AMD HAINAN"; |
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| 377 | case CHIP_BONAIRE: return "AMD BONAIRE"; |
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| 378 | case CHIP_KAVERI: return "AMD KAVERI"; |
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| 379 | case CHIP_KABINI: return "AMD KABINI"; |
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| 380 | case CHIP_HAWAII: return "AMD HAWAII"; |
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| 381 | case CHIP_MULLINS: return "AMD MULLINS"; |
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| 382 | default: return "AMD unknown"; |
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| 383 | } |
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| 384 | } |
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| 385 | |||
| 386 | static float r600_get_paramf(struct pipe_screen* pscreen, |
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| 387 | enum pipe_capf param) |
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| 388 | { |
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| 389 | struct r600_common_screen *rscreen = (struct r600_common_screen *)pscreen; |
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| 390 | |||
| 391 | switch (param) { |
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| 392 | case PIPE_CAPF_MAX_LINE_WIDTH: |
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| 393 | case PIPE_CAPF_MAX_LINE_WIDTH_AA: |
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| 394 | case PIPE_CAPF_MAX_POINT_WIDTH: |
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| 395 | case PIPE_CAPF_MAX_POINT_WIDTH_AA: |
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| 396 | if (rscreen->family >= CHIP_CEDAR) |
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| 397 | return 16384.0f; |
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| 398 | else |
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| 399 | return 8192.0f; |
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| 400 | case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY: |
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| 401 | return 16.0f; |
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| 402 | case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS: |
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| 403 | return 16.0f; |
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| 404 | case PIPE_CAPF_GUARD_BAND_LEFT: |
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| 405 | case PIPE_CAPF_GUARD_BAND_TOP: |
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| 406 | case PIPE_CAPF_GUARD_BAND_RIGHT: |
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| 407 | case PIPE_CAPF_GUARD_BAND_BOTTOM: |
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| 408 | return 0.0f; |
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| 409 | } |
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| 410 | return 0.0f; |
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| 411 | } |
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| 412 | |||
| 413 | static int r600_get_video_param(struct pipe_screen *screen, |
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| 414 | enum pipe_video_profile profile, |
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| 415 | enum pipe_video_entrypoint entrypoint, |
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| 416 | enum pipe_video_cap param) |
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| 417 | { |
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| 418 | switch (param) { |
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| 419 | case PIPE_VIDEO_CAP_SUPPORTED: |
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| 420 | return vl_profile_supported(screen, profile, entrypoint); |
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| 421 | case PIPE_VIDEO_CAP_NPOT_TEXTURES: |
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| 422 | return 1; |
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| 423 | case PIPE_VIDEO_CAP_MAX_WIDTH: |
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| 424 | case PIPE_VIDEO_CAP_MAX_HEIGHT: |
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| 425 | return vl_video_buffer_max_size(screen); |
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| 426 | case PIPE_VIDEO_CAP_PREFERED_FORMAT: |
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| 427 | return PIPE_FORMAT_NV12; |
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| 428 | case PIPE_VIDEO_CAP_PREFERS_INTERLACED: |
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| 429 | return false; |
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| 430 | case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED: |
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| 431 | return false; |
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| 432 | case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE: |
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| 433 | return true; |
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| 434 | case PIPE_VIDEO_CAP_MAX_LEVEL: |
||
| 435 | return vl_level_supported(screen, profile); |
||
| 436 | default: |
||
| 437 | return 0; |
||
| 438 | } |
||
| 439 | } |
||
| 440 | |||
| 441 | const char *r600_get_llvm_processor_name(enum radeon_family family) |
||
| 442 | { |
||
| 443 | switch (family) { |
||
| 444 | case CHIP_R600: |
||
| 445 | case CHIP_RV630: |
||
| 446 | case CHIP_RV635: |
||
| 447 | case CHIP_RV670: |
||
| 448 | return "r600"; |
||
| 449 | case CHIP_RV610: |
||
| 450 | case CHIP_RV620: |
||
| 451 | case CHIP_RS780: |
||
| 452 | case CHIP_RS880: |
||
| 453 | return "rs880"; |
||
| 454 | case CHIP_RV710: |
||
| 455 | return "rv710"; |
||
| 456 | case CHIP_RV730: |
||
| 457 | return "rv730"; |
||
| 458 | case CHIP_RV740: |
||
| 459 | case CHIP_RV770: |
||
| 460 | return "rv770"; |
||
| 461 | case CHIP_PALM: |
||
| 462 | case CHIP_CEDAR: |
||
| 463 | return "cedar"; |
||
| 464 | case CHIP_SUMO: |
||
| 465 | case CHIP_SUMO2: |
||
| 466 | return "sumo"; |
||
| 467 | case CHIP_REDWOOD: |
||
| 468 | return "redwood"; |
||
| 469 | case CHIP_JUNIPER: |
||
| 470 | return "juniper"; |
||
| 471 | case CHIP_HEMLOCK: |
||
| 472 | case CHIP_CYPRESS: |
||
| 473 | return "cypress"; |
||
| 474 | case CHIP_BARTS: |
||
| 475 | return "barts"; |
||
| 476 | case CHIP_TURKS: |
||
| 477 | return "turks"; |
||
| 478 | case CHIP_CAICOS: |
||
| 479 | return "caicos"; |
||
| 480 | case CHIP_CAYMAN: |
||
| 481 | case CHIP_ARUBA: |
||
| 482 | return "cayman"; |
||
| 483 | |||
| 484 | case CHIP_TAHITI: return "tahiti"; |
||
| 485 | case CHIP_PITCAIRN: return "pitcairn"; |
||
| 486 | case CHIP_VERDE: return "verde"; |
||
| 487 | case CHIP_OLAND: return "oland"; |
||
| 488 | case CHIP_HAINAN: return "hainan"; |
||
| 489 | case CHIP_BONAIRE: return "bonaire"; |
||
| 490 | case CHIP_KABINI: return "kabini"; |
||
| 491 | case CHIP_KAVERI: return "kaveri"; |
||
| 492 | case CHIP_HAWAII: return "hawaii"; |
||
| 493 | case CHIP_MULLINS: |
||
| 494 | #if HAVE_LLVM >= 0x0305 |
||
| 495 | return "mullins"; |
||
| 496 | #else |
||
| 497 | return "kabini"; |
||
| 498 | #endif |
||
| 499 | default: return ""; |
||
| 500 | } |
||
| 501 | } |
||
| 502 | |||
| 503 | static int r600_get_compute_param(struct pipe_screen *screen, |
||
| 504 | enum pipe_compute_cap param, |
||
| 505 | void *ret) |
||
| 506 | { |
||
| 507 | struct r600_common_screen *rscreen = (struct r600_common_screen *)screen; |
||
| 508 | |||
| 509 | //TODO: select these params by asic |
||
| 510 | switch (param) { |
||
| 511 | case PIPE_COMPUTE_CAP_IR_TARGET: { |
||
| 512 | const char *gpu; |
||
| 513 | const char *triple; |
||
| 514 | if (rscreen->family <= CHIP_ARUBA || HAVE_LLVM < 0x0306) { |
||
| 515 | triple = "r600--"; |
||
| 516 | } else { |
||
| 517 | triple = "amdgcn--"; |
||
| 518 | } |
||
| 519 | switch(rscreen->family) { |
||
| 520 | /* Clang < 3.6 is missing Hainan in its list of |
||
| 521 | * GPUs, so we need to use the name of a similar GPU. |
||
| 522 | */ |
||
| 523 | #if HAVE_LLVM < 0x0306 |
||
| 524 | case CHIP_HAINAN: |
||
| 525 | gpu = "oland"; |
||
| 526 | break; |
||
| 527 | #endif |
||
| 528 | default: |
||
| 529 | gpu = r600_get_llvm_processor_name(rscreen->family); |
||
| 530 | break; |
||
| 531 | } |
||
| 532 | if (ret) { |
||
| 533 | sprintf(ret, "%s-%s", gpu, triple); |
||
| 534 | } |
||
| 535 | /* +2 for dash and terminating NIL byte */ |
||
| 536 | return (strlen(triple) + strlen(gpu) + 2) * sizeof(char); |
||
| 537 | } |
||
| 538 | case PIPE_COMPUTE_CAP_GRID_DIMENSION: |
||
| 539 | if (ret) { |
||
| 540 | uint64_t *grid_dimension = ret; |
||
| 541 | grid_dimension[0] = 3; |
||
| 542 | } |
||
| 543 | return 1 * sizeof(uint64_t); |
||
| 544 | |||
| 545 | case PIPE_COMPUTE_CAP_MAX_GRID_SIZE: |
||
| 546 | if (ret) { |
||
| 547 | uint64_t *grid_size = ret; |
||
| 548 | grid_size[0] = 65535; |
||
| 549 | grid_size[1] = 65535; |
||
| 550 | grid_size[2] = 1; |
||
| 551 | } |
||
| 552 | return 3 * sizeof(uint64_t) ; |
||
| 553 | |||
| 554 | case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE: |
||
| 555 | if (ret) { |
||
| 556 | uint64_t *block_size = ret; |
||
| 557 | block_size[0] = 256; |
||
| 558 | block_size[1] = 256; |
||
| 559 | block_size[2] = 256; |
||
| 560 | } |
||
| 561 | return 3 * sizeof(uint64_t); |
||
| 562 | |||
| 563 | case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK: |
||
| 564 | if (ret) { |
||
| 565 | uint64_t *max_threads_per_block = ret; |
||
| 566 | *max_threads_per_block = 256; |
||
| 567 | } |
||
| 568 | return sizeof(uint64_t); |
||
| 569 | |||
| 570 | case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: |
||
| 571 | if (ret) { |
||
| 572 | uint64_t *max_global_size = ret; |
||
| 573 | uint64_t max_mem_alloc_size; |
||
| 574 | |||
| 575 | r600_get_compute_param(screen, |
||
| 576 | PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE, |
||
| 577 | &max_mem_alloc_size); |
||
| 578 | |||
| 579 | /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least |
||
| 580 | * 1/4 of the MAX_GLOBAL_SIZE. Since the |
||
| 581 | * MAX_MEM_ALLOC_SIZE is fixed for older kernels, |
||
| 582 | * make sure we never report more than |
||
| 583 | * 4 * MAX_MEM_ALLOC_SIZE. |
||
| 584 | */ |
||
| 585 | *max_global_size = MIN2(4 * max_mem_alloc_size, |
||
| 586 | rscreen->info.gart_size + |
||
| 587 | rscreen->info.vram_size); |
||
| 588 | } |
||
| 589 | return sizeof(uint64_t); |
||
| 590 | |||
| 591 | case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: |
||
| 592 | if (ret) { |
||
| 593 | uint64_t *max_local_size = ret; |
||
| 594 | /* Value reported by the closed source driver. */ |
||
| 595 | *max_local_size = 32768; |
||
| 596 | } |
||
| 597 | return sizeof(uint64_t); |
||
| 598 | |||
| 599 | case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: |
||
| 600 | if (ret) { |
||
| 601 | uint64_t *max_input_size = ret; |
||
| 602 | /* Value reported by the closed source driver. */ |
||
| 603 | *max_input_size = 1024; |
||
| 604 | } |
||
| 605 | return sizeof(uint64_t); |
||
| 606 | |||
| 607 | case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE: |
||
| 608 | if (ret) { |
||
| 609 | uint64_t *max_mem_alloc_size = ret; |
||
| 610 | |||
| 611 | /* XXX: The limit in older kernels is 256 MB. We |
||
| 612 | * should add a query here for newer kernels. |
||
| 613 | */ |
||
| 614 | *max_mem_alloc_size = 256 * 1024 * 1024; |
||
| 615 | } |
||
| 616 | return sizeof(uint64_t); |
||
| 617 | |||
| 618 | case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY: |
||
| 619 | if (ret) { |
||
| 620 | uint32_t *max_clock_frequency = ret; |
||
| 621 | *max_clock_frequency = rscreen->info.max_sclk; |
||
| 622 | } |
||
| 623 | return sizeof(uint32_t); |
||
| 624 | |||
| 625 | case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS: |
||
| 626 | if (ret) { |
||
| 627 | uint32_t *max_compute_units = ret; |
||
| 628 | *max_compute_units = rscreen->info.max_compute_units; |
||
| 629 | } |
||
| 630 | return sizeof(uint32_t); |
||
| 631 | |||
| 632 | case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED: |
||
| 633 | if (ret) { |
||
| 634 | uint32_t *images_supported = ret; |
||
| 635 | *images_supported = 0; |
||
| 636 | } |
||
| 637 | return sizeof(uint32_t); |
||
| 638 | case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: |
||
| 639 | break; /* unused */ |
||
| 640 | } |
||
| 641 | |||
| 642 | fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param); |
||
| 643 | return 0; |
||
| 644 | } |
||
| 645 | |||
| 646 | static uint64_t r600_get_timestamp(struct pipe_screen *screen) |
||
| 647 | { |
||
| 648 | struct r600_common_screen *rscreen = (struct r600_common_screen*)screen; |
||
| 649 | |||
| 650 | return 1000000 * rscreen->ws->query_value(rscreen->ws, RADEON_TIMESTAMP) / |
||
| 651 | rscreen->info.r600_clock_crystal_freq; |
||
| 652 | } |
||
| 653 | |||
| 654 | static int r600_get_driver_query_info(struct pipe_screen *screen, |
||
| 655 | unsigned index, |
||
| 656 | struct pipe_driver_query_info *info) |
||
| 657 | { |
||
| 658 | struct r600_common_screen *rscreen = (struct r600_common_screen*)screen; |
||
| 659 | struct pipe_driver_query_info list[] = { |
||
| 660 | {"draw-calls", R600_QUERY_DRAW_CALLS, {0}}, |
||
| 661 | {"requested-VRAM", R600_QUERY_REQUESTED_VRAM, {rscreen->info.vram_size}, PIPE_DRIVER_QUERY_TYPE_BYTES}, |
||
| 662 | {"requested-GTT", R600_QUERY_REQUESTED_GTT, {rscreen->info.gart_size}, PIPE_DRIVER_QUERY_TYPE_BYTES}, |
||
| 663 | {"buffer-wait-time", R600_QUERY_BUFFER_WAIT_TIME, {0}}, |
||
| 664 | {"num-cs-flushes", R600_QUERY_NUM_CS_FLUSHES, {0}}, |
||
| 665 | {"num-bytes-moved", R600_QUERY_NUM_BYTES_MOVED, {0}, PIPE_DRIVER_QUERY_TYPE_BYTES}, |
||
| 666 | {"VRAM-usage", R600_QUERY_VRAM_USAGE, {rscreen->info.vram_size}, PIPE_DRIVER_QUERY_TYPE_BYTES}, |
||
| 667 | {"GTT-usage", R600_QUERY_GTT_USAGE, {rscreen->info.gart_size}, PIPE_DRIVER_QUERY_TYPE_BYTES}, |
||
| 668 | {"temperature", R600_QUERY_GPU_TEMPERATURE, {100}}, |
||
| 669 | {"shader-clock", R600_QUERY_CURRENT_GPU_SCLK, {0}}, |
||
| 670 | {"memory-clock", R600_QUERY_CURRENT_GPU_MCLK, {0}}, |
||
| 671 | {"GPU-load", R600_QUERY_GPU_LOAD, {100}} |
||
| 672 | }; |
||
| 673 | unsigned num_queries; |
||
| 674 | |||
| 675 | if (rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 42) |
||
| 676 | num_queries = Elements(list); |
||
| 677 | else |
||
| 678 | num_queries = 8; |
||
| 679 | |||
| 680 | if (!info) |
||
| 681 | return num_queries; |
||
| 682 | |||
| 683 | if (index >= num_queries) |
||
| 684 | return 0; |
||
| 685 | |||
| 686 | *info = list[index]; |
||
| 687 | return 1; |
||
| 688 | } |
||
| 689 | |||
| 690 | static void r600_fence_reference(struct pipe_screen *screen, |
||
| 691 | struct pipe_fence_handle **ptr, |
||
| 692 | struct pipe_fence_handle *fence) |
||
| 693 | { |
||
| 694 | struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws; |
||
| 695 | |||
| 696 | rws->fence_reference(ptr, fence); |
||
| 697 | } |
||
| 698 | |||
| 699 | static boolean r600_fence_signalled(struct pipe_screen *screen, |
||
| 700 | struct pipe_fence_handle *fence) |
||
| 701 | { |
||
| 702 | struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws; |
||
| 703 | |||
| 704 | return rws->fence_wait(rws, fence, 0); |
||
| 705 | } |
||
| 706 | |||
| 707 | static boolean r600_fence_finish(struct pipe_screen *screen, |
||
| 708 | struct pipe_fence_handle *fence, |
||
| 709 | uint64_t timeout) |
||
| 710 | { |
||
| 711 | struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws; |
||
| 712 | |||
| 713 | return rws->fence_wait(rws, fence, timeout); |
||
| 714 | } |
||
| 715 | |||
| 716 | static bool r600_interpret_tiling(struct r600_common_screen *rscreen, |
||
| 717 | uint32_t tiling_config) |
||
| 718 | { |
||
| 719 | switch ((tiling_config & 0xe) >> 1) { |
||
| 720 | case 0: |
||
| 721 | rscreen->tiling_info.num_channels = 1; |
||
| 722 | break; |
||
| 723 | case 1: |
||
| 724 | rscreen->tiling_info.num_channels = 2; |
||
| 725 | break; |
||
| 726 | case 2: |
||
| 727 | rscreen->tiling_info.num_channels = 4; |
||
| 728 | break; |
||
| 729 | case 3: |
||
| 730 | rscreen->tiling_info.num_channels = 8; |
||
| 731 | break; |
||
| 732 | default: |
||
| 733 | return false; |
||
| 734 | } |
||
| 735 | |||
| 736 | switch ((tiling_config & 0x30) >> 4) { |
||
| 737 | case 0: |
||
| 738 | rscreen->tiling_info.num_banks = 4; |
||
| 739 | break; |
||
| 740 | case 1: |
||
| 741 | rscreen->tiling_info.num_banks = 8; |
||
| 742 | break; |
||
| 743 | default: |
||
| 744 | return false; |
||
| 745 | |||
| 746 | } |
||
| 747 | switch ((tiling_config & 0xc0) >> 6) { |
||
| 748 | case 0: |
||
| 749 | rscreen->tiling_info.group_bytes = 256; |
||
| 750 | break; |
||
| 751 | case 1: |
||
| 752 | rscreen->tiling_info.group_bytes = 512; |
||
| 753 | break; |
||
| 754 | default: |
||
| 755 | return false; |
||
| 756 | } |
||
| 757 | return true; |
||
| 758 | } |
||
| 759 | |||
| 760 | static bool evergreen_interpret_tiling(struct r600_common_screen *rscreen, |
||
| 761 | uint32_t tiling_config) |
||
| 762 | { |
||
| 763 | switch (tiling_config & 0xf) { |
||
| 764 | case 0: |
||
| 765 | rscreen->tiling_info.num_channels = 1; |
||
| 766 | break; |
||
| 767 | case 1: |
||
| 768 | rscreen->tiling_info.num_channels = 2; |
||
| 769 | break; |
||
| 770 | case 2: |
||
| 771 | rscreen->tiling_info.num_channels = 4; |
||
| 772 | break; |
||
| 773 | case 3: |
||
| 774 | rscreen->tiling_info.num_channels = 8; |
||
| 775 | break; |
||
| 776 | default: |
||
| 777 | return false; |
||
| 778 | } |
||
| 779 | |||
| 780 | switch ((tiling_config & 0xf0) >> 4) { |
||
| 781 | case 0: |
||
| 782 | rscreen->tiling_info.num_banks = 4; |
||
| 783 | break; |
||
| 784 | case 1: |
||
| 785 | rscreen->tiling_info.num_banks = 8; |
||
| 786 | break; |
||
| 787 | case 2: |
||
| 788 | rscreen->tiling_info.num_banks = 16; |
||
| 789 | break; |
||
| 790 | default: |
||
| 791 | return false; |
||
| 792 | } |
||
| 793 | |||
| 794 | switch ((tiling_config & 0xf00) >> 8) { |
||
| 795 | case 0: |
||
| 796 | rscreen->tiling_info.group_bytes = 256; |
||
| 797 | break; |
||
| 798 | case 1: |
||
| 799 | rscreen->tiling_info.group_bytes = 512; |
||
| 800 | break; |
||
| 801 | default: |
||
| 802 | return false; |
||
| 803 | } |
||
| 804 | return true; |
||
| 805 | } |
||
| 806 | |||
| 807 | static bool r600_init_tiling(struct r600_common_screen *rscreen) |
||
| 808 | { |
||
| 809 | uint32_t tiling_config = rscreen->info.r600_tiling_config; |
||
| 810 | |||
| 811 | /* set default group bytes, overridden by tiling info ioctl */ |
||
| 812 | if (rscreen->chip_class <= R700) { |
||
| 813 | rscreen->tiling_info.group_bytes = 256; |
||
| 814 | } else { |
||
| 815 | rscreen->tiling_info.group_bytes = 512; |
||
| 816 | } |
||
| 817 | |||
| 818 | if (!tiling_config) |
||
| 819 | return true; |
||
| 820 | |||
| 821 | if (rscreen->chip_class <= R700) { |
||
| 822 | return r600_interpret_tiling(rscreen, tiling_config); |
||
| 823 | } else { |
||
| 824 | return evergreen_interpret_tiling(rscreen, tiling_config); |
||
| 825 | } |
||
| 826 | } |
||
| 827 | |||
| 828 | struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen, |
||
| 829 | const struct pipe_resource *templ) |
||
| 830 | { |
||
| 831 | if (templ->target == PIPE_BUFFER) { |
||
| 832 | return r600_buffer_create(screen, templ, 4096); |
||
| 833 | } else { |
||
| 834 | return r600_texture_create(screen, templ); |
||
| 835 | } |
||
| 836 | } |
||
| 837 | |||
| 838 | bool r600_common_screen_init(struct r600_common_screen *rscreen, |
||
| 839 | struct radeon_winsys *ws) |
||
| 840 | { |
||
| 841 | ws->query_info(ws, &rscreen->info); |
||
| 842 | |||
| 843 | rscreen->b.get_name = r600_get_name; |
||
| 844 | rscreen->b.get_vendor = r600_get_vendor; |
||
| 845 | rscreen->b.get_device_vendor = r600_get_device_vendor; |
||
| 846 | rscreen->b.get_compute_param = r600_get_compute_param; |
||
| 847 | rscreen->b.get_paramf = r600_get_paramf; |
||
| 848 | rscreen->b.get_driver_query_info = r600_get_driver_query_info; |
||
| 849 | rscreen->b.get_timestamp = r600_get_timestamp; |
||
| 850 | rscreen->b.fence_finish = r600_fence_finish; |
||
| 851 | rscreen->b.fence_reference = r600_fence_reference; |
||
| 852 | rscreen->b.fence_signalled = r600_fence_signalled; |
||
| 853 | rscreen->b.resource_destroy = u_resource_destroy_vtbl; |
||
| 854 | rscreen->b.resource_from_user_memory = r600_buffer_from_user_memory; |
||
| 855 | |||
| 856 | if (rscreen->info.has_uvd) { |
||
| 857 | rscreen->b.get_video_param = rvid_get_video_param; |
||
| 858 | rscreen->b.is_video_format_supported = rvid_is_format_supported; |
||
| 859 | } else { |
||
| 860 | rscreen->b.get_video_param = r600_get_video_param; |
||
| 861 | rscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported; |
||
| 862 | } |
||
| 863 | |||
| 864 | r600_init_screen_texture_functions(rscreen); |
||
| 865 | |||
| 866 | rscreen->ws = ws; |
||
| 867 | rscreen->family = rscreen->info.family; |
||
| 868 | rscreen->chip_class = rscreen->info.chip_class; |
||
| 869 | rscreen->debug_flags = debug_get_flags_option("R600_DEBUG", common_debug_options, 0); |
||
| 870 | |||
| 871 | if (!r600_init_tiling(rscreen)) { |
||
| 872 | return false; |
||
| 873 | } |
||
| 874 | util_format_s3tc_init(); |
||
| 875 | pipe_mutex_init(rscreen->aux_context_lock); |
||
| 876 | pipe_mutex_init(rscreen->gpu_load_mutex); |
||
| 877 | |||
| 878 | if (rscreen->info.drm_minor >= 28 && (rscreen->debug_flags & DBG_TRACE_CS)) { |
||
| 879 | rscreen->trace_bo = (struct r600_resource*)pipe_buffer_create(&rscreen->b, |
||
| 880 | PIPE_BIND_CUSTOM, |
||
| 881 | PIPE_USAGE_STAGING, |
||
| 882 | 4096); |
||
| 883 | if (rscreen->trace_bo) { |
||
| 884 | rscreen->trace_ptr = rscreen->ws->buffer_map(rscreen->trace_bo->cs_buf, NULL, |
||
| 885 | PIPE_TRANSFER_UNSYNCHRONIZED); |
||
| 886 | } |
||
| 887 | } |
||
| 888 | |||
| 889 | if (rscreen->debug_flags & DBG_INFO) { |
||
| 890 | printf("pci_id = 0x%x\n", rscreen->info.pci_id); |
||
| 891 | printf("family = %i\n", rscreen->info.family); |
||
| 892 | printf("chip_class = %i\n", rscreen->info.chip_class); |
||
| 893 | printf("gart_size = %i MB\n", (int)(rscreen->info.gart_size >> 20)); |
||
| 894 | printf("vram_size = %i MB\n", (int)(rscreen->info.vram_size >> 20)); |
||
| 895 | printf("max_sclk = %i\n", rscreen->info.max_sclk); |
||
| 896 | printf("max_compute_units = %i\n", rscreen->info.max_compute_units); |
||
| 897 | printf("max_se = %i\n", rscreen->info.max_se); |
||
| 898 | printf("max_sh_per_se = %i\n", rscreen->info.max_sh_per_se); |
||
| 899 | printf("drm = %i.%i.%i\n", rscreen->info.drm_major, |
||
| 900 | rscreen->info.drm_minor, rscreen->info.drm_patchlevel); |
||
| 901 | printf("has_uvd = %i\n", rscreen->info.has_uvd); |
||
| 902 | printf("vce_fw_version = %i\n", rscreen->info.vce_fw_version); |
||
| 903 | printf("r600_num_backends = %i\n", rscreen->info.r600_num_backends); |
||
| 904 | printf("r600_clock_crystal_freq = %i\n", rscreen->info.r600_clock_crystal_freq); |
||
| 905 | printf("r600_tiling_config = 0x%x\n", rscreen->info.r600_tiling_config); |
||
| 906 | printf("r600_num_tile_pipes = %i\n", rscreen->info.r600_num_tile_pipes); |
||
| 907 | printf("r600_max_pipes = %i\n", rscreen->info.r600_max_pipes); |
||
| 908 | printf("r600_virtual_address = %i\n", rscreen->info.r600_virtual_address); |
||
| 909 | printf("r600_has_dma = %i\n", rscreen->info.r600_has_dma); |
||
| 910 | printf("r600_backend_map = %i\n", rscreen->info.r600_backend_map); |
||
| 911 | printf("r600_backend_map_valid = %i\n", rscreen->info.r600_backend_map_valid); |
||
| 912 | printf("si_tile_mode_array_valid = %i\n", rscreen->info.si_tile_mode_array_valid); |
||
| 913 | printf("cik_macrotile_mode_array_valid = %i\n", rscreen->info.cik_macrotile_mode_array_valid); |
||
| 914 | } |
||
| 915 | return true; |
||
| 916 | } |
||
| 917 | |||
| 918 | void r600_destroy_common_screen(struct r600_common_screen *rscreen) |
||
| 919 | { |
||
| 920 | r600_gpu_load_kill_thread(rscreen); |
||
| 921 | |||
| 922 | pipe_mutex_destroy(rscreen->gpu_load_mutex); |
||
| 923 | pipe_mutex_destroy(rscreen->aux_context_lock); |
||
| 924 | rscreen->aux_context->destroy(rscreen->aux_context); |
||
| 925 | |||
| 926 | if (rscreen->trace_bo) { |
||
| 927 | rscreen->ws->buffer_unmap(rscreen->trace_bo->cs_buf); |
||
| 928 | pipe_resource_reference((struct pipe_resource**)&rscreen->trace_bo, NULL); |
||
| 929 | } |
||
| 930 | |||
| 931 | rscreen->ws->destroy(rscreen->ws); |
||
| 932 | FREE(rscreen); |
||
| 933 | } |
||
| 934 | |||
| 935 | bool r600_can_dump_shader(struct r600_common_screen *rscreen, |
||
| 936 | const struct tgsi_token *tokens) |
||
| 937 | { |
||
| 938 | /* Compute shader don't have tgsi_tokens */ |
||
| 939 | if (!tokens) |
||
| 940 | return (rscreen->debug_flags & DBG_CS) != 0; |
||
| 941 | |||
| 942 | switch (tgsi_get_processor_type(tokens)) { |
||
| 943 | case TGSI_PROCESSOR_VERTEX: |
||
| 944 | return (rscreen->debug_flags & DBG_VS) != 0; |
||
| 945 | case TGSI_PROCESSOR_GEOMETRY: |
||
| 946 | return (rscreen->debug_flags & DBG_GS) != 0; |
||
| 947 | case TGSI_PROCESSOR_FRAGMENT: |
||
| 948 | return (rscreen->debug_flags & DBG_PS) != 0; |
||
| 949 | case TGSI_PROCESSOR_COMPUTE: |
||
| 950 | return (rscreen->debug_flags & DBG_CS) != 0; |
||
| 951 | default: |
||
| 952 | return false; |
||
| 953 | } |
||
| 954 | } |
||
| 955 | |||
| 956 | void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst, |
||
| 957 | unsigned offset, unsigned size, unsigned value, |
||
| 958 | bool is_framebuffer) |
||
| 959 | { |
||
| 960 | struct r600_common_context *rctx = (struct r600_common_context*)rscreen->aux_context; |
||
| 961 | |||
| 962 | pipe_mutex_lock(rscreen->aux_context_lock); |
||
| 963 | rctx->clear_buffer(&rctx->b, dst, offset, size, value, is_framebuffer); |
||
| 964 | rscreen->aux_context->flush(rscreen->aux_context, NULL, 0); |
||
| 965 | pipe_mutex_unlock(rscreen->aux_context_lock); |
||
| 966 | } |