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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 5564 | serge | 1 | /* |
| 2 | * Copyright 2010 Jerome Glisse |
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| 3 | * |
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| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 5 | * copy of this software and associated documentation files (the "Software"), |
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| 6 | * to deal in the Software without restriction, including without limitation |
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| 7 | * on the rights to use, copy, modify, merge, publish, distribute, sub |
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| 8 | * license, and/or sell copies of the Software, and to permit persons to whom |
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| 9 | * the Software is furnished to do so, subject to the following conditions: |
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| 10 | * |
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| 11 | * The above copyright notice and this permission notice (including the next |
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| 12 | * paragraph) shall be included in all copies or substantial portions of the |
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| 13 | * Software. |
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| 14 | * |
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| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL |
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| 18 | * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, |
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| 19 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR |
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| 20 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE |
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| 21 | * USE OR OTHER DEALINGS IN THE SOFTWARE. |
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| 22 | */ |
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| 23 | #include "r600_pipe.h" |
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| 24 | #include "r600_public.h" |
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| 25 | #include "r600_isa.h" |
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| 26 | #include "evergreen_compute.h" |
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| 27 | #include "r600d.h" |
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| 28 | |||
| 29 | #include "sb/sb_public.h" |
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| 30 | |||
| 31 | #include |
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| 32 | #include "pipe/p_shader_tokens.h" |
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| 33 | #include "util/u_debug.h" |
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| 34 | #include "util/u_memory.h" |
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| 35 | #include "util/u_simple_shaders.h" |
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| 36 | #include "util/u_upload_mgr.h" |
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| 37 | #include "util/u_math.h" |
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| 38 | #include "vl/vl_decoder.h" |
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| 39 | #include "vl/vl_video_buffer.h" |
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| 40 | #include "radeon/radeon_video.h" |
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| 41 | #include "radeon/radeon_uvd.h" |
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| 42 | #include "os/os_time.h" |
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| 43 | |||
| 44 | static const struct debug_named_value r600_debug_options[] = { |
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| 45 | /* features */ |
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| 46 | #if defined(R600_USE_LLVM) |
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| 47 | { "llvm", DBG_LLVM, "Enable the LLVM shader compiler" }, |
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| 48 | #endif |
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| 49 | { "nocpdma", DBG_NO_CP_DMA, "Disable CP DMA" }, |
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| 50 | |||
| 51 | /* shader backend */ |
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| 52 | { "nosb", DBG_NO_SB, "Disable sb backend for graphics shaders" }, |
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| 53 | { "sbcl", DBG_SB_CS, "Enable sb backend for compute shaders" }, |
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| 54 | { "sbdry", DBG_SB_DRY_RUN, "Don't use optimized bytecode (just print the dumps)" }, |
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| 55 | { "sbstat", DBG_SB_STAT, "Print optimization statistics for shaders" }, |
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| 56 | { "sbdump", DBG_SB_DUMP, "Print IR dumps after some optimization passes" }, |
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| 57 | { "sbnofallback", DBG_SB_NO_FALLBACK, "Abort on errors instead of fallback" }, |
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| 58 | { "sbdisasm", DBG_SB_DISASM, "Use sb disassembler for shader dumps" }, |
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| 59 | { "sbsafemath", DBG_SB_SAFEMATH, "Disable unsafe math optimizations" }, |
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| 60 | |||
| 61 | DEBUG_NAMED_VALUE_END /* must be last */ |
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| 62 | }; |
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| 63 | |||
| 64 | /* |
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| 65 | * pipe_context |
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| 66 | */ |
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| 67 | |||
| 68 | static void r600_destroy_context(struct pipe_context *context) |
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| 69 | { |
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| 70 | struct r600_context *rctx = (struct r600_context *)context; |
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| 71 | |||
| 72 | r600_isa_destroy(rctx->isa); |
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| 73 | |||
| 74 | r600_sb_context_destroy(rctx->sb_context); |
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| 75 | |||
| 76 | pipe_resource_reference((struct pipe_resource**)&rctx->dummy_cmask, NULL); |
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| 77 | pipe_resource_reference((struct pipe_resource**)&rctx->dummy_fmask, NULL); |
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| 78 | |||
| 79 | if (rctx->dummy_pixel_shader) { |
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| 80 | rctx->b.b.delete_fs_state(&rctx->b.b, rctx->dummy_pixel_shader); |
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| 81 | } |
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| 82 | if (rctx->custom_dsa_flush) { |
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| 83 | rctx->b.b.delete_depth_stencil_alpha_state(&rctx->b.b, rctx->custom_dsa_flush); |
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| 84 | } |
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| 85 | if (rctx->custom_blend_resolve) { |
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| 86 | rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_resolve); |
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| 87 | } |
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| 88 | if (rctx->custom_blend_decompress) { |
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| 89 | rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_decompress); |
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| 90 | } |
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| 91 | if (rctx->custom_blend_fastclear) { |
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| 92 | rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_fastclear); |
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| 93 | } |
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| 94 | util_unreference_framebuffer_state(&rctx->framebuffer.state); |
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| 95 | |||
| 96 | if (rctx->blitter) { |
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| 97 | util_blitter_destroy(rctx->blitter); |
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| 98 | } |
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| 99 | if (rctx->allocator_fetch_shader) { |
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| 100 | u_suballocator_destroy(rctx->allocator_fetch_shader); |
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| 101 | } |
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| 102 | |||
| 103 | r600_release_command_buffer(&rctx->start_cs_cmd); |
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| 104 | |||
| 105 | FREE(rctx->start_compute_cs_cmd.buf); |
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| 106 | |||
| 107 | r600_common_context_cleanup(&rctx->b); |
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| 108 | FREE(rctx); |
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| 109 | } |
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| 110 | |||
| 111 | static struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv) |
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| 112 | { |
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| 113 | struct r600_context *rctx = CALLOC_STRUCT(r600_context); |
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| 114 | struct r600_screen* rscreen = (struct r600_screen *)screen; |
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| 115 | struct radeon_winsys *ws = rscreen->b.ws; |
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| 116 | |||
| 117 | if (rctx == NULL) |
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| 118 | return NULL; |
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| 119 | |||
| 120 | rctx->b.b.screen = screen; |
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| 121 | rctx->b.b.priv = priv; |
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| 122 | rctx->b.b.destroy = r600_destroy_context; |
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| 123 | |||
| 124 | if (!r600_common_context_init(&rctx->b, &rscreen->b)) |
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| 125 | goto fail; |
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| 126 | |||
| 127 | rctx->screen = rscreen; |
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| 128 | rctx->keep_tiling_flags = rscreen->b.info.drm_minor >= 12; |
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| 129 | |||
| 130 | r600_init_blit_functions(rctx); |
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| 131 | |||
| 132 | if (rscreen->b.info.has_uvd) { |
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| 133 | rctx->b.b.create_video_codec = r600_uvd_create_decoder; |
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| 134 | rctx->b.b.create_video_buffer = r600_video_buffer_create; |
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| 135 | } else { |
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| 136 | rctx->b.b.create_video_codec = vl_create_decoder; |
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| 137 | rctx->b.b.create_video_buffer = vl_video_buffer_create; |
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| 138 | } |
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| 139 | |||
| 140 | r600_init_common_state_functions(rctx); |
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| 141 | |||
| 142 | switch (rctx->b.chip_class) { |
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| 143 | case R600: |
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| 144 | case R700: |
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| 145 | r600_init_state_functions(rctx); |
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| 146 | r600_init_atom_start_cs(rctx); |
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| 147 | rctx->custom_dsa_flush = r600_create_db_flush_dsa(rctx); |
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| 148 | rctx->custom_blend_resolve = rctx->b.chip_class == R700 ? r700_create_resolve_blend(rctx) |
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| 149 | : r600_create_resolve_blend(rctx); |
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| 150 | rctx->custom_blend_decompress = r600_create_decompress_blend(rctx); |
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| 151 | rctx->has_vertex_cache = !(rctx->b.family == CHIP_RV610 || |
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| 152 | rctx->b.family == CHIP_RV620 || |
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| 153 | rctx->b.family == CHIP_RS780 || |
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| 154 | rctx->b.family == CHIP_RS880 || |
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| 155 | rctx->b.family == CHIP_RV710); |
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| 156 | break; |
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| 157 | case EVERGREEN: |
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| 158 | case CAYMAN: |
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| 159 | evergreen_init_state_functions(rctx); |
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| 160 | evergreen_init_atom_start_cs(rctx); |
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| 161 | evergreen_init_atom_start_compute_cs(rctx); |
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| 162 | rctx->custom_dsa_flush = evergreen_create_db_flush_dsa(rctx); |
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| 163 | rctx->custom_blend_resolve = evergreen_create_resolve_blend(rctx); |
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| 164 | rctx->custom_blend_decompress = evergreen_create_decompress_blend(rctx); |
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| 165 | rctx->custom_blend_fastclear = evergreen_create_fastclear_blend(rctx); |
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| 166 | rctx->has_vertex_cache = !(rctx->b.family == CHIP_CEDAR || |
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| 167 | rctx->b.family == CHIP_PALM || |
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| 168 | rctx->b.family == CHIP_SUMO || |
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| 169 | rctx->b.family == CHIP_SUMO2 || |
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| 170 | rctx->b.family == CHIP_CAICOS || |
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| 171 | rctx->b.family == CHIP_CAYMAN || |
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| 172 | rctx->b.family == CHIP_ARUBA); |
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| 173 | break; |
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| 174 | default: |
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| 175 | R600_ERR("Unsupported chip class %d.\n", rctx->b.chip_class); |
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| 176 | goto fail; |
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| 177 | } |
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| 178 | |||
| 179 | rctx->b.rings.gfx.cs = ws->cs_create(ws, RING_GFX, |
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| 180 | r600_context_gfx_flush, rctx, |
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| 181 | rscreen->b.trace_bo ? |
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| 182 | rscreen->b.trace_bo->cs_buf : NULL); |
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| 183 | rctx->b.rings.gfx.flush = r600_context_gfx_flush; |
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| 184 | |||
| 185 | rctx->allocator_fetch_shader = u_suballocator_create(&rctx->b.b, 64 * 1024, 256, |
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| 186 | 0, PIPE_USAGE_DEFAULT, FALSE); |
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| 187 | if (!rctx->allocator_fetch_shader) |
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| 188 | goto fail; |
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| 189 | |||
| 190 | rctx->isa = calloc(1, sizeof(struct r600_isa)); |
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| 191 | if (!rctx->isa || r600_isa_init(rctx, rctx->isa)) |
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| 192 | goto fail; |
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| 193 | |||
| 194 | if (rscreen->b.debug_flags & DBG_FORCE_DMA) |
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| 195 | rctx->b.b.resource_copy_region = rctx->b.dma_copy; |
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| 196 | |||
| 197 | rctx->blitter = util_blitter_create(&rctx->b.b); |
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| 198 | if (rctx->blitter == NULL) |
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| 199 | goto fail; |
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| 200 | util_blitter_set_texture_multisample(rctx->blitter, rscreen->has_msaa); |
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| 201 | rctx->blitter->draw_rectangle = r600_draw_rectangle; |
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| 202 | |||
| 203 | r600_begin_new_cs(rctx); |
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| 204 | r600_query_init_backend_mask(&rctx->b); /* this emits commands and must be last */ |
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| 205 | |||
| 206 | rctx->dummy_pixel_shader = |
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| 207 | util_make_fragment_cloneinput_shader(&rctx->b.b, 0, |
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| 208 | TGSI_SEMANTIC_GENERIC, |
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| 209 | TGSI_INTERPOLATE_CONSTANT); |
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| 210 | rctx->b.b.bind_fs_state(&rctx->b.b, rctx->dummy_pixel_shader); |
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| 211 | |||
| 212 | return &rctx->b.b; |
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| 213 | |||
| 214 | fail: |
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| 215 | r600_destroy_context(&rctx->b.b); |
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| 216 | return NULL; |
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| 217 | } |
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| 218 | |||
| 219 | /* |
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| 220 | * pipe_screen |
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| 221 | */ |
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| 222 | |||
| 223 | static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param) |
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| 224 | { |
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| 225 | struct r600_screen *rscreen = (struct r600_screen *)pscreen; |
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| 226 | enum radeon_family family = rscreen->b.family; |
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| 227 | |||
| 228 | switch (param) { |
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| 229 | /* Supported features (boolean caps). */ |
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| 230 | case PIPE_CAP_NPOT_TEXTURES: |
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| 231 | case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES: |
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| 232 | case PIPE_CAP_TWO_SIDED_STENCIL: |
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| 233 | case PIPE_CAP_ANISOTROPIC_FILTER: |
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| 234 | case PIPE_CAP_POINT_SPRITE: |
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| 235 | case PIPE_CAP_OCCLUSION_QUERY: |
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| 236 | case PIPE_CAP_TEXTURE_SHADOW_MAP: |
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| 237 | case PIPE_CAP_TEXTURE_MIRROR_CLAMP: |
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| 238 | case PIPE_CAP_BLEND_EQUATION_SEPARATE: |
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| 239 | case PIPE_CAP_TEXTURE_SWIZZLE: |
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| 240 | case PIPE_CAP_DEPTH_CLIP_DISABLE: |
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| 241 | case PIPE_CAP_SHADER_STENCIL_EXPORT: |
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| 242 | case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: |
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| 243 | case PIPE_CAP_MIXED_COLORBUFFER_FORMATS: |
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| 244 | case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT: |
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| 245 | case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER: |
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| 246 | case PIPE_CAP_SM3: |
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| 247 | case PIPE_CAP_SEAMLESS_CUBE_MAP: |
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| 248 | case PIPE_CAP_PRIMITIVE_RESTART: |
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| 249 | case PIPE_CAP_CONDITIONAL_RENDER: |
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| 250 | case PIPE_CAP_TEXTURE_BARRIER: |
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| 251 | case PIPE_CAP_VERTEX_COLOR_UNCLAMPED: |
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| 252 | case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION: |
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| 253 | case PIPE_CAP_TGSI_INSTANCEID: |
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| 254 | case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY: |
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| 255 | case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY: |
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| 256 | case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY: |
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| 257 | case PIPE_CAP_USER_INDEX_BUFFERS: |
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| 258 | case PIPE_CAP_USER_CONSTANT_BUFFERS: |
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| 259 | case PIPE_CAP_START_INSTANCE: |
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| 260 | case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS: |
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| 261 | case PIPE_CAP_TEXTURE_BUFFER_OBJECTS: |
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| 262 | case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER: |
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| 263 | case PIPE_CAP_QUERY_PIPELINE_STATISTICS: |
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| 264 | case PIPE_CAP_TEXTURE_MULTISAMPLE: |
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| 265 | case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT: |
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| 266 | case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION: |
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| 267 | case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT: |
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| 268 | case PIPE_CAP_SAMPLE_SHADING: |
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| 269 | case PIPE_CAP_CLIP_HALFZ: |
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| 270 | case PIPE_CAP_POLYGON_OFFSET_CLAMP: |
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| 271 | return 1; |
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| 272 | |||
| 273 | case PIPE_CAP_RESOURCE_FROM_USER_MEMORY: |
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| 274 | return !R600_BIG_ENDIAN && rscreen->b.info.has_userptr; |
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| 275 | |||
| 276 | case PIPE_CAP_COMPUTE: |
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| 277 | return rscreen->b.chip_class > R700; |
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| 278 | |||
| 279 | case PIPE_CAP_TGSI_TEXCOORD: |
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| 280 | return 0; |
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| 281 | |||
| 282 | case PIPE_CAP_FAKE_SW_MSAA: |
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| 283 | return 0; |
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| 284 | |||
| 285 | case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE: |
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| 286 | return MIN2(rscreen->b.info.vram_size, 0xFFFFFFFF); |
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| 287 | |||
| 288 | case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT: |
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| 289 | return R600_MAP_BUFFER_ALIGNMENT; |
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| 290 | |||
| 291 | case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT: |
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| 292 | return 256; |
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| 293 | |||
| 294 | case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT: |
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| 295 | return 1; |
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| 296 | |||
| 297 | case PIPE_CAP_GLSL_FEATURE_LEVEL: |
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| 298 | if (family >= CHIP_CEDAR) |
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| 299 | return 330; |
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| 300 | /* pre-evergreen geom shaders need newer kernel */ |
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| 301 | if (rscreen->b.info.drm_minor >= 37) |
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| 302 | return 330; |
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| 303 | return 140; |
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| 304 | |||
| 305 | /* Supported except the original R600. */ |
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| 306 | case PIPE_CAP_INDEP_BLEND_ENABLE: |
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| 307 | case PIPE_CAP_INDEP_BLEND_FUNC: |
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| 308 | /* R600 doesn't support per-MRT blends */ |
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| 309 | return family == CHIP_R600 ? 0 : 1; |
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| 310 | |||
| 311 | /* Supported on Evergreen. */ |
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| 312 | case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE: |
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| 313 | case PIPE_CAP_CUBE_MAP_ARRAY: |
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| 314 | case PIPE_CAP_TEXTURE_GATHER_SM5: |
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| 315 | case PIPE_CAP_TEXTURE_QUERY_LOD: |
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| 316 | case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE: |
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| 317 | return family >= CHIP_CEDAR ? 1 : 0; |
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| 318 | case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS: |
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| 319 | return family >= CHIP_CEDAR ? 4 : 0; |
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| 320 | case PIPE_CAP_DRAW_INDIRECT: |
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| 321 | /* kernel command checker support is also required */ |
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| 322 | return family >= CHIP_CEDAR && rscreen->b.info.drm_minor >= 41; |
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| 323 | |||
| 324 | /* Unsupported features. */ |
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| 325 | case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT: |
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| 326 | case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER: |
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| 327 | case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS: |
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| 328 | case PIPE_CAP_FRAGMENT_COLOR_CLAMPED: |
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| 329 | case PIPE_CAP_VERTEX_COLOR_CLAMPED: |
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| 330 | case PIPE_CAP_USER_VERTEX_BUFFERS: |
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| 331 | case PIPE_CAP_TEXTURE_GATHER_OFFSETS: |
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| 332 | case PIPE_CAP_CONDITIONAL_RENDER_INVERTED: |
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| 333 | case PIPE_CAP_SAMPLER_VIEW_TARGET: |
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| 334 | case PIPE_CAP_VERTEXID_NOBASE: |
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| 335 | case PIPE_CAP_DEVICE_RESET_STATUS_QUERY: |
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| 336 | return 0; |
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| 337 | |||
| 338 | /* Stream output. */ |
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| 339 | case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS: |
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| 340 | return rscreen->b.has_streamout ? 4 : 0; |
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| 341 | case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME: |
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| 342 | return rscreen->b.has_streamout ? 1 : 0; |
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| 343 | case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS: |
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| 344 | case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS: |
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| 345 | return 32*4; |
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| 346 | |||
| 347 | /* Geometry shader output. */ |
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| 348 | case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES: |
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| 349 | return 1024; |
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| 350 | case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS: |
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| 351 | return 16384; |
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| 352 | case PIPE_CAP_MAX_VERTEX_STREAMS: |
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| 353 | return 1; |
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| 354 | |||
| 355 | case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE: |
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| 356 | return 2047; |
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| 357 | |||
| 358 | /* Texturing. */ |
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| 359 | case PIPE_CAP_MAX_TEXTURE_2D_LEVELS: |
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| 360 | case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS: |
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| 361 | if (family >= CHIP_CEDAR) |
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| 362 | return 15; |
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| 363 | else |
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| 364 | return 14; |
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| 365 | case PIPE_CAP_MAX_TEXTURE_3D_LEVELS: |
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| 366 | /* textures support 8192, but layered rendering supports 2048 */ |
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| 367 | return 12; |
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| 368 | case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS: |
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| 369 | /* textures support 8192, but layered rendering supports 2048 */ |
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| 370 | return rscreen->b.info.drm_minor >= 9 ? 2048 : 0; |
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| 371 | |||
| 372 | /* Render targets. */ |
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| 373 | case PIPE_CAP_MAX_RENDER_TARGETS: |
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| 374 | /* XXX some r6xx are buggy and can only do 4 */ |
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| 375 | return 8; |
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| 376 | |||
| 377 | case PIPE_CAP_MAX_VIEWPORTS: |
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| 378 | return R600_MAX_VIEWPORTS; |
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| 379 | |||
| 380 | /* Timer queries, present when the clock frequency is non zero. */ |
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| 381 | case PIPE_CAP_QUERY_TIME_ELAPSED: |
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| 382 | return rscreen->b.info.r600_clock_crystal_freq != 0; |
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| 383 | case PIPE_CAP_QUERY_TIMESTAMP: |
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| 384 | return rscreen->b.info.drm_minor >= 20 && |
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| 385 | rscreen->b.info.r600_clock_crystal_freq != 0; |
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| 386 | |||
| 387 | case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET: |
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| 388 | case PIPE_CAP_MIN_TEXEL_OFFSET: |
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| 389 | return -8; |
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| 390 | |||
| 391 | case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET: |
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| 392 | case PIPE_CAP_MAX_TEXEL_OFFSET: |
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| 393 | return 7; |
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| 394 | |||
| 395 | case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK: |
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| 396 | return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600; |
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| 397 | case PIPE_CAP_ENDIANNESS: |
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| 398 | return PIPE_ENDIAN_LITTLE; |
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| 399 | |||
| 400 | case PIPE_CAP_VENDOR_ID: |
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| 401 | return 0x1002; |
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| 402 | case PIPE_CAP_DEVICE_ID: |
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| 403 | return rscreen->b.info.pci_id; |
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| 404 | case PIPE_CAP_ACCELERATED: |
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| 405 | return 1; |
||
| 406 | case PIPE_CAP_VIDEO_MEMORY: |
||
| 407 | return rscreen->b.info.vram_size >> 20; |
||
| 408 | case PIPE_CAP_UMA: |
||
| 409 | return 0; |
||
| 410 | case PIPE_CAP_MULTISAMPLE_Z_RESOLVE: |
||
| 411 | return rscreen->b.chip_class >= R700; |
||
| 412 | } |
||
| 413 | return 0; |
||
| 414 | } |
||
| 415 | |||
| 416 | static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param) |
||
| 417 | { |
||
| 418 | struct r600_screen *rscreen = (struct r600_screen *)pscreen; |
||
| 419 | |||
| 420 | switch(shader) |
||
| 421 | { |
||
| 422 | case PIPE_SHADER_FRAGMENT: |
||
| 423 | case PIPE_SHADER_VERTEX: |
||
| 424 | case PIPE_SHADER_COMPUTE: |
||
| 425 | break; |
||
| 426 | case PIPE_SHADER_GEOMETRY: |
||
| 427 | if (rscreen->b.family >= CHIP_CEDAR) |
||
| 428 | break; |
||
| 429 | /* pre-evergreen geom shaders need newer kernel */ |
||
| 430 | if (rscreen->b.info.drm_minor >= 37) |
||
| 431 | break; |
||
| 432 | return 0; |
||
| 433 | default: |
||
| 434 | /* XXX: support tessellation on Evergreen */ |
||
| 435 | return 0; |
||
| 436 | } |
||
| 437 | |||
| 438 | switch (param) { |
||
| 439 | case PIPE_SHADER_CAP_MAX_INSTRUCTIONS: |
||
| 440 | case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS: |
||
| 441 | case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS: |
||
| 442 | case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS: |
||
| 443 | return 16384; |
||
| 444 | case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH: |
||
| 445 | return 32; |
||
| 446 | case PIPE_SHADER_CAP_MAX_INPUTS: |
||
| 447 | return shader == PIPE_SHADER_VERTEX ? 16 : 32; |
||
| 448 | case PIPE_SHADER_CAP_MAX_OUTPUTS: |
||
| 449 | return shader == PIPE_SHADER_FRAGMENT ? 8 : 32; |
||
| 450 | case PIPE_SHADER_CAP_MAX_TEMPS: |
||
| 451 | return 256; /* Max native temporaries. */ |
||
| 452 | case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: |
||
| 453 | if (shader == PIPE_SHADER_COMPUTE) { |
||
| 454 | uint64_t max_const_buffer_size; |
||
| 455 | pscreen->get_compute_param(pscreen, |
||
| 456 | PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE, |
||
| 457 | &max_const_buffer_size); |
||
| 458 | return max_const_buffer_size; |
||
| 459 | |||
| 460 | } else { |
||
| 461 | return R600_MAX_CONST_BUFFER_SIZE; |
||
| 462 | } |
||
| 463 | case PIPE_SHADER_CAP_MAX_CONST_BUFFERS: |
||
| 464 | return R600_MAX_USER_CONST_BUFFERS; |
||
| 465 | case PIPE_SHADER_CAP_MAX_PREDS: |
||
| 466 | return 0; /* nothing uses this */ |
||
| 467 | case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED: |
||
| 468 | return 1; |
||
| 469 | case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED: |
||
| 470 | return 1; |
||
| 471 | case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR: |
||
| 472 | case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR: |
||
| 473 | case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR: |
||
| 474 | case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR: |
||
| 475 | return 1; |
||
| 476 | case PIPE_SHADER_CAP_SUBROUTINES: |
||
| 477 | return 0; |
||
| 478 | case PIPE_SHADER_CAP_INTEGERS: |
||
| 479 | return 1; |
||
| 480 | case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS: |
||
| 481 | case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS: |
||
| 482 | return 16; |
||
| 483 | case PIPE_SHADER_CAP_PREFERRED_IR: |
||
| 484 | if (shader == PIPE_SHADER_COMPUTE) { |
||
| 485 | #if HAVE_LLVM < 0x0306 |
||
| 486 | return PIPE_SHADER_IR_LLVM; |
||
| 487 | #else |
||
| 488 | return PIPE_SHADER_IR_NATIVE; |
||
| 489 | #endif |
||
| 490 | } else { |
||
| 491 | return PIPE_SHADER_IR_TGSI; |
||
| 492 | } |
||
| 493 | case PIPE_SHADER_CAP_DOUBLES: |
||
| 494 | return 0; |
||
| 495 | case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED: |
||
| 496 | case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED: |
||
| 497 | case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED: |
||
| 498 | return 0; |
||
| 499 | } |
||
| 500 | return 0; |
||
| 501 | } |
||
| 502 | |||
| 503 | static void r600_destroy_screen(struct pipe_screen* pscreen) |
||
| 504 | { |
||
| 505 | struct r600_screen *rscreen = (struct r600_screen *)pscreen; |
||
| 506 | |||
| 507 | if (rscreen == NULL) |
||
| 508 | return; |
||
| 509 | |||
| 510 | if (!rscreen->b.ws->unref(rscreen->b.ws)) |
||
| 511 | return; |
||
| 512 | |||
| 513 | if (rscreen->global_pool) { |
||
| 514 | compute_memory_pool_delete(rscreen->global_pool); |
||
| 515 | } |
||
| 516 | |||
| 517 | r600_destroy_common_screen(&rscreen->b); |
||
| 518 | } |
||
| 519 | |||
| 520 | static struct pipe_resource *r600_resource_create(struct pipe_screen *screen, |
||
| 521 | const struct pipe_resource *templ) |
||
| 522 | { |
||
| 523 | if (templ->target == PIPE_BUFFER && |
||
| 524 | (templ->bind & PIPE_BIND_GLOBAL)) |
||
| 525 | return r600_compute_global_buffer_create(screen, templ); |
||
| 526 | |||
| 527 | return r600_resource_create_common(screen, templ); |
||
| 528 | } |
||
| 529 | |||
| 530 | struct pipe_screen *r600_screen_create(struct radeon_winsys *ws) |
||
| 531 | { |
||
| 532 | struct r600_screen *rscreen = CALLOC_STRUCT(r600_screen); |
||
| 533 | |||
| 534 | if (rscreen == NULL) { |
||
| 535 | return NULL; |
||
| 536 | } |
||
| 537 | |||
| 538 | /* Set functions first. */ |
||
| 539 | rscreen->b.b.context_create = r600_create_context; |
||
| 540 | rscreen->b.b.destroy = r600_destroy_screen; |
||
| 541 | rscreen->b.b.get_param = r600_get_param; |
||
| 542 | rscreen->b.b.get_shader_param = r600_get_shader_param; |
||
| 543 | rscreen->b.b.resource_create = r600_resource_create; |
||
| 544 | |||
| 545 | if (!r600_common_screen_init(&rscreen->b, ws)) { |
||
| 546 | FREE(rscreen); |
||
| 547 | return NULL; |
||
| 548 | } |
||
| 549 | |||
| 550 | if (rscreen->b.info.chip_class >= EVERGREEN) { |
||
| 551 | rscreen->b.b.is_format_supported = evergreen_is_format_supported; |
||
| 552 | } else { |
||
| 553 | rscreen->b.b.is_format_supported = r600_is_format_supported; |
||
| 554 | } |
||
| 555 | |||
| 556 | rscreen->b.debug_flags |= debug_get_flags_option("R600_DEBUG", r600_debug_options, 0); |
||
| 557 | if (debug_get_bool_option("R600_DEBUG_COMPUTE", FALSE)) |
||
| 558 | rscreen->b.debug_flags |= DBG_COMPUTE; |
||
| 559 | if (debug_get_bool_option("R600_DUMP_SHADERS", FALSE)) |
||
| 560 | rscreen->b.debug_flags |= DBG_FS | DBG_VS | DBG_GS | DBG_PS | DBG_CS; |
||
| 561 | if (!debug_get_bool_option("R600_HYPERZ", TRUE)) |
||
| 562 | rscreen->b.debug_flags |= DBG_NO_HYPERZ; |
||
| 563 | if (debug_get_bool_option("R600_LLVM", FALSE)) |
||
| 564 | rscreen->b.debug_flags |= DBG_LLVM; |
||
| 565 | |||
| 566 | if (rscreen->b.family == CHIP_UNKNOWN) { |
||
| 567 | fprintf(stderr, "r600: Unknown chipset 0x%04X\n", rscreen->b.info.pci_id); |
||
| 568 | FREE(rscreen); |
||
| 569 | return NULL; |
||
| 570 | } |
||
| 571 | |||
| 572 | /* Figure out streamout kernel support. */ |
||
| 573 | switch (rscreen->b.chip_class) { |
||
| 574 | case R600: |
||
| 575 | if (rscreen->b.family < CHIP_RS780) { |
||
| 576 | rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 14; |
||
| 577 | } else { |
||
| 578 | rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 23; |
||
| 579 | } |
||
| 580 | break; |
||
| 581 | case R700: |
||
| 582 | rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 17; |
||
| 583 | break; |
||
| 584 | case EVERGREEN: |
||
| 585 | case CAYMAN: |
||
| 586 | rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 14; |
||
| 587 | break; |
||
| 588 | default: |
||
| 589 | rscreen->b.has_streamout = FALSE; |
||
| 590 | break; |
||
| 591 | } |
||
| 592 | |||
| 593 | /* MSAA support. */ |
||
| 594 | switch (rscreen->b.chip_class) { |
||
| 595 | case R600: |
||
| 596 | case R700: |
||
| 597 | rscreen->has_msaa = rscreen->b.info.drm_minor >= 22; |
||
| 598 | rscreen->has_compressed_msaa_texturing = false; |
||
| 599 | break; |
||
| 600 | case EVERGREEN: |
||
| 601 | rscreen->has_msaa = rscreen->b.info.drm_minor >= 19; |
||
| 602 | rscreen->has_compressed_msaa_texturing = rscreen->b.info.drm_minor >= 24; |
||
| 603 | break; |
||
| 604 | case CAYMAN: |
||
| 605 | rscreen->has_msaa = rscreen->b.info.drm_minor >= 19; |
||
| 606 | rscreen->has_compressed_msaa_texturing = true; |
||
| 607 | break; |
||
| 608 | default: |
||
| 609 | rscreen->has_msaa = FALSE; |
||
| 610 | rscreen->has_compressed_msaa_texturing = false; |
||
| 611 | } |
||
| 612 | |||
| 613 | rscreen->b.has_cp_dma = rscreen->b.info.drm_minor >= 27 && |
||
| 614 | !(rscreen->b.debug_flags & DBG_NO_CP_DMA); |
||
| 615 | |||
| 616 | rscreen->global_pool = compute_memory_pool_new(rscreen); |
||
| 617 | |||
| 618 | /* Create the auxiliary context. This must be done last. */ |
||
| 619 | rscreen->b.aux_context = rscreen->b.b.context_create(&rscreen->b.b, NULL); |
||
| 620 | |||
| 621 | #if 0 /* This is for testing whether aux_context and buffer clearing work correctly. */ |
||
| 622 | struct pipe_resource templ = {}; |
||
| 623 | |||
| 624 | templ.width0 = 4; |
||
| 625 | templ.height0 = 2048; |
||
| 626 | templ.depth0 = 1; |
||
| 627 | templ.array_size = 1; |
||
| 628 | templ.target = PIPE_TEXTURE_2D; |
||
| 629 | templ.format = PIPE_FORMAT_R8G8B8A8_UNORM; |
||
| 630 | templ.usage = PIPE_USAGE_DEFAULT; |
||
| 631 | |||
| 632 | struct r600_resource *res = r600_resource(rscreen->screen.resource_create(&rscreen->screen, &templ)); |
||
| 633 | unsigned char *map = ws->buffer_map(res->cs_buf, NULL, PIPE_TRANSFER_WRITE); |
||
| 634 | |||
| 635 | memset(map, 0, 256); |
||
| 636 | |||
| 637 | r600_screen_clear_buffer(rscreen, &res->b.b, 4, 4, 0xCC); |
||
| 638 | r600_screen_clear_buffer(rscreen, &res->b.b, 8, 4, 0xDD); |
||
| 639 | r600_screen_clear_buffer(rscreen, &res->b.b, 12, 4, 0xEE); |
||
| 640 | r600_screen_clear_buffer(rscreen, &res->b.b, 20, 4, 0xFF); |
||
| 641 | r600_screen_clear_buffer(rscreen, &res->b.b, 32, 20, 0x87); |
||
| 642 | |||
| 643 | ws->buffer_wait(res->buf, RADEON_USAGE_WRITE); |
||
| 644 | |||
| 645 | int i; |
||
| 646 | for (i = 0; i < 256; i++) { |
||
| 647 | printf("%02X", map[i]); |
||
| 648 | if (i % 16 == 15) |
||
| 649 | printf("\n"); |
||
| 650 | } |
||
| 651 | #endif |
||
| 652 | |||
| 653 | return &rscreen->b.b; |
||
| 654 | } |