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5564 | serge | 1 | #ifndef GEN_RENDER_MEDIA_XML |
2 | #define GEN_RENDER_MEDIA_XML |
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3 | |||
4 | /* Autogenerated file, DO NOT EDIT manually! |
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5 | |||
6 | This file was generated by the rules-ng-ng headergen tool in this git repository: |
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7 | https://github.com/olvaffe/envytools/ |
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8 | git clone https://github.com/olvaffe/envytools.git |
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9 | |||
10 | Copyright (C) 2014-2015 by the following authors: |
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11 | - Chia-I Wu |
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12 | |||
13 | Permission is hereby granted, free of charge, to any person obtaining |
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14 | a copy of this software and associated documentation files (the |
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15 | "Software"), to deal in the Software without restriction, including |
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16 | without limitation the rights to use, copy, modify, merge, publish, |
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17 | distribute, sublicense, and/or sell copies of the Software, and to |
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18 | permit persons to whom the Software is furnished to do so, subject to |
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19 | the following conditions: |
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20 | |||
21 | The above copyright notice and this permission notice (including the |
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22 | next paragraph) shall be included in all copies or substantial |
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23 | portions of the Software. |
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24 | |||
25 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
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26 | EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
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27 | MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
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28 | IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE |
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29 | LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION |
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30 | OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION |
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31 | WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
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32 | */ |
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33 | |||
34 | |||
35 | #define GEN6_INTERFACE_DESCRIPTOR_DATA__SIZE 8 |
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36 | |||
37 | #define GEN6_IDRT_DW0_KERNEL_ADDR__MASK 0xffffffc0 |
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38 | #define GEN6_IDRT_DW0_KERNEL_ADDR__SHIFT 6 |
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39 | #define GEN6_IDRT_DW0_KERNEL_ADDR__SHR 6 |
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40 | |||
41 | #define GEN6_IDRT_DW1_SPF (0x1 << 18) |
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42 | #define GEN6_IDRT_DW1_PRIORITY_HIGH (0x1 << 17) |
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43 | #define GEN6_IDRT_DW1_FP_MODE_ALT (0x1 << 16) |
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44 | #define GEN6_IDRT_DW1_ILLEGAL_CODE_EXCEPTION (0x1 << 13) |
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45 | #define GEN6_IDRT_DW1_MASK_STACK_EXCEPTION (0x1 << 11) |
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46 | #define GEN6_IDRT_DW1_SOFTWARE_EXCEPTION (0x1 << 7) |
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47 | |||
48 | #define GEN6_IDRT_DW2_SAMPLER_COUNT__MASK 0x0000001c |
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49 | #define GEN6_IDRT_DW2_SAMPLER_COUNT__SHIFT 2 |
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50 | #define GEN6_IDRT_DW2_SAMPLER_ADDR__MASK 0xffffffe0 |
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51 | #define GEN6_IDRT_DW2_SAMPLER_ADDR__SHIFT 5 |
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52 | #define GEN6_IDRT_DW2_SAMPLER_ADDR__SHR 5 |
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53 | |||
54 | #define GEN6_IDRT_DW3_BINDING_TABLE_SIZE__MASK 0x0000001f |
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55 | #define GEN6_IDRT_DW3_BINDING_TABLE_SIZE__SHIFT 0 |
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56 | |||
57 | #define GEN6_IDRT_DW4_CURBE_READ_LEN__MASK 0xffff0000 |
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58 | #define GEN6_IDRT_DW4_CURBE_READ_LEN__SHIFT 16 |
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59 | #define GEN6_IDRT_DW4_CURBE_READ_OFFSET__MASK 0x0000ffff |
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60 | #define GEN6_IDRT_DW4_CURBE_READ_OFFSET__SHIFT 0 |
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61 | |||
62 | #define GEN6_IDRT_DW5_BARRIER_ID__MASK 0x0000000f |
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63 | #define GEN6_IDRT_DW5_BARRIER_ID__SHIFT 0 |
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64 | |||
65 | #define GEN7_IDRT_DW5_BARRIER_RETURN_GRF__MASK 0xff000000 |
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66 | #define GEN7_IDRT_DW5_BARRIER_RETURN_GRF__SHIFT 24 |
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67 | #define GEN7_IDRT_DW5_ROUNDING_MODE__MASK 0x00c00000 |
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68 | #define GEN7_IDRT_DW5_ROUNDING_MODE__SHIFT 22 |
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69 | #define GEN7_IDRT_DW5_ROUNDING_MODE_RTNE (0x0 << 22) |
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70 | #define GEN7_IDRT_DW5_ROUNDING_MODE_RU (0x1 << 22) |
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71 | #define GEN7_IDRT_DW5_ROUNDING_MODE_RD (0x2 << 22) |
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72 | #define GEN7_IDRT_DW5_ROUNDING_MODE_RTZ (0x3 << 22) |
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73 | #define GEN7_IDRT_DW5_BARRIER_ENABLE (0x1 << 21) |
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74 | #define GEN7_IDRT_DW5_SLM_SIZE__MASK 0x001f0000 |
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75 | #define GEN7_IDRT_DW5_SLM_SIZE__SHIFT 16 |
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76 | #define GEN7_IDRT_DW5_BARRIER_RETURN_BYTE__MASK 0x0000ff00 |
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77 | #define GEN7_IDRT_DW5_BARRIER_RETURN_BYTE__SHIFT 8 |
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78 | #define GEN7_IDRT_DW5_THREAD_GROUP_SIZE__MASK 0x000000ff |
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79 | #define GEN7_IDRT_DW5_THREAD_GROUP_SIZE__SHIFT 0 |
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80 | |||
81 | #define GEN75_IDRT_DW6_CROSS_THREAD_CURBE_READ_LEN__MASK 0x000000ff |
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82 | #define GEN75_IDRT_DW6_CROSS_THREAD_CURBE_READ_LEN__SHIFT 0 |
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83 | |||
84 | |||
85 | |||
86 | #define GEN8_IDRT_DW0_KERNEL_ADDR__MASK 0xffffffc0 |
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87 | #define GEN8_IDRT_DW0_KERNEL_ADDR__SHIFT 6 |
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88 | #define GEN8_IDRT_DW0_KERNEL_ADDR__SHR 6 |
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89 | |||
90 | |||
91 | #define GEN8_IDRT_DW2_THREAD_PREEMPTION_DISABLE (0x1 << 20) |
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92 | #define GEN8_IDRT_DW2_DENORM__MASK 0x00080000 |
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93 | #define GEN8_IDRT_DW2_DENORM__SHIFT 19 |
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94 | #define GEN8_IDRT_DW2_DENORM_FTZ (0x0 << 19) |
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95 | #define GEN8_IDRT_DW2_DENORM_RET (0x1 << 19) |
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96 | #define GEN8_IDRT_DW2_SPF (0x1 << 18) |
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97 | #define GEN8_IDRT_DW2_PRIORITY_HIGH (0x1 << 17) |
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98 | #define GEN8_IDRT_DW2_FP_MODE_ALT (0x1 << 16) |
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99 | #define GEN8_IDRT_DW2_ILLEGAL_CODE_EXCEPTION (0x1 << 13) |
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100 | #define GEN8_IDRT_DW2_MASK_STACK_EXCEPTION (0x1 << 11) |
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101 | #define GEN8_IDRT_DW2_SOFTWARE_EXCEPTION (0x1 << 7) |
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102 | |||
103 | #define GEN8_IDRT_DW3_SAMPLER_COUNT__MASK 0x0000001c |
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104 | #define GEN8_IDRT_DW3_SAMPLER_COUNT__SHIFT 2 |
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105 | #define GEN8_IDRT_DW3_SAMPLER_ADDR__MASK 0xffffffe0 |
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106 | #define GEN8_IDRT_DW3_SAMPLER_ADDR__SHIFT 5 |
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107 | #define GEN8_IDRT_DW3_SAMPLER_ADDR__SHR 5 |
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108 | |||
109 | #define GEN8_IDRT_DW4_BINDING_TABLE_SIZE__MASK 0x0000001f |
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110 | #define GEN8_IDRT_DW4_BINDING_TABLE_SIZE__SHIFT 0 |
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111 | |||
112 | #define GEN8_IDRT_DW5_CURBE_READ_LEN__MASK 0xffff0000 |
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113 | #define GEN8_IDRT_DW5_CURBE_READ_LEN__SHIFT 16 |
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114 | |||
115 | #define GEN8_IDRT_DW6_ROUNDING_MODE__MASK 0x00c00000 |
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116 | #define GEN8_IDRT_DW6_ROUNDING_MODE__SHIFT 22 |
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117 | #define GEN8_IDRT_DW6_ROUNDING_MODE_RTNE (0x0 << 22) |
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118 | #define GEN8_IDRT_DW6_ROUNDING_MODE_RU (0x1 << 22) |
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119 | #define GEN8_IDRT_DW6_ROUNDING_MODE_RD (0x2 << 22) |
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120 | #define GEN8_IDRT_DW6_ROUNDING_MODE_RTZ (0x3 << 22) |
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121 | #define GEN8_IDRT_DW6_BARRIER_ENABLE (0x1 << 21) |
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122 | #define GEN8_IDRT_DW6_SLM_SIZE__MASK 0x001f0000 |
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123 | #define GEN8_IDRT_DW6_SLM_SIZE__SHIFT 16 |
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124 | #define GEN8_IDRT_DW6_THREAD_GROUP_SIZE__MASK 0x000000ff |
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125 | #define GEN8_IDRT_DW6_THREAD_GROUP_SIZE__SHIFT 0 |
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126 | |||
127 | #define GEN8_IDRT_DW7_CROSS_THREAD_CURBE_READ_LEN__MASK 0x000000ff |
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128 | #define GEN8_IDRT_DW7_CROSS_THREAD_CURBE_READ_LEN__SHIFT 0 |
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129 | |||
130 | #define GEN6_MEDIA_VFE_STATE__SIZE 9 |
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131 | |||
132 | |||
133 | #define GEN6_VFE_DW1_SCRATCH_STACK_SIZE__MASK 0x000000f0 |
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134 | #define GEN6_VFE_DW1_SCRATCH_STACK_SIZE__SHIFT 4 |
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135 | #define GEN6_VFE_DW1_SCRATCH_SPACE_PER_THREAD__MASK 0x0000000f |
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136 | #define GEN6_VFE_DW1_SCRATCH_SPACE_PER_THREAD__SHIFT 0 |
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137 | #define GEN6_VFE_DW1_SCRATCH_ADDR__MASK 0xfffffc00 |
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138 | #define GEN6_VFE_DW1_SCRATCH_ADDR__SHIFT 10 |
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139 | #define GEN6_VFE_DW1_SCRATCH_ADDR__SHR 10 |
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140 | |||
141 | #define GEN6_VFE_DW2_MAX_THREADS__MASK 0xffff0000 |
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142 | #define GEN6_VFE_DW2_MAX_THREADS__SHIFT 16 |
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143 | #define GEN6_VFE_DW2_URB_ENTRY_COUNT__MASK 0x0000ff00 |
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144 | #define GEN6_VFE_DW2_URB_ENTRY_COUNT__SHIFT 8 |
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145 | #define GEN6_VFE_DW2_RESET_GATEWAY_TIMER (0x1 << 7) |
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146 | #define GEN6_VFE_DW2_BYPASS_GATEWAY_CONTROL (0x1 << 6) |
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147 | #define GEN6_VFE_DW2_FAST_PREEMPT (0x1 << 5) |
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148 | #define GEN7_VFE_DW2_GATEWAY_MMIO__MASK 0x00000018 |
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149 | #define GEN7_VFE_DW2_GATEWAY_MMIO__SHIFT 3 |
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150 | #define GEN7_VFE_DW2_GATEWAY_MMIO_NONE (0x0 << 3) |
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151 | #define GEN7_VFE_DW2_GATEWAY_MMIO_ANY (0x2 << 3) |
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152 | #define GEN7_VFE_DW2_GPGPU_MODE (0x1 << 2) |
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153 | |||
154 | #define GEN75_VFE_DW3_HALF_SLICE_DISABLE__MASK 0x00000003 |
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155 | #define GEN75_VFE_DW3_HALF_SLICE_DISABLE__SHIFT 0 |
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156 | #define GEN75_VFE_DW3_HALF_SLICE_DISABLE_NONE 0x0 |
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157 | #define GEN75_VFE_DW3_HALF_SLICE_DISABLE_23 0x1 |
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158 | #define GEN75_VFE_DW3_HALF_SLICE_DISABLE_123 0x3 |
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159 | |||
160 | #define GEN6_VFE_DW4_URB_ENTRY_SIZE__MASK 0xffff0000 |
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161 | #define GEN6_VFE_DW4_URB_ENTRY_SIZE__SHIFT 16 |
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162 | #define GEN6_VFE_DW4_CURBE_SIZE__MASK 0x0000ffff |
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163 | #define GEN6_VFE_DW4_CURBE_SIZE__SHIFT 0 |
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164 | |||
165 | #define GEN6_VFE_DW5_SCOREBOARD_ENABLE (0x1 << 31) |
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166 | #define GEN6_VFE_DW5_SCOREBOARD_TYPE__MASK 0x40000000 |
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167 | #define GEN6_VFE_DW5_SCOREBOARD_TYPE__SHIFT 30 |
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168 | #define GEN6_VFE_DW5_SCOREBOARD_TYPE_STALLING (0x0 << 30) |
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169 | #define GEN6_VFE_DW5_SCOREBOARD_TYPE_NON_STALLING (0x1 << 30) |
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170 | #define GEN6_VFE_DW5_SCOREBOARD_MASK__MASK 0x000000ff |
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171 | #define GEN6_VFE_DW5_SCOREBOARD_MASK__SHIFT 0 |
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172 | |||
173 | |||
174 | |||
175 | |||
176 | #define GEN8_VFE_DW1_SCRATCH_STACK_SIZE__MASK 0x000000f0 |
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177 | #define GEN8_VFE_DW1_SCRATCH_STACK_SIZE__SHIFT 4 |
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178 | #define GEN8_VFE_DW1_SCRATCH_SPACE_PER_THREAD__MASK 0x0000000f |
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179 | #define GEN8_VFE_DW1_SCRATCH_SPACE_PER_THREAD__SHIFT 0 |
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180 | #define GEN8_VFE_DW1_SCRATCH_ADDR__MASK 0xfffffc00 |
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181 | #define GEN8_VFE_DW1_SCRATCH_ADDR__SHIFT 10 |
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182 | #define GEN8_VFE_DW1_SCRATCH_ADDR__SHR 10 |
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183 | |||
184 | |||
185 | #define GEN8_VFE_DW3_MAX_THREADS__MASK 0xffff0000 |
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186 | #define GEN8_VFE_DW3_MAX_THREADS__SHIFT 16 |
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187 | #define GEN8_VFE_DW3_URB_ENTRY_COUNT__MASK 0x0000ff00 |
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188 | #define GEN8_VFE_DW3_URB_ENTRY_COUNT__SHIFT 8 |
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189 | #define GEN8_VFE_DW3_RESET_GATEWAY_TIMER (0x1 << 7) |
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190 | #define GEN8_VFE_DW3_BYPASS_GATEWAY_CONTROL (0x1 << 6) |
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191 | |||
192 | #define GEN8_VFE_DW4_HALF_SLICE_DISABLE__MASK 0x00000003 |
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193 | #define GEN8_VFE_DW4_HALF_SLICE_DISABLE__SHIFT 0 |
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194 | #define GEN8_VFE_DW4_HALF_SLICE_DISABLE_NONE 0x0 |
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195 | #define GEN8_VFE_DW4_HALF_SLICE_DISABLE_23 0x1 |
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196 | #define GEN8_VFE_DW4_HALF_SLICE_DISABLE_123 0x3 |
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197 | |||
198 | #define GEN8_VFE_DW5_URB_ENTRY_SIZE__MASK 0xffff0000 |
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199 | #define GEN8_VFE_DW5_URB_ENTRY_SIZE__SHIFT 16 |
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200 | #define GEN8_VFE_DW5_CURBE_SIZE__MASK 0x0000ffff |
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201 | #define GEN8_VFE_DW5_CURBE_SIZE__SHIFT 0 |
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202 | |||
203 | #define GEN8_VFE_DW6_SCOREBOARD_ENABLE (0x1 << 31) |
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204 | #define GEN8_VFE_DW6_SCOREBOARD_TYPE__MASK 0x40000000 |
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205 | #define GEN8_VFE_DW6_SCOREBOARD_TYPE__SHIFT 30 |
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206 | #define GEN8_VFE_DW6_SCOREBOARD_TYPE_STALLING (0x0 << 30) |
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207 | #define GEN8_VFE_DW6_SCOREBOARD_TYPE_NON_STALLING (0x1 << 30) |
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208 | #define GEN8_VFE_DW6_SCOREBOARD_MASK__MASK 0x000000ff |
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209 | #define GEN8_VFE_DW6_SCOREBOARD_MASK__SHIFT 0 |
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210 | |||
211 | |||
212 | #define GEN6_MEDIA_CURBE_LOAD__SIZE 4 |
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213 | |||
214 | |||
215 | |||
216 | #define GEN6_CURBE_LOAD_DW2_LEN__MASK 0x0001ffff |
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217 | #define GEN6_CURBE_LOAD_DW2_LEN__SHIFT 0 |
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218 | |||
219 | #define GEN6_CURBE_LOAD_DW3_ADDR__MASK 0xffffffe0 |
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220 | #define GEN6_CURBE_LOAD_DW3_ADDR__SHIFT 5 |
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221 | #define GEN6_CURBE_LOAD_DW3_ADDR__SHR 5 |
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222 | |||
223 | #define GEN6_MEDIA_INTERFACE_DESCRIPTOR_LOAD__SIZE 4 |
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224 | |||
225 | |||
226 | |||
227 | #define GEN6_IDRT_LOAD_DW2_LEN__MASK 0x0001ffff |
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228 | #define GEN6_IDRT_LOAD_DW2_LEN__SHIFT 0 |
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229 | |||
230 | #define GEN6_IDRT_LOAD_DW3_ADDR__MASK 0xffffffe0 |
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231 | #define GEN6_IDRT_LOAD_DW3_ADDR__SHIFT 5 |
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232 | #define GEN6_IDRT_LOAD_DW3_ADDR__SHR 5 |
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233 | |||
234 | #define GEN6_MEDIA_STATE_FLUSH__SIZE 2 |
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235 | |||
236 | |||
237 | #define GEN6_MEDIA_FLUSH_DW1_THREAD_COUNT_WATERMARK__MASK 0x00ff0000 |
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238 | #define GEN6_MEDIA_FLUSH_DW1_THREAD_COUNT_WATERMARK__SHIFT 16 |
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239 | #define GEN6_MEDIA_FLUSH_DW1_BARRIER_MASK__MASK 0x0000ffff |
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240 | #define GEN6_MEDIA_FLUSH_DW1_BARRIER_MASK__SHIFT 0 |
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241 | |||
242 | #define GEN7_MEDIA_FLUSH_DW1_DISABLE_PREEMPTION (0x1 << 8) |
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243 | #define GEN75_MEDIA_FLUSH_DW1_FLUSH_TO_GO (0x1 << 7) |
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244 | #define GEN7_MEDIA_FLUSH_DW1_WATERMARK_REQUIRED (0x1 << 6) |
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245 | #define GEN7_MEDIA_FLUSH_DW1_IDRT_OFFSET__MASK 0x0000003f |
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246 | #define GEN7_MEDIA_FLUSH_DW1_IDRT_OFFSET__SHIFT 0 |
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247 | |||
248 | #define GEN7_GPGPU_WALKER__SIZE 15 |
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249 | |||
250 | #define GEN7_GPGPU_DW0_INDIRECT_PARAM_ENABLE (0x1 << 10) |
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251 | #define GEN7_GPGPU_DW0_PREDICATE_ENABLE (0x1 << 8) |
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252 | |||
253 | #define GEN7_GPGPU_DW1_IDRT_OFFSET__MASK 0x0000003f |
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254 | #define GEN7_GPGPU_DW1_IDRT_OFFSET__SHIFT 0 |
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255 | |||
256 | #define GEN7_GPGPU_DW2_SIMD_SIZE__MASK 0xc0000000 |
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257 | #define GEN7_GPGPU_DW2_SIMD_SIZE__SHIFT 30 |
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258 | #define GEN7_GPGPU_DW2_SIMD_SIZE_SIMD8 (0x0 << 30) |
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259 | #define GEN7_GPGPU_DW2_SIMD_SIZE_SIMD16 (0x1 << 30) |
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260 | #define GEN7_GPGPU_DW2_SIMD_SIZE_SIMD32 (0x2 << 30) |
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261 | #define GEN7_GPGPU_DW2_THREAD_MAX_Z__MASK 0x003f0000 |
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262 | #define GEN7_GPGPU_DW2_THREAD_MAX_Z__SHIFT 16 |
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263 | #define GEN7_GPGPU_DW2_THREAD_MAX_Y__MASK 0x00003f00 |
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264 | #define GEN7_GPGPU_DW2_THREAD_MAX_Y__SHIFT 8 |
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265 | #define GEN7_GPGPU_DW2_THREAD_MAX_X__MASK 0x0000003f |
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266 | #define GEN7_GPGPU_DW2_THREAD_MAX_X__SHIFT 0 |
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267 | |||
268 | |||
269 | |||
270 | |||
271 | |||
272 | |||
273 | |||
274 | |||
275 | |||
276 | |||
277 | #define GEN8_GPGPU_DW0_INDIRECT_PARAM_ENABLE (0x1 << 10) |
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278 | #define GEN8_GPGPU_DW0_PREDICATE_ENABLE (0x1 << 8) |
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279 | |||
280 | #define GEN8_GPGPU_DW1_IDRT_OFFSET__MASK 0x0000003f |
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281 | #define GEN8_GPGPU_DW1_IDRT_OFFSET__SHIFT 0 |
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282 | |||
283 | |||
284 | #define GEN8_GPGPU_DW3_INDIRECT_ADDR__MASK 0xffffffe0 |
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285 | #define GEN8_GPGPU_DW3_INDIRECT_ADDR__SHIFT 5 |
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286 | #define GEN8_GPGPU_DW3_INDIRECT_ADDR__SHR 5 |
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287 | |||
288 | #define GEN8_GPGPU_DW4_SIMD_SIZE__MASK 0xc0000000 |
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289 | #define GEN8_GPGPU_DW4_SIMD_SIZE__SHIFT 30 |
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290 | #define GEN8_GPGPU_DW4_SIMD_SIZE_SIMD8 (0x0 << 30) |
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291 | #define GEN8_GPGPU_DW4_SIMD_SIZE_SIMD16 (0x1 << 30) |
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292 | #define GEN8_GPGPU_DW4_SIMD_SIZE_SIMD32 (0x2 << 30) |
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293 | #define GEN8_GPGPU_DW4_THREAD_MAX_Z__MASK 0x003f0000 |
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294 | #define GEN8_GPGPU_DW4_THREAD_MAX_Z__SHIFT 16 |
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295 | #define GEN8_GPGPU_DW4_THREAD_MAX_Y__MASK 0x00003f00 |
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296 | #define GEN8_GPGPU_DW4_THREAD_MAX_Y__SHIFT 8 |
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297 | #define GEN8_GPGPU_DW4_THREAD_MAX_X__MASK 0x0000003f |
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298 | #define GEN8_GPGPU_DW4_THREAD_MAX_X__SHIFT 0 |
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299 | |||
300 | |||
301 | |||
302 | |||
303 | |||
304 | |||
305 | |||
306 | |||
307 | |||
308 | |||
309 | |||
310 | |||
311 | #endif /* GEN_RENDER_MEDIA_XML */><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><> |