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5564 serge 1
/* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
2
 
3
/*
4
 * Copyright (C) 2012 Rob Clark 
5
 *
6
 * Permission is hereby granted, free of charge, to any person obtaining a
7
 * copy of this software and associated documentation files (the "Software"),
8
 * to deal in the Software without restriction, including without limitation
9
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10
 * and/or sell copies of the Software, and to permit persons to whom the
11
 * Software is furnished to do so, subject to the following conditions:
12
 *
13
 * The above copyright notice and this permission notice (including the next
14
 * paragraph) shall be included in all copies or substantial portions of the
15
 * Software.
16
 *
17
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
20
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23
 * SOFTWARE.
24
 *
25
 * Authors:
26
 *    Rob Clark 
27
 */
28
 
29
 
30
#include "pipe/p_defines.h"
31
#include "pipe/p_screen.h"
32
#include "pipe/p_state.h"
33
 
34
#include "util/u_memory.h"
35
#include "util/u_inlines.h"
36
#include "util/u_format.h"
37
#include "util/u_format_s3tc.h"
38
#include "util/u_string.h"
39
#include "util/u_debug.h"
40
 
41
#include "os/os_time.h"
42
 
43
#include 
44
#include 
45
#include 
46
 
47
#include "freedreno_screen.h"
48
#include "freedreno_resource.h"
49
#include "freedreno_fence.h"
50
#include "freedreno_query.h"
51
#include "freedreno_util.h"
52
 
53
#include "a2xx/fd2_screen.h"
54
#include "a3xx/fd3_screen.h"
55
#include "a4xx/fd4_screen.h"
56
 
57
/* XXX this should go away */
58
#include "state_tracker/drm_driver.h"
59
 
60
static const struct debug_named_value debug_options[] = {
61
		{"msgs",      FD_DBG_MSGS,   "Print debug messages"},
62
		{"disasm",    FD_DBG_DISASM, "Dump TGSI and adreno shader disassembly"},
63
		{"dclear",    FD_DBG_DCLEAR, "Mark all state dirty after clear"},
64
		{"flush",     FD_DBG_FLUSH,  "Force flush after every draw"},
65
		{"noscis",    FD_DBG_NOSCIS, "Disable scissor optimization"},
66
		{"direct",    FD_DBG_DIRECT, "Force inline (SS_DIRECT) state loads"},
67
		{"nobypass",  FD_DBG_NOBYPASS, "Disable GMEM bypass"},
68
		{"fraghalf",  FD_DBG_FRAGHALF, "Use half-precision in fragment shader"},
69
		{"nobin",     FD_DBG_NOBIN,  "Disable hw binning"},
70
		{"optmsgs",   FD_DBG_OPTMSGS,"Enable optimizer debug messages"},
71
		{"optdump",   FD_DBG_OPTDUMP,"Dump shader DAG to .dot files"},
72
		{"glsl120",   FD_DBG_GLSL120,"Temporary flag to force GLSL 120 (rather than 130) on a3xx+"},
73
		{"nocp",      FD_DBG_NOCP,   "Disable copy-propagation"},
74
		{"nir",       FD_DBG_NIR,    "Enable experimental NIR compiler"},
75
		DEBUG_NAMED_VALUE_END
76
};
77
 
78
DEBUG_GET_ONCE_FLAGS_OPTION(fd_mesa_debug, "FD_MESA_DEBUG", debug_options, 0)
79
 
80
int fd_mesa_debug = 0;
81
bool fd_binning_enabled = true;
82
static bool glsl120 = false;
83
 
84
static const char *
85
fd_screen_get_name(struct pipe_screen *pscreen)
86
{
87
	static char buffer[128];
88
	util_snprintf(buffer, sizeof(buffer), "FD%03d",
89
			fd_screen(pscreen)->device_id);
90
	return buffer;
91
}
92
 
93
static const char *
94
fd_screen_get_vendor(struct pipe_screen *pscreen)
95
{
96
	return "freedreno";
97
}
98
 
99
static const char *
100
fd_screen_get_device_vendor(struct pipe_screen *pscreen)
101
{
102
	return "Qualcomm";
103
}
104
 
105
 
106
static uint64_t
107
fd_screen_get_timestamp(struct pipe_screen *pscreen)
108
{
109
	int64_t cpu_time = os_time_get() * 1000;
110
	return cpu_time + fd_screen(pscreen)->cpu_gpu_time_delta;
111
}
112
 
113
static void
114
fd_screen_destroy(struct pipe_screen *pscreen)
115
{
116
	struct fd_screen *screen = fd_screen(pscreen);
117
 
118
	if (screen->pipe)
119
		fd_pipe_del(screen->pipe);
120
 
121
	if (screen->dev)
122
		fd_device_del(screen->dev);
123
 
124
	free(screen);
125
}
126
 
127
/*
128
TODO either move caps to a2xx/a3xx specific code, or maybe have some
129
tables for things that differ if the delta is not too much..
130
 */
131
static int
132
fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
133
{
134
	struct fd_screen *screen = fd_screen(pscreen);
135
 
136
	/* this is probably not totally correct.. but it's a start: */
137
	switch (param) {
138
	/* Supported features (boolean caps). */
139
	case PIPE_CAP_NPOT_TEXTURES:
140
	case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
141
	case PIPE_CAP_TWO_SIDED_STENCIL:
142
	case PIPE_CAP_ANISOTROPIC_FILTER:
143
	case PIPE_CAP_POINT_SPRITE:
144
	case PIPE_CAP_TEXTURE_SHADOW_MAP:
145
	case PIPE_CAP_BLEND_EQUATION_SEPARATE:
146
	case PIPE_CAP_TEXTURE_SWIZZLE:
147
	case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
148
	case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
149
	case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
150
	case PIPE_CAP_SEAMLESS_CUBE_MAP:
151
	case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
152
	case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
153
	case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
154
	case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
155
	case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
156
	case PIPE_CAP_USER_CONSTANT_BUFFERS:
157
	case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
158
	case PIPE_CAP_VERTEXID_NOBASE:
159
		return 1;
160
 
161
	case PIPE_CAP_SHADER_STENCIL_EXPORT:
162
	case PIPE_CAP_TGSI_TEXCOORD:
163
	case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
164
	case PIPE_CAP_CONDITIONAL_RENDER:
165
	case PIPE_CAP_TEXTURE_MULTISAMPLE:
166
	case PIPE_CAP_TEXTURE_BARRIER:
167
	case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
168
	case PIPE_CAP_CUBE_MAP_ARRAY:
169
	case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
170
	case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
171
	case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
172
	case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
173
	case PIPE_CAP_START_INSTANCE:
174
	case PIPE_CAP_COMPUTE:
175
		return 0;
176
 
177
	case PIPE_CAP_SM3:
178
	case PIPE_CAP_PRIMITIVE_RESTART:
179
	case PIPE_CAP_TGSI_INSTANCEID:
180
	case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
181
		return is_a3xx(screen) || is_a4xx(screen);
182
 
183
	case PIPE_CAP_INDEP_BLEND_ENABLE:
184
	case PIPE_CAP_INDEP_BLEND_FUNC:
185
	case PIPE_CAP_DEPTH_CLIP_DISABLE:
186
		return is_a3xx(screen);
187
 
188
	case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
189
		return 256;
190
 
191
	case PIPE_CAP_GLSL_FEATURE_LEVEL:
192
		if (glsl120)
193
			return 120;
194
		return (is_a3xx(screen) || is_a4xx(screen)) ? 130 : 120;
195
 
196
	/* Unsupported features. */
197
	case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
198
	case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
199
	case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
200
	case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
201
	case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
202
	case PIPE_CAP_VERTEX_COLOR_CLAMPED:
203
	case PIPE_CAP_USER_VERTEX_BUFFERS:
204
	case PIPE_CAP_USER_INDEX_BUFFERS:
205
	case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
206
	case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
207
	case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
208
	case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
209
	case PIPE_CAP_TEXTURE_GATHER_SM5:
210
	case PIPE_CAP_FAKE_SW_MSAA:
211
	case PIPE_CAP_TEXTURE_QUERY_LOD:
212
	case PIPE_CAP_SAMPLE_SHADING:
213
	case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
214
	case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
215
	case PIPE_CAP_DRAW_INDIRECT:
216
	case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
217
	case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
218
	case PIPE_CAP_SAMPLER_VIEW_TARGET:
219
	case PIPE_CAP_CLIP_HALFZ:
220
	case PIPE_CAP_POLYGON_OFFSET_CLAMP:
221
	case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
222
	case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
223
	case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
224
		return 0;
225
 
226
	case PIPE_CAP_MAX_VIEWPORTS:
227
		return 1;
228
 
229
	/* Stream output. */
230
	case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
231
	case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
232
	case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
233
	case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
234
		return 0;
235
 
236
	/* Geometry shader output, unsupported. */
237
	case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
238
	case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
239
	case PIPE_CAP_MAX_VERTEX_STREAMS:
240
		return 0;
241
 
242
	case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
243
		return 2048;
244
 
245
	/* Texturing. */
246
	case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
247
	case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
248
		return MAX_MIP_LEVELS;
249
	case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
250
		return 11;
251
 
252
	case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
253
		return (is_a3xx(screen) || is_a4xx(screen)) ? 256 : 0;
254
 
255
	/* Render targets. */
256
	case PIPE_CAP_MAX_RENDER_TARGETS:
257
		return screen->max_rts;
258
 
259
	/* Queries. */
260
	case PIPE_CAP_QUERY_TIME_ELAPSED:
261
	case PIPE_CAP_QUERY_TIMESTAMP:
262
		return 0;
263
	case PIPE_CAP_OCCLUSION_QUERY:
264
		/* TODO still missing on a4xx, but we lie to get gl2..
265
		 * it's not a feature, it's a bug!
266
		 */
267
		return is_a3xx(screen) || is_a4xx(screen);
268
 
269
	case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
270
	case PIPE_CAP_MIN_TEXEL_OFFSET:
271
		return -8;
272
 
273
	case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
274
	case PIPE_CAP_MAX_TEXEL_OFFSET:
275
		return 7;
276
 
277
	case PIPE_CAP_ENDIANNESS:
278
		return PIPE_ENDIAN_LITTLE;
279
 
280
	case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
281
		return 64;
282
 
283
	case PIPE_CAP_VENDOR_ID:
284
		return 0x5143;
285
	case PIPE_CAP_DEVICE_ID:
286
		return 0xFFFFFFFF;
287
	case PIPE_CAP_ACCELERATED:
288
		return 1;
289
	case PIPE_CAP_VIDEO_MEMORY:
290
		DBG("FINISHME: The value returned is incorrect\n");
291
		return 10;
292
	case PIPE_CAP_UMA:
293
		return 1;
294
	}
295
	debug_printf("unknown param %d\n", param);
296
	return 0;
297
}
298
 
299
static float
300
fd_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
301
{
302
	switch (param) {
303
	case PIPE_CAPF_MAX_LINE_WIDTH:
304
	case PIPE_CAPF_MAX_LINE_WIDTH_AA:
305
	case PIPE_CAPF_MAX_POINT_WIDTH:
306
	case PIPE_CAPF_MAX_POINT_WIDTH_AA:
307
		return 4092.0f;
308
	case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
309
		return 16.0f;
310
	case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
311
		return 15.0f;
312
	case PIPE_CAPF_GUARD_BAND_LEFT:
313
	case PIPE_CAPF_GUARD_BAND_TOP:
314
	case PIPE_CAPF_GUARD_BAND_RIGHT:
315
	case PIPE_CAPF_GUARD_BAND_BOTTOM:
316
		return 0.0f;
317
	}
318
	debug_printf("unknown paramf %d\n", param);
319
	return 0;
320
}
321
 
322
static int
323
fd_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
324
		enum pipe_shader_cap param)
325
{
326
	struct fd_screen *screen = fd_screen(pscreen);
327
 
328
	switch(shader)
329
	{
330
	case PIPE_SHADER_FRAGMENT:
331
	case PIPE_SHADER_VERTEX:
332
		break;
333
	case PIPE_SHADER_COMPUTE:
334
	case PIPE_SHADER_GEOMETRY:
335
		/* maye we could emulate.. */
336
		return 0;
337
	default:
338
		DBG("unknown shader type %d", shader);
339
		return 0;
340
	}
341
 
342
	/* this is probably not totally correct.. but it's a start: */
343
	switch (param) {
344
	case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
345
	case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
346
	case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
347
	case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
348
		return 16384;
349
	case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
350
		return 8; /* XXX */
351
	case PIPE_SHADER_CAP_MAX_INPUTS:
352
	case PIPE_SHADER_CAP_MAX_OUTPUTS:
353
		return 16;
354
	case PIPE_SHADER_CAP_MAX_TEMPS:
355
		return 64; /* Max native temporaries. */
356
	case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
357
		/* NOTE: seems to be limit for a3xx is actually 512 but
358
		 * split between VS and FS.  Use lower limit of 256 to
359
		 * avoid getting into impossible situations:
360
		 */
361
		return ((is_a3xx(screen) || is_a4xx(screen)) ? 4096 : 64) * sizeof(float[4]);
362
	case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
363
		return (is_a3xx(screen) || is_a4xx(screen)) ? 16 : 1;
364
	case PIPE_SHADER_CAP_MAX_PREDS:
365
		return 0; /* nothing uses this */
366
	case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
367
		return 1;
368
	case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
369
	case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
370
	case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
371
	case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
372
		return 1;
373
	case PIPE_SHADER_CAP_SUBROUTINES:
374
	case PIPE_SHADER_CAP_DOUBLES:
375
	case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
376
	case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
377
	case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
378
		return 0;
379
	case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
380
		return 1;
381
	case PIPE_SHADER_CAP_INTEGERS:
382
		if (glsl120)
383
			return 0;
384
		return (is_a3xx(screen) || is_a4xx(screen)) ? 1 : 0;
385
	case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
386
	case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
387
		return 16;
388
	case PIPE_SHADER_CAP_PREFERRED_IR:
389
		return PIPE_SHADER_IR_TGSI;
390
	}
391
	debug_printf("unknown shader param %d\n", param);
392
	return 0;
393
}
394
 
395
boolean
396
fd_screen_bo_get_handle(struct pipe_screen *pscreen,
397
		struct fd_bo *bo,
398
		unsigned stride,
399
		struct winsys_handle *whandle)
400
{
401
	whandle->stride = stride;
402
 
403
	if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
404
		return fd_bo_get_name(bo, &whandle->handle) == 0;
405
	} else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) {
406
		whandle->handle = fd_bo_handle(bo);
407
		return TRUE;
408
	} else if (whandle->type == DRM_API_HANDLE_TYPE_FD) {
409
		whandle->handle = fd_bo_dmabuf(bo);
410
		return TRUE;
411
	} else {
412
		return FALSE;
413
	}
414
}
415
 
416
struct fd_bo *
417
fd_screen_bo_from_handle(struct pipe_screen *pscreen,
418
		struct winsys_handle *whandle,
419
		unsigned *out_stride)
420
{
421
	struct fd_screen *screen = fd_screen(pscreen);
422
	struct fd_bo *bo;
423
 
424
	if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
425
		bo = fd_bo_from_name(screen->dev, whandle->handle);
426
	} else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) {
427
		bo = fd_bo_from_handle(screen->dev, whandle->handle, 0);
428
	} else if (whandle->type == DRM_API_HANDLE_TYPE_FD) {
429
		bo = fd_bo_from_dmabuf(screen->dev, whandle->handle);
430
	} else {
431
		DBG("Attempt to import unsupported handle type %d", whandle->type);
432
		return NULL;
433
	}
434
 
435
	if (!bo) {
436
		DBG("ref name 0x%08x failed", whandle->handle);
437
		return NULL;
438
	}
439
 
440
	*out_stride = whandle->stride;
441
 
442
	return bo;
443
}
444
 
445
struct pipe_screen *
446
fd_screen_create(struct fd_device *dev)
447
{
448
	struct fd_screen *screen = CALLOC_STRUCT(fd_screen);
449
	struct pipe_screen *pscreen;
450
	uint64_t val;
451
 
452
	fd_mesa_debug = debug_get_option_fd_mesa_debug();
453
 
454
	if (fd_mesa_debug & FD_DBG_NOBIN)
455
		fd_binning_enabled = false;
456
 
457
	glsl120 = !!(fd_mesa_debug & FD_DBG_GLSL120);
458
 
459
	if (!screen)
460
		return NULL;
461
 
462
	pscreen = &screen->base;
463
 
464
	screen->dev = dev;
465
 
466
	// maybe this should be in context?
467
	screen->pipe = fd_pipe_new(screen->dev, FD_PIPE_3D);
468
	if (!screen->pipe) {
469
		DBG("could not create 3d pipe");
470
		goto fail;
471
	}
472
 
473
	if (fd_pipe_get_param(screen->pipe, FD_GMEM_SIZE, &val)) {
474
		DBG("could not get GMEM size");
475
		goto fail;
476
	}
477
	screen->gmemsize_bytes = val;
478
 
479
	if (fd_pipe_get_param(screen->pipe, FD_DEVICE_ID, &val)) {
480
		DBG("could not get device-id");
481
		goto fail;
482
	}
483
	screen->device_id = val;
484
 
485
	if (fd_pipe_get_param(screen->pipe, FD_GPU_ID, &val)) {
486
		DBG("could not get gpu-id");
487
		goto fail;
488
	}
489
	screen->gpu_id = val;
490
 
491
	if (fd_pipe_get_param(screen->pipe, FD_CHIP_ID, &val)) {
492
		DBG("could not get chip-id");
493
		/* older kernels may not have this property: */
494
		unsigned core  = screen->gpu_id / 100;
495
		unsigned major = (screen->gpu_id % 100) / 10;
496
		unsigned minor = screen->gpu_id % 10;
497
		unsigned patch = 0;  /* assume the worst */
498
		val = (patch & 0xff) | ((minor & 0xff) << 8) |
499
			((major & 0xff) << 16) | ((core & 0xff) << 24);
500
	}
501
	screen->chip_id = val;
502
 
503
	DBG("Pipe Info:");
504
	DBG(" GPU-id:          %d", screen->gpu_id);
505
	DBG(" Chip-id:         0x%08x", screen->chip_id);
506
	DBG(" GMEM size:       0x%08x", screen->gmemsize_bytes);
507
 
508
	/* explicitly checking for GPU revisions that are known to work.  This
509
	 * may be overly conservative for a3xx, where spoofing the gpu_id with
510
	 * the blob driver seems to generate identical cmdstream dumps.  But
511
	 * on a2xx, there seem to be small differences between the GPU revs
512
	 * so it is probably better to actually test first on real hardware
513
	 * before enabling:
514
	 *
515
	 * If you have a different adreno version, feel free to add it to one
516
	 * of the cases below and see what happens.  And if it works, please
517
	 * send a patch ;-)
518
	 */
519
	switch (screen->gpu_id) {
520
	case 220:
521
		fd2_screen_init(pscreen);
522
		break;
523
	case 307:
524
	case 320:
525
	case 330:
526
		fd3_screen_init(pscreen);
527
		break;
528
	case 420:
529
		fd4_screen_init(pscreen);
530
		break;
531
	default:
532
		debug_printf("unsupported GPU: a%03d\n", screen->gpu_id);
533
		goto fail;
534
	}
535
 
536
	pscreen->destroy = fd_screen_destroy;
537
	pscreen->get_param = fd_screen_get_param;
538
	pscreen->get_paramf = fd_screen_get_paramf;
539
	pscreen->get_shader_param = fd_screen_get_shader_param;
540
 
541
	fd_resource_screen_init(pscreen);
542
	fd_query_screen_init(pscreen);
543
 
544
	pscreen->get_name = fd_screen_get_name;
545
	pscreen->get_vendor = fd_screen_get_vendor;
546
	pscreen->get_device_vendor = fd_screen_get_device_vendor;
547
 
548
	pscreen->get_timestamp = fd_screen_get_timestamp;
549
 
550
	pscreen->fence_reference = fd_screen_fence_ref;
551
	pscreen->fence_signalled = fd_screen_fence_signalled;
552
	pscreen->fence_finish = fd_screen_fence_finish;
553
 
554
	util_format_s3tc_init();
555
 
556
	return pscreen;
557
 
558
fail:
559
	fd_screen_destroy(pscreen);
560
	return NULL;
561
}