Rev 3598 | Go to most recent revision | Details | Compare with Previous | Last modification | View Log | RSS feed
Rev | Author | Line No. | Line |
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3520 | clevermous | 1 | ; Code for OHCI controllers. |
2 | ; Note: it should be moved to an external driver, |
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3 | ; it was convenient to have this code compiled into the kernel during initial |
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4 | ; development, but there are no reasons to keep it here. |
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5 | |||
6 | ; ============================================================================= |
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7 | ; ================================= Constants ================================= |
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8 | ; ============================================================================= |
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9 | ; OHCI register declarations |
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10 | ; All of the registers should be read and written as Dwords. |
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11 | ; Partition 1. Control and Status registers. |
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12 | OhciRevisionReg = 0 |
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13 | OhciControlReg = 4 |
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14 | OhciCommandStatusReg = 8 |
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15 | OhciInterruptStatusReg = 0Ch |
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16 | OhciInterruptEnableReg = 10h |
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17 | OhciInterruptDisableReg = 14h |
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18 | ; Partition 2. Memory Pointer registers. |
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19 | OhciHCCAReg = 18h |
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20 | OhciPeriodCurrentEDReg = 1Ch |
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21 | OhciControlHeadEDReg = 20h |
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22 | OhciControlCurrentEDReg = 24h |
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23 | OhciBulkHeadEDReg = 28h |
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24 | OhciBulkCurrentEDReg = 2Ch |
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25 | OhciDoneHeadReg = 30h |
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26 | ; Partition 3. Frame Counter registers. |
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27 | OhciFmIntervalReg = 34h |
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28 | OhciFmRemainingReg = 38h |
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29 | OhciFmNumberReg = 3Ch |
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30 | OhciPeriodicStartReg = 40h |
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31 | OhciLSThresholdReg = 44h |
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32 | ; Partition 4. Root Hub registers. |
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33 | OhciRhDescriptorAReg = 48h |
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34 | OhciRhDescriptorBReg = 4Ch |
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35 | OhciRhStatusReg = 50h |
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36 | OhciRhPortStatusReg = 54h |
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37 | |||
38 | ; ============================================================================= |
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39 | ; ================================ Structures ================================= |
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40 | ; ============================================================================= |
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41 | |||
42 | ; OHCI-specific part of a pipe descriptor. |
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43 | ; * This structure corresponds to the Endpoint Descriptor aka ED from the OHCI |
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44 | ; specification. |
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45 | ; * The hardware requires 16-bytes alignment of the hardware part. |
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46 | ; Since the allocator (usb_allocate_common) allocates memory sequentially |
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3653 | clevermous | 47 | ; from page start (aligned on 0x1000 bytes), block size for the allocator |
48 | ; must be divisible by 16; usb1_allocate_endpoint ensures this. |
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3520 | clevermous | 49 | struct ohci_pipe |
50 | ; All addresses are physical. |
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51 | Flags dd ? |
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52 | ; 1. Lower 7 bits (bits 0-6) are FunctionAddress. This is the USB address of |
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53 | ; the function containing the endpoint that this ED controls. |
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54 | ; 2. Next 4 bits (bits 7-10) are EndpointNumber. This is the USB address of |
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55 | ; the endpoint within the function. |
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56 | ; 3. Next 2 bits (bits 11-12) are Direction. This 2-bit field indicates the |
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57 | ; direction of data flow: 1 = IN, 2 = OUT. If neither IN nor OUT is |
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58 | ; specified, then the direction is determined from the PID field of the TD. |
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59 | ; For CONTROL endpoints, the transfer direction is different |
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60 | ; for different transfers, so the value of this field is 0 |
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61 | ; (3 would have the same effect) and the actual direction |
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62 | ; of one transfer is encoded in the Transfer Descriptor. |
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63 | ; 4. Next bit (bit 13) is Speed bit. It indicates the speed of the endpoint: |
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64 | ; full-speed (S = 0) or low-speed (S = 1). |
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65 | ; 5. Next bit (bit 14) is sKip bit. When this bit is set, the hardware |
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66 | ; continues on to the next ED on the list without attempting access |
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67 | ; to the TD queue or issuing any USB token for the endpoint. |
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68 | ; Always cleared. |
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69 | ; 6. Next bit (bit 15) is Format bit. It must be 0 for Control, Bulk and |
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70 | ; Interrupt endpoints and 1 for Isochronous endpoints. |
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71 | ; 7. Next 11 bits (bits 16-26) are MaximumPacketSize. This field indicates |
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72 | ; the maximum number of bytes that can be sent to or received from the |
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73 | ; endpoint in a single data packet. |
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74 | TailP dd ? |
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75 | ; Physical address of the tail descriptor in the TD queue. |
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76 | ; The descriptor itself is not in the queue. See also HeadP. |
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77 | HeadP dd ? |
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78 | ; 1. First bit (bit 0) is Halted bit. This bit is set by the hardware to |
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79 | ; indicate that processing of the TD queue on the endpoint is halted. |
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80 | ; 2. Second bit (bit 1) is toggleCarry bit. Whenever a TD is retired, this |
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81 | ; bit is written to contain the last data toggle value from the retired TD. |
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82 | ; 3. Next two bits (bits 2-3) are reserved and always zero. |
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83 | ; 4. With masked 4 lower bits, this is HeadP itself: physical address of the |
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84 | ; head descriptor in the TD queue, that is, next TD to be processed for this |
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85 | ; endpoint. Note that a TD must be 16-bytes aligned. |
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86 | ; Empty queue is characterized by the condition HeadP == TailP. |
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87 | NextED dd ? |
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88 | ; If nonzero, then this entry is a physical address of the next ED to be |
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89 | ; processed. See also the description before NextVirt field of the usb_pipe |
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90 | ; structure. Additionally to that description, the following is specific for |
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91 | ; the OHCI controller: |
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92 | ; * n=5, N=32, there are 32 "leaf" periodic lists. |
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93 | ; * The 1ms periodic list also serves Isochronous endpoints, which should be |
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94 | ; in the end of the list. |
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95 | ; * There is no "next" list for Bulk and Control lists, they are processed |
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96 | ; separately from others. |
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97 | ; * There is no "next" list for Periodic list for 1ms interval. |
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98 | ends |
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99 | |||
100 | ; This structure describes the static head of every list of pipes. |
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101 | ; The hardware requires 16-bytes alignment of this structure. |
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102 | ; All instances of this structure are located sequentially in uhci_controller, |
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103 | ; uhci_controller is page-aligned, so it is sufficient to make this structure |
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104 | ; 16-bytes aligned and verify that the first instance is 16-bytes aligned |
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105 | ; inside uhci_controller. |
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106 | struct ohci_static_ep |
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107 | Flags dd ? |
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108 | ; Same as ohci_pipe.Flags. |
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109 | ; sKip bit is set, so the hardware ignores other fields except NextED. |
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110 | dd ? |
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111 | ; Corresponds to ohci_pipe.TailP. Not used. |
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112 | NextList dd ? |
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113 | ; Virtual address of the next list. |
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114 | NextED dd ? |
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115 | ; Same as ohci_pipe.NextED. |
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116 | SoftwarePart rd sizeof.usb_static_ep/4 |
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117 | ; Software part, common for all controllers. |
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118 | dd ? |
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119 | ; Padding for 16-bytes alignment. |
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120 | ends |
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121 | |||
122 | if sizeof.ohci_static_ep mod 16 |
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123 | .err ohci_static_ep must be 16-bytes aligned |
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124 | end if |
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125 | |||
126 | ; OHCI-specific part of controller data. |
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127 | ; * The structure describes the memory area used for controller data, |
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128 | ; additionally to the registers of the controller. |
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129 | ; * The structure includes two parts, the hardware part and the software part. |
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130 | ; * The hardware part consists of first 256 bytes and corresponds to |
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131 | ; the HCCA from OHCI specification. |
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132 | ; * The hardware requires 256-bytes alignment of the hardware part, so |
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133 | ; the entire descriptor must be 256-bytes aligned. |
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134 | ; This structure is allocated with kernel_alloc (see usb_init_controller), |
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135 | ; this gives page-aligned data. |
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136 | ; * The controller is described by both ohci_controller and usb_controller |
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137 | ; structures, for each controller there is one ohci_controller and one |
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138 | ; usb_controller structure. These structures are located sequentially |
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139 | ; in the memory: beginning from some page start, there is ohci_controller |
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140 | ; structure - this enforces hardware alignment requirements - and then |
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141 | ; usb_controller structure. |
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142 | ; * The code keeps pointer to usb_controller structure. The ohci_controller |
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143 | ; structure is addressed as [ptr + ohci_controller.field - sizeof.ohci_controller]. |
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144 | struct ohci_controller |
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145 | ; ------------------------------ hardware fields ------------------------------ |
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146 | InterruptTable rd 32 |
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147 | ; Pointers to interrupt EDs. The hardware starts processing of periodic lists |
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148 | ; within the frame N from the ED pointed to by [InterruptTable+(N and 31)*4]. |
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149 | ; See also the description of periodic lists inside ohci_pipe structure. |
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150 | FrameNumber dw ? |
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151 | ; The current frame number. This field is written by hardware only. |
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152 | ; This field is read by ohci_process_deferred and ohci_irq to |
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153 | ; communicate when control/bulk processing needs to be temporarily |
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154 | ; stopped/restarted. |
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155 | dw ? |
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156 | ; Padding. Written as zero at every update of FrameNumber. |
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157 | DoneHead dd ? |
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158 | ; Physical pointer to the start of Done Queue. |
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159 | ; When the hardware updates this field, it sets bit 0 to one if there is |
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160 | ; unmasked interrupt pending. |
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161 | rb 120 |
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162 | ; Reserved for the hardware. |
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163 | ; ------------------------------ software fields ------------------------------ |
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164 | IntEDs ohci_static_ep |
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165 | rb 62 * sizeof.ohci_static_ep |
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166 | ; Heads of 63 Periodic lists, see the description in usb_pipe. |
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167 | ControlED ohci_static_ep |
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168 | ; Head of Control list, see the description in usb_pipe. |
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169 | BulkED ohci_static_ep |
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170 | ; Head of Bulk list, see the description in usb_pipe. |
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171 | MMIOBase dd ? |
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172 | ; Virtual address of memory-mapped area with OHCI registers OhciXxxReg. |
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173 | PoweredUp db ? |
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174 | ; 1 in normal work, 0 during early phases of the initialization. |
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175 | ; This field is initialized to zero during memory allocation |
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176 | ; (see usb_init_controller), set to one by ohci_init when ports of the root hub |
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177 | ; are powered up, so connect/disconnect events can be handled. |
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178 | rb 3 ; alignment |
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179 | DoneList dd ? |
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180 | ; List of descriptors which were processed by the controller and now need |
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181 | ; to be finalized. |
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182 | DoneListEndPtr dd ? |
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183 | ; Pointer to dword which should receive a pointer to the next item in DoneList. |
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184 | ; If DoneList is empty, this is a pointer to DoneList itself; |
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185 | ; otherwise, this is a pointer to NextTD field of the last item in DoneList. |
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186 | ends |
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187 | |||
188 | if ohci_controller.IntEDs mod 16 |
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189 | .err Static endpoint descriptors must be 16-bytes aligned inside ohci_controller |
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190 | end if |
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191 | |||
192 | ; OHCI general transfer descriptor. |
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193 | ; * The structure describes transfers to be performed on Control, Bulk or |
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194 | ; Interrupt endpoints. |
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195 | ; * The structure includes two parts, the hardware part and the software part. |
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196 | ; * The hardware part consists of first 16 bytes and corresponds to |
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197 | ; the General Transfer Descriptor aka general TD from OHCI specification. |
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198 | ; * The hardware requires 16-bytes alignment of the hardware part, so |
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199 | ; the entire descriptor must be 16-bytes aligned. Since the allocator |
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200 | ; (usb_allocate_common) allocates memory sequentially from page start |
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3653 | clevermous | 201 | ; (aligned on 0x1000 bytes), block size for the allocator must be |
202 | ; divisible by 16; usb1_allocate_generic_td ensures this. |
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3520 | clevermous | 203 | struct ohci_gtd |
204 | ; ------------------------------ hardware fields ------------------------------ |
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205 | ; All addresses in this part are physical. |
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206 | Flags dd ? |
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207 | ; 1. Lower 18 bits (bits 0-17) are ignored and not modified by the hardware. |
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208 | ; 2. Next bit (bit 18) is bufferRounding bit. If this bit is 0, then the last |
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209 | ; data packet must exactly fill the defined data buffer. If this bit is 1, |
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210 | ; then the last data packet may be smaller than the defined buffer without |
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211 | ; causing an error condition on the TD. |
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212 | ; 3. Next 2 bits (bits 19-20) are Direction field. This field indicates the |
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213 | ; direction of data flow. If the Direction field in the ED is OUT or IN, |
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214 | ; this field is ignored and the direction from the ED is used instead. |
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215 | ; Otherwise, 0 = SETUP, 1 = OUT, 2 = IN, 3 is reserved. |
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216 | ; 4. Next 3 bits (bits 21-23) are DelayInterrupt field. This field contains |
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217 | ; the interrupt delay count for this TD. When a TD is complete, the hardware |
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218 | ; may wait up to DelayInterrupt frames before generating an interrupt. |
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219 | ; If DelayInterrupt is 7 (maximum possible), then there is no interrupt |
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220 | ; associated with completion of this TD. |
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221 | ; 5. Next 2 bits (bits 24-25) are DataToggle field. This field is used to |
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222 | ; generate/compare the data PID value (DATA0 or DATA1). It is updated after |
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223 | ; each successful transmission/reception of a data packet. The bit 25 |
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224 | ; is 0 when the data toggle value is acquired from the toggleCarry field in |
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225 | ; the ED and 1 when the data toggle value is taken from the bit 24. |
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226 | ; 6. Next 2 bits (bits 26-27) are ErrorCount field. For each transmission |
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227 | ; error, this value is incremented. If ErrorCount is 2 and another error |
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228 | ; occurs, the TD is retired with error. When a transaction completes without |
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229 | ; error, ErrorCount is reset to 0. |
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230 | ; 7. Upper 4 bits (bits 28-31) are ConditionCode field. This field contains |
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231 | ; the status of the last attempted transaction, one of USB_STATUS_* values. |
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232 | CurBufPtr dd ? |
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233 | ; Physical address of the next memory location that will be accessed for |
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234 | ; transfer to/from the endpoint. 0 means zero-length data packet or that all |
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235 | ; bytes have been transferred. |
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236 | NextTD dd ? |
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237 | ; This field has different meanings depending on the status of the descriptor. |
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238 | ; When the descriptor is queued for processing, but not yet processed: |
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239 | ; Physical address of the next TD for the endpoint. |
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240 | ; When the descriptor is processed by hardware, but not yet by software: |
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241 | ; Physical address of the previous processed TD. |
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242 | ; When the descriptor is processed by the IRQ handler, but not yet completed: |
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243 | ; Virtual pointer to the next processed TD. |
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244 | BufEnd dd ? |
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245 | ; Physical address of the last byte in the buffer for this TD. |
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3653 | clevermous | 246 | dd ? ; padding to align with uhci_gtd |
3520 | clevermous | 247 | ends |
248 | |||
249 | ; OHCI isochronous transfer descriptor. |
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250 | ; * The structure describes transfers to be performed on Isochronous endpoints. |
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251 | ; * The structure includes two parts, the hardware part and the software part. |
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252 | ; * The hardware part consists of first 32 bytes and corresponds to |
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253 | ; the Isochronous Transfer Descriptor aka isochronous TD from OHCI |
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254 | ; specification. |
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255 | ; * The hardware requires 32-bytes alignment of the hardware part, so |
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256 | ; the entire descriptor must be 32-bytes aligned. |
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257 | ; * The isochronous endpoints are not supported yet, so only hardware part is |
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258 | ; defined at the moment. |
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259 | struct ohci_itd |
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260 | StartingFrame dw ? |
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261 | ; This field contains the low order 16 bits of the frame number in which the |
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262 | ; first data packet of the Isochronous TD is to be sent. |
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263 | Flags dw ? |
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264 | ; 1. Lower 5 bits (bits 0-4) are ignored and not modified by the hardware. |
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265 | ; 2. Next 3 bits (bits 5-7) are DelayInterrupt field. |
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266 | ; 3. Next 3 bits (bits 8-10) are FrameCount field. The TD describes |
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267 | ; FrameCount+1 data packets. |
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268 | ; 4. Next bit (bit 11) is ignored and not modified by the hardware. |
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269 | ; 5. Upper 4 bits (bits 12-15) are ConditionCode field. This field contains |
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270 | ; the completion code, one of USB_STATUS_* values, when the TD is moved to |
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271 | ; the Done Queue. |
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272 | BufPage0 dd ? |
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273 | ; Lower 12 bits are ignored and not modified by the hardware. |
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274 | ; With masked 12 bits this field is the physical page containing all buffers. |
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275 | NextTD dd ? |
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276 | ; Physical address of the next TD in the transfer queue. |
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277 | BufEnd dd ? |
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278 | ; Physical address of the last byte in the buffer. |
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279 | OffsetArray rw 8 |
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280 | ; Initialized by software, read by hardware: Offset for packet 0..7. |
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281 | ; Used to determine size and starting address of an isochronous data packet. |
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282 | ; Written by hardware, read by software: PacketStatusWord for packet 0..7. |
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283 | ; Contains completion code and, if applicable, size received for an isochronous |
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284 | ; data packet. |
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285 | ends |
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286 | |||
287 | ; Description of OHCI-specific data and functions for |
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288 | ; controller-independent code. |
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289 | ; Implements the structure usb_hardware_func from hccommon.inc for OHCI. |
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290 | iglobal |
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291 | align 4 |
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292 | ohci_hardware_func: |
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293 | dd 'OHCI' |
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294 | dd sizeof.ohci_controller |
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295 | dd ohci_init |
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296 | dd ohci_process_deferred |
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297 | dd ohci_set_device_address |
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298 | dd ohci_get_device_address |
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299 | dd ohci_port_disable |
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300 | dd ohci_new_port.reset |
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301 | dd ohci_set_endpoint_packet_size |
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302 | dd usb1_allocate_endpoint |
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303 | dd usb1_free_endpoint |
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304 | dd ohci_init_pipe |
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305 | dd ohci_unlink_pipe |
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306 | dd usb1_allocate_general_td |
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307 | dd usb1_free_general_td |
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308 | dd ohci_alloc_transfer |
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309 | dd ohci_insert_transfer |
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310 | dd ohci_new_device |
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311 | endg |
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312 | |||
313 | ; ============================================================================= |
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314 | ; =================================== Code ==================================== |
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315 | ; ============================================================================= |
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316 | |||
317 | ; Controller-specific initialization function. |
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318 | ; Called from usb_init_controller. Initializes the hardware and |
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319 | ; OHCI-specific parts of software structures. |
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320 | ; eax = pointer to ohci_controller to be initialized |
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321 | ; [ebp-4] = pcidevice |
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322 | proc ohci_init |
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323 | ; inherit some variables from the parent (usb_init_controller) |
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324 | .devfn equ ebp - 4 |
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325 | .bus equ ebp - 3 |
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326 | ; 1. Store pointer to ohci_controller for further use. |
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327 | push eax |
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328 | mov edi, eax |
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329 | ; 2. Initialize hardware fields of ohci_controller. |
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330 | ; Namely, InterruptTable needs to be initialized with |
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331 | ; physical addresses of heads of first 32 Periodic lists. |
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332 | ; Note that all static heads fit in one page, so one call |
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333 | ; to get_pg_addr is sufficient. |
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334 | if (ohci_controller.IntEDs / 0x1000) <> (ohci_controller.BulkED / 0x1000) |
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335 | .err assertion failed |
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336 | end if |
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337 | if ohci_controller.IntEDs >= 0x1000 |
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338 | .err assertion failed |
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339 | end if |
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340 | lea esi, [eax+ohci_controller.IntEDs+32*sizeof.ohci_static_ep] |
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341 | call get_pg_addr |
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342 | add eax, ohci_controller.IntEDs |
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3598 | clevermous | 343 | movi ecx, 32 |
3520 | clevermous | 344 | mov edx, ecx |
345 | @@: |
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346 | stosd |
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347 | add eax, sizeof.ohci_static_ep |
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348 | loop @b |
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349 | ; 3. Initialize static heads ohci_controller.IntEDs, .ControlED, .BulkED. |
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350 | ; Use the loop over groups: first group consists of first 32 Periodic |
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351 | ; descriptors, next group consists of next 16 Periodic descriptors, |
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352 | ; ..., last group consists of the last Periodic descriptor. |
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353 | ; 3a. Prepare for the loop. |
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354 | ; make edi point to start of ohci_controller.IntEDs, |
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355 | ; other registers are already set. |
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356 | ; -128 fits in one byte, +128 does not fit. |
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357 | sub edi, -128 |
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358 | ; 3b. Loop over groups. On every iteration: |
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359 | ; edx = size of group, edi = pointer to the current group, |
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360 | ; esi = pointer to the next group, eax = physical address of the next group. |
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361 | .init_static_eds: |
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362 | ; 3c. Get the size of the next group. |
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363 | shr edx, 1 |
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364 | ; 3d. Exit the loop if there is no next group. |
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365 | jz .init_static_eds_done |
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366 | ; 3e. Initialize the first half of the current group. |
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367 | ; Advance edi to the second half. |
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368 | push eax esi |
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369 | call ohci_init_static_ep_group |
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370 | pop esi eax |
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371 | ; 3f. Initialize the second half of the current group |
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372 | ; with the same values. |
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373 | ; Advance edi to the next group, esi/eax to the next of the next group. |
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374 | call ohci_init_static_ep_group |
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375 | jmp .init_static_eds |
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376 | .init_static_eds_done: |
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377 | ; 3g. Initialize the head of the last Periodic list. |
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378 | xor eax, eax |
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379 | xor esi, esi |
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380 | call ohci_init_static_endpoint |
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381 | ; 3i. Initialize the heads of Control and Bulk lists. |
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382 | call ohci_init_static_endpoint |
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383 | call ohci_init_static_endpoint |
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384 | ; 4. Create a virtual memory area to talk with the controller. |
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385 | ; 4a. Enable memory & bus master access. |
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386 | mov ch, [.bus] |
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387 | mov cl, 0 |
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388 | mov eax, ecx |
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389 | mov bh, [.devfn] |
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390 | mov bl, 4 |
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391 | call pci_read_reg |
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392 | or al, 6 |
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393 | xchg eax, ecx |
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394 | call pci_write_reg |
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395 | ; 4b. Read memory base address. |
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396 | mov ah, [.bus] |
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397 | mov al, 2 |
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398 | mov bl, 10h |
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399 | call pci_read_reg |
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400 | and al, not 0Fh |
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401 | ; 4c. Create mapping for physical memory. 256 bytes are sufficient. |
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402 | stdcall map_io_mem, eax, 100h, PG_SW+PG_NOCACHE |
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403 | test eax, eax |
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404 | jz .fail |
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405 | stosd ; fill ohci_controller.MMIOBase |
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406 | xchg eax, edi |
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407 | ; now edi = MMIOBase |
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408 | ; 5. Reset the controller if needed. |
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409 | ; 5a. Check operational state. |
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410 | ; 0 = reset, 1 = resume, 2 = operational, 3 = suspended |
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411 | mov eax, [edi+OhciControlReg] |
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412 | and al, 3 shl 6 |
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413 | cmp al, 2 shl 6 |
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414 | jz .operational |
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415 | ; 5b. State is not operational, reset is needed. |
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416 | .reset: |
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417 | ; 5c. Save FmInterval register. |
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418 | pushd [edi+OhciFmIntervalReg] |
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419 | ; 5d. Issue software reset and wait up to 10ms, checking status every 1 ms. |
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3598 | clevermous | 420 | movi ecx, 1 |
421 | movi edx, 10 |
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3520 | clevermous | 422 | mov [edi+OhciCommandStatusReg], ecx |
423 | @@: |
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424 | mov esi, ecx |
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425 | call delay_ms |
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426 | test [edi+OhciCommandStatusReg], ecx |
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427 | jz .resetdone |
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428 | dec edx |
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429 | jnz @b |
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430 | pop eax |
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431 | dbgstr 'controller reset timeout' |
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432 | jmp .fail_unmap |
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433 | .resetdone: |
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434 | ; 5e. Restore FmInterval register. |
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435 | pop eax |
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436 | mov edx, eax |
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437 | and edx, 3FFFh |
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438 | jz .setfminterval |
||
439 | cmp dx, 2EDFh ; default value? |
||
440 | jnz @f ; assume that BIOS has configured the value |
||
441 | .setfminterval: |
||
442 | mov eax, 27792EDFh ; default value |
||
443 | @@: |
||
444 | mov [edi+OhciFmIntervalReg], eax |
||
445 | ; 5f. Set PeriodicStart to 90% of FmInterval. |
||
446 | movzx eax, ax |
||
447 | ; Two following lines are equivalent to eax = floor(eax * 0.9) |
||
448 | ; for any 0 <= eax < 1C71C71Dh, which of course is far from maximum 0FFFFh. |
||
449 | mov edx, 0E6666667h |
||
450 | mul edx |
||
451 | mov [edi+OhciPeriodicStartReg], edx |
||
452 | .operational: |
||
453 | ; 6. Setup controller registers. |
||
454 | pop esi ; restore pointer to ohci_controller saved in step 1 |
||
455 | ; 6a. Physical address of HCCA. |
||
456 | mov eax, esi |
||
457 | call get_pg_addr |
||
458 | mov [edi+OhciHCCAReg], eax |
||
459 | ; 6b. Transition to operational state and clear all Enable bits. |
||
460 | mov cl, 2 shl 6 |
||
461 | mov [edi+OhciControlReg], ecx |
||
462 | ; 6c. Physical addresses of head of Control and Bulk lists. |
||
463 | if ohci_controller.BulkED >= 0x1000 |
||
464 | .err assertion failed |
||
465 | end if |
||
466 | add eax, ohci_controller.ControlED |
||
467 | mov [edi+OhciControlHeadEDReg], eax |
||
468 | add eax, ohci_controller.BulkED - ohci_controller.ControlED |
||
469 | mov [edi+OhciBulkHeadEDReg], eax |
||
470 | ; 6d. Zero Head registers: there are no active Control and Bulk descriptors yet. |
||
471 | xor eax, eax |
||
472 | ; mov [edi+OhciPeriodCurrentEDReg], eax |
||
473 | mov [edi+OhciControlCurrentEDReg], eax |
||
474 | mov [edi+OhciBulkCurrentEDReg], eax |
||
475 | ; mov [edi+OhciDoneHeadReg], eax |
||
476 | ; 6e. Enable processing of all lists with control:bulk ratio = 1:1. |
||
477 | mov dword [edi+OhciControlReg], 10111100b |
||
478 | ; 7. Get number of ports. |
||
479 | add esi, sizeof.ohci_controller |
||
480 | mov eax, [edi+OhciRhDescriptorAReg] |
||
481 | and eax, 0xF |
||
482 | mov [esi+usb_controller.NumPorts], eax |
||
483 | ; 8. Initialize DoneListEndPtr to point to DoneList. |
||
484 | lea eax, [esi+ohci_controller.DoneList-sizeof.ohci_controller] |
||
485 | mov [esi+ohci_controller.DoneListEndPtr-sizeof.ohci_controller], eax |
||
486 | ; 9. Hook interrupt. |
||
487 | mov ah, [.bus] |
||
488 | mov al, 0 |
||
489 | mov bh, [.devfn] |
||
490 | mov bl, 3Ch |
||
491 | call pci_read_reg |
||
492 | ; al = IRQ |
||
493 | movzx eax, al |
||
494 | stdcall attach_int_handler, eax, ohci_irq, esi |
||
495 | ; 10. Enable controller interrupt on HcDoneHead writeback and RootHubStatusChange. |
||
496 | mov dword [edi+OhciInterruptEnableReg], 80000042h |
||
497 | DEBUGF 1,'K : OHCI controller at %x:%x with %d ports initialized\n',[.bus]:2,[.devfn]:2,[esi+usb_controller.NumPorts] |
||
498 | ; 11. Initialize ports of the controller. |
||
499 | ; 11a. Initiate power up, disable all ports, clear all "changed" bits. |
||
500 | mov dword [edi+OhciRhStatusReg], 10000h ; SetGlobalPower |
||
501 | xor ecx, ecx |
||
502 | @@: |
||
503 | mov dword [edi+OhciRhPortStatusReg+ecx*4], 1F0101h ; SetPortPower+ClearPortEnable+clear "changed" bits |
||
504 | inc ecx |
||
505 | cmp ecx, [esi+usb_controller.NumPorts] |
||
506 | jb @b |
||
507 | ; 11b. Wait for power up. |
||
508 | ; VirtualBox has AReg == 0, delay_ms doesn't like zero value; ignore zero delay |
||
509 | push esi |
||
510 | mov esi, [edi+OhciRhDescriptorAReg] |
||
511 | shr esi, 24 |
||
512 | add esi, esi |
||
513 | jz @f |
||
514 | call delay_ms |
||
515 | @@: |
||
516 | pop esi |
||
517 | ; 11c. Ports are powered up; now it is ok to process connect/disconnect events. |
||
518 | mov [esi+ohci_controller.PoweredUp-sizeof.ohci_controller], 1 |
||
519 | ; IRQ handler doesn't accept connect/disconnect events before this point |
||
520 | ; 11d. We could miss some events while waiting for powering up; |
||
521 | ; scan all ports manually and check for connected devices. |
||
522 | xor ecx, ecx |
||
523 | .port_loop: |
||
524 | test dword [edi+OhciRhPortStatusReg+ecx*4], 1 |
||
525 | jz .next_port |
||
526 | ; There is a connected device; mark the port as 'connected' |
||
527 | ; and save the connected time. |
||
528 | ; Note that ConnectedTime must be set before 'connected' mark, |
||
529 | ; otherwise the code in ohci_process_deferred could use incorrect time. |
||
530 | mov eax, [timer_ticks] |
||
531 | mov [esi+usb_controller.ConnectedTime+ecx*4], eax |
||
532 | lock bts [esi+usb_controller.NewConnected], ecx |
||
533 | .next_port: |
||
534 | inc ecx |
||
535 | cmp ecx, [esi+usb_controller.NumPorts] |
||
536 | jb .port_loop |
||
537 | ; 12. Return pointer to usb_controller. |
||
538 | xchg eax, esi |
||
539 | ret |
||
540 | .fail_unmap: |
||
541 | ; On error after step 4, release the virtual memory area. |
||
542 | stdcall free_kernel_space, edi |
||
543 | .fail: |
||
544 | ; On error, free the ohci_controller structure and return zero. |
||
545 | ; Note that the pointer was placed in the stack at step 1. |
||
546 | ; Note also that there can be no errors after step 8, |
||
547 | ; where that pointer is popped from the stack. |
||
548 | pop ecx |
||
549 | .nothing: |
||
550 | xor eax, eax |
||
551 | ret |
||
552 | endp |
||
553 | |||
554 | ; Helper procedure for step 3 of ohci_init. |
||
555 | ; Initializes the static head of one list. |
||
556 | ; eax = physical address of the "next" list, esi = pointer to the "next" list, |
||
557 | ; edi = pointer to head to initialize. |
||
558 | ; Advances edi to the next head, keeps eax/esi. |
||
559 | proc ohci_init_static_endpoint |
||
560 | mov byte [edi+ohci_static_ep.Flags+1], 1 shl (14 - 8) ; sKip this endpoint |
||
561 | mov [edi+ohci_static_ep.NextED], eax |
||
562 | mov [edi+ohci_static_ep.NextList], esi |
||
563 | add edi, ohci_static_ep.SoftwarePart |
||
564 | call usb_init_static_endpoint |
||
565 | add edi, sizeof.ohci_static_ep - ohci_static_ep.SoftwarePart |
||
566 | ret |
||
567 | endp |
||
568 | |||
569 | ; Helper procedure for step 3 of ohci_init. |
||
570 | ; Initializes one half of group of static heads. |
||
571 | ; edx = size of the next group = half of size of the group, |
||
572 | ; edi = pointer to the group, eax = physical address of the next group, |
||
573 | ; esi = pointer to the next group. |
||
574 | ; Advances eax, esi, edi to next group, keeps edx. |
||
575 | proc ohci_init_static_ep_group |
||
576 | push edx |
||
577 | @@: |
||
578 | call ohci_init_static_endpoint |
||
579 | add eax, sizeof.ohci_static_ep |
||
580 | add esi, sizeof.ohci_static_ep |
||
581 | dec edx |
||
582 | jnz @b |
||
583 | pop edx |
||
584 | ret |
||
585 | endp |
||
586 | |||
587 | ; Controller-specific pre-initialization function: take ownership from BIOS. |
||
588 | ; Some BIOSes, although not all of them, provide legacy emulation |
||
589 | ; for USB keyboard and/or mice as PS/2-devices. In this case, |
||
590 | ; we must notify the BIOS that we don't need that emulation and know how to |
||
591 | ; deal with USB devices. |
||
592 | proc ohci_kickoff_bios |
||
593 | ; 1. Get the physical address of MMIO registers. |
||
594 | mov ah, [esi+PCIDEV.bus] |
||
595 | mov bh, [esi+PCIDEV.devfn] |
||
596 | mov al, 2 |
||
597 | mov bl, 10h |
||
598 | call pci_read_reg |
||
599 | and al, not 0Fh |
||
600 | ; 2. Create mapping for physical memory. 256 bytes are sufficient. |
||
601 | stdcall map_io_mem, eax, 100h, PG_SW+PG_NOCACHE |
||
602 | test eax, eax |
||
603 | jz .nothing |
||
604 | ; 3. Some BIOSes enable controller interrupts as a result of giving |
||
605 | ; controller away. At this point the system knows nothing about how to serve |
||
606 | ; OHCI interrupts, so such an interrupt will send the system into an infinite |
||
607 | ; loop handling the same IRQ again and again. Thus, we need to block OHCI |
||
608 | ; interrupts. We can't do this at the controller level until step 5, |
||
609 | ; because the controller is currently owned by BIOS, so we block all hardware |
||
610 | ; interrupts on this processor until step 5. |
||
611 | pushf |
||
612 | cli |
||
613 | ; 4. Take the ownership over the controller. |
||
614 | ; 4a. Check whether BIOS handles this controller at all. |
||
615 | mov edx, 100h |
||
616 | test dword [eax+OhciControlReg], edx |
||
617 | jz .has_ownership |
||
618 | ; 4b. Send "take ownership" command to the BIOS. |
||
619 | ; (This should generate SMI, BIOS should release its ownership in SMI handler.) |
||
620 | mov dword [eax+OhciCommandStatusReg], 8 |
||
621 | ; 4c. Wait for result no more than 50 ms, checking for status every 1 ms. |
||
3598 | clevermous | 622 | movi ecx, 50 |
3520 | clevermous | 623 | @@: |
624 | test dword [eax+OhciControlReg], edx |
||
625 | jz .has_ownership |
||
626 | push esi |
||
3598 | clevermous | 627 | movi esi, 1 |
3520 | clevermous | 628 | call delay_ms |
629 | pop esi |
||
630 | loop @b |
||
631 | dbgstr 'warning: taking OHCI ownership from BIOS timeout' |
||
632 | .has_ownership: |
||
633 | ; 5. Disable all controller interrupts until the system will be ready to |
||
634 | ; process them. |
||
635 | mov dword [eax+OhciInterruptDisableReg], 0C000007Fh |
||
636 | ; 6. Now we can unblock interrupts in the processor. |
||
637 | popf |
||
638 | ; 7. Release memory mapping created in step 2 and return. |
||
639 | stdcall free_kernel_space, eax |
||
640 | .nothing: |
||
641 | ret |
||
642 | endp |
||
643 | |||
644 | ; IRQ handler for OHCI controllers. |
||
645 | ohci_irq.noint: |
||
646 | ; Not our interrupt: restore registers and return zero. |
||
647 | xor eax, eax |
||
648 | pop edi esi ebx |
||
649 | ret |
||
650 | |||
651 | proc ohci_irq |
||
652 | push ebx esi edi ; save used registers to be cdecl |
||
653 | virtual at esp |
||
654 | rd 3 ; saved registers |
||
655 | dd ? ; return address |
||
656 | .controller dd ? |
||
657 | end virtual |
||
658 | ; 1. ebx will hold whether some deferred processing is needed, |
||
659 | ; that cannot be done from the interrupt handler. Initialize to zero. |
||
660 | xor ebx, ebx |
||
661 | ; 2. Get the mask of events which should be processed. |
||
662 | mov esi, [.controller] |
||
663 | mov edi, [esi+ohci_controller.MMIOBase-sizeof.ohci_controller] |
||
664 | mov eax, [edi+OhciInterruptStatusReg] |
||
665 | ; 3. Check whether that interrupt has been generated by our controller. |
||
666 | ; (One IRQ can be shared by several devices.) |
||
667 | and eax, [edi+OhciInterruptEnableReg] |
||
668 | jz .noint |
||
669 | ; 4. Get the physical pointer to the last processed descriptor. |
||
670 | ; All processed descriptors form single-linked list from last to first |
||
671 | ; with the help of NextTD field. The list is restarted every time when |
||
672 | ; the controller writes to DoneHead, so grab the pointer now (before the next |
||
673 | ; step) or it could be lost (the controller could write new value to DoneHead |
||
674 | ; any time after WorkDone bit is cleared in OhciInterruptStatusReg). |
||
675 | mov ecx, [esi+ohci_controller.DoneHead-sizeof.ohci_controller] |
||
676 | and ecx, not 1 |
||
677 | ; 5. Clear the events we know of. |
||
678 | ; Note that this should be done before processing of events: |
||
679 | ; new events could arise while we are processing those, this way we won't lose |
||
680 | ; them (the controller would generate another interrupt |
||
681 | ; after completion of this one). |
||
682 | mov [edi+OhciInterruptStatusReg], eax |
||
683 | ; 6. Save the mask of events for further reference. |
||
684 | push eax |
||
685 | ; 7. Handle 'transfer is done' events. |
||
686 | ; 7a. Test whether there are such events. |
||
687 | test al, 2 |
||
688 | jz .skip_donehead |
||
689 | ; There are some 'transfer is done' events, processed descriptors are linked |
||
690 | ; through physical addresses in the reverse order. |
||
691 | ; We can't do much in an interrupt handler, since callbacks could require |
||
692 | ; waiting for locks and that can't be done in an interrupt handler. |
||
693 | ; However, we can't also just defer all work to the USB thread, since |
||
694 | ; it is possible that previous lists are not yet processed and it is hard |
||
695 | ; to store unlimited number of list heads. Thus, we reverse the current list, |
||
696 | ; append it to end of the previous list (if there is one) and defer other |
||
697 | ; processing to the USB thread; this way there always is no more than one list |
||
698 | ; (possibly joined from several controller-reported lists). |
||
699 | ; The list traversal requires converting physical addresses to virtual pointers, |
||
700 | ; so we may as well store pointers instead of physical addresses. |
||
701 | ; 7b. Prepare for the reversing loop. |
||
702 | push ebx |
||
703 | xor ebx, ebx |
||
704 | test ecx, ecx |
||
705 | jz .tddone |
||
706 | call usb_td_to_virt |
||
707 | test eax, eax |
||
708 | jz .tddone |
||
709 | lea edx, [eax+ohci_gtd.NextTD] |
||
710 | ; 7c. Reverse the list, converting physical to virtual. On every iteration: |
||
711 | ; ecx = physical address of the current item |
||
712 | ; eax = virtual pointer to the current item |
||
713 | ; edx = virtual pointer to the last item.NextTD (first in the reverse list) |
||
714 | ; ebx = virtual pointer to the next item (previous in the reverse list) |
||
715 | .tdloop: |
||
716 | mov ecx, [eax+ohci_gtd.NextTD] |
||
717 | mov [eax+ohci_gtd.NextTD], ebx |
||
3653 | clevermous | 718 | lea ebx, [eax+sizeof.ohci_gtd] |
3520 | clevermous | 719 | test ecx, ecx |
720 | jz .tddone |
||
721 | call usb_td_to_virt |
||
722 | test eax, eax |
||
723 | jnz .tdloop |
||
724 | .tddone: |
||
725 | mov ecx, ebx |
||
726 | pop ebx |
||
727 | ; 7d. The list is reversed, |
||
728 | ; ecx = pointer to the first item, edx = pointer to the last item.NextTD. |
||
729 | ; If the list is empty (unusual case), step 7 is done. |
||
730 | test ecx, ecx |
||
731 | jz .skip_donehead |
||
732 | ; 7e. Otherwise, append this list to the end of previous one. |
||
733 | ; Note that in theory the interrupt handler and the USB thread |
||
734 | ; could execute in parallel. |
||
735 | .append_restart: |
||
736 | ; Atomically get DoneListEndPtr in eax and set it to edx. |
||
737 | mov eax, [esi+ohci_controller.DoneListEndPtr-sizeof.ohci_controller] |
||
738 | lock cmpxchg [esi+ohci_controller.DoneListEndPtr-sizeof.ohci_controller], edx |
||
739 | jnz .append_restart |
||
740 | ; Store pointer to the new list. |
||
741 | ; Note: we cannot perform any operations with [DoneListEndPtr] |
||
742 | ; until we switch DoneListEndPtr to a new descriptor: |
||
743 | ; it is possible that after first line of .append_restart loop |
||
744 | ; ohci_process_deferred obtains the control, finishes processing |
||
745 | ; of the old list, sets DoneListEndPtr to address of DoneList, |
||
746 | ; frees all old descriptors, so eax would point to invalid location. |
||
747 | ; This way, .append_restart loop would detect that DoneListEndPtr |
||
748 | ; has changed, so eax needs to be re-read. |
||
749 | mov [eax], ecx |
||
750 | ; 7f. Notify the USB thread that there is new work. |
||
751 | inc ebx |
||
752 | .skip_donehead: |
||
753 | ; 8. Handle start-of-frame events. |
||
754 | ; 8a. Test whether there are such events. |
||
755 | test byte [esp], 4 |
||
756 | jz .skip_sof |
||
757 | ; We enable SOF interrupt only when some pipes are waiting after changes. |
||
758 | spin_lock_irqsave [esi+usb_controller.WaitSpinlock] |
||
759 | ; 8b. Make sure that there was at least one frame update |
||
760 | ; since the request. If not, wait for the next SOF. |
||
761 | movzx eax, [esi+ohci_controller.FrameNumber-sizeof.ohci_controller] |
||
762 | cmp eax, [esi+usb_controller.StartWaitFrame] |
||
763 | jz .sof_unlock |
||
764 | ; 8c. Copy WaitPipeRequest* to ReadyPipeHead*. |
||
765 | mov eax, [esi+usb_controller.WaitPipeRequestAsync] |
||
766 | mov [esi+usb_controller.ReadyPipeHeadAsync], eax |
||
767 | mov eax, [esi+usb_controller.WaitPipeRequestPeriodic] |
||
768 | mov [esi+usb_controller.ReadyPipeHeadPeriodic], eax |
||
769 | ; 8d. It is possible that pipe change is due to removal and |
||
770 | ; Control/BulkCurrentED registers still point to one of pipes to be removed. |
||
771 | ; The code responsible for disconnect events has temporarily stopped |
||
772 | ; Control/Bulk processing, so it is safe to clear Control/BulkCurrentED. |
||
773 | ; After that, restart processing. |
||
774 | xor edx, edx |
||
775 | mov [edi+OhciControlCurrentEDReg], edx |
||
776 | mov [edi+OhciBulkCurrentEDReg], edx |
||
777 | mov dword [edi+OhciCommandStatusReg], 6 |
||
778 | or dword [edi+OhciControlReg], 30h |
||
779 | ; 8e. Disable further interrupts on SOF. |
||
780 | ; Note: OhciInterruptEnableReg/OhciInterruptDisableReg have unusual semantics. |
||
781 | mov dword [edi+OhciInterruptDisableReg], 4 |
||
782 | ; Notify the USB thread that there is new work (with pipes from ReadyPipeHead*). |
||
783 | inc ebx |
||
784 | .sof_unlock: |
||
785 | spin_unlock_irqrestore [esi+usb_controller.RemoveSpinlock] |
||
786 | .skip_sof: |
||
787 | ; Handle roothub events. |
||
788 | ; 9. Test whether there are such events. |
||
789 | test byte [esp], 40h |
||
790 | jz .skip_roothub |
||
791 | ; 10. Check the status of the roothub itself. |
||
792 | ; 10a. Global overcurrent? |
||
793 | test dword [edi+OhciRhStatusReg], 2 |
||
794 | jz @f |
||
795 | ; Note: this needs work. |
||
796 | dbgstr 'global overcurrent' |
||
797 | @@: |
||
798 | ; 10b. Clear roothub events. |
||
799 | mov dword [edi+OhciRhStatusReg], 80020000h |
||
800 | ; 11. Check the status of individual ports. |
||
801 | ; Look for connect/disconnect and reset events. |
||
802 | ; 11a. Prepare for the loop: start from port 0. |
||
803 | xor ecx, ecx |
||
804 | .portloop: |
||
805 | ; 11b. Get the port status and changes of it. |
||
806 | ; Accumulate change information. |
||
807 | ; Look to "11.12.3 Port Change Information Processing" of the USB2 spec. |
||
808 | xor eax, eax |
||
809 | .accloop: |
||
810 | mov edx, [edi+OhciRhPortStatusReg+ecx*4] |
||
811 | xor ax, ax |
||
812 | or eax, edx |
||
813 | test edx, 1F0000h |
||
814 | jz .accdone |
||
815 | mov dword [edi+OhciRhPortStatusReg+ecx*4], 1F0000h |
||
816 | jmp .accloop |
||
817 | .accdone: |
||
818 | ; debugging output, not needed for work |
||
819 | ; test eax, 1F0000h |
||
820 | ; jz @f |
||
821 | ; DEBUGF 1,'K : ohci irq [%d] status of port %d is %x\n',[timer_ticks],ecx,eax |
||
822 | ;@@: |
||
823 | ; 11c. Ignore any events until all ports are powered up. |
||
824 | ; They will be processed by ohci_init. |
||
825 | cmp [esi+ohci_controller.PoweredUp-sizeof.ohci_controller], 0 |
||
826 | jz .nextport |
||
827 | ; Handle changing of connection status. |
||
828 | test eax, 10000h |
||
829 | jz .nocsc |
||
830 | ; There was a connect or disconnect event at this port. |
||
831 | ; 11d. Disconnect the old device on this port, if any. |
||
832 | ; if the port was resetting, indicate fail and signal |
||
833 | cmp cl, [esi+usb_controller.ResettingPort] |
||
834 | jnz @f |
||
835 | mov [esi+usb_controller.ResettingStatus], -1 |
||
836 | inc ebx |
||
837 | @@: |
||
838 | lock bts [esi+usb_controller.NewDisconnected], ecx |
||
839 | ; notify the USB thread that new work is waiting |
||
840 | inc ebx |
||
841 | ; 11e. Change connected status. For the connection event, also |
||
842 | ; store the connection time; any further processing is permitted only |
||
843 | ; after USB_CONNECT_DELAY ticks. |
||
844 | test al, 1 |
||
845 | jz .disconnect |
||
846 | ; Note: ConnectedTime must be stored before setting the 'connected' bit, |
||
847 | ; otherwise ohci_process_deferred could use an old time. |
||
848 | mov eax, [timer_ticks] |
||
849 | mov [esi+usb_controller.ConnectedTime+ecx*4], eax |
||
850 | lock bts [esi+usb_controller.NewConnected], ecx |
||
851 | jmp .nextport |
||
852 | .disconnect: |
||
853 | lock btr [esi+usb_controller.NewConnected], ecx |
||
854 | jmp .nextport |
||
855 | .nocsc: |
||
856 | ; 11f. Process 'reset done' events. |
||
857 | test eax, 100000h |
||
858 | jz .nextport |
||
859 | test al, 10h |
||
860 | jnz .nextport |
||
861 | mov edx, [timer_ticks] |
||
862 | mov [esi+usb_controller.ResetTime], edx |
||
863 | mov [esi+usb_controller.ResettingStatus], 2 |
||
864 | inc ebx |
||
865 | .nextport: |
||
866 | ; 11g. Continue the loop for the next port. |
||
867 | inc ecx |
||
868 | cmp ecx, [esi+usb_controller.NumPorts] |
||
869 | jb .portloop |
||
870 | .skip_roothub: |
||
871 | ; 12. Restore the stack after step 6. |
||
872 | pop eax |
||
873 | ; 13. Notify the USB thread if some deferred processing is required. |
||
874 | call usb_wakeup_if_needed |
||
875 | ; 14. Interrupt processed; return something non-zero. |
||
876 | mov al, 1 |
||
877 | pop edi esi ebx ; restore used registers to be stdcall |
||
878 | ret |
||
879 | endp |
||
880 | |||
881 | ; This procedure is called from usb_set_address_callback |
||
882 | ; and stores USB device address in the ohci_pipe structure. |
||
883 | ; in: esi -> usb_controller, ebx -> usb_pipe, cl = address |
||
884 | proc ohci_set_device_address |
||
3653 | clevermous | 885 | mov byte [ebx+ohci_pipe.Flags-sizeof.ohci_pipe], cl |
3520 | clevermous | 886 | ; Wait until the hardware will forget the old value. |
887 | call usb_subscribe_control |
||
888 | ret |
||
889 | endp |
||
890 | |||
891 | ; This procedure returns USB device address from the usb_pipe structure. |
||
892 | ; in: esi -> usb_controller, ebx -> usb_pipe |
||
893 | ; out: eax = endpoint address |
||
894 | proc ohci_get_device_address |
||
3653 | clevermous | 895 | mov eax, [ebx+ohci_pipe.Flags-sizeof.ohci_pipe] |
3520 | clevermous | 896 | and eax, 7Fh |
897 | ret |
||
898 | endp |
||
899 | |||
900 | ; This procedure is called from usb_set_address_callback |
||
901 | ; if the device does not accept SET_ADDRESS command and needs |
||
902 | ; to be disabled at the port level. |
||
903 | ; in: esi -> usb_controller, ecx = port |
||
904 | proc ohci_port_disable |
||
905 | mov edx, [esi+ohci_controller.MMIOBase-sizeof.ohci_controller] |
||
906 | mov dword [edx+OhciRhPortStatusReg+ecx*4], 1 |
||
907 | ret |
||
908 | endp |
||
909 | |||
910 | ; This procedure is called from usb_get_descr8_callback when |
||
911 | ; the packet size for zero endpoint becomes known and |
||
912 | ; stores the packet size in ohci_pipe structure. |
||
913 | ; in: esi -> usb_controller, ebx -> usb_pipe, ecx = packet size |
||
914 | proc ohci_set_endpoint_packet_size |
||
3653 | clevermous | 915 | mov byte [ebx+ohci_pipe.Flags+2-sizeof.ohci_pipe], cl |
3520 | clevermous | 916 | ; Wait until the hardware will forget the old value. |
917 | call usb_subscribe_control |
||
918 | ret |
||
919 | endp |
||
920 | |||
921 | ; This procedure is called from API usb_open_pipe and processes |
||
922 | ; the controller-specific part of this API. See docs. |
||
923 | ; in: edi -> usb_pipe for target, ecx -> usb_pipe for config pipe, |
||
924 | ; esi -> usb_controller, eax -> usb_gtd for the first TD, |
||
925 | ; [ebp+12] = endpoint, [ebp+16] = maxpacket, [ebp+20] = type |
||
926 | proc ohci_init_pipe |
||
927 | virtual at ebp+8 |
||
928 | .config_pipe dd ? |
||
929 | .endpoint dd ? |
||
930 | .maxpacket dd ? |
||
931 | .type dd ? |
||
932 | .interval dd ? |
||
933 | end virtual |
||
934 | ; 1. Initialize the queue of transfer descriptors: empty. |
||
3653 | clevermous | 935 | sub eax, sizeof.ohci_gtd |
3520 | clevermous | 936 | call get_phys_addr |
3653 | clevermous | 937 | mov [edi+ohci_pipe.TailP-sizeof.ohci_pipe], eax |
938 | mov [edi+ohci_pipe.HeadP-sizeof.ohci_pipe], eax |
||
3520 | clevermous | 939 | ; 2. Generate ohci_pipe.Flags, see the description in ohci_pipe. |
3653 | clevermous | 940 | mov eax, [ecx+ohci_pipe.Flags-sizeof.ohci_pipe] |
3520 | clevermous | 941 | and eax, 0x207F ; keep Speed bit and FunctionAddress |
942 | mov edx, [.endpoint] |
||
943 | and edx, 15 |
||
944 | shl edx, 7 |
||
945 | or eax, edx |
||
3653 | clevermous | 946 | mov [edi+ohci_pipe.Flags-sizeof.ohci_pipe], eax |
3520 | clevermous | 947 | mov eax, [.maxpacket] |
3653 | clevermous | 948 | mov word [edi+ohci_pipe.Flags+2-sizeof.ohci_pipe], ax |
3520 | clevermous | 949 | cmp [.type], CONTROL_PIPE |
950 | jz @f |
||
951 | test byte [.endpoint], 80h |
||
952 | setnz al |
||
953 | inc eax |
||
954 | shl al, 3 |
||
3653 | clevermous | 955 | or byte [edi+ohci_pipe.Flags+1-sizeof.ohci_pipe], al |
3520 | clevermous | 956 | @@: |
957 | ; 3. Insert the new pipe to the corresponding list of endpoints. |
||
958 | ; 3a. Use Control list for control pipes, Bulk list for bulk pipes. |
||
959 | lea edx, [esi+ohci_controller.ControlED.SoftwarePart-sizeof.ohci_controller] |
||
960 | cmp [.type], BULK_PIPE |
||
961 | jb .insert ; control pipe |
||
962 | lea edx, [esi+ohci_controller.BulkED.SoftwarePart-sizeof.ohci_controller] |
||
963 | jz .insert ; bulk pipe |
||
964 | .interrupt_pipe: |
||
965 | ; 3b. For interrupt pipes, let the scheduler select the appropriate list |
||
966 | ; based on the current bandwidth distribution and the requested bandwidth. |
||
967 | ; This could fail if the requested bandwidth is not available; |
||
968 | ; if so, return an error. |
||
969 | lea edx, [esi + ohci_controller.IntEDs - sizeof.ohci_controller] |
||
970 | lea eax, [esi + ohci_controller.IntEDs + 32*sizeof.ohci_static_ep - sizeof.ohci_controller] |
||
3598 | clevermous | 971 | movi ecx, 64 |
3520 | clevermous | 972 | call usb1_select_interrupt_list |
973 | test edx, edx |
||
974 | jz .return0 |
||
975 | ; 3c. Insert endpoint at edi to the head of list in edx. |
||
976 | ; Inserting to tail would work as well, |
||
977 | ; but let's be consistent with other controllers. |
||
978 | .insert: |
||
979 | mov ecx, [edx+usb_pipe.NextVirt] |
||
980 | mov [edi+usb_pipe.NextVirt], ecx |
||
981 | mov [edi+usb_pipe.PrevVirt], edx |
||
982 | mov [ecx+usb_pipe.PrevVirt], edi |
||
983 | mov [edx+usb_pipe.NextVirt], edi |
||
3653 | clevermous | 984 | mov ecx, [edx+ohci_pipe.NextED-sizeof.ohci_pipe] |
985 | mov [edi+ohci_pipe.NextED-sizeof.ohci_pipe], ecx |
||
986 | lea eax, [edi-sizeof.ohci_pipe] |
||
3520 | clevermous | 987 | call get_phys_addr |
3653 | clevermous | 988 | mov [edx+ohci_pipe.NextED-sizeof.ohci_pipe], eax |
3520 | clevermous | 989 | ; 4. Return something non-zero. |
990 | ret |
||
991 | .return0: |
||
992 | xor eax, eax |
||
993 | ret |
||
994 | endp |
||
995 | |||
996 | ; This function is called from ohci_process_deferred when |
||
997 | ; a new device was connected at least USB_CONNECT_DELAY ticks |
||
998 | ; and therefore is ready to be configured. |
||
999 | ; ecx = port, esi -> usb_controller |
||
1000 | proc ohci_new_port |
||
1001 | ; test whether we are configuring another port |
||
1002 | ; if so, postpone configuring and return |
||
1003 | bts [esi+usb_controller.PendingPorts], ecx |
||
1004 | cmp [esi+usb_controller.ResettingPort], -1 |
||
1005 | jnz .nothing |
||
1006 | btr [esi+usb_controller.PendingPorts], ecx |
||
1007 | ; fall through to ohci_new_port.reset |
||
1008 | |||
1009 | ; This function is called from usb_test_pending_port. |
||
1010 | ; It starts reset signalling for the port. Note that in USB first stages |
||
1011 | ; of configuration can not be done for several ports in parallel. |
||
1012 | .reset: |
||
1013 | ; reset port |
||
1014 | and [esi+usb_controller.ResettingHub], 0 |
||
1015 | mov [esi+usb_controller.ResettingPort], cl |
||
1016 | ; Note: setting status must be the last action: |
||
1017 | ; it is possible that the device has been disconnected |
||
1018 | ; after timeout of USB_CONNECT_DELAY but before call to ohci_new_port. |
||
1019 | ; In this case, ohci_irq would not set reset status to 'failed', |
||
1020 | ; because ohci_irq would not know that this port is to be reset. |
||
1021 | ; However, the hardware would generate another interrupt |
||
1022 | ; in a response to reset a disconnected port, and this time |
||
1023 | ; ohci_irq knows that it needs to generate 'reset failed' event |
||
1024 | ; (because ResettingPort is now filled). |
||
1025 | push edi |
||
1026 | mov edi, [esi+ohci_controller.MMIOBase-sizeof.ohci_controller] |
||
1027 | mov dword [edi+OhciRhPortStatusReg+ecx*4], 10h |
||
1028 | pop edi |
||
1029 | .nothing: |
||
1030 | ret |
||
1031 | endp |
||
1032 | |||
1033 | ; This procedure is called from the several places in main USB code |
||
1034 | ; and allocates required packets for the given transfer. |
||
1035 | ; ebx = pipe, other parameters are passed through the stack: |
||
1036 | ; buffer,size = data to transfer |
||
1037 | ; flags = same as in usb_open_pipe: bit 0 = allow short transfer, other bits reserved |
||
1038 | ; td = pointer to the current end-of-queue descriptor |
||
1039 | ; direction = |
||
1040 | ; 0000b for normal transfers, |
||
1041 | ; 1000b for control SETUP transfer, |
||
1042 | ; 1101b for control OUT transfer, |
||
1043 | ; 1110b for control IN transfer |
||
1044 | ; returns eax = pointer to the new end-of-queue descriptor |
||
1045 | ; (not included in the queue itself) or 0 on error |
||
1046 | proc ohci_alloc_transfer stdcall uses edi, \ |
||
1047 | buffer:dword, size:dword, flags:dword, td:dword, direction:dword |
||
1048 | locals |
||
1049 | origTD dd ? |
||
1050 | packetSize dd ? ; must be the last variable, see usb_init_transfer |
||
1051 | endl |
||
1052 | ; 1. Save original value of td: |
||
1053 | ; it will be useful for rollback if something would fail. |
||
1054 | mov eax, [td] |
||
1055 | mov [origTD], eax |
||
1056 | ; One transfer descriptor can describe up to two pages. |
||
1057 | ; In the worst case (when the buffer is something*1000h+0FFFh) |
||
1058 | ; this corresponds to 1001h bytes. If the requested size is |
||
1059 | ; greater, we should split the transfer into several descriptors. |
||
1060 | ; Boundaries to split must be multiples of endpoint transfer size |
||
1061 | ; to avoid short packets except in the end of the transfer, |
||
1062 | ; 1000h is always a good value. |
||
1063 | ; 2. While the remaining data cannot fit in one packet, |
||
1064 | ; allocate page-sized descriptors. |
||
1065 | mov edi, 1000h |
||
1066 | mov [packetSize], edi |
||
1067 | .fullpackets: |
||
1068 | cmp [size], edi |
||
1069 | jbe .lastpacket |
||
1070 | call ohci_alloc_packet |
||
1071 | test eax, eax |
||
1072 | jz .fail |
||
1073 | mov [td], eax |
||
1074 | add [buffer], edi |
||
1075 | sub [size], edi |
||
1076 | jmp .fullpackets |
||
1077 | ; 3. The remaining data can fit in one descriptor; |
||
1078 | ; allocate the last descriptor with size = size of remaining data. |
||
1079 | .lastpacket: |
||
1080 | mov eax, [size] |
||
1081 | mov [packetSize], eax |
||
1082 | call ohci_alloc_packet |
||
1083 | test eax, eax |
||
1084 | jz .fail |
||
1085 | ; 4. Enable an immediate interrupt on completion of the last packet. |
||
3653 | clevermous | 1086 | and byte [ecx+ohci_gtd.Flags+2-sizeof.ohci_gtd], not (7 shl (21-16)) |
3520 | clevermous | 1087 | ; 5. If a short transfer is ok for a caller, set the corresponding bit in |
1088 | ; the last descriptor, but not in others. |
||
1089 | ; Note: even if the caller says that short transfers are ok, |
||
1090 | ; all packets except the last one are marked as 'must be complete': |
||
1091 | ; if one of them will be short, the software intervention is needed |
||
1092 | ; to skip remaining packets; ohci_process_finalized_td will handle this |
||
1093 | ; transparently to the caller. |
||
1094 | test [flags], 1 |
||
1095 | jz @f |
||
3653 | clevermous | 1096 | or byte [ecx+ohci_gtd.Flags+2-sizeof.ohci_gtd], 1 shl (18-16) |
3520 | clevermous | 1097 | @@: |
1098 | ret |
||
1099 | .fail: |
||
1100 | mov edi, ohci_hardware_func |
||
1101 | mov eax, [td] |
||
1102 | stdcall usb_undo_tds, [origTD] |
||
1103 | xor eax, eax |
||
1104 | ret |
||
1105 | endp |
||
1106 | |||
1107 | ; Helper procedure for ohci_alloc_transfer. |
||
1108 | ; Allocates and initializes one transfer descriptor. |
||
1109 | ; ebx = pipe, other parameters are passed through the stack; |
||
1110 | ; fills the current last descriptor and |
||
1111 | ; returns eax = next descriptor (not filled). |
||
1112 | proc ohci_alloc_packet |
||
1113 | ; inherit some variables from the parent ohci_alloc_transfer |
||
1114 | virtual at ebp-8 |
||
1115 | .origTD dd ? |
||
1116 | .packetSize dd ? |
||
1117 | rd 2 |
||
1118 | .buffer dd ? |
||
1119 | .transferSize dd ? |
||
1120 | .Flags dd ? |
||
1121 | .td dd ? |
||
1122 | .direction dd ? |
||
1123 | end virtual |
||
1124 | ; 1. Allocate the next TD. |
||
1125 | call usb1_allocate_general_td |
||
1126 | test eax, eax |
||
1127 | jz .nothing |
||
1128 | ; 2. Initialize controller-independent parts of both TDs. |
||
1129 | push eax |
||
1130 | call usb_init_transfer |
||
1131 | pop eax |
||
1132 | ; 3. Save the returned value (next descriptor). |
||
1133 | push eax |
||
1134 | ; 4. Store the physical address of the next descriptor. |
||
3653 | clevermous | 1135 | sub eax, sizeof.ohci_gtd |
3520 | clevermous | 1136 | call get_phys_addr |
3653 | clevermous | 1137 | mov [ecx+ohci_gtd.NextTD-sizeof.ohci_gtd], eax |
3520 | clevermous | 1138 | ; 5. For zero-length transfers, store zero in both fields for buffer addresses. |
1139 | ; Otherwise, fill them with real values. |
||
1140 | xor eax, eax |
||
3653 | clevermous | 1141 | mov [ecx+ohci_gtd.CurBufPtr-sizeof.ohci_gtd], eax |
1142 | mov [ecx+ohci_gtd.BufEnd-sizeof.ohci_gtd], eax |
||
3520 | clevermous | 1143 | cmp [.packetSize], eax |
1144 | jz @f |
||
1145 | mov eax, [.buffer] |
||
1146 | call get_phys_addr |
||
3653 | clevermous | 1147 | mov [ecx+ohci_gtd.CurBufPtr-sizeof.ohci_gtd], eax |
3520 | clevermous | 1148 | mov eax, [.buffer] |
1149 | add eax, [.packetSize] |
||
1150 | dec eax |
||
1151 | call get_phys_addr |
||
3653 | clevermous | 1152 | mov [ecx+ohci_gtd.BufEnd-sizeof.ohci_gtd], eax |
3520 | clevermous | 1153 | @@: |
1154 | ; 6. Generate Flags field: |
||
1155 | ; - set bufferRounding (bit 18) to zero = disallow short transfers; |
||
1156 | ; for the last transfer in a row, ohci_alloc_transfer would set the real value; |
||
1157 | ; - set Direction (bits 19-20) to lower 2 bits of [.direction]; |
||
1158 | ; - set DelayInterrupt (bits 21-23) to 7 = do not generate interrupt; |
||
1159 | ; for the last transfer in a row, ohci_alloc_transfer would set the real value; |
||
1160 | ; - set DataToggle (bits 24-25) to next 2 bits of [.direction]; |
||
1161 | ; - set ConditionCode (bits 28-31) to 1111b as a indicator that there was no |
||
1162 | ; attempts to perform this transfer yet; |
||
1163 | ; - zero all other bits. |
||
1164 | mov eax, [.direction] |
||
1165 | mov edx, eax |
||
1166 | and eax, 3 |
||
1167 | shl eax, 19 |
||
1168 | and edx, (3 shl 2) |
||
1169 | shl edx, 24 - 2 |
||
1170 | lea eax, [eax + edx + (7 shl 21) + (15 shl 28)] |
||
3653 | clevermous | 1171 | mov [ecx+ohci_gtd.Flags-sizeof.ohci_gtd], eax |
3520 | clevermous | 1172 | ; 7. Restore the returned value saved in step 3. |
1173 | pop eax |
||
1174 | .nothing: |
||
1175 | ret |
||
1176 | endp |
||
1177 | |||
1178 | ; This procedure is called from the several places in main USB code |
||
1179 | ; and activates the transfer which was previously allocated by |
||
1180 | ; ohci_alloc_transfer. |
||
1181 | ; ecx -> last descriptor for the transfer, ebx -> usb_pipe |
||
1182 | proc ohci_insert_transfer |
||
1183 | ; 1. Advance the queue of transfer descriptors. |
||
3653 | clevermous | 1184 | mov eax, [ecx+ohci_gtd.NextTD-sizeof.ohci_gtd] |
1185 | mov [ebx+ohci_pipe.TailP-sizeof.ohci_pipe], eax |
||
3520 | clevermous | 1186 | ; 2. For control and bulk pipes, notify the controller that |
1187 | ; there is new work in control/bulk queue respectively. |
||
1188 | ohci_notify_new_work: |
||
1189 | mov edx, [ebx+usb_pipe.Controller] |
||
1190 | mov edx, [edx+ohci_controller.MMIOBase-sizeof.ohci_controller] |
||
1191 | cmp [ebx+usb_pipe.Type], CONTROL_PIPE |
||
1192 | jz .control |
||
1193 | cmp [ebx+usb_pipe.Type], BULK_PIPE |
||
1194 | jnz .nothing |
||
1195 | .bulk: |
||
1196 | mov dword [edx+OhciCommandStatusReg], 4 |
||
1197 | jmp .nothing |
||
1198 | .control: |
||
1199 | mov dword [edx+OhciCommandStatusReg], 2 |
||
1200 | .nothing: |
||
1201 | ret |
||
1202 | endp |
||
1203 | |||
1204 | ; This function is called from ohci_process_deferred when |
||
1205 | ; a new device has been reset and needs to be configured. |
||
1206 | proc ohci_port_after_reset |
||
1207 | ; 1. Get the status. |
||
1208 | ; If reset has been failed (device disconnected during reset), |
||
1209 | ; continue to next device (if there is one). |
||
1210 | xor eax, eax |
||
1211 | xchg al, [esi+usb_controller.ResettingStatus] |
||
1212 | test al, al |
||
1213 | js usb_test_pending_port |
||
1214 | ; If the controller has disabled the port (e.g. overcurrent), |
||
1215 | ; continue to next device (if there is one). |
||
1216 | movzx ecx, [esi+usb_controller.ResettingPort] |
||
1217 | mov eax, [edi+OhciRhPortStatusReg+ecx*4] |
||
1218 | test al, 2 |
||
1219 | jnz @f |
||
1220 | DEBUGF 1,'K : USB port disabled after reset, status=%x\n',eax |
||
1221 | jmp usb_test_pending_port |
||
1222 | @@: |
||
1223 | push ecx |
||
1224 | ; 2. Get LowSpeed bit to bit 0 of eax and call the worker procedure |
||
1225 | ; to notify the protocol layer about new OHCI device. |
||
1226 | mov eax, [edi+OhciRhPortStatusReg+ecx*4] |
||
1227 | DEBUGF 1,'K : port_after_reset [%d] status of port %d is %x\n',[timer_ticks],ecx,eax |
||
1228 | shr eax, 9 |
||
1229 | call ohci_new_device |
||
1230 | pop ecx |
||
1231 | ; 3. If something at the protocol layer has failed |
||
1232 | ; (no memory, no bus address), disable the port and stop the initialization. |
||
1233 | test eax, eax |
||
1234 | jnz .nothing |
||
1235 | .disable_exit: |
||
1236 | mov dword [edi+OhciRhPortStatusReg+ecx*4], 1 |
||
1237 | jmp usb_test_pending_port |
||
1238 | .nothing: |
||
1239 | ret |
||
1240 | endp |
||
1241 | |||
1242 | ; This procedure is called from uhci_port_init and from hub support code |
||
1243 | ; when a new device is connected and has been reset. |
||
1244 | ; It calls usb_new_device at the protocol layer with correct parameters. |
||
1245 | ; in: esi -> usb_controller, eax = speed; |
||
1246 | ; OHCI is USB1 device, so only low bit of eax (LowSpeed) is used. |
||
1247 | proc ohci_new_device |
||
1248 | ; 1. Clear all bits of speed except bit 0. |
||
1249 | and eax, 1 |
||
1250 | ; 2. Store the speed for the protocol layer. |
||
1251 | mov [esi+usb_controller.ResettingSpeed], al |
||
1252 | ; 3. Create pseudo-pipe in the stack. |
||
1253 | ; See ohci_init_pipe: only .Controller and .Flags fields are used. |
||
1254 | shl eax, 13 |
||
1255 | push esi ; .Controller |
||
1256 | mov ecx, esp |
||
1257 | sub esp, 12 ; ignored fields |
||
1258 | push eax ; .Flags |
||
1259 | ; 4. Notify the protocol layer. |
||
1260 | call usb_new_device |
||
1261 | ; 5. Cleanup the stack after step 3 and return. |
||
1262 | add esp, 20 |
||
1263 | ret |
||
1264 | endp |
||
1265 | |||
1266 | ; This procedure is called in the USB thread from usb_thread_proc, |
||
1267 | ; processes regular actions and those actions which can't be safely done |
||
1268 | ; from interrupt handler. |
||
1269 | ; Returns maximal time delta before the next call. |
||
1270 | proc ohci_process_deferred |
||
1271 | push ebx edi ; save used registers to be stdcall |
||
1272 | ; 1. Initialize the return value. |
||
1273 | push -1 |
||
1274 | ; 2. Process disconnect events. |
||
1275 | call usb_disconnect_stage2 |
||
1276 | ; 3. Check for connected devices. |
||
1277 | ; If there is a connected device which was connected less than |
||
1278 | ; USB_CONNECT_DELAY ticks ago, plan to wake up when the delay will be over. |
||
1279 | ; Otherwise, call ohci_new_port. |
||
1280 | mov edi, [esi+ohci_controller.MMIOBase-sizeof.ohci_controller] |
||
1281 | xor ecx, ecx |
||
1282 | cmp [esi+usb_controller.NewConnected], ecx |
||
1283 | jz .skip_newconnected |
||
1284 | .portloop: |
||
1285 | bt [esi+usb_controller.NewConnected], ecx |
||
1286 | jnc .noconnect |
||
1287 | mov eax, [timer_ticks] |
||
1288 | sub eax, [esi+usb_controller.ConnectedTime+ecx*4] |
||
1289 | sub eax, USB_CONNECT_DELAY |
||
1290 | jge .connected |
||
1291 | neg eax |
||
1292 | cmp [esp], eax |
||
1293 | jb .nextport |
||
1294 | mov [esp], eax |
||
1295 | jmp .nextport |
||
1296 | .connected: |
||
1297 | lock btr [esi+usb_controller.NewConnected], ecx |
||
1298 | jnc .nextport |
||
1299 | call ohci_new_port |
||
1300 | .noconnect: |
||
1301 | .nextport: |
||
1302 | inc ecx |
||
1303 | cmp ecx, [esi+usb_controller.NumPorts] |
||
1304 | jb .portloop |
||
1305 | .skip_newconnected: |
||
1306 | ; 4. Check for end of reset signalling. If so, call ohci_port_after_reset. |
||
1307 | cmp [esi+usb_controller.ResettingStatus], 2 |
||
1308 | jnz .no_reset_recovery |
||
1309 | mov eax, [timer_ticks] |
||
1310 | sub eax, [esi+usb_controller.ResetTime] |
||
1311 | sub eax, USB_RESET_RECOVERY_TIME |
||
1312 | jge .reset_done |
||
1313 | neg eax |
||
1314 | cmp [esp], eax |
||
1315 | jb .skip_roothub |
||
1316 | mov [esp], eax |
||
1317 | jmp .skip_roothub |
||
1318 | .no_reset_recovery: |
||
1319 | cmp [esi+usb_controller.ResettingStatus], 0 |
||
1320 | jz .skip_roothub |
||
1321 | .reset_done: |
||
1322 | call ohci_port_after_reset |
||
1323 | .skip_roothub: |
||
1324 | ; 5. Finalize transfers processed by hardware. |
||
1325 | ; It is better to perform this step after processing disconnect events, |
||
1326 | ; although not strictly obligatory. This way, an active transfer aborted |
||
1327 | ; due to disconnect would be handled with more specific USB_STATUS_CLOSED, |
||
1328 | ; not USB_STATUS_NORESPONSE. |
||
1329 | ; Loop over all items in DoneList, call ohci_process_finalized_td for each. |
||
1330 | xor ebx, ebx |
||
1331 | xchg ebx, [esi+ohci_controller.DoneList-sizeof.ohci_controller] |
||
1332 | .tdloop: |
||
1333 | test ebx, ebx |
||
1334 | jz .tddone |
||
1335 | call ohci_process_finalized_td |
||
1336 | jmp .tdloop |
||
1337 | .tddone: |
||
1338 | ; 6. Process wait-done notifications, test for new wait requests. |
||
1339 | ; Note: that must be done after steps 2 and 5 which could create new requests. |
||
1340 | ; 6a. Call the worker function from main USB code. |
||
1341 | call usb_process_wait_lists |
||
1342 | ; 6b. If no new requests, skip the rest of this step. |
||
1343 | test eax, eax |
||
1344 | jz @f |
||
1345 | ; 6c. OHCI is not allowed to cache anything; we don't know what is |
||
1346 | ; processed right now, but we can be sure that the controller will not |
||
1347 | ; use any removed structure starting from the next frame. |
||
1348 | ; Schedule SOF event. |
||
1349 | spin_lock_irq [esi+usb_controller.RemoveSpinlock] |
||
1350 | mov eax, [esi+usb_controller.WaitPipeListAsync] |
||
1351 | mov [esi+usb_controller.WaitPipeRequestAsync], eax |
||
1352 | mov eax, [esi+usb_controller.WaitPipeListPeriodic] |
||
1353 | mov [esi+usb_controller.WaitPipeRequestPeriodic], eax |
||
1354 | ; temporarily stop bulk and interrupt processing; |
||
1355 | ; this is required for handler of SOF event |
||
1356 | and dword [edi+OhciControlReg], not 30h |
||
1357 | ; remember the frame number when processing has been stopped |
||
1358 | ; (needs to be done after stopping) |
||
1359 | movzx eax, [esi+ohci_controller.FrameNumber-sizeof.ohci_controller] |
||
1360 | mov [esi+usb_controller.StartWaitFrame], eax |
||
1361 | ; make sure that the next SOF will happen after the request |
||
1362 | mov dword [edi+OhciInterruptStatusReg], 4 |
||
1363 | ; enable interrupt on SOF |
||
1364 | ; Note: OhciInterruptEnableReg/OhciInterruptDisableReg have unusual semantics, |
||
1365 | ; so there should be 'mov' here, not 'or' |
||
1366 | mov dword [edi+OhciInterruptEnableReg], 4 |
||
1367 | spin_unlock_irq [esi+usb_controller.RemoveSpinlock] |
||
1368 | @@: |
||
1369 | ; 7. Restore the return value and return. |
||
1370 | pop eax |
||
1371 | pop edi ebx ; restore used registers to be stdcall |
||
1372 | ret |
||
1373 | endp |
||
1374 | |||
1375 | ; Helper procedure for ohci_process_deferred. Processes one completed TD. |
||
1376 | ; in: esi -> usb_controller, ebx -> usb_gtd, out: ebx -> next usb_gtd. |
||
1377 | proc ohci_process_finalized_td |
||
1378 | ; DEBUGF 1,'K : processing %x\n',ebx |
||
1379 | ; 1. Check whether the pipe has been closed, either due to API call or due to |
||
1380 | ; disconnect; if so, the callback will be called by usb_pipe_closed with |
||
1381 | ; correct status, so go to step 6 with ebx = 0 (do not free the TD). |
||
1382 | mov edx, [ebx+usb_gtd.Pipe] |
||
1383 | test [edx+usb_pipe.Flags], USB_FLAG_CLOSED |
||
1384 | jz @f |
||
3653 | clevermous | 1385 | lea eax, [ebx+ohci_gtd.NextTD-sizeof.ohci_gtd] |
3520 | clevermous | 1386 | xor ebx, ebx |
1387 | jmp .next_td2 |
||
1388 | @@: |
||
1389 | ; 2. Remove the descriptor from the descriptors queue. |
||
1390 | call usb_unlink_td |
||
1391 | ; 3. Get number of bytes that remain to be transferred. |
||
1392 | ; If CurBufPtr is zero, everything was transferred. |
||
1393 | xor edx, edx |
||
3653 | clevermous | 1394 | cmp [ebx+ohci_gtd.CurBufPtr-sizeof.ohci_gtd], edx |
3520 | clevermous | 1395 | jz .gotlen |
1396 | ; Otherwise, the remaining length is |
||
1397 | ; (BufEnd and 0xFFF) - (CurBufPtr and 0xFFF) + 1, |
||
1398 | ; plus 0x1000 if BufEnd and CurBufPtr are in different pages. |
||
3653 | clevermous | 1399 | mov edx, [ebx+ohci_gtd.BufEnd-sizeof.ohci_gtd] |
1400 | mov eax, [ebx+ohci_gtd.CurBufPtr-sizeof.ohci_gtd] |
||
3520 | clevermous | 1401 | mov ecx, edx |
1402 | and edx, 0xFFF |
||
1403 | inc edx |
||
1404 | xor ecx, eax |
||
1405 | and ecx, -0x1000 |
||
1406 | jz @f |
||
1407 | add edx, 0x1000 |
||
1408 | @@: |
||
1409 | and eax, 0xFFF |
||
1410 | sub edx, eax |
||
1411 | .gotlen: |
||
1412 | ; The actual length is Length - (remaining length). |
||
1413 | sub edx, [ebx+usb_gtd.Length] |
||
1414 | neg edx |
||
1415 | ; 4. Check for error. If so, go to 7. |
||
1416 | push ebx |
||
3653 | clevermous | 1417 | mov eax, [ebx+ohci_gtd.Flags-sizeof.ohci_gtd] |
3520 | clevermous | 1418 | shr eax, 28 |
1419 | jnz .error |
||
1420 | .notify: |
||
1421 | ; 5. Successful completion. |
||
1422 | ; 5a. Check whether this descriptor has an associated callback. |
||
1423 | mov ecx, [ebx+usb_gtd.Callback] |
||
1424 | test ecx, ecx |
||
1425 | jz .ok_nocallback |
||
1426 | ; 5b. If so, call the callback. |
||
1427 | stdcall_verify ecx, [ebx+usb_gtd.Pipe], eax, \ |
||
1428 | [ebx+usb_gtd.Buffer], edx, [ebx+usb_gtd.UserData] |
||
1429 | jmp .next_td |
||
1430 | .ok_nocallback: |
||
1431 | ; 5c. Otherwise, add length of the current descriptor to the next descriptor. |
||
1432 | mov eax, [ebx+usb_gtd.NextVirt] |
||
1433 | add [eax+usb_gtd.Length], edx |
||
1434 | .next_td: |
||
1435 | ; 6. Free the current descriptor and advance to the next item. |
||
1436 | ; If the current item is the last in the list, |
||
1437 | ; set DoneListEndPtr to pointer to DoneList. |
||
1438 | cmp ebx, [esp] |
||
1439 | jz @f |
||
1440 | stdcall usb1_free_general_td, ebx |
||
1441 | @@: |
||
1442 | pop ebx |
||
3653 | clevermous | 1443 | lea eax, [ebx+ohci_gtd.NextTD-sizeof.ohci_gtd] |
3520 | clevermous | 1444 | .next_td2: |
1445 | push ebx |
||
1446 | mov ebx, eax |
||
1447 | lea edx, [esi+ohci_controller.DoneList-sizeof.ohci_controller] |
||
1448 | xor ecx, ecx ; no next item |
||
1449 | lock cmpxchg [esi+ohci_controller.DoneListEndPtr-sizeof.ohci_controller], edx |
||
1450 | jz .last |
||
1451 | ; The current item is not the last. |
||
1452 | ; It is possible, although very rare, that ohci_irq has already advanced |
||
1453 | ; DoneListEndPtr, but not yet written NextTD. Wait until NextTD is nonzero. |
||
1454 | @@: |
||
1455 | mov ecx, [ebx] |
||
1456 | test ecx, ecx |
||
1457 | jz @b |
||
1458 | .last: |
||
1459 | pop ebx |
||
1460 | ; ecx = the next item |
||
1461 | push ecx |
||
1462 | ; Free the current item, set ebx to the next item, continue to 5a. |
||
1463 | test ebx, ebx |
||
1464 | jz @f |
||
1465 | stdcall usb1_free_general_td, ebx |
||
1466 | @@: |
||
1467 | pop ebx |
||
1468 | ret |
||
1469 | .error: |
||
1470 | ; 7. There was an error while processing this descriptor. |
||
1471 | ; The hardware has stopped processing the queue. |
||
1472 | ; 7a. Save status and length. |
||
1473 | push eax |
||
1474 | push edx |
||
1475 | ; DEBUGF 1,'K : TD failed:\n' |
||
3653 | clevermous | 1476 | ; DEBUGF 1,'K : %x %x %x %x\n',[ebx-sizeof.ohci_gtd],[ebx-sizeof.ohci_gtd+4],[ebx-sizeof.ohci_gtd+8],[ebx-sizeof.ohci_gtd+12] |
1477 | ; DEBUGF 1,'K : %x %x %x %x\n',[ebx-sizeof.ohci_gtd+16],[ebx-sizeof.ohci_gtd+20],[ebx-sizeof.ohci_gtd+24],[ebx-sizeof.ohci_gtd+28] |
||
3520 | clevermous | 1478 | ; mov eax, [ebx+usb_gtd.Pipe] |
3653 | clevermous | 1479 | ; DEBUGF 1,'K : pipe: %x %x %x %x\n',[eax-sizeof.ohci_pipe],[eax-sizeof.ohci_pipe+4],[eax-sizeof.ohci_pipe+8],[eax-sizeof.ohci_pipe+12] |
3520 | clevermous | 1480 | ; 7b. Traverse the list of descriptors looking for the final packet |
1481 | ; for this transfer. |
||
1482 | ; Free and unlink non-final descriptors, except the current one. |
||
1483 | ; Final descriptor will be freed in step 6. |
||
1484 | call usb_is_final_packet |
||
1485 | jnc .found_final |
||
1486 | mov ebx, [ebx+usb_gtd.NextVirt] |
||
1487 | virtual at esp |
||
1488 | .length dd ? |
||
1489 | .error_code dd ? |
||
1490 | .current_item dd ? |
||
1491 | end virtual |
||
1492 | .look_final: |
||
1493 | call usb_unlink_td |
||
1494 | call usb_is_final_packet |
||
1495 | jnc .found_final |
||
1496 | push [ebx+usb_gtd.NextVirt] |
||
1497 | stdcall usb1_free_general_td, ebx |
||
1498 | pop ebx |
||
1499 | jmp .look_final |
||
1500 | .found_final: |
||
1501 | ; 7c. If error code is USB_STATUS_UNDERRUN and the last TD allows short packets, |
||
1502 | ; it is not an error. |
||
1503 | ; Note: all TDs except the last one in any transfer stage are marked |
||
1504 | ; as short-packet-is-error to stop controller from further processing |
||
1505 | ; of that stage; we need to restart processing from a TD following the last. |
||
1506 | ; After that, go to step 5 with eax = 0 (no error). |
||
1507 | cmp dword [.error_code], USB_STATUS_UNDERRUN |
||
1508 | jnz .no_underrun |
||
3653 | clevermous | 1509 | test byte [ebx+ohci_gtd.Flags+2-sizeof.ohci_gtd], 1 shl (18-16) |
3520 | clevermous | 1510 | jz .no_underrun |
1511 | and dword [.error_code], 0 |
||
1512 | mov ecx, [ebx+usb_gtd.Pipe] |
||
3653 | clevermous | 1513 | mov edx, [ecx+ohci_pipe.HeadP-sizeof.ohci_pipe] |
3520 | clevermous | 1514 | and edx, 2 |
1515 | .advance_queue: |
||
1516 | mov eax, [ebx+usb_gtd.NextVirt] |
||
3653 | clevermous | 1517 | sub eax, sizeof.ohci_gtd |
3520 | clevermous | 1518 | call get_phys_addr |
1519 | or eax, edx |
||
3653 | clevermous | 1520 | mov [ecx+ohci_pipe.HeadP-sizeof.ohci_pipe], eax |
3520 | clevermous | 1521 | push ebx |
1522 | mov ebx, ecx |
||
1523 | call ohci_notify_new_work |
||
1524 | pop ebx |
||
1525 | pop edx eax |
||
1526 | jmp .notify |
||
1527 | ; 7d. Abort the entire transfer. |
||
1528 | ; There are two cases: either there is only one transfer stage |
||
1529 | ; (everything except control transfers), then ebx points to the last TD and |
||
1530 | ; all previous TD were unlinked and dismissed (if possible), |
||
1531 | ; or there are several stages (a control transfer) and ebx points to the last |
||
1532 | ; TD of Data or Status stage (usb_is_final_packet does not stop in Setup stage, |
||
1533 | ; because Setup stage can not produce short packets); for Data stage, we need |
||
1534 | ; to unlink and free (if possible) one more TD and advance ebx to the next one. |
||
1535 | .no_underrun: |
||
1536 | cmp [ebx+usb_gtd.Callback], 0 |
||
1537 | jnz .halted |
||
1538 | cmp ebx, [.current_item] |
||
1539 | push [ebx+usb_gtd.NextVirt] |
||
1540 | jz @f |
||
1541 | stdcall usb1_free_general_td, ebx |
||
1542 | @@: |
||
1543 | pop ebx |
||
1544 | call usb_unlink_td |
||
1545 | .halted: |
||
1546 | ; 7e. For bulk/interrupt transfers we have no choice but halt the queue, |
||
1547 | ; the driver should intercede (through some API which is not written yet). |
||
1548 | ; Control pipes normally recover at the next SETUP transaction (first stage |
||
1549 | ; of any control transfer), so we hope on the best and just advance the queue |
||
1550 | ; to the next transfer. (According to the standard, "A control pipe may also |
||
1551 | ; support functional stall as well, but this is not recommended."). |
||
1552 | ; Advance the transfer queue to the next descriptor. |
||
1553 | mov ecx, [ebx+usb_gtd.Pipe] |
||
3653 | clevermous | 1554 | mov edx, [ecx+ohci_pipe.HeadP-sizeof.ohci_pipe] |
3520 | clevermous | 1555 | and edx, 2 ; keep toggleCarry bit |
1556 | cmp [ecx+usb_pipe.Type], CONTROL_PIPE |
||
1557 | jnz @f |
||
1558 | inc edx ; set Halted bit |
||
1559 | @@: |
||
1560 | jmp .advance_queue |
||
1561 | endp |
||
1562 | |||
1563 | ; This procedure is called when a pipe is closing (either due to API call |
||
1564 | ; or due to disconnect); it unlinks the pipe from the corresponding list. |
||
1565 | ; esi -> usb_controller, ebx -> usb_pipe |
||
1566 | proc ohci_unlink_pipe |
||
1567 | cmp [ebx+usb_pipe.Type], INTERRUPT_PIPE |
||
1568 | jnz @f |
||
3653 | clevermous | 1569 | mov eax, [ebx+ohci_pipe.Flags-sizeof.ohci_pipe] |
3520 | clevermous | 1570 | bt eax, 13 |
1571 | setc cl |
||
1572 | bt eax, 11 |
||
1573 | setc ch |
||
1574 | shr eax, 16 |
||
1575 | stdcall usb1_interrupt_list_unlink, eax, ecx |
||
1576 | @@: |
||
1577 | mov edx, [ebx+usb_pipe.NextVirt] |
||
1578 | mov eax, [ebx+usb_pipe.PrevVirt] |
||
1579 | mov [edx+usb_pipe.PrevVirt], eax |
||
1580 | mov [eax+usb_pipe.NextVirt], edx |
||
3653 | clevermous | 1581 | mov edx, [ebx+ohci_pipe.NextED-sizeof.ohci_pipe] |
1582 | mov [eax+ohci_pipe.NextED-sizeof.ohci_pipe], edx |
||
3520 | clevermous | 1583 | ret |
1584 | endp>=>> |