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5078 | serge | 1 | /* |
2 | * Copyright 2011 Advanced Micro Devices, Inc. |
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3 | * |
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4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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5 | * copy of this software and associated documentation files (the "Software"), |
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6 | * to deal in the Software without restriction, including without limitation |
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7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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8 | * and/or sell copies of the Software, and to permit persons to whom the |
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9 | * Software is furnished to do so, subject to the following conditions: |
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10 | * |
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11 | * The above copyright notice and this permission notice shall be included in |
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12 | * all copies or substantial portions of the Software. |
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13 | * |
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14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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20 | * OTHER DEALINGS IN THE SOFTWARE. |
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21 | * |
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22 | * Authors: Alex Deucher |
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23 | */ |
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24 | |||
25 | #ifndef __RV6XX_DPM_H__ |
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26 | #define __RV6XX_DPM_H__ |
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27 | |||
28 | #include "r600_dpm.h" |
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29 | |||
30 | /* Represents a single SCLK step. */ |
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31 | struct rv6xx_sclk_stepping |
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32 | { |
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33 | u32 vco_frequency; |
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34 | u32 post_divider; |
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35 | }; |
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36 | |||
37 | struct rv6xx_pm_hw_state { |
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38 | u32 sclks[R600_PM_NUMBER_OF_ACTIVITY_LEVELS]; |
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39 | u32 mclks[R600_PM_NUMBER_OF_MCLKS]; |
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40 | u16 vddc[R600_PM_NUMBER_OF_VOLTAGE_LEVELS]; |
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41 | bool backbias[R600_PM_NUMBER_OF_VOLTAGE_LEVELS]; |
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42 | bool pcie_gen2[R600_PM_NUMBER_OF_ACTIVITY_LEVELS]; |
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43 | u8 high_sclk_index; |
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44 | u8 medium_sclk_index; |
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45 | u8 low_sclk_index; |
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46 | u8 high_mclk_index; |
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47 | u8 medium_mclk_index; |
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48 | u8 low_mclk_index; |
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49 | u8 high_vddc_index; |
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50 | u8 medium_vddc_index; |
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51 | u8 low_vddc_index; |
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52 | u8 rp[R600_PM_NUMBER_OF_ACTIVITY_LEVELS]; |
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53 | u8 lp[R600_PM_NUMBER_OF_ACTIVITY_LEVELS]; |
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54 | }; |
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55 | |||
56 | struct rv6xx_power_info { |
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57 | /* flags */ |
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58 | bool voltage_control; |
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59 | bool sclk_ss; |
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60 | bool mclk_ss; |
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61 | bool dynamic_ss; |
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62 | bool dynamic_pcie_gen2; |
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63 | bool thermal_protection; |
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64 | bool display_gap; |
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65 | bool gfx_clock_gating; |
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66 | /* clk values */ |
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67 | u32 fb_div_scale; |
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68 | u32 spll_ref_div; |
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69 | u32 mpll_ref_div; |
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70 | u32 bsu; |
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71 | u32 bsp; |
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72 | /* */ |
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73 | u32 active_auto_throttle_sources; |
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74 | /* current power state */ |
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75 | u32 restricted_levels; |
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76 | struct rv6xx_pm_hw_state hw; |
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77 | }; |
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78 | |||
79 | struct rv6xx_pl { |
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80 | u32 sclk; |
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81 | u32 mclk; |
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82 | u16 vddc; |
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83 | u32 flags; |
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84 | }; |
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85 | |||
86 | struct rv6xx_ps { |
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87 | struct rv6xx_pl high; |
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88 | struct rv6xx_pl medium; |
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89 | struct rv6xx_pl low; |
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90 | }; |
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91 | |||
92 | #define RV6XX_DEFAULT_VCLK_FREQ 40000 /* 10 khz */ |
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93 | #define RV6XX_DEFAULT_DCLK_FREQ 30000 /* 10 khz */ |
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94 | |||
95 | #endif |