WebSVN – Kolibri OS – Blame – /drivers/video/drm/radeon/rv6xx_dpm.c

Rev	Author	Line No.	Line
5078	serge	1	/*
		2	* Copyright 2011 Advanced Micro Devices, Inc.
		3	*
		4	* Permission is hereby granted, free of charge, to any person obtaining a
		5	* copy of this software and associated documentation files (the "Software"),
		6	* to deal in the Software without restriction, including without limitation
		7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		8	* and/or sell copies of the Software, and to permit persons to whom the
		9	* Software is furnished to do so, subject to the following conditions:
		10	*
		11	* The above copyright notice and this permission notice shall be included in
		12	* all copies or substantial portions of the Software.
		13	*
		14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
		18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
		19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
		20	* OTHER DEALINGS IN THE SOFTWARE.
		21	*
		22	* Authors: Alex Deucher
		23	*/
		24
		25	#include "drmP.h"
		26	#include "radeon.h"
		27	#include "rv6xxd.h"
		28	#include "r600_dpm.h"
		29	#include "rv6xx_dpm.h"
		30	#include "atom.h"
		31	#include
		32
		33	static u32 rv6xx_scale_count_given_unit(struct radeon_device *rdev,
		34	u32 unscaled_count, u32 unit);
		35
		36	static struct rv6xx_ps rv6xx_get_ps(struct radeon_ps rps)
		37	{
		38	struct rv6xx_ps *ps = rps->ps_priv;
		39
		40	return ps;
		41	}
		42
		43	static struct rv6xx_power_info rv6xx_get_pi(struct radeon_device rdev)
		44	{
		45	struct rv6xx_power_info *pi = rdev->pm.dpm.priv;
		46
		47	return pi;
		48	}
		49
		50	static void rv6xx_force_pcie_gen1(struct radeon_device *rdev)
		51	{
		52	u32 tmp;
		53	int i;
		54
		55	tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
		56	tmp &= LC_GEN2_EN;
		57	WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);
		58
		59	tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
		60	tmp \|= LC_INITIATE_LINK_SPEED_CHANGE;
		61	WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);
		62
		63	for (i = 0; i < rdev->usec_timeout; i++) {
		64	if (!(RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE))
		65	break;
		66	udelay(1);
		67	}
		68
		69	tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
		70	tmp &= ~LC_INITIATE_LINK_SPEED_CHANGE;
		71	WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);
		72	}
		73
		74	static void rv6xx_enable_pcie_gen2_support(struct radeon_device *rdev)
		75	{
		76	u32 tmp;
		77
		78	tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
		79
		80	if ((tmp & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
		81	(tmp & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
		82	tmp \|= LC_GEN2_EN;
		83	WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);
		84	}
		85	}
		86
		87	static void rv6xx_enable_bif_dynamic_pcie_gen2(struct radeon_device *rdev,
		88	bool enable)
		89	{
		90	u32 tmp;
		91
		92	tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & ~LC_HW_VOLTAGE_IF_CONTROL_MASK;
		93	if (enable)
		94	tmp \|= LC_HW_VOLTAGE_IF_CONTROL(1);
		95	else
		96	tmp \|= LC_HW_VOLTAGE_IF_CONTROL(0);
		97	WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);
		98	}
		99
		100	static void rv6xx_enable_l0s(struct radeon_device *rdev)
		101	{
		102	u32 tmp;
		103
		104	tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL) & ~LC_L0S_INACTIVITY_MASK;
		105	tmp \|= LC_L0S_INACTIVITY(3);
		106	WREG32_PCIE_PORT(PCIE_LC_CNTL, tmp);
		107	}
		108
		109	static void rv6xx_enable_l1(struct radeon_device *rdev)
		110	{
		111	u32 tmp;
		112
		113	tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL);
		114	tmp &= ~LC_L1_INACTIVITY_MASK;
		115	tmp \|= LC_L1_INACTIVITY(4);
		116	tmp &= ~LC_PMI_TO_L1_DIS;
		117	tmp &= ~LC_ASPM_TO_L1_DIS;
		118	WREG32_PCIE_PORT(PCIE_LC_CNTL, tmp);
		119	}
		120
		121	static void rv6xx_enable_pll_sleep_in_l1(struct radeon_device *rdev)
		122	{
		123	u32 tmp;
		124
		125	tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL) & ~LC_L1_INACTIVITY_MASK;
		126	tmp \|= LC_L1_INACTIVITY(8);
		127	WREG32_PCIE_PORT(PCIE_LC_CNTL, tmp);
		128
		129	/* NOTE, this is a PCIE indirect reg, not PCIE PORT */
		130	tmp = RREG32_PCIE(PCIE_P_CNTL);
		131	tmp \|= P_PLL_PWRDN_IN_L1L23;
		132	tmp &= ~P_PLL_BUF_PDNB;
		133	tmp &= ~P_PLL_PDNB;
		134	tmp \|= P_ALLOW_PRX_FRONTEND_SHUTOFF;
		135	WREG32_PCIE(PCIE_P_CNTL, tmp);
		136	}
		137
		138	static int rv6xx_convert_clock_to_stepping(struct radeon_device *rdev,
		139	u32 clock, struct rv6xx_sclk_stepping *step)
		140	{
		141	int ret;
		142	struct atom_clock_dividers dividers;
		143
		144	ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
		145	clock, false, ÷rs);
		146	if (ret)
		147	return ret;
		148
		149	if (dividers.enable_post_div)
		150	step->post_divider = 2 + (dividers.post_div & 0xF) + (dividers.post_div >> 4);
		151	else
		152	step->post_divider = 1;
		153
		154	step->vco_frequency = clock * step->post_divider;
		155
		156	return 0;
		157	}
		158
		159	static void rv6xx_output_stepping(struct radeon_device *rdev,
		160	u32 step_index, struct rv6xx_sclk_stepping *step)
		161	{
		162	struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
		163	u32 ref_clk = rdev->clock.spll.reference_freq;
		164	u32 fb_divider;
		165	u32 spll_step_count = rv6xx_scale_count_given_unit(rdev,
		166	R600_SPLLSTEPTIME_DFLT *
		167	pi->spll_ref_div,
		168	R600_SPLLSTEPUNIT_DFLT);
		169
		170	r600_engine_clock_entry_enable(rdev, step_index, true);
		171	r600_engine_clock_entry_enable_pulse_skipping(rdev, step_index, false);
		172
		173	if (step->post_divider == 1)
		174	r600_engine_clock_entry_enable_post_divider(rdev, step_index, false);
		175	else {
		176	u32 lo_len = (step->post_divider - 2) / 2;
		177	u32 hi_len = step->post_divider - 2 - lo_len;
		178
		179	r600_engine_clock_entry_enable_post_divider(rdev, step_index, true);
		180	r600_engine_clock_entry_set_post_divider(rdev, step_index, (hi_len << 4) \| lo_len);
		181	}
		182
		183	fb_divider = ((step->vco_frequency * pi->spll_ref_div) / ref_clk) >>
		184	pi->fb_div_scale;
		185
		186	r600_engine_clock_entry_set_reference_divider(rdev, step_index,
		187	pi->spll_ref_div - 1);
		188	r600_engine_clock_entry_set_feedback_divider(rdev, step_index, fb_divider);
		189	r600_engine_clock_entry_set_step_time(rdev, step_index, spll_step_count);
		190
		191	}
		192
		193	static struct rv6xx_sclk_stepping rv6xx_next_vco_step(struct radeon_device *rdev,
		194	struct rv6xx_sclk_stepping *cur,
		195	bool increasing_vco, u32 step_size)
		196	{
		197	struct rv6xx_sclk_stepping next;
		198
		199	next.post_divider = cur->post_divider;
		200
		201	if (increasing_vco)
		202	next.vco_frequency = (cur->vco_frequency * (100 + step_size)) / 100;
		203	else
		204	next.vco_frequency = (cur->vco_frequency * 100 + 99 + step_size) / (100 + step_size);
		205
		206	return next;
		207	}
		208
		209	static bool rv6xx_can_step_post_div(struct radeon_device *rdev,
		210	struct rv6xx_sclk_stepping *cur,
		211	struct rv6xx_sclk_stepping *target)
		212	{
		213	return (cur->post_divider > target->post_divider) &&
		214	((cur->vco_frequency * target->post_divider) <=
		215	(target->vco_frequency * (cur->post_divider - 1)));
		216	}
		217
		218	static struct rv6xx_sclk_stepping rv6xx_next_post_div_step(struct radeon_device *rdev,
		219	struct rv6xx_sclk_stepping *cur,
		220	struct rv6xx_sclk_stepping *target)
		221	{
		222	struct rv6xx_sclk_stepping next = *cur;
		223
		224	while (rv6xx_can_step_post_div(rdev, &next, target))
		225	next.post_divider--;
		226
		227	return next;
		228	}
		229
		230	static bool rv6xx_reached_stepping_target(struct radeon_device *rdev,
		231	struct rv6xx_sclk_stepping *cur,
		232	struct rv6xx_sclk_stepping *target,
		233	bool increasing_vco)
		234	{
		235	return (increasing_vco && (cur->vco_frequency >= target->vco_frequency)) \|\|
		236	(!increasing_vco && (cur->vco_frequency <= target->vco_frequency));
		237	}
		238
		239	static void rv6xx_generate_steps(struct radeon_device *rdev,
		240	u32 low, u32 high,
		241	u32 start_index, u8 *end_index)
		242	{
		243	struct rv6xx_sclk_stepping cur;
		244	struct rv6xx_sclk_stepping target;
		245	bool increasing_vco;
		246	u32 step_index = start_index;
		247
		248	rv6xx_convert_clock_to_stepping(rdev, low, &cur);
		249	rv6xx_convert_clock_to_stepping(rdev, high, &target);
		250
		251	rv6xx_output_stepping(rdev, step_index++, &cur);
		252
		253	increasing_vco = (target.vco_frequency >= cur.vco_frequency);
		254
		255	if (target.post_divider > cur.post_divider)
		256	cur.post_divider = target.post_divider;
		257
		258	while (1) {
		259	struct rv6xx_sclk_stepping next;
		260
		261	if (rv6xx_can_step_post_div(rdev, &cur, &target))
		262	next = rv6xx_next_post_div_step(rdev, &cur, &target);
		263	else
		264	next = rv6xx_next_vco_step(rdev, &cur, increasing_vco, R600_VCOSTEPPCT_DFLT);
		265
		266	if (rv6xx_reached_stepping_target(rdev, &next, &target, increasing_vco)) {
		267	struct rv6xx_sclk_stepping tiny =
		268	rv6xx_next_vco_step(rdev, &target, !increasing_vco, R600_ENDINGVCOSTEPPCT_DFLT);
		269	tiny.post_divider = next.post_divider;
		270
		271	if (!rv6xx_reached_stepping_target(rdev, &tiny, &cur, !increasing_vco))
		272	rv6xx_output_stepping(rdev, step_index++, &tiny);
		273
		274	if ((next.post_divider != target.post_divider) &&
		275	(next.vco_frequency != target.vco_frequency)) {
		276	struct rv6xx_sclk_stepping final_vco;
		277
		278	final_vco.vco_frequency = target.vco_frequency;
		279	final_vco.post_divider = next.post_divider;
		280
		281	rv6xx_output_stepping(rdev, step_index++, &final_vco);
		282	}
		283
		284	rv6xx_output_stepping(rdev, step_index++, &target);
		285	break;
		286	} else
		287	rv6xx_output_stepping(rdev, step_index++, &next);
		288
		289	cur = next;
		290	}
		291
		292	*end_index = (u8)step_index - 1;
		293
		294	}
		295
		296	static void rv6xx_generate_single_step(struct radeon_device *rdev,
		297	u32 clock, u32 index)
		298	{
		299	struct rv6xx_sclk_stepping step;
		300
		301	rv6xx_convert_clock_to_stepping(rdev, clock, &step);
		302	rv6xx_output_stepping(rdev, index, &step);
		303	}
		304
		305	static void rv6xx_invalidate_intermediate_steps_range(struct radeon_device *rdev,
		306	u32 start_index, u32 end_index)
		307	{
		308	u32 step_index;
		309
		310	for (step_index = start_index + 1; step_index < end_index; step_index++)
		311	r600_engine_clock_entry_enable(rdev, step_index, false);
		312	}
		313
		314	static void rv6xx_set_engine_spread_spectrum_clk_s(struct radeon_device *rdev,
		315	u32 index, u32 clk_s)
		316	{
		317	WREG32_P(CG_SPLL_SPREAD_SPECTRUM_LOW + (index * 4),
		318	CLKS(clk_s), ~CLKS_MASK);
		319	}
		320
		321	static void rv6xx_set_engine_spread_spectrum_clk_v(struct radeon_device *rdev,
		322	u32 index, u32 clk_v)
		323	{
		324	WREG32_P(CG_SPLL_SPREAD_SPECTRUM_LOW + (index * 4),
		325	CLKV(clk_v), ~CLKV_MASK);
		326	}
		327
		328	static void rv6xx_enable_engine_spread_spectrum(struct radeon_device *rdev,
		329	u32 index, bool enable)
		330	{
		331	if (enable)
		332	WREG32_P(CG_SPLL_SPREAD_SPECTRUM_LOW + (index * 4),
		333	SSEN, ~SSEN);
		334	else
		335	WREG32_P(CG_SPLL_SPREAD_SPECTRUM_LOW + (index * 4),
		336	0, ~SSEN);
		337	}
		338
		339	static void rv6xx_set_memory_spread_spectrum_clk_s(struct radeon_device *rdev,
		340	u32 clk_s)
		341	{
		342	WREG32_P(CG_MPLL_SPREAD_SPECTRUM, CLKS(clk_s), ~CLKS_MASK);
		343	}
		344
		345	static void rv6xx_set_memory_spread_spectrum_clk_v(struct radeon_device *rdev,
		346	u32 clk_v)
		347	{
		348	WREG32_P(CG_MPLL_SPREAD_SPECTRUM, CLKV(clk_v), ~CLKV_MASK);
		349	}
		350
		351	static void rv6xx_enable_memory_spread_spectrum(struct radeon_device *rdev,
		352	bool enable)
		353	{
		354	if (enable)
		355	WREG32_P(CG_MPLL_SPREAD_SPECTRUM, SSEN, ~SSEN);
		356	else
		357	WREG32_P(CG_MPLL_SPREAD_SPECTRUM, 0, ~SSEN);
		358	}
		359
		360	static void rv6xx_enable_dynamic_spread_spectrum(struct radeon_device *rdev,
		361	bool enable)
		362	{
		363	if (enable)
		364	WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN);
		365	else
		366	WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN);
		367	}
		368
		369	static void rv6xx_memory_clock_entry_enable_post_divider(struct radeon_device *rdev,
		370	u32 index, bool enable)
		371	{
		372	if (enable)
		373	WREG32_P(MPLL_FREQ_LEVEL_0 + (index * 4),
		374	LEVEL0_MPLL_DIV_EN, ~LEVEL0_MPLL_DIV_EN);
		375	else
		376	WREG32_P(MPLL_FREQ_LEVEL_0 + (index * 4), 0, ~LEVEL0_MPLL_DIV_EN);
		377	}
		378
		379	static void rv6xx_memory_clock_entry_set_post_divider(struct radeon_device *rdev,
		380	u32 index, u32 divider)
		381	{
		382	WREG32_P(MPLL_FREQ_LEVEL_0 + (index * 4),
		383	LEVEL0_MPLL_POST_DIV(divider), ~LEVEL0_MPLL_POST_DIV_MASK);
		384	}
		385
		386	static void rv6xx_memory_clock_entry_set_feedback_divider(struct radeon_device *rdev,
		387	u32 index, u32 divider)
		388	{
		389	WREG32_P(MPLL_FREQ_LEVEL_0 + (index * 4), LEVEL0_MPLL_FB_DIV(divider),
		390	~LEVEL0_MPLL_FB_DIV_MASK);
		391	}
		392
		393	static void rv6xx_memory_clock_entry_set_reference_divider(struct radeon_device *rdev,
		394	u32 index, u32 divider)
		395	{
		396	WREG32_P(MPLL_FREQ_LEVEL_0 + (index * 4),
		397	LEVEL0_MPLL_REF_DIV(divider), ~LEVEL0_MPLL_REF_DIV_MASK);
		398	}
		399
		400	static void rv6xx_vid_response_set_brt(struct radeon_device *rdev, u32 rt)
		401	{
		402	WREG32_P(VID_RT, BRT(rt), ~BRT_MASK);
		403	}
		404
		405	static void rv6xx_enable_engine_feedback_and_reference_sync(struct radeon_device *rdev)
		406	{
		407	WREG32_P(SPLL_CNTL_MODE, SPLL_DIV_SYNC, ~SPLL_DIV_SYNC);
		408	}
		409
		410	static u32 rv6xx_clocks_per_unit(u32 unit)
		411	{
		412	u32 tmp = 1 << (2 * unit);
		413
		414	return tmp;
		415	}
		416
		417	static u32 rv6xx_scale_count_given_unit(struct radeon_device *rdev,
		418	u32 unscaled_count, u32 unit)
		419	{
		420	u32 count_per_unit = rv6xx_clocks_per_unit(unit);
		421
		422	return (unscaled_count + count_per_unit - 1) / count_per_unit;
		423	}
		424
		425	static u32 rv6xx_compute_count_for_delay(struct radeon_device *rdev,
		426	u32 delay_us, u32 unit)
		427	{
		428	u32 ref_clk = rdev->clock.spll.reference_freq;
		429
		430	return rv6xx_scale_count_given_unit(rdev, delay_us * (ref_clk / 100), unit);
		431	}
		432
		433	static void rv6xx_calculate_engine_speed_stepping_parameters(struct radeon_device *rdev,
		434	struct rv6xx_ps *state)
		435	{
		436	struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
		437
		438	pi->hw.sclks[R600_POWER_LEVEL_LOW] =
		439	state->low.sclk;
		440	pi->hw.sclks[R600_POWER_LEVEL_MEDIUM] =
		441	state->medium.sclk;
		442	pi->hw.sclks[R600_POWER_LEVEL_HIGH] =
		443	state->high.sclk;
		444
		445	pi->hw.low_sclk_index = R600_POWER_LEVEL_LOW;
		446	pi->hw.medium_sclk_index = R600_POWER_LEVEL_MEDIUM;
		447	pi->hw.high_sclk_index = R600_POWER_LEVEL_HIGH;
		448	}
		449
		450	static void rv6xx_calculate_memory_clock_stepping_parameters(struct radeon_device *rdev,
		451	struct rv6xx_ps *state)
		452	{
		453	struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
		454
		455	pi->hw.mclks[R600_POWER_LEVEL_CTXSW] =
		456	state->high.mclk;
		457	pi->hw.mclks[R600_POWER_LEVEL_HIGH] =
		458	state->high.mclk;
		459	pi->hw.mclks[R600_POWER_LEVEL_MEDIUM] =
		460	state->medium.mclk;
		461	pi->hw.mclks[R600_POWER_LEVEL_LOW] =
		462	state->low.mclk;
		463
		464	pi->hw.high_mclk_index = R600_POWER_LEVEL_HIGH;
		465
		466	if (state->high.mclk == state->medium.mclk)
		467	pi->hw.medium_mclk_index =
		468	pi->hw.high_mclk_index;
		469	else
		470	pi->hw.medium_mclk_index = R600_POWER_LEVEL_MEDIUM;
		471
		472
		473	if (state->medium.mclk == state->low.mclk)
		474	pi->hw.low_mclk_index =
		475	pi->hw.medium_mclk_index;
		476	else
		477	pi->hw.low_mclk_index = R600_POWER_LEVEL_LOW;
		478	}
		479
		480	static void rv6xx_calculate_voltage_stepping_parameters(struct radeon_device *rdev,
		481	struct rv6xx_ps *state)
		482	{
		483	struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
		484
		485	pi->hw.vddc[R600_POWER_LEVEL_CTXSW] = state->high.vddc;
		486	pi->hw.vddc[R600_POWER_LEVEL_HIGH] = state->high.vddc;
		487	pi->hw.vddc[R600_POWER_LEVEL_MEDIUM] = state->medium.vddc;
		488	pi->hw.vddc[R600_POWER_LEVEL_LOW] = state->low.vddc;
		489
		490	pi->hw.backbias[R600_POWER_LEVEL_CTXSW] =
		491	(state->high.flags & ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE) ? true : false;
		492	pi->hw.backbias[R600_POWER_LEVEL_HIGH] =
		493	(state->high.flags & ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE) ? true : false;
		494	pi->hw.backbias[R600_POWER_LEVEL_MEDIUM] =
		495	(state->medium.flags & ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE) ? true : false;
		496	pi->hw.backbias[R600_POWER_LEVEL_LOW] =
		497	(state->low.flags & ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE) ? true : false;
		498
		499	pi->hw.pcie_gen2[R600_POWER_LEVEL_HIGH] =
		500	(state->high.flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) ? true : false;
		501	pi->hw.pcie_gen2[R600_POWER_LEVEL_MEDIUM] =
		502	(state->medium.flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) ? true : false;
		503	pi->hw.pcie_gen2[R600_POWER_LEVEL_LOW] =
		504	(state->low.flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) ? true : false;
		505
		506	pi->hw.high_vddc_index = R600_POWER_LEVEL_HIGH;
		507
		508	if ((state->high.vddc == state->medium.vddc) &&
		509	((state->high.flags & ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE) ==
		510	(state->medium.flags & ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE)))
		511	pi->hw.medium_vddc_index =
		512	pi->hw.high_vddc_index;
		513	else
		514	pi->hw.medium_vddc_index = R600_POWER_LEVEL_MEDIUM;
		515
		516	if ((state->medium.vddc == state->low.vddc) &&
		517	((state->medium.flags & ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE) ==
		518	(state->low.flags & ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE)))
		519	pi->hw.low_vddc_index =
		520	pi->hw.medium_vddc_index;
		521	else
		522	pi->hw.medium_vddc_index = R600_POWER_LEVEL_LOW;
		523	}
		524
		525	static inline u32 rv6xx_calculate_vco_frequency(u32 ref_clock,
		526	struct atom_clock_dividers *dividers,
		527	u32 fb_divider_scale)
		528	{
		529	return ref_clock * ((dividers->fb_div & ~1) << fb_divider_scale) /
		530	(dividers->ref_div + 1);
		531	}
		532
		533	static inline u32 rv6xx_calculate_spread_spectrum_clk_v(u32 vco_freq, u32 ref_freq,
		534	u32 ss_rate, u32 ss_percent,
		535	u32 fb_divider_scale)
		536	{
		537	u32 fb_divider = vco_freq / ref_freq;
		538
		539	return (ss_percent * ss_rate * 4 * (fb_divider * fb_divider) /
		540	(5375 * ((vco_freq * 10) / (4096 >> fb_divider_scale))));
		541	}
		542
		543	static inline u32 rv6xx_calculate_spread_spectrum_clk_s(u32 ss_rate, u32 ref_freq)
		544	{
		545	return (((ref_freq * 10) / (ss_rate * 2)) - 1) / 4;
		546	}
		547
		548	static void rv6xx_program_engine_spread_spectrum(struct radeon_device *rdev,
		549	u32 clock, enum r600_power_level level)
		550	{
		551	u32 ref_clk = rdev->clock.spll.reference_freq;
		552	struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
		553	struct atom_clock_dividers dividers;
		554	struct radeon_atom_ss ss;
		555	u32 vco_freq, clk_v, clk_s;
		556
		557	rv6xx_enable_engine_spread_spectrum(rdev, level, false);
		558
		559	if (clock && pi->sclk_ss) {
		560	if (radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, clock, false, ÷rs) == 0) {
		561	vco_freq = rv6xx_calculate_vco_frequency(ref_clk, ÷rs,
		562	pi->fb_div_scale);
		563
		564	if (radeon_atombios_get_asic_ss_info(rdev, &ss,
		565	ASIC_INTERNAL_ENGINE_SS, vco_freq)) {
		566	clk_v = rv6xx_calculate_spread_spectrum_clk_v(vco_freq,
		567	(ref_clk / (dividers.ref_div + 1)),
		568	ss.rate,
		569	ss.percentage,
		570	pi->fb_div_scale);
		571
		572	clk_s = rv6xx_calculate_spread_spectrum_clk_s(ss.rate,
		573	(ref_clk / (dividers.ref_div + 1)));
		574
		575	rv6xx_set_engine_spread_spectrum_clk_v(rdev, level, clk_v);
		576	rv6xx_set_engine_spread_spectrum_clk_s(rdev, level, clk_s);
		577	rv6xx_enable_engine_spread_spectrum(rdev, level, true);
		578	}
		579	}
		580	}
		581	}
		582
		583	static void rv6xx_program_sclk_spread_spectrum_parameters_except_lowest_entry(struct radeon_device *rdev)
		584	{
		585	struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
		586
		587	rv6xx_program_engine_spread_spectrum(rdev,
		588	pi->hw.sclks[R600_POWER_LEVEL_HIGH],
		589	R600_POWER_LEVEL_HIGH);
		590
		591	rv6xx_program_engine_spread_spectrum(rdev,
		592	pi->hw.sclks[R600_POWER_LEVEL_MEDIUM],
		593	R600_POWER_LEVEL_MEDIUM);
		594
		595	}
		596
		597	static int rv6xx_program_mclk_stepping_entry(struct radeon_device *rdev,
		598	u32 entry, u32 clock)
		599	{
		600	struct atom_clock_dividers dividers;
		601
		602	if (radeon_atom_get_clock_dividers(rdev, COMPUTE_MEMORY_PLL_PARAM, clock, false, ÷rs))
		603	return -EINVAL;
		604
		605
		606	rv6xx_memory_clock_entry_set_reference_divider(rdev, entry, dividers.ref_div);
		607	rv6xx_memory_clock_entry_set_feedback_divider(rdev, entry, dividers.fb_div);
		608	rv6xx_memory_clock_entry_set_post_divider(rdev, entry, dividers.post_div);
		609
		610	if (dividers.enable_post_div)
		611	rv6xx_memory_clock_entry_enable_post_divider(rdev, entry, true);
		612	else
		613	rv6xx_memory_clock_entry_enable_post_divider(rdev, entry, false);
		614
		615	return 0;
		616	}
		617
		618	static void rv6xx_program_mclk_stepping_parameters_except_lowest_entry(struct radeon_device *rdev)
		619	{
		620	struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
		621	int i;
		622
		623	for (i = 1; i < R600_PM_NUMBER_OF_MCLKS; i++) {
		624	if (pi->hw.mclks[i])
		625	rv6xx_program_mclk_stepping_entry(rdev, i,
		626	pi->hw.mclks[i]);
		627	}
		628	}
		629
		630	static void rv6xx_find_memory_clock_with_highest_vco(struct radeon_device *rdev,
		631	u32 requested_memory_clock,
		632	u32 ref_clk,
		633	struct atom_clock_dividers *dividers,
		634	u32 *vco_freq)
		635	{
		636	struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
		637	struct atom_clock_dividers req_dividers;
		638	u32 vco_freq_temp;
		639
		640	if (radeon_atom_get_clock_dividers(rdev, COMPUTE_MEMORY_PLL_PARAM,
		641	requested_memory_clock, false, &req_dividers) == 0) {
		642	vco_freq_temp = rv6xx_calculate_vco_frequency(ref_clk, &req_dividers,
		643	pi->fb_div_scale);
		644
		645	if (vco_freq_temp > *vco_freq) {
		646	*dividers = req_dividers;
		647	*vco_freq = vco_freq_temp;
		648	}
		649	}
		650	}
		651
		652	static void rv6xx_program_mclk_spread_spectrum_parameters(struct radeon_device *rdev)
		653	{
		654	struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
		655	u32 ref_clk = rdev->clock.mpll.reference_freq;
		656	struct atom_clock_dividers dividers;
		657	struct radeon_atom_ss ss;
		658	u32 vco_freq = 0, clk_v, clk_s;
		659
		660	rv6xx_enable_memory_spread_spectrum(rdev, false);
		661
		662	if (pi->mclk_ss) {
		663	rv6xx_find_memory_clock_with_highest_vco(rdev,
		664	pi->hw.mclks[pi->hw.high_mclk_index],
		665	ref_clk,
		666	÷rs,
		667	&vco_freq);
		668
		669	rv6xx_find_memory_clock_with_highest_vco(rdev,
		670	pi->hw.mclks[pi->hw.medium_mclk_index],
		671	ref_clk,
		672	÷rs,
		673	&vco_freq);
		674
		675	rv6xx_find_memory_clock_with_highest_vco(rdev,
		676	pi->hw.mclks[pi->hw.low_mclk_index],
		677	ref_clk,
		678	÷rs,
		679	&vco_freq);
		680
		681	if (vco_freq) {
		682	if (radeon_atombios_get_asic_ss_info(rdev, &ss,
		683	ASIC_INTERNAL_MEMORY_SS, vco_freq)) {
		684	clk_v = rv6xx_calculate_spread_spectrum_clk_v(vco_freq,
		685	(ref_clk / (dividers.ref_div + 1)),
		686	ss.rate,
		687	ss.percentage,
		688	pi->fb_div_scale);
		689
		690	clk_s = rv6xx_calculate_spread_spectrum_clk_s(ss.rate,
		691	(ref_clk / (dividers.ref_div + 1)));
		692
		693	rv6xx_set_memory_spread_spectrum_clk_v(rdev, clk_v);
		694	rv6xx_set_memory_spread_spectrum_clk_s(rdev, clk_s);
		695	rv6xx_enable_memory_spread_spectrum(rdev, true);
		696	}
		697	}
		698	}
		699	}
		700
		701	static int rv6xx_program_voltage_stepping_entry(struct radeon_device *rdev,
		702	u32 entry, u16 voltage)
		703	{
		704	u32 mask, set_pins;
		705	int ret;
		706
		707	ret = radeon_atom_get_voltage_gpio_settings(rdev, voltage,
		708	SET_VOLTAGE_TYPE_ASIC_VDDC,
		709	&set_pins, &mask);
		710	if (ret)
		711	return ret;
		712
		713	r600_voltage_control_program_voltages(rdev, entry, set_pins);
		714
		715	return 0;
		716	}
		717
		718	static void rv6xx_program_voltage_stepping_parameters_except_lowest_entry(struct radeon_device *rdev)
		719	{
		720	struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
		721	int i;
		722
		723	for (i = 1; i < R600_PM_NUMBER_OF_VOLTAGE_LEVELS; i++)
		724	rv6xx_program_voltage_stepping_entry(rdev, i,
		725	pi->hw.vddc[i]);
		726
		727	}
		728
		729	static void rv6xx_program_backbias_stepping_parameters_except_lowest_entry(struct radeon_device *rdev)
		730	{
		731	struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
		732
		733	if (pi->hw.backbias[1])
		734	WREG32_P(VID_UPPER_GPIO_CNTL, MEDIUM_BACKBIAS_VALUE, ~MEDIUM_BACKBIAS_VALUE);
		735	else
		736	WREG32_P(VID_UPPER_GPIO_CNTL, 0, ~MEDIUM_BACKBIAS_VALUE);
		737
		738	if (pi->hw.backbias[2])
		739	WREG32_P(VID_UPPER_GPIO_CNTL, HIGH_BACKBIAS_VALUE, ~HIGH_BACKBIAS_VALUE);
		740	else
		741	WREG32_P(VID_UPPER_GPIO_CNTL, 0, ~HIGH_BACKBIAS_VALUE);
		742	}
		743
		744	static void rv6xx_program_sclk_spread_spectrum_parameters_lowest_entry(struct radeon_device *rdev)
		745	{
		746	struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
		747
		748	rv6xx_program_engine_spread_spectrum(rdev,
		749	pi->hw.sclks[R600_POWER_LEVEL_LOW],
		750	R600_POWER_LEVEL_LOW);
		751	}
		752
		753	static void rv6xx_program_mclk_stepping_parameters_lowest_entry(struct radeon_device *rdev)
		754	{
		755	struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
		756
		757	if (pi->hw.mclks[0])
		758	rv6xx_program_mclk_stepping_entry(rdev, 0,
		759	pi->hw.mclks[0]);
		760	}
		761
		762	static void rv6xx_program_voltage_stepping_parameters_lowest_entry(struct radeon_device *rdev)
		763	{
		764	struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
		765
		766	rv6xx_program_voltage_stepping_entry(rdev, 0,
		767	pi->hw.vddc[0]);
		768
		769	}
		770
		771	static void rv6xx_program_backbias_stepping_parameters_lowest_entry(struct radeon_device *rdev)
		772	{
		773	struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
		774
		775	if (pi->hw.backbias[0])
		776	WREG32_P(VID_UPPER_GPIO_CNTL, LOW_BACKBIAS_VALUE, ~LOW_BACKBIAS_VALUE);
		777	else
		778	WREG32_P(VID_UPPER_GPIO_CNTL, 0, ~LOW_BACKBIAS_VALUE);
		779	}
		780
		781	static u32 calculate_memory_refresh_rate(struct radeon_device *rdev,
		782	u32 engine_clock)
		783	{
		784	u32 dram_rows, dram_refresh_rate;
		785	u32 tmp;
		786
		787	tmp = (RREG32(RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
		788	dram_rows = 1 << (tmp + 10);
		789	dram_refresh_rate = 1 << ((RREG32(MC_SEQ_RESERVE_M) & 0x3) + 3);
		790
		791	return ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64;
		792	}
		793
		794	static void rv6xx_program_memory_timing_parameters(struct radeon_device *rdev)
		795	{
		796	struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
		797	u32 sqm_ratio;
		798	u32 arb_refresh_rate;
		799	u32 high_clock;
		800
		801	if (pi->hw.sclks[R600_POWER_LEVEL_HIGH] <
		802	(pi->hw.sclks[R600_POWER_LEVEL_LOW] * 0xFF / 0x40))
		803	high_clock = pi->hw.sclks[R600_POWER_LEVEL_HIGH];
		804	else
		805	high_clock =
		806	pi->hw.sclks[R600_POWER_LEVEL_LOW] * 0xFF / 0x40;
		807
		808	radeon_atom_set_engine_dram_timings(rdev, high_clock, 0);
		809
		810	sqm_ratio = (STATE0(64 * high_clock / pi->hw.sclks[R600_POWER_LEVEL_LOW]) \|
		811	STATE1(64 * high_clock / pi->hw.sclks[R600_POWER_LEVEL_MEDIUM]) \|
		812	STATE2(64 * high_clock / pi->hw.sclks[R600_POWER_LEVEL_HIGH]) \|
		813	STATE3(64 * high_clock / pi->hw.sclks[R600_POWER_LEVEL_HIGH]));
		814	WREG32(SQM_RATIO, sqm_ratio);
		815
		816	arb_refresh_rate =
		817	(POWERMODE0(calculate_memory_refresh_rate(rdev,
		818	pi->hw.sclks[R600_POWER_LEVEL_LOW])) \|
		819	POWERMODE1(calculate_memory_refresh_rate(rdev,
		820	pi->hw.sclks[R600_POWER_LEVEL_MEDIUM])) \|
		821	POWERMODE2(calculate_memory_refresh_rate(rdev,
		822	pi->hw.sclks[R600_POWER_LEVEL_HIGH])) \|
		823	POWERMODE3(calculate_memory_refresh_rate(rdev,
		824	pi->hw.sclks[R600_POWER_LEVEL_HIGH])));
		825	WREG32(ARB_RFSH_RATE, arb_refresh_rate);
		826	}
		827
		828	static void rv6xx_program_mpll_timing_parameters(struct radeon_device *rdev)
		829	{
		830	struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
		831
		832	r600_set_mpll_lock_time(rdev, R600_MPLLLOCKTIME_DFLT *
		833	pi->mpll_ref_div);
		834	r600_set_mpll_reset_time(rdev, R600_MPLLRESETTIME_DFLT);
		835	}
		836
		837	static void rv6xx_program_bsp(struct radeon_device *rdev)
		838	{
		839	struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
		840	u32 ref_clk = rdev->clock.spll.reference_freq;
		841
		842	r600_calculate_u_and_p(R600_ASI_DFLT,
		843	ref_clk, 16,
		844	&pi->bsp,
		845	&pi->bsu);
		846
		847	r600_set_bsp(rdev, pi->bsu, pi->bsp);
		848	}
		849
		850	static void rv6xx_program_at(struct radeon_device *rdev)
		851	{
		852	struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
		853
		854	r600_set_at(rdev,
		855	(pi->hw.rp[0] * pi->bsp) / 200,
		856	(pi->hw.rp[1] * pi->bsp) / 200,
		857	(pi->hw.lp[2] * pi->bsp) / 200,
		858	(pi->hw.lp[1] * pi->bsp) / 200);
		859	}
		860
		861	static void rv6xx_program_git(struct radeon_device *rdev)
		862	{
		863	r600_set_git(rdev, R600_GICST_DFLT);
		864	}
		865
		866	static void rv6xx_program_tp(struct radeon_device *rdev)
		867	{
		868	int i;
		869
		870	for (i = 0; i < R600_PM_NUMBER_OF_TC; i++)
		871	r600_set_tc(rdev, i, r600_utc[i], r600_dtc[i]);
		872
		873	r600_select_td(rdev, R600_TD_DFLT);
		874	}
		875
		876	static void rv6xx_program_vc(struct radeon_device *rdev)
		877	{
		878	r600_set_vrc(rdev, R600_VRC_DFLT);
		879	}
		880
		881	static void rv6xx_clear_vc(struct radeon_device *rdev)
		882	{
		883	r600_set_vrc(rdev, 0);
		884	}
		885
		886	static void rv6xx_program_tpp(struct radeon_device *rdev)
		887	{
		888	r600_set_tpu(rdev, R600_TPU_DFLT);
		889	r600_set_tpc(rdev, R600_TPC_DFLT);
		890	}
		891
		892	static void rv6xx_program_sstp(struct radeon_device *rdev)
		893	{
		894	r600_set_sstu(rdev, R600_SSTU_DFLT);
		895	r600_set_sst(rdev, R600_SST_DFLT);
		896	}
		897
		898	static void rv6xx_program_fcp(struct radeon_device *rdev)
		899	{
		900	r600_set_fctu(rdev, R600_FCTU_DFLT);
		901	r600_set_fct(rdev, R600_FCT_DFLT);
		902	}
		903
		904	static void rv6xx_program_vddc3d_parameters(struct radeon_device *rdev)
		905	{
		906	r600_set_vddc3d_oorsu(rdev, R600_VDDC3DOORSU_DFLT);
		907	r600_set_vddc3d_oorphc(rdev, R600_VDDC3DOORPHC_DFLT);
		908	r600_set_vddc3d_oorsdc(rdev, R600_VDDC3DOORSDC_DFLT);
		909	r600_set_ctxcgtt3d_rphc(rdev, R600_CTXCGTT3DRPHC_DFLT);
		910	r600_set_ctxcgtt3d_rsdc(rdev, R600_CTXCGTT3DRSDC_DFLT);
		911	}
		912
		913	static void rv6xx_program_voltage_timing_parameters(struct radeon_device *rdev)
		914	{
		915	u32 rt;
		916
		917	r600_vid_rt_set_vru(rdev, R600_VRU_DFLT);
		918
		919	r600_vid_rt_set_vrt(rdev,
		920	rv6xx_compute_count_for_delay(rdev,
		921	rdev->pm.dpm.voltage_response_time,
		922	R600_VRU_DFLT));
		923
		924	rt = rv6xx_compute_count_for_delay(rdev,
		925	rdev->pm.dpm.backbias_response_time,
		926	R600_VRU_DFLT);
		927
		928	rv6xx_vid_response_set_brt(rdev, (rt + 0x1F) >> 5);
		929	}
		930
		931	static void rv6xx_program_engine_speed_parameters(struct radeon_device *rdev)
		932	{
		933	r600_vid_rt_set_ssu(rdev, R600_SPLLSTEPUNIT_DFLT);
		934	rv6xx_enable_engine_feedback_and_reference_sync(rdev);
		935	}
		936
		937	static u64 rv6xx_get_master_voltage_mask(struct radeon_device *rdev)
		938	{
		939	struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
		940	u64 master_mask = 0;
		941	int i;
		942
		943	for (i = 0; i < R600_PM_NUMBER_OF_VOLTAGE_LEVELS; i++) {
		944	u32 tmp_mask, tmp_set_pins;
		945	int ret;
		946
		947	ret = radeon_atom_get_voltage_gpio_settings(rdev,
		948	pi->hw.vddc[i],
		949	SET_VOLTAGE_TYPE_ASIC_VDDC,
		950	&tmp_set_pins, &tmp_mask);
		951
		952	if (ret == 0)
		953	master_mask \|= tmp_mask;
		954	}
		955
		956	return master_mask;
		957	}
		958
		959	static void rv6xx_program_voltage_gpio_pins(struct radeon_device *rdev)
		960	{
		961	r600_voltage_control_enable_pins(rdev,
		962	rv6xx_get_master_voltage_mask(rdev));
		963	}
		964
		965	static void rv6xx_enable_static_voltage_control(struct radeon_device *rdev,
		966	struct radeon_ps *new_ps,
		967	bool enable)
		968	{
		969	struct rv6xx_ps *new_state = rv6xx_get_ps(new_ps);
		970
		971	if (enable)
		972	radeon_atom_set_voltage(rdev,
		973	new_state->low.vddc,
		974	SET_VOLTAGE_TYPE_ASIC_VDDC);
		975	else
		976	r600_voltage_control_deactivate_static_control(rdev,
		977	rv6xx_get_master_voltage_mask(rdev));
		978	}
		979
		980	static void rv6xx_enable_display_gap(struct radeon_device *rdev, bool enable)
		981	{
		982	if (enable) {
		983	u32 tmp = (DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM) \|
		984	DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM) \|
		985	DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE) \|
		986	DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE) \|
		987	VBI_TIMER_COUNT(0x3FFF) \|
		988	VBI_TIMER_UNIT(7));
		989	WREG32(CG_DISPLAY_GAP_CNTL, tmp);
		990
		991	WREG32_P(MCLK_PWRMGT_CNTL, USE_DISPLAY_GAP, ~USE_DISPLAY_GAP);
		992	} else
		993	WREG32_P(MCLK_PWRMGT_CNTL, 0, ~USE_DISPLAY_GAP);
		994	}
		995
		996	static void rv6xx_program_power_level_enter_state(struct radeon_device *rdev)
		997	{
		998	r600_power_level_set_enter_index(rdev, R600_POWER_LEVEL_MEDIUM);
		999	}
		1000
		1001	static void rv6xx_calculate_t(u32 l_f, u32 h_f, int h,
		1002	int d_l, int d_r, u8 l, u8 r)
		1003	{
		1004	int a_n, a_d, h_r, l_r;
		1005
		1006	h_r = d_l;
		1007	l_r = 100 - d_r;
		1008
		1009	a_n = (int)h_f * d_l + (int)l_f * (h - d_r);
		1010	a_d = (int)l_f * l_r + (int)h_f * h_r;
		1011
		1012	if (a_d != 0) {
		1013	l = d_l - h_r a_n / a_d;
		1014	r = d_r + l_r a_n / a_d;
		1015	}
		1016	}
		1017
		1018	static void rv6xx_calculate_ap(struct radeon_device *rdev,
		1019	struct rv6xx_ps *state)
		1020	{
		1021	struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
		1022
		1023	pi->hw.lp[0] = 0;
		1024	pi->hw.rp[R600_PM_NUMBER_OF_ACTIVITY_LEVELS - 1]
		1025	= 100;
		1026
		1027	rv6xx_calculate_t(state->low.sclk,
		1028	state->medium.sclk,
		1029	R600_AH_DFLT,
		1030	R600_LMP_DFLT,
		1031	R600_RLP_DFLT,
		1032	&pi->hw.lp[1],
		1033	&pi->hw.rp[0]);
		1034
		1035	rv6xx_calculate_t(state->medium.sclk,
		1036	state->high.sclk,
		1037	R600_AH_DFLT,
		1038	R600_LHP_DFLT,
		1039	R600_RMP_DFLT,
		1040	&pi->hw.lp[2],
		1041	&pi->hw.rp[1]);
		1042
		1043	}
		1044
		1045	static void rv6xx_calculate_stepping_parameters(struct radeon_device *rdev,
		1046	struct radeon_ps *new_ps)
		1047	{
		1048	struct rv6xx_ps *new_state = rv6xx_get_ps(new_ps);
		1049
		1050	rv6xx_calculate_engine_speed_stepping_parameters(rdev, new_state);
		1051	rv6xx_calculate_memory_clock_stepping_parameters(rdev, new_state);
		1052	rv6xx_calculate_voltage_stepping_parameters(rdev, new_state);
		1053	rv6xx_calculate_ap(rdev, new_state);
		1054	}
		1055
		1056	static void rv6xx_program_stepping_parameters_except_lowest_entry(struct radeon_device *rdev)
		1057	{
		1058	struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
		1059
		1060	rv6xx_program_mclk_stepping_parameters_except_lowest_entry(rdev);
		1061	if (pi->voltage_control)
		1062	rv6xx_program_voltage_stepping_parameters_except_lowest_entry(rdev);
		1063	rv6xx_program_backbias_stepping_parameters_except_lowest_entry(rdev);
		1064	rv6xx_program_sclk_spread_spectrum_parameters_except_lowest_entry(rdev);
		1065	rv6xx_program_mclk_spread_spectrum_parameters(rdev);
		1066	rv6xx_program_memory_timing_parameters(rdev);
		1067	}
		1068
		1069	static void rv6xx_program_stepping_parameters_lowest_entry(struct radeon_device *rdev)
		1070	{
		1071	struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
		1072
		1073	rv6xx_program_mclk_stepping_parameters_lowest_entry(rdev);
		1074	if (pi->voltage_control)
		1075	rv6xx_program_voltage_stepping_parameters_lowest_entry(rdev);
		1076	rv6xx_program_backbias_stepping_parameters_lowest_entry(rdev);
		1077	rv6xx_program_sclk_spread_spectrum_parameters_lowest_entry(rdev);
		1078	}
		1079
		1080	static void rv6xx_program_power_level_low(struct radeon_device *rdev)
		1081	{
		1082	struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
		1083
		1084	r600_power_level_set_voltage_index(rdev, R600_POWER_LEVEL_LOW,
		1085	pi->hw.low_vddc_index);
		1086	r600_power_level_set_mem_clock_index(rdev, R600_POWER_LEVEL_LOW,
		1087	pi->hw.low_mclk_index);
		1088	r600_power_level_set_eng_clock_index(rdev, R600_POWER_LEVEL_LOW,
		1089	pi->hw.low_sclk_index);
		1090	r600_power_level_set_watermark_id(rdev, R600_POWER_LEVEL_LOW,
		1091	R600_DISPLAY_WATERMARK_LOW);
		1092	r600_power_level_set_pcie_gen2(rdev, R600_POWER_LEVEL_LOW,
		1093	pi->hw.pcie_gen2[R600_POWER_LEVEL_LOW]);
		1094	}
		1095
		1096	static void rv6xx_program_power_level_low_to_lowest_state(struct radeon_device *rdev)
		1097	{
		1098	struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
		1099
		1100	r600_power_level_set_voltage_index(rdev, R600_POWER_LEVEL_LOW, 0);
		1101	r600_power_level_set_mem_clock_index(rdev, R600_POWER_LEVEL_LOW, 0);
		1102	r600_power_level_set_eng_clock_index(rdev, R600_POWER_LEVEL_LOW, 0);
		1103
		1104	r600_power_level_set_watermark_id(rdev, R600_POWER_LEVEL_LOW,
		1105	R600_DISPLAY_WATERMARK_LOW);
		1106
		1107	r600_power_level_set_pcie_gen2(rdev, R600_POWER_LEVEL_LOW,
		1108	pi->hw.pcie_gen2[R600_POWER_LEVEL_LOW]);
		1109
		1110	}
		1111
		1112	static void rv6xx_program_power_level_medium(struct radeon_device *rdev)
		1113	{
		1114	struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
		1115
		1116	r600_power_level_set_voltage_index(rdev, R600_POWER_LEVEL_MEDIUM,
		1117	pi->hw.medium_vddc_index);
		1118	r600_power_level_set_mem_clock_index(rdev, R600_POWER_LEVEL_MEDIUM,
		1119	pi->hw.medium_mclk_index);
		1120	r600_power_level_set_eng_clock_index(rdev, R600_POWER_LEVEL_MEDIUM,
		1121	pi->hw.medium_sclk_index);
		1122	r600_power_level_set_watermark_id(rdev, R600_POWER_LEVEL_MEDIUM,
		1123	R600_DISPLAY_WATERMARK_LOW);
		1124	r600_power_level_set_pcie_gen2(rdev, R600_POWER_LEVEL_MEDIUM,
		1125	pi->hw.pcie_gen2[R600_POWER_LEVEL_MEDIUM]);
		1126	}
		1127
		1128	static void rv6xx_program_power_level_medium_for_transition(struct radeon_device *rdev)
		1129	{
		1130	struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
		1131
		1132	rv6xx_program_mclk_stepping_entry(rdev,
		1133	R600_POWER_LEVEL_CTXSW,
		1134	pi->hw.mclks[pi->hw.low_mclk_index]);
		1135
		1136	r600_power_level_set_voltage_index(rdev, R600_POWER_LEVEL_MEDIUM, 1);
		1137
		1138	r600_power_level_set_mem_clock_index(rdev, R600_POWER_LEVEL_MEDIUM,
		1139	R600_POWER_LEVEL_CTXSW);
		1140	r600_power_level_set_eng_clock_index(rdev, R600_POWER_LEVEL_MEDIUM,
		1141	pi->hw.medium_sclk_index);
		1142
		1143	r600_power_level_set_watermark_id(rdev, R600_POWER_LEVEL_MEDIUM,
		1144	R600_DISPLAY_WATERMARK_LOW);
		1145
		1146	rv6xx_enable_engine_spread_spectrum(rdev, R600_POWER_LEVEL_MEDIUM, false);
		1147
		1148	r600_power_level_set_pcie_gen2(rdev, R600_POWER_LEVEL_MEDIUM,
		1149	pi->hw.pcie_gen2[R600_POWER_LEVEL_LOW]);
		1150	}
		1151
		1152	static void rv6xx_program_power_level_high(struct radeon_device *rdev)
		1153	{
		1154	struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
		1155
		1156	r600_power_level_set_voltage_index(rdev, R600_POWER_LEVEL_HIGH,
		1157	pi->hw.high_vddc_index);
		1158	r600_power_level_set_mem_clock_index(rdev, R600_POWER_LEVEL_HIGH,
		1159	pi->hw.high_mclk_index);
		1160	r600_power_level_set_eng_clock_index(rdev, R600_POWER_LEVEL_HIGH,
		1161	pi->hw.high_sclk_index);
		1162
		1163	r600_power_level_set_watermark_id(rdev, R600_POWER_LEVEL_HIGH,
		1164	R600_DISPLAY_WATERMARK_HIGH);
		1165
		1166	r600_power_level_set_pcie_gen2(rdev, R600_POWER_LEVEL_HIGH,
		1167	pi->hw.pcie_gen2[R600_POWER_LEVEL_HIGH]);
		1168	}
		1169
		1170	static void rv6xx_enable_backbias(struct radeon_device *rdev, bool enable)
		1171	{
		1172	if (enable)
		1173	WREG32_P(GENERAL_PWRMGT, BACKBIAS_PAD_EN \| BACKBIAS_DPM_CNTL,
		1174	~(BACKBIAS_PAD_EN \| BACKBIAS_DPM_CNTL));
		1175	else
		1176	WREG32_P(GENERAL_PWRMGT, 0,
		1177	~(BACKBIAS_VALUE \| BACKBIAS_PAD_EN \| BACKBIAS_DPM_CNTL));
		1178	}
		1179
		1180	static void rv6xx_program_display_gap(struct radeon_device *rdev)
		1181	{
		1182	u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);
		1183
		1184	tmp &= ~(DISP1_GAP_MCHG_MASK \| DISP2_GAP_MCHG_MASK);
		1185	if (rdev->pm.dpm.new_active_crtcs & 1) {
		1186	tmp \|= DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK);
		1187	tmp \|= DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE);
		1188	} else if (rdev->pm.dpm.new_active_crtcs & 2) {
		1189	tmp \|= DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE);
		1190	tmp \|= DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK);
		1191	} else {
		1192	tmp \|= DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE);
		1193	tmp \|= DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE);
		1194	}
		1195	WREG32(CG_DISPLAY_GAP_CNTL, tmp);
		1196	}
		1197
		1198	static void rv6xx_set_sw_voltage_to_safe(struct radeon_device *rdev,
		1199	struct radeon_ps *new_ps,
		1200	struct radeon_ps *old_ps)
		1201	{
		1202	struct rv6xx_ps *new_state = rv6xx_get_ps(new_ps);
		1203	struct rv6xx_ps *old_state = rv6xx_get_ps(old_ps);
		1204	u16 safe_voltage;
		1205
		1206	safe_voltage = (new_state->low.vddc >= old_state->low.vddc) ?
		1207	new_state->low.vddc : old_state->low.vddc;
		1208
		1209	rv6xx_program_voltage_stepping_entry(rdev, R600_POWER_LEVEL_CTXSW,
		1210	safe_voltage);
		1211
		1212	WREG32_P(GENERAL_PWRMGT, SW_GPIO_INDEX(R600_POWER_LEVEL_CTXSW),
		1213	~SW_GPIO_INDEX_MASK);
		1214	}
		1215
		1216	static void rv6xx_set_sw_voltage_to_low(struct radeon_device *rdev,
		1217	struct radeon_ps *old_ps)
		1218	{
		1219	struct rv6xx_ps *old_state = rv6xx_get_ps(old_ps);
		1220
		1221	rv6xx_program_voltage_stepping_entry(rdev, R600_POWER_LEVEL_CTXSW,
		1222	old_state->low.vddc);
		1223
		1224	WREG32_P(GENERAL_PWRMGT, SW_GPIO_INDEX(R600_POWER_LEVEL_CTXSW),
		1225	~SW_GPIO_INDEX_MASK);
		1226	}
		1227
		1228	static void rv6xx_set_safe_backbias(struct radeon_device *rdev,
		1229	struct radeon_ps *new_ps,
		1230	struct radeon_ps *old_ps)
		1231	{
		1232	struct rv6xx_ps *new_state = rv6xx_get_ps(new_ps);
		1233	struct rv6xx_ps *old_state = rv6xx_get_ps(old_ps);
		1234
		1235	if ((new_state->low.flags & ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE) &&
		1236	(old_state->low.flags & ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE))
		1237	WREG32_P(GENERAL_PWRMGT, BACKBIAS_VALUE, ~BACKBIAS_VALUE);
		1238	else
		1239	WREG32_P(GENERAL_PWRMGT, 0, ~BACKBIAS_VALUE);
		1240	}
		1241
		1242	static void rv6xx_set_safe_pcie_gen2(struct radeon_device *rdev,
		1243	struct radeon_ps *new_ps,
		1244	struct radeon_ps *old_ps)
		1245	{
		1246	struct rv6xx_ps *new_state = rv6xx_get_ps(new_ps);
		1247	struct rv6xx_ps *old_state = rv6xx_get_ps(old_ps);
		1248
		1249	if ((new_state->low.flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) !=
		1250	(old_state->low.flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2))
		1251	rv6xx_force_pcie_gen1(rdev);
		1252	}
		1253
		1254	static void rv6xx_enable_dynamic_voltage_control(struct radeon_device *rdev,
		1255	bool enable)
		1256	{
		1257	if (enable)
		1258	WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN);
		1259	else
		1260	WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN);
		1261	}
		1262
		1263	static void rv6xx_enable_dynamic_backbias_control(struct radeon_device *rdev,
		1264	bool enable)
		1265	{
		1266	if (enable)
		1267	WREG32_P(GENERAL_PWRMGT, BACKBIAS_DPM_CNTL, ~BACKBIAS_DPM_CNTL);
		1268	else
		1269	WREG32_P(GENERAL_PWRMGT, 0, ~BACKBIAS_DPM_CNTL);
		1270	}
		1271
		1272	static int rv6xx_step_sw_voltage(struct radeon_device *rdev,
		1273	u16 initial_voltage,
		1274	u16 target_voltage)
		1275	{
		1276	u16 current_voltage;
		1277	u16 true_target_voltage;
		1278	u16 voltage_step;
		1279	int signed_voltage_step;
		1280
		1281	if ((radeon_atom_get_voltage_step(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
		1282	&voltage_step)) \|\|
		1283	(radeon_atom_round_to_true_voltage(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
		1284	initial_voltage, ¤t_voltage)) \|\|
		1285	(radeon_atom_round_to_true_voltage(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
		1286	target_voltage, &true_target_voltage)))
		1287	return -EINVAL;
		1288
		1289	if (true_target_voltage < current_voltage)
		1290	signed_voltage_step = -(int)voltage_step;
		1291	else
		1292	signed_voltage_step = voltage_step;
		1293
		1294	while (current_voltage != true_target_voltage) {
		1295	current_voltage += signed_voltage_step;
		1296	rv6xx_program_voltage_stepping_entry(rdev, R600_POWER_LEVEL_CTXSW,
		1297	current_voltage);
		1298	msleep((rdev->pm.dpm.voltage_response_time + 999) / 1000);
		1299	}
		1300
		1301	return 0;
		1302	}
		1303
		1304	static int rv6xx_step_voltage_if_increasing(struct radeon_device *rdev,
		1305	struct radeon_ps *new_ps,
		1306	struct radeon_ps *old_ps)
		1307	{
		1308	struct rv6xx_ps *new_state = rv6xx_get_ps(new_ps);
		1309	struct rv6xx_ps *old_state = rv6xx_get_ps(old_ps);
		1310
		1311	if (new_state->low.vddc > old_state->low.vddc)
		1312	return rv6xx_step_sw_voltage(rdev,
		1313	old_state->low.vddc,
		1314	new_state->low.vddc);
		1315
		1316	return 0;
		1317	}
		1318
		1319	static int rv6xx_step_voltage_if_decreasing(struct radeon_device *rdev,
		1320	struct radeon_ps *new_ps,
		1321	struct radeon_ps *old_ps)
		1322	{
		1323	struct rv6xx_ps *new_state = rv6xx_get_ps(new_ps);
		1324	struct rv6xx_ps *old_state = rv6xx_get_ps(old_ps);
		1325
		1326	if (new_state->low.vddc < old_state->low.vddc)
		1327	return rv6xx_step_sw_voltage(rdev,
		1328	old_state->low.vddc,
		1329	new_state->low.vddc);
		1330	else
		1331	return 0;
		1332	}
		1333
		1334	static void rv6xx_enable_high(struct radeon_device *rdev)
		1335	{
		1336	struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
		1337
		1338	if ((pi->restricted_levels < 1) \|\|
		1339	(pi->restricted_levels == 3))
		1340	r600_power_level_enable(rdev, R600_POWER_LEVEL_HIGH, true);
		1341	}
		1342
		1343	static void rv6xx_enable_medium(struct radeon_device *rdev)
		1344	{
		1345	struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
		1346
		1347	if (pi->restricted_levels < 2)
		1348	r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, true);
		1349	}
		1350
		1351	static void rv6xx_set_dpm_event_sources(struct radeon_device *rdev, u32 sources)
		1352	{
		1353	struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
		1354	bool want_thermal_protection;
		1355	enum radeon_dpm_event_src dpm_event_src;
		1356
		1357	switch (sources) {
		1358	case 0:
		1359	default:
		1360	want_thermal_protection = false;
		1361	break;
		1362	case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL):
		1363	want_thermal_protection = true;
		1364	dpm_event_src = RADEON_DPM_EVENT_SRC_DIGITAL;
		1365	break;
		1366
		1367	case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL):
		1368	want_thermal_protection = true;
		1369	dpm_event_src = RADEON_DPM_EVENT_SRC_EXTERNAL;
		1370	break;
		1371
		1372	case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL) \|
		1373	(1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL)):
		1374	want_thermal_protection = true;
		1375	dpm_event_src = RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL;
		1376	break;
		1377	}
		1378
		1379	if (want_thermal_protection) {
		1380	WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK);
		1381	if (pi->thermal_protection)
		1382	WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
		1383	} else {
		1384	WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
		1385	}
		1386	}
		1387
		1388	static void rv6xx_enable_auto_throttle_source(struct radeon_device *rdev,
		1389	enum radeon_dpm_auto_throttle_src source,
		1390	bool enable)
		1391	{
		1392	struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
		1393
		1394	if (enable) {
		1395	if (!(pi->active_auto_throttle_sources & (1 << source))) {
		1396	pi->active_auto_throttle_sources \|= 1 << source;
		1397	rv6xx_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
		1398	}
		1399	} else {
		1400	if (pi->active_auto_throttle_sources & (1 << source)) {
		1401	pi->active_auto_throttle_sources &= ~(1 << source);
		1402	rv6xx_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
		1403	}
		1404	}
		1405	}
		1406
		1407
		1408	static void rv6xx_enable_thermal_protection(struct radeon_device *rdev,
		1409	bool enable)
		1410	{
		1411	struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
		1412
		1413	if (pi->active_auto_throttle_sources)
		1414	r600_enable_thermal_protection(rdev, enable);
		1415	}
		1416
		1417	static void rv6xx_generate_transition_stepping(struct radeon_device *rdev,
		1418	struct radeon_ps *new_ps,
		1419	struct radeon_ps *old_ps)
		1420	{
		1421	struct rv6xx_ps *new_state = rv6xx_get_ps(new_ps);
		1422	struct rv6xx_ps *old_state = rv6xx_get_ps(old_ps);
		1423	struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
		1424
		1425	rv6xx_generate_steps(rdev,
		1426	old_state->low.sclk,
		1427	new_state->low.sclk,
		1428	0, &pi->hw.medium_sclk_index);
		1429	}
		1430
		1431	static void rv6xx_generate_low_step(struct radeon_device *rdev,
		1432	struct radeon_ps *new_ps)
		1433	{
		1434	struct rv6xx_ps *new_state = rv6xx_get_ps(new_ps);
		1435	struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
		1436
		1437	pi->hw.low_sclk_index = 0;
		1438	rv6xx_generate_single_step(rdev,
		1439	new_state->low.sclk,
		1440	0);
		1441	}
		1442
		1443	static void rv6xx_invalidate_intermediate_steps(struct radeon_device *rdev)
		1444	{
		1445	struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
		1446
		1447	rv6xx_invalidate_intermediate_steps_range(rdev, 0,
		1448	pi->hw.medium_sclk_index);
		1449	}
		1450
		1451	static void rv6xx_generate_stepping_table(struct radeon_device *rdev,
		1452	struct radeon_ps *new_ps)
		1453	{
		1454	struct rv6xx_ps *new_state = rv6xx_get_ps(new_ps);
		1455	struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
		1456
		1457	pi->hw.low_sclk_index = 0;
		1458
		1459	rv6xx_generate_steps(rdev,
		1460	new_state->low.sclk,
		1461	new_state->medium.sclk,
		1462	0,
		1463	&pi->hw.medium_sclk_index);
		1464	rv6xx_generate_steps(rdev,
		1465	new_state->medium.sclk,
		1466	new_state->high.sclk,
		1467	pi->hw.medium_sclk_index,
		1468	&pi->hw.high_sclk_index);
		1469	}
		1470
		1471	static void rv6xx_enable_spread_spectrum(struct radeon_device *rdev,
		1472	bool enable)
		1473	{
		1474	if (enable)
		1475	rv6xx_enable_dynamic_spread_spectrum(rdev, true);
		1476	else {
		1477	rv6xx_enable_engine_spread_spectrum(rdev, R600_POWER_LEVEL_LOW, false);
		1478	rv6xx_enable_engine_spread_spectrum(rdev, R600_POWER_LEVEL_MEDIUM, false);
		1479	rv6xx_enable_engine_spread_spectrum(rdev, R600_POWER_LEVEL_HIGH, false);
		1480	rv6xx_enable_dynamic_spread_spectrum(rdev, false);
		1481	rv6xx_enable_memory_spread_spectrum(rdev, false);
		1482	}
		1483	}
		1484
		1485	static void rv6xx_reset_lvtm_data_sync(struct radeon_device *rdev)
		1486	{
		1487	if (ASIC_IS_DCE3(rdev))
		1488	WREG32_P(DCE3_LVTMA_DATA_SYNCHRONIZATION, LVTMA_PFREQCHG, ~LVTMA_PFREQCHG);
		1489	else
		1490	WREG32_P(LVTMA_DATA_SYNCHRONIZATION, LVTMA_PFREQCHG, ~LVTMA_PFREQCHG);
		1491	}
		1492
		1493	static void rv6xx_enable_dynamic_pcie_gen2(struct radeon_device *rdev,
		1494	struct radeon_ps *new_ps,
		1495	bool enable)
		1496	{
		1497	struct rv6xx_ps *new_state = rv6xx_get_ps(new_ps);
		1498
		1499	if (enable) {
		1500	rv6xx_enable_bif_dynamic_pcie_gen2(rdev, true);
		1501	rv6xx_enable_pcie_gen2_support(rdev);
		1502	r600_enable_dynamic_pcie_gen2(rdev, true);
		1503	} else {
		1504	if (!(new_state->low.flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2))
		1505	rv6xx_force_pcie_gen1(rdev);
		1506	rv6xx_enable_bif_dynamic_pcie_gen2(rdev, false);
		1507	r600_enable_dynamic_pcie_gen2(rdev, false);
		1508	}
		1509	}
		1510
		1511	static void rv6xx_set_uvd_clock_before_set_eng_clock(struct radeon_device *rdev,
		1512	struct radeon_ps *new_ps,
		1513	struct radeon_ps *old_ps)
		1514	{
		1515	struct rv6xx_ps *new_state = rv6xx_get_ps(new_ps);
		1516	struct rv6xx_ps *current_state = rv6xx_get_ps(old_ps);
		1517
		1518	if ((new_ps->vclk == old_ps->vclk) &&
		1519	(new_ps->dclk == old_ps->dclk))
		1520	return;
		1521
		1522	if (new_state->high.sclk >= current_state->high.sclk)
		1523	return;
		1524
		1525	radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk);
		1526	}
		1527
		1528	static void rv6xx_set_uvd_clock_after_set_eng_clock(struct radeon_device *rdev,
		1529	struct radeon_ps *new_ps,
		1530	struct radeon_ps *old_ps)
		1531	{
		1532	struct rv6xx_ps *new_state = rv6xx_get_ps(new_ps);
		1533	struct rv6xx_ps *current_state = rv6xx_get_ps(old_ps);
		1534
		1535	if ((new_ps->vclk == old_ps->vclk) &&
		1536	(new_ps->dclk == old_ps->dclk))
		1537	return;
		1538
		1539	if (new_state->high.sclk < current_state->high.sclk)
		1540	return;
		1541
		1542	radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk);
		1543	}
		1544
		1545	int rv6xx_dpm_enable(struct radeon_device *rdev)
		1546	{
		1547	struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
		1548	struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
		1549
		1550	if (r600_dynamicpm_enabled(rdev))
		1551	return -EINVAL;
		1552
		1553	if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_BACKBIAS)
		1554	rv6xx_enable_backbias(rdev, true);
		1555
		1556	if (pi->dynamic_ss)
		1557	rv6xx_enable_spread_spectrum(rdev, true);
		1558
		1559	rv6xx_program_mpll_timing_parameters(rdev);
		1560	rv6xx_program_bsp(rdev);
		1561	rv6xx_program_git(rdev);
		1562	rv6xx_program_tp(rdev);
		1563	rv6xx_program_tpp(rdev);
		1564	rv6xx_program_sstp(rdev);
		1565	rv6xx_program_fcp(rdev);
		1566	rv6xx_program_vddc3d_parameters(rdev);
		1567	rv6xx_program_voltage_timing_parameters(rdev);
		1568	rv6xx_program_engine_speed_parameters(rdev);
		1569
		1570	rv6xx_enable_display_gap(rdev, true);
		1571	if (pi->display_gap == false)
		1572	rv6xx_enable_display_gap(rdev, false);
		1573
		1574	rv6xx_program_power_level_enter_state(rdev);
		1575
		1576	rv6xx_calculate_stepping_parameters(rdev, boot_ps);
		1577
		1578	if (pi->voltage_control)
		1579	rv6xx_program_voltage_gpio_pins(rdev);
		1580
		1581	rv6xx_generate_stepping_table(rdev, boot_ps);
		1582
		1583	rv6xx_program_stepping_parameters_except_lowest_entry(rdev);
		1584	rv6xx_program_stepping_parameters_lowest_entry(rdev);
		1585
		1586	rv6xx_program_power_level_low(rdev);
		1587	rv6xx_program_power_level_medium(rdev);
		1588	rv6xx_program_power_level_high(rdev);
		1589	rv6xx_program_vc(rdev);
		1590	rv6xx_program_at(rdev);
		1591
		1592	r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW, true);
		1593	r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, true);
		1594	r600_power_level_enable(rdev, R600_POWER_LEVEL_HIGH, true);
		1595
		1596	rv6xx_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
		1597
		1598	r600_start_dpm(rdev);
		1599
		1600	if (pi->voltage_control)
		1601	rv6xx_enable_static_voltage_control(rdev, boot_ps, false);
		1602
		1603	if (pi->dynamic_pcie_gen2)
		1604	rv6xx_enable_dynamic_pcie_gen2(rdev, boot_ps, true);
		1605
		1606	if (pi->gfx_clock_gating)
		1607	r600_gfx_clockgating_enable(rdev, true);
		1608
		1609	return 0;
		1610	}
		1611
		1612	void rv6xx_dpm_disable(struct radeon_device *rdev)
		1613	{
		1614	struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
		1615	struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
		1616
		1617	if (!r600_dynamicpm_enabled(rdev))
		1618	return;
		1619
		1620	r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW, true);
		1621	r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, true);
		1622	rv6xx_enable_display_gap(rdev, false);
		1623	rv6xx_clear_vc(rdev);
		1624	r600_set_at(rdev, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF);
		1625
		1626	if (pi->thermal_protection)
		1627	r600_enable_thermal_protection(rdev, false);
		1628
		1629	r600_wait_for_power_level(rdev, R600_POWER_LEVEL_LOW);
		1630	r600_power_level_enable(rdev, R600_POWER_LEVEL_HIGH, false);
		1631	r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, false);
		1632
		1633	if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_BACKBIAS)
		1634	rv6xx_enable_backbias(rdev, false);
		1635
		1636	rv6xx_enable_spread_spectrum(rdev, false);
		1637
		1638	if (pi->voltage_control)
		1639	rv6xx_enable_static_voltage_control(rdev, boot_ps, true);
		1640
		1641	if (pi->dynamic_pcie_gen2)
		1642	rv6xx_enable_dynamic_pcie_gen2(rdev, boot_ps, false);
		1643
		1644	if (rdev->irq.installed &&
		1645	r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
		1646	rdev->irq.dpm_thermal = false;
		1647	radeon_irq_set(rdev);
		1648	}
		1649
		1650	if (pi->gfx_clock_gating)
		1651	r600_gfx_clockgating_enable(rdev, false);
		1652
		1653	r600_stop_dpm(rdev);
		1654	}
		1655
		1656	int rv6xx_dpm_set_power_state(struct radeon_device *rdev)
		1657	{
		1658	struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
		1659	struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps;
		1660	struct radeon_ps *old_ps = rdev->pm.dpm.current_ps;
		1661	int ret;
		1662
		1663	pi->restricted_levels = 0;
		1664
		1665	rv6xx_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps);
		1666
		1667	rv6xx_clear_vc(rdev);
		1668	r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW, true);
		1669	r600_set_at(rdev, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF);
		1670
		1671	if (pi->thermal_protection)
		1672	r600_enable_thermal_protection(rdev, false);
		1673
		1674	r600_wait_for_power_level(rdev, R600_POWER_LEVEL_LOW);
		1675	r600_power_level_enable(rdev, R600_POWER_LEVEL_HIGH, false);
		1676	r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, false);
		1677
		1678	rv6xx_generate_transition_stepping(rdev, new_ps, old_ps);
		1679	rv6xx_program_power_level_medium_for_transition(rdev);
		1680
		1681	if (pi->voltage_control) {
		1682	rv6xx_set_sw_voltage_to_safe(rdev, new_ps, old_ps);
		1683	if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
		1684	rv6xx_set_sw_voltage_to_low(rdev, old_ps);
		1685	}
		1686
		1687	if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_BACKBIAS)
		1688	rv6xx_set_safe_backbias(rdev, new_ps, old_ps);
		1689
		1690	if (pi->dynamic_pcie_gen2)
		1691	rv6xx_set_safe_pcie_gen2(rdev, new_ps, old_ps);
		1692
		1693	if (pi->voltage_control)
		1694	rv6xx_enable_dynamic_voltage_control(rdev, false);
		1695
		1696	if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_BACKBIAS)
		1697	rv6xx_enable_dynamic_backbias_control(rdev, false);
		1698
		1699	if (pi->voltage_control) {
		1700	if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
		1701	rv6xx_step_voltage_if_increasing(rdev, new_ps, old_ps);
		1702	msleep((rdev->pm.dpm.voltage_response_time + 999) / 1000);
		1703	}
		1704
		1705	r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, true);
		1706	r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW, false);
		1707	r600_wait_for_power_level_unequal(rdev, R600_POWER_LEVEL_LOW);
		1708
		1709	rv6xx_generate_low_step(rdev, new_ps);
		1710	rv6xx_invalidate_intermediate_steps(rdev);
		1711	rv6xx_calculate_stepping_parameters(rdev, new_ps);
		1712	rv6xx_program_stepping_parameters_lowest_entry(rdev);
		1713	rv6xx_program_power_level_low_to_lowest_state(rdev);
		1714
		1715	r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW, true);
		1716	r600_wait_for_power_level(rdev, R600_POWER_LEVEL_LOW);
		1717	r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, false);
		1718
		1719	if (pi->voltage_control) {
		1720	if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC) {
		1721	ret = rv6xx_step_voltage_if_decreasing(rdev, new_ps, old_ps);
		1722	if (ret)
		1723	return ret;
		1724	}
		1725	rv6xx_enable_dynamic_voltage_control(rdev, true);
		1726	}
		1727
		1728	if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_BACKBIAS)
		1729	rv6xx_enable_dynamic_backbias_control(rdev, true);
		1730
		1731	if (pi->dynamic_pcie_gen2)
		1732	rv6xx_enable_dynamic_pcie_gen2(rdev, new_ps, true);
		1733
		1734	rv6xx_reset_lvtm_data_sync(rdev);
		1735
		1736	rv6xx_generate_stepping_table(rdev, new_ps);
		1737	rv6xx_program_stepping_parameters_except_lowest_entry(rdev);
		1738	rv6xx_program_power_level_low(rdev);
		1739	rv6xx_program_power_level_medium(rdev);
		1740	rv6xx_program_power_level_high(rdev);
		1741	rv6xx_enable_medium(rdev);
		1742	rv6xx_enable_high(rdev);
		1743
		1744	if (pi->thermal_protection)
		1745	rv6xx_enable_thermal_protection(rdev, true);
		1746	rv6xx_program_vc(rdev);
		1747	rv6xx_program_at(rdev);
		1748
		1749	rv6xx_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps);
		1750
		1751	return 0;
		1752	}
		1753
		1754	void rv6xx_setup_asic(struct radeon_device *rdev)
		1755	{
		1756	r600_enable_acpi_pm(rdev);
		1757
		1758	if (radeon_aspm != 0) {
		1759	if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_ASPM_L0s)
		1760	rv6xx_enable_l0s(rdev);
		1761	if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_ASPM_L1)
		1762	rv6xx_enable_l1(rdev);
		1763	if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_TURNOFFPLL_ASPML1)
		1764	rv6xx_enable_pll_sleep_in_l1(rdev);
		1765	}
		1766	}
		1767
		1768	void rv6xx_dpm_display_configuration_changed(struct radeon_device *rdev)
		1769	{
		1770	rv6xx_program_display_gap(rdev);
		1771	}
		1772
		1773	union power_info {
		1774	struct _ATOM_POWERPLAY_INFO info;
		1775	struct _ATOM_POWERPLAY_INFO_V2 info_2;
		1776	struct _ATOM_POWERPLAY_INFO_V3 info_3;
		1777	struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
		1778	struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
		1779	struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
		1780	};
		1781
		1782	union pplib_clock_info {
		1783	struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
		1784	struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
		1785	struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
		1786	struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
		1787	};
		1788
		1789	union pplib_power_state {
		1790	struct _ATOM_PPLIB_STATE v1;
		1791	struct _ATOM_PPLIB_STATE_V2 v2;
		1792	};
		1793
		1794	static void rv6xx_parse_pplib_non_clock_info(struct radeon_device *rdev,
		1795	struct radeon_ps *rps,
		1796	struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info)
		1797	{
		1798	rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
		1799	rps->class = le16_to_cpu(non_clock_info->usClassification);
		1800	rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
		1801
		1802	if (r600_is_uvd_state(rps->class, rps->class2)) {
		1803	rps->vclk = RV6XX_DEFAULT_VCLK_FREQ;
		1804	rps->dclk = RV6XX_DEFAULT_DCLK_FREQ;
		1805	} else {
		1806	rps->vclk = 0;
		1807	rps->dclk = 0;
		1808	}
		1809
		1810	if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
		1811	rdev->pm.dpm.boot_ps = rps;
		1812	if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
		1813	rdev->pm.dpm.uvd_ps = rps;
		1814	}
		1815
		1816	static void rv6xx_parse_pplib_clock_info(struct radeon_device *rdev,
		1817	struct radeon_ps *rps, int index,
		1818	union pplib_clock_info *clock_info)
		1819	{
		1820	struct rv6xx_ps *ps = rv6xx_get_ps(rps);
		1821	u32 sclk, mclk;
		1822	u16 vddc;
		1823	struct rv6xx_pl *pl;
		1824
		1825	switch (index) {
		1826	case 0:
		1827	pl = &ps->low;
		1828	break;
		1829	case 1:
		1830	pl = &ps->medium;
		1831	break;
		1832	case 2:
		1833	default:
		1834	pl = &ps->high;
		1835	break;
		1836	}
		1837
		1838	sclk = le16_to_cpu(clock_info->r600.usEngineClockLow);
		1839	sclk \|= clock_info->r600.ucEngineClockHigh << 16;
		1840	mclk = le16_to_cpu(clock_info->r600.usMemoryClockLow);
		1841	mclk \|= clock_info->r600.ucMemoryClockHigh << 16;
		1842
		1843	pl->mclk = mclk;
		1844	pl->sclk = sclk;
		1845	pl->vddc = le16_to_cpu(clock_info->r600.usVDDC);
		1846	pl->flags = le32_to_cpu(clock_info->r600.ulFlags);
		1847
		1848	/* patch up vddc if necessary */
		1849	if (pl->vddc == 0xff01) {
		1850	if (radeon_atom_get_max_vddc(rdev, 0, 0, &vddc) == 0)
		1851	pl->vddc = vddc;
		1852	}
		1853
		1854	/* fix up pcie gen2 */
		1855	if (pl->flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) {
		1856	if ((rdev->family == CHIP_RV610) \|\| (rdev->family == CHIP_RV630)) {
		1857	if (pl->vddc < 1100)
		1858	pl->flags &= ~ATOM_PPLIB_R600_FLAGS_PCIEGEN2;
		1859	}
		1860	}
		1861
		1862	/* patch up boot state */
		1863	if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
		1864	u16 vddc, vddci, mvdd;
		1865	radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd);
		1866	pl->mclk = rdev->clock.default_mclk;
		1867	pl->sclk = rdev->clock.default_sclk;
		1868	pl->vddc = vddc;
		1869	}
		1870	}
		1871
		1872	static int rv6xx_parse_power_table(struct radeon_device *rdev)
		1873	{
		1874	struct radeon_mode_info *mode_info = &rdev->mode_info;
		1875	struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
		1876	union pplib_power_state *power_state;
		1877	int i, j;
		1878	union pplib_clock_info *clock_info;
		1879	union power_info *power_info;
		1880	int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
		1881	u16 data_offset;
		1882	u8 frev, crev;
		1883	struct rv6xx_ps *ps;
		1884
		1885	if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
		1886	&frev, &crev, &data_offset))
		1887	return -EINVAL;
		1888	power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
		1889
		1890	rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) *
		1891	power_info->pplib.ucNumStates, GFP_KERNEL);
		1892	if (!rdev->pm.dpm.ps)
		1893	return -ENOMEM;
		1894
		1895	for (i = 0; i < power_info->pplib.ucNumStates; i++) {
		1896	power_state = (union pplib_power_state *)
		1897	(mode_info->atom_context->bios + data_offset +
		1898	le16_to_cpu(power_info->pplib.usStateArrayOffset) +
		1899	i * power_info->pplib.ucStateEntrySize);
		1900	non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
		1901	(mode_info->atom_context->bios + data_offset +
		1902	le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) +
		1903	(power_state->v1.ucNonClockStateIndex *
		1904	power_info->pplib.ucNonClockSize));
		1905	if (power_info->pplib.ucStateEntrySize - 1) {
		1906	u8 *idx;
		1907	ps = kzalloc(sizeof(struct rv6xx_ps), GFP_KERNEL);
		1908	if (ps == NULL) {
		1909	kfree(rdev->pm.dpm.ps);
		1910	return -ENOMEM;
		1911	}
		1912	rdev->pm.dpm.ps[i].ps_priv = ps;
		1913	rv6xx_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
		1914	non_clock_info);
		1915	idx = (u8 *)&power_state->v1.ucClockStateIndices[0];
		1916	for (j = 0; j < (power_info->pplib.ucStateEntrySize - 1); j++) {
		1917	clock_info = (union pplib_clock_info *)
		1918	(mode_info->atom_context->bios + data_offset +
		1919	le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) +
		1920	(idx[j] * power_info->pplib.ucClockInfoSize));
		1921	rv6xx_parse_pplib_clock_info(rdev,
		1922	&rdev->pm.dpm.ps[i], j,
		1923	clock_info);
		1924	}
		1925	}
		1926	}
		1927	rdev->pm.dpm.num_ps = power_info->pplib.ucNumStates;
		1928	return 0;
		1929	}
		1930
		1931	int rv6xx_dpm_init(struct radeon_device *rdev)
		1932	{
		1933	struct radeon_atom_ss ss;
		1934	struct atom_clock_dividers dividers;
		1935	struct rv6xx_power_info *pi;
		1936	int ret;
		1937
		1938	pi = kzalloc(sizeof(struct rv6xx_power_info), GFP_KERNEL);
		1939	if (pi == NULL)
		1940	return -ENOMEM;
		1941	rdev->pm.dpm.priv = pi;
		1942
		1943	ret = r600_get_platform_caps(rdev);
		1944	if (ret)
		1945	return ret;
		1946
		1947	ret = rv6xx_parse_power_table(rdev);
		1948	if (ret)
		1949	return ret;
		1950
		1951	if (rdev->pm.dpm.voltage_response_time == 0)
		1952	rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT;
		1953	if (rdev->pm.dpm.backbias_response_time == 0)
		1954	rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT;
		1955
		1956	ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
		1957	0, false, ÷rs);
		1958	if (ret)
		1959	pi->spll_ref_div = dividers.ref_div + 1;
		1960	else
		1961	pi->spll_ref_div = R600_REFERENCEDIVIDER_DFLT;
		1962
		1963	ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_MEMORY_PLL_PARAM,
		1964	0, false, ÷rs);
		1965	if (ret)
		1966	pi->mpll_ref_div = dividers.ref_div + 1;
		1967	else
		1968	pi->mpll_ref_div = R600_REFERENCEDIVIDER_DFLT;
		1969
		1970	if (rdev->family >= CHIP_RV670)
		1971	pi->fb_div_scale = 1;
		1972	else
		1973	pi->fb_div_scale = 0;
		1974
		1975	pi->voltage_control =
		1976	radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 0);
		1977
		1978	pi->gfx_clock_gating = true;
		1979
		1980	pi->sclk_ss = radeon_atombios_get_asic_ss_info(rdev, &ss,
		1981	ASIC_INTERNAL_ENGINE_SS, 0);
		1982	pi->mclk_ss = radeon_atombios_get_asic_ss_info(rdev, &ss,
		1983	ASIC_INTERNAL_MEMORY_SS, 0);
		1984
		1985	/* Disable sclk ss, causes hangs on a lot of systems */
		1986	pi->sclk_ss = false;
		1987
		1988	if (pi->sclk_ss \|\| pi->mclk_ss)
		1989	pi->dynamic_ss = true;
		1990	else
		1991	pi->dynamic_ss = false;
		1992
		1993	pi->dynamic_pcie_gen2 = true;
		1994
		1995	if (pi->gfx_clock_gating &&
		1996	(rdev->pm.int_thermal_type != THERMAL_TYPE_NONE))
		1997	pi->thermal_protection = true;
		1998	else
		1999	pi->thermal_protection = false;
		2000
		2001	pi->display_gap = true;
		2002
		2003	return 0;
		2004	}
		2005
		2006	void rv6xx_dpm_print_power_state(struct radeon_device *rdev,
		2007	struct radeon_ps *rps)
		2008	{
		2009	struct rv6xx_ps *ps = rv6xx_get_ps(rps);
		2010	struct rv6xx_pl *pl;
		2011
		2012	r600_dpm_print_class_info(rps->class, rps->class2);
		2013	r600_dpm_print_cap_info(rps->caps);
		2014	printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
		2015	pl = &ps->low;
		2016	printk("\t\tpower level 0 sclk: %u mclk: %u vddc: %u\n",
		2017	pl->sclk, pl->mclk, pl->vddc);
		2018	pl = &ps->medium;
		2019	printk("\t\tpower level 1 sclk: %u mclk: %u vddc: %u\n",
		2020	pl->sclk, pl->mclk, pl->vddc);
		2021	pl = &ps->high;
		2022	printk("\t\tpower level 2 sclk: %u mclk: %u vddc: %u\n",
		2023	pl->sclk, pl->mclk, pl->vddc);
		2024	r600_dpm_print_ps_status(rdev, rps);
		2025	}
		2026
		2027	void rv6xx_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
		2028	struct seq_file *m)
		2029	{
		2030	struct radeon_ps *rps = rdev->pm.dpm.current_ps;
		2031	struct rv6xx_ps *ps = rv6xx_get_ps(rps);
		2032	struct rv6xx_pl *pl;
		2033	u32 current_index =
		2034	(RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_PROFILE_INDEX_MASK) >>
		2035	CURRENT_PROFILE_INDEX_SHIFT;
		2036
		2037	if (current_index > 2) {
		2038	seq_printf(m, "invalid dpm profile %d\n", current_index);
		2039	} else {
		2040	if (current_index == 0)
		2041	pl = &ps->low;
		2042	else if (current_index == 1)
		2043	pl = &ps->medium;
		2044	else /* current_index == 2 */
		2045	pl = &ps->high;
		2046	seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
		2047	seq_printf(m, "power level %d sclk: %u mclk: %u vddc: %u\n",
		2048	current_index, pl->sclk, pl->mclk, pl->vddc);
		2049	}
		2050	}
		2051
		2052	void rv6xx_dpm_fini(struct radeon_device *rdev)
		2053	{
		2054	int i;
		2055
		2056	for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
		2057	kfree(rdev->pm.dpm.ps[i].ps_priv);
		2058	}
		2059	kfree(rdev->pm.dpm.ps);
		2060	kfree(rdev->pm.dpm.priv);
		2061	}
		2062
		2063	u32 rv6xx_dpm_get_sclk(struct radeon_device *rdev, bool low)
		2064	{
		2065	struct rv6xx_ps *requested_state = rv6xx_get_ps(rdev->pm.dpm.requested_ps);
		2066
		2067	if (low)
		2068	return requested_state->low.sclk;
		2069	else
		2070	return requested_state->high.sclk;
		2071	}
		2072
		2073	u32 rv6xx_dpm_get_mclk(struct radeon_device *rdev, bool low)
		2074	{
		2075	struct rv6xx_ps *requested_state = rv6xx_get_ps(rdev->pm.dpm.requested_ps);
		2076
		2077	if (low)
		2078	return requested_state->low.mclk;
		2079	else
		2080	return requested_state->high.mclk;
		2081	}
		2082
		2083	int rv6xx_dpm_force_performance_level(struct radeon_device *rdev,
		2084	enum radeon_dpm_forced_level level)
		2085	{
		2086	struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
		2087
		2088	if (level == RADEON_DPM_FORCED_LEVEL_HIGH) {
		2089	pi->restricted_levels = 3;
		2090	} else if (level == RADEON_DPM_FORCED_LEVEL_LOW) {
		2091	pi->restricted_levels = 2;
		2092	} else {
		2093	pi->restricted_levels = 0;
		2094	}
		2095
		2096	rv6xx_clear_vc(rdev);
		2097	r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW, true);
		2098	r600_set_at(rdev, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF);
		2099	r600_wait_for_power_level(rdev, R600_POWER_LEVEL_LOW);
		2100	r600_power_level_enable(rdev, R600_POWER_LEVEL_HIGH, false);
		2101	r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, false);
		2102	rv6xx_enable_medium(rdev);
		2103	rv6xx_enable_high(rdev);
		2104	if (pi->restricted_levels == 3)
		2105	r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW, false);
		2106	rv6xx_program_vc(rdev);
		2107	rv6xx_program_at(rdev);
		2108
		2109	rdev->pm.dpm.forced_level = level;
		2110
		2111	return 0;
		2112	}

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(root)/drivers/video/drm/radeon/rv6xx_dpm.c – Rev 5179