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1128 | serge | 1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
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3 | * Copyright 2008 Red Hat Inc. |
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4 | * Copyright 2009 Jerome Glisse. |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the "Software"), |
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8 | * to deal in the Software without restriction, including without limitation |
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9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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10 | * and/or sell copies of the Software, and to permit persons to whom the |
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11 | * Software is furnished to do so, subject to the following conditions: |
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12 | * |
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13 | * The above copyright notice and this permission notice shall be included in |
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14 | * all copies or substantial portions of the Software. |
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15 | * |
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16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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22 | * OTHER DEALINGS IN THE SOFTWARE. |
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23 | * |
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24 | * Authors: Dave Airlie |
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25 | * Alex Deucher |
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26 | * Jerome Glisse |
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27 | */ |
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1221 | serge | 28 | /* RS600 / Radeon X1250/X1270 integrated GPU |
29 | * |
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30 | * This file gather function specific to RS600 which is the IGP of |
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31 | * the X1250/X1270 family supporting intel CPU (while RS690/RS740 |
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32 | * is the X1250/X1270 supporting AMD CPU). The display engine are |
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33 | * the avivo one, bios is an atombios, 3D block are the one of the |
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34 | * R4XX family. The GART is different from the RS400 one and is very |
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35 | * close to the one of the R600 family (R600 likely being an evolution |
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36 | * of the RS600 GART block). |
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37 | */ |
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1128 | serge | 38 | #include "drmP.h" |
39 | #include "radeon.h" |
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1221 | serge | 40 | #include "atom.h" |
41 | #include "rs600d.h" |
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1128 | serge | 42 | |
1179 | serge | 43 | #include "rs600_reg_safe.h" |
44 | |||
1128 | serge | 45 | void rs600_gpu_init(struct radeon_device *rdev); |
46 | int rs600_mc_wait_for_idle(struct radeon_device *rdev); |
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47 | |||
1321 | serge | 48 | int rs600_mc_init(struct radeon_device *rdev) |
49 | { |
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50 | /* read back the MC value from the hw */ |
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51 | int r; |
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52 | u32 tmp; |
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53 | |||
54 | /* Setup GPU memory space */ |
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55 | tmp = RREG32_MC(R_000004_MC_FB_LOCATION); |
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56 | rdev->mc.vram_location = G_000004_MC_FB_START(tmp) << 16; |
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57 | rdev->mc.gtt_location = 0xffffffffUL; |
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58 | r = radeon_mc_setup(rdev); |
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1403 | serge | 59 | rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); |
1321 | serge | 60 | if (r) |
61 | return r; |
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62 | return 0; |
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63 | } |
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64 | |||
65 | /* hpd for digital panel detect/disconnect */ |
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66 | bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) |
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67 | { |
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68 | u32 tmp; |
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69 | bool connected = false; |
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70 | |||
71 | switch (hpd) { |
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72 | case RADEON_HPD_1: |
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73 | tmp = RREG32(R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS); |
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74 | if (G_007D04_DC_HOT_PLUG_DETECT1_SENSE(tmp)) |
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75 | connected = true; |
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76 | break; |
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77 | case RADEON_HPD_2: |
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78 | tmp = RREG32(R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS); |
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79 | if (G_007D14_DC_HOT_PLUG_DETECT2_SENSE(tmp)) |
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80 | connected = true; |
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81 | break; |
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82 | default: |
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83 | break; |
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84 | } |
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85 | return connected; |
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86 | } |
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87 | |||
88 | void rs600_hpd_set_polarity(struct radeon_device *rdev, |
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89 | enum radeon_hpd_id hpd) |
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90 | { |
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91 | u32 tmp; |
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92 | bool connected = rs600_hpd_sense(rdev, hpd); |
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93 | |||
94 | switch (hpd) { |
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95 | case RADEON_HPD_1: |
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96 | tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL); |
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97 | if (connected) |
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98 | tmp &= ~S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1); |
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99 | else |
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100 | tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1); |
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101 | WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); |
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102 | break; |
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103 | case RADEON_HPD_2: |
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104 | tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL); |
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105 | if (connected) |
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106 | tmp &= ~S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1); |
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107 | else |
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108 | tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1); |
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109 | WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); |
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110 | break; |
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111 | default: |
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112 | break; |
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113 | } |
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114 | } |
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115 | |||
116 | void rs600_hpd_init(struct radeon_device *rdev) |
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117 | { |
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118 | struct drm_device *dev = rdev->ddev; |
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119 | struct drm_connector *connector; |
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120 | |||
121 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
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122 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
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123 | switch (radeon_connector->hpd.hpd) { |
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124 | case RADEON_HPD_1: |
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125 | WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL, |
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126 | S_007D00_DC_HOT_PLUG_DETECT1_EN(1)); |
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1403 | serge | 127 | // rdev->irq.hpd[0] = true; |
1321 | serge | 128 | break; |
129 | case RADEON_HPD_2: |
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130 | WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL, |
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131 | S_007D10_DC_HOT_PLUG_DETECT2_EN(1)); |
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1403 | serge | 132 | // rdev->irq.hpd[1] = true; |
1321 | serge | 133 | break; |
134 | default: |
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135 | break; |
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136 | } |
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137 | } |
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1403 | serge | 138 | // if (rdev->irq.installed) |
139 | // rs600_irq_set(rdev); |
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1321 | serge | 140 | } |
141 | |||
142 | void rs600_hpd_fini(struct radeon_device *rdev) |
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143 | { |
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144 | struct drm_device *dev = rdev->ddev; |
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145 | struct drm_connector *connector; |
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146 | |||
147 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
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148 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
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149 | switch (radeon_connector->hpd.hpd) { |
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150 | case RADEON_HPD_1: |
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151 | WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL, |
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152 | S_007D00_DC_HOT_PLUG_DETECT1_EN(0)); |
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1403 | serge | 153 | // rdev->irq.hpd[0] = false; |
1321 | serge | 154 | break; |
155 | case RADEON_HPD_2: |
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156 | WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL, |
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157 | S_007D10_DC_HOT_PLUG_DETECT2_EN(0)); |
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1403 | serge | 158 | // rdev->irq.hpd[1] = false; |
1321 | serge | 159 | break; |
160 | default: |
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161 | break; |
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162 | } |
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163 | } |
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164 | } |
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165 | |||
1128 | serge | 166 | /* |
167 | * GART. |
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168 | */ |
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169 | void rs600_gart_tlb_flush(struct radeon_device *rdev) |
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170 | { |
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171 | uint32_t tmp; |
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172 | |||
1221 | serge | 173 | tmp = RREG32_MC(R_000100_MC_PT0_CNTL); |
174 | tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE; |
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175 | WREG32_MC(R_000100_MC_PT0_CNTL, tmp); |
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1128 | serge | 176 | |
1221 | serge | 177 | tmp = RREG32_MC(R_000100_MC_PT0_CNTL); |
178 | tmp |= S_000100_INVALIDATE_ALL_L1_TLBS(1) & S_000100_INVALIDATE_L2_CACHE(1); |
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179 | WREG32_MC(R_000100_MC_PT0_CNTL, tmp); |
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1128 | serge | 180 | |
1221 | serge | 181 | tmp = RREG32_MC(R_000100_MC_PT0_CNTL); |
182 | tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE; |
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183 | WREG32_MC(R_000100_MC_PT0_CNTL, tmp); |
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184 | tmp = RREG32_MC(R_000100_MC_PT0_CNTL); |
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1128 | serge | 185 | } |
186 | |||
1221 | serge | 187 | int rs600_gart_init(struct radeon_device *rdev) |
1128 | serge | 188 | { |
189 | int r; |
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190 | |||
1221 | serge | 191 | if (rdev->gart.table.vram.robj) { |
192 | WARN(1, "RS600 GART already initialized.\n"); |
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193 | return 0; |
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194 | } |
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1128 | serge | 195 | /* Initialize common gart structure */ |
196 | r = radeon_gart_init(rdev); |
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197 | if (r) { |
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198 | return r; |
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199 | } |
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200 | rdev->gart.table_size = rdev->gart.num_gpu_pages * 8; |
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1221 | serge | 201 | return radeon_gart_table_vram_alloc(rdev); |
202 | } |
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203 | |||
204 | int rs600_gart_enable(struct radeon_device *rdev) |
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205 | { |
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206 | u32 tmp; |
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207 | int r, i; |
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208 | |||
209 | if (rdev->gart.table.vram.robj == NULL) { |
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210 | dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); |
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211 | return -EINVAL; |
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212 | } |
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213 | r = radeon_gart_table_vram_pin(rdev); |
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214 | if (r) |
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1128 | serge | 215 | return r; |
1221 | serge | 216 | /* Enable bus master */ |
217 | tmp = RREG32(R_00004C_BUS_CNTL) & C_00004C_BUS_MASTER_DIS; |
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218 | WREG32(R_00004C_BUS_CNTL, tmp); |
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1128 | serge | 219 | /* FIXME: setup default page */ |
1221 | serge | 220 | WREG32_MC(R_000100_MC_PT0_CNTL, |
221 | (S_000100_EFFECTIVE_L2_CACHE_SIZE(6) | |
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222 | S_000100_EFFECTIVE_L2_QUEUE_SIZE(6))); |
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1321 | serge | 223 | |
1128 | serge | 224 | for (i = 0; i < 19; i++) { |
1221 | serge | 225 | WREG32_MC(R_00016C_MC_PT0_CLIENT0_CNTL + i, |
226 | S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(1) | |
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227 | S_00016C_SYSTEM_ACCESS_MODE_MASK( |
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1321 | serge | 228 | V_00016C_SYSTEM_ACCESS_MODE_NOT_IN_SYS) | |
1221 | serge | 229 | S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS( |
1321 | serge | 230 | V_00016C_SYSTEM_APERTURE_UNMAPPED_PASSTHROUGH) | |
231 | S_00016C_EFFECTIVE_L1_CACHE_SIZE(3) | |
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1221 | serge | 232 | S_00016C_ENABLE_FRAGMENT_PROCESSING(1) | |
1321 | serge | 233 | S_00016C_EFFECTIVE_L1_QUEUE_SIZE(3)); |
1128 | serge | 234 | } |
235 | /* enable first context */ |
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1221 | serge | 236 | WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL, |
237 | S_000102_ENABLE_PAGE_TABLE(1) | |
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238 | S_000102_PAGE_TABLE_DEPTH(V_000102_PAGE_TABLE_FLAT)); |
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1321 | serge | 239 | |
1128 | serge | 240 | /* disable all other contexts */ |
1321 | serge | 241 | for (i = 1; i < 8; i++) |
1221 | serge | 242 | WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL + i, 0); |
1128 | serge | 243 | |
244 | /* setup the page table */ |
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1221 | serge | 245 | WREG32_MC(R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR, |
1128 | serge | 246 | rdev->gart.table_addr); |
1321 | serge | 247 | WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start); |
248 | WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR, rdev->mc.gtt_end); |
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1221 | serge | 249 | WREG32_MC(R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0); |
1128 | serge | 250 | |
1321 | serge | 251 | /* System context maps to VRAM space */ |
252 | WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start); |
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253 | WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end); |
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254 | |||
1128 | serge | 255 | /* enable page tables */ |
1221 | serge | 256 | tmp = RREG32_MC(R_000100_MC_PT0_CNTL); |
257 | WREG32_MC(R_000100_MC_PT0_CNTL, (tmp | S_000100_ENABLE_PT(1))); |
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258 | tmp = RREG32_MC(R_000009_MC_CNTL1); |
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259 | WREG32_MC(R_000009_MC_CNTL1, (tmp | S_000009_ENABLE_PAGE_TABLES(1))); |
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1128 | serge | 260 | rs600_gart_tlb_flush(rdev); |
261 | rdev->gart.ready = true; |
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262 | return 0; |
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263 | } |
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264 | |||
265 | void rs600_gart_disable(struct radeon_device *rdev) |
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266 | { |
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1321 | serge | 267 | u32 tmp; |
268 | int r; |
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1128 | serge | 269 | |
270 | /* FIXME: disable out of gart access */ |
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1221 | serge | 271 | WREG32_MC(R_000100_MC_PT0_CNTL, 0); |
272 | tmp = RREG32_MC(R_000009_MC_CNTL1); |
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273 | WREG32_MC(R_000009_MC_CNTL1, tmp & C_000009_ENABLE_PAGE_TABLES); |
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274 | if (rdev->gart.table.vram.robj) { |
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1404 | serge | 275 | r = radeon_bo_reserve(rdev->gart.table.vram.robj, false); |
276 | if (r == 0) { |
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277 | radeon_bo_kunmap(rdev->gart.table.vram.robj); |
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278 | radeon_bo_unpin(rdev->gart.table.vram.robj); |
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279 | radeon_bo_unreserve(rdev->gart.table.vram.robj); |
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280 | } |
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1221 | serge | 281 | } |
1128 | serge | 282 | } |
283 | |||
1221 | serge | 284 | void rs600_gart_fini(struct radeon_device *rdev) |
285 | { |
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286 | rs600_gart_disable(rdev); |
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287 | radeon_gart_table_vram_free(rdev); |
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288 | radeon_gart_fini(rdev); |
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289 | } |
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290 | |||
1128 | serge | 291 | #define R600_PTE_VALID (1 << 0) |
292 | #define R600_PTE_SYSTEM (1 << 1) |
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293 | #define R600_PTE_SNOOPED (1 << 2) |
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294 | #define R600_PTE_READABLE (1 << 5) |
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295 | #define R600_PTE_WRITEABLE (1 << 6) |
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296 | |||
297 | int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) |
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298 | { |
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299 | void __iomem *ptr = (void *)rdev->gart.table.vram.ptr; |
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300 | |||
301 | if (i < 0 || i > rdev->gart.num_gpu_pages) { |
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302 | return -EINVAL; |
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303 | } |
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304 | addr = addr & 0xFFFFFFFFFFFFF000ULL; |
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305 | addr |= R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED; |
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306 | addr |= R600_PTE_READABLE | R600_PTE_WRITEABLE; |
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307 | writeq(addr, ((void __iomem *)ptr) + (i * 8)); |
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308 | return 0; |
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309 | } |
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310 | |||
1403 | serge | 311 | /* |
1321 | serge | 312 | int rs600_irq_set(struct radeon_device *rdev) |
313 | { |
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314 | uint32_t tmp = 0; |
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315 | uint32_t mode_int = 0; |
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316 | u32 hpd1 = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL) & |
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317 | ~S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1); |
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318 | u32 hpd2 = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL) & |
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319 | ~S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1); |
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1128 | serge | 320 | |
1403 | serge | 321 | if (!rdev->irq.installed) { |
322 | WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n"); |
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323 | WREG32(R_000040_GEN_INT_CNTL, 0); |
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324 | return -EINVAL; |
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325 | } |
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1321 | serge | 326 | if (rdev->irq.sw_int) { |
327 | tmp |= S_000040_SW_INT_EN(1); |
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328 | } |
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329 | if (rdev->irq.crtc_vblank_int[0]) { |
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330 | mode_int |= S_006540_D1MODE_VBLANK_INT_MASK(1); |
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331 | } |
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332 | if (rdev->irq.crtc_vblank_int[1]) { |
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333 | mode_int |= S_006540_D2MODE_VBLANK_INT_MASK(1); |
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334 | } |
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335 | if (rdev->irq.hpd[0]) { |
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336 | hpd1 |= S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1); |
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337 | } |
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338 | if (rdev->irq.hpd[1]) { |
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339 | hpd2 |= S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1); |
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340 | } |
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341 | WREG32(R_000040_GEN_INT_CNTL, tmp); |
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342 | WREG32(R_006540_DxMODE_INT_MASK, mode_int); |
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343 | WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1); |
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344 | WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2); |
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345 | return 0; |
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346 | } |
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1403 | serge | 347 | */ |
1128 | serge | 348 | |
1221 | serge | 349 | static inline uint32_t rs600_irq_ack(struct radeon_device *rdev, u32 *r500_disp_int) |
1128 | serge | 350 | { |
1221 | serge | 351 | uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS); |
352 | uint32_t irq_mask = ~C_000044_SW_INT; |
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1321 | serge | 353 | u32 tmp; |
1128 | serge | 354 | |
1221 | serge | 355 | if (G_000044_DISPLAY_INT_STAT(irqs)) { |
356 | *r500_disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS); |
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357 | if (G_007EDC_LB_D1_VBLANK_INTERRUPT(*r500_disp_int)) { |
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358 | WREG32(R_006534_D1MODE_VBLANK_STATUS, |
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359 | S_006534_D1MODE_VBLANK_ACK(1)); |
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360 | } |
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361 | if (G_007EDC_LB_D2_VBLANK_INTERRUPT(*r500_disp_int)) { |
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362 | WREG32(R_006D34_D2MODE_VBLANK_STATUS, |
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363 | S_006D34_D2MODE_VBLANK_ACK(1)); |
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364 | } |
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1321 | serge | 365 | if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(*r500_disp_int)) { |
366 | tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL); |
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367 | tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_ACK(1); |
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368 | WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); |
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369 | } |
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370 | if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(*r500_disp_int)) { |
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371 | tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL); |
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372 | tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_ACK(1); |
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373 | WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); |
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374 | } |
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1221 | serge | 375 | } else { |
376 | *r500_disp_int = 0; |
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1129 | serge | 377 | } |
1128 | serge | 378 | |
1221 | serge | 379 | if (irqs) { |
380 | WREG32(R_000044_GEN_INT_STATUS, irqs); |
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1128 | serge | 381 | } |
1221 | serge | 382 | return irqs & irq_mask; |
1128 | serge | 383 | } |
384 | |||
1221 | serge | 385 | void rs600_irq_disable(struct radeon_device *rdev) |
1128 | serge | 386 | { |
1221 | serge | 387 | u32 tmp; |
388 | |||
389 | WREG32(R_000040_GEN_INT_CNTL, 0); |
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390 | WREG32(R_006540_DxMODE_INT_MASK, 0); |
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391 | /* Wait and acknowledge irq */ |
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392 | mdelay(1); |
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393 | rs600_irq_ack(rdev, &tmp); |
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1128 | serge | 394 | } |
395 | |||
396 | |||
1221 | serge | 397 | u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc) |
1128 | serge | 398 | { |
1221 | serge | 399 | if (crtc == 0) |
400 | return RREG32(R_0060A4_D1CRTC_STATUS_FRAME_COUNT); |
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401 | else |
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402 | return RREG32(R_0068A4_D2CRTC_STATUS_FRAME_COUNT); |
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1128 | serge | 403 | } |
404 | |||
405 | int rs600_mc_wait_for_idle(struct radeon_device *rdev) |
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406 | { |
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407 | unsigned i; |
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408 | |||
409 | for (i = 0; i < rdev->usec_timeout; i++) { |
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1221 | serge | 410 | if (G_000000_MC_IDLE(RREG32_MC(R_000000_MC_STATUS))) |
1128 | serge | 411 | return 0; |
1221 | serge | 412 | udelay(1); |
1128 | serge | 413 | } |
414 | return -1; |
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415 | } |
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416 | |||
417 | void rs600_gpu_init(struct radeon_device *rdev) |
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418 | { |
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419 | r100_hdp_reset(rdev); |
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420 | r420_pipes_init(rdev); |
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1221 | serge | 421 | /* Wait for mc idle */ |
422 | if (rs600_mc_wait_for_idle(rdev)) |
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423 | dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); |
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1128 | serge | 424 | } |
425 | |||
426 | void rs600_vram_info(struct radeon_device *rdev) |
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427 | { |
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428 | rdev->mc.vram_is_ddr = true; |
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429 | rdev->mc.vram_width = 128; |
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1321 | serge | 430 | |
431 | rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); |
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432 | rdev->mc.mc_vram_size = rdev->mc.real_vram_size; |
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433 | |||
434 | rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); |
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435 | rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); |
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436 | |||
437 | if (rdev->mc.mc_vram_size > rdev->mc.aper_size) |
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438 | rdev->mc.mc_vram_size = rdev->mc.aper_size; |
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439 | |||
440 | if (rdev->mc.real_vram_size > rdev->mc.aper_size) |
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441 | rdev->mc.real_vram_size = rdev->mc.aper_size; |
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1128 | serge | 442 | } |
443 | |||
1179 | serge | 444 | void rs600_bandwidth_update(struct radeon_device *rdev) |
445 | { |
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446 | /* FIXME: implement, should this be like rs690 ? */ |
||
447 | } |
||
1128 | serge | 448 | |
449 | uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg) |
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450 | { |
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1221 | serge | 451 | WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) | |
452 | S_000070_MC_IND_CITF_ARB0(1)); |
||
453 | return RREG32(R_000074_MC_IND_DATA); |
||
454 | } |
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1128 | serge | 455 | |
1221 | serge | 456 | void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
457 | { |
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458 | WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) | |
||
459 | S_000070_MC_IND_CITF_ARB0(1) | S_000070_MC_IND_WR_EN(1)); |
||
460 | WREG32(R_000074_MC_IND_DATA, v); |
||
461 | } |
||
462 | |||
463 | void rs600_debugfs(struct radeon_device *rdev) |
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464 | { |
||
465 | if (r100_debugfs_rbbm_init(rdev)) |
||
466 | DRM_ERROR("Failed to register debugfs file for RBBM !\n"); |
||
467 | } |
||
468 | |||
469 | void rs600_set_safe_registers(struct radeon_device *rdev) |
||
470 | { |
||
471 | rdev->config.r300.reg_safe_bm = rs600_reg_safe_bm; |
||
472 | rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rs600_reg_safe_bm); |
||
473 | } |
||
474 | |||
475 | static void rs600_mc_program(struct radeon_device *rdev) |
||
476 | { |
||
477 | struct rv515_mc_save save; |
||
478 | |||
479 | /* Stops all mc clients */ |
||
480 | rv515_mc_stop(rdev, &save); |
||
481 | |||
482 | /* Wait for mc idle */ |
||
483 | if (rs600_mc_wait_for_idle(rdev)) |
||
484 | dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); |
||
485 | |||
486 | /* FIXME: What does AGP means for such chipset ? */ |
||
487 | WREG32_MC(R_000005_MC_AGP_LOCATION, 0x0FFFFFFF); |
||
488 | WREG32_MC(R_000006_AGP_BASE, 0); |
||
489 | WREG32_MC(R_000007_AGP_BASE_2, 0); |
||
490 | /* Program MC */ |
||
491 | WREG32_MC(R_000004_MC_FB_LOCATION, |
||
492 | S_000004_MC_FB_START(rdev->mc.vram_start >> 16) | |
||
493 | S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16)); |
||
494 | WREG32(R_000134_HDP_FB_LOCATION, |
||
495 | S_000134_HDP_FB_START(rdev->mc.vram_start >> 16)); |
||
496 | |||
497 | rv515_mc_resume(rdev, &save); |
||
498 | } |
||
499 | |||
500 | static int rs600_startup(struct radeon_device *rdev) |
||
501 | { |
||
502 | int r; |
||
503 | |||
504 | rs600_mc_program(rdev); |
||
505 | /* Resume clock */ |
||
506 | rv515_clock_startup(rdev); |
||
507 | /* Initialize GPU configuration (# pipes, ...) */ |
||
508 | rs600_gpu_init(rdev); |
||
509 | /* Initialize GART (initialize after TTM so we can allocate |
||
510 | * memory through TTM but finalize after TTM) */ |
||
511 | r = rs600_gart_enable(rdev); |
||
512 | if (r) |
||
1128 | serge | 513 | return r; |
1221 | serge | 514 | /* Enable IRQ */ |
515 | // rs600_irq_set(rdev); |
||
1403 | serge | 516 | rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); |
1221 | serge | 517 | /* 1M ring buffer */ |
1413 | serge | 518 | r = r100_cp_init(rdev, 1024 * 1024); |
519 | if (r) { |
||
520 | dev_err(rdev->dev, "failled initializing CP (%d).\n", r); |
||
521 | return r; |
||
522 | } |
||
1221 | serge | 523 | // r = r100_wb_init(rdev); |
524 | // if (r) |
||
525 | // dev_err(rdev->dev, "failled initializing WB (%d).\n", r); |
||
526 | // r = r100_ib_init(rdev); |
||
527 | // if (r) { |
||
528 | // dev_err(rdev->dev, "failled initializing IB (%d).\n", r); |
||
529 | // return r; |
||
530 | // } |
||
531 | return 0; |
||
1128 | serge | 532 | } |
533 | |||
1221 | serge | 534 | |
535 | |||
536 | int rs600_init(struct radeon_device *rdev) |
||
1128 | serge | 537 | { |
1221 | serge | 538 | int r; |
539 | |||
540 | /* Disable VGA */ |
||
541 | rv515_vga_render_disable(rdev); |
||
542 | /* Initialize scratch registers */ |
||
543 | radeon_scratch_init(rdev); |
||
544 | /* Initialize surface registers */ |
||
545 | radeon_surface_init(rdev); |
||
546 | /* BIOS */ |
||
547 | if (!radeon_get_bios(rdev)) { |
||
548 | if (ASIC_IS_AVIVO(rdev)) |
||
549 | return -EINVAL; |
||
550 | } |
||
551 | if (rdev->is_atom_bios) { |
||
552 | r = radeon_atombios_init(rdev); |
||
553 | if (r) |
||
554 | return r; |
||
555 | } else { |
||
556 | dev_err(rdev->dev, "Expecting atombios for RS600 GPU\n"); |
||
557 | return -EINVAL; |
||
558 | } |
||
559 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ |
||
560 | if (radeon_gpu_reset(rdev)) { |
||
561 | dev_warn(rdev->dev, |
||
562 | "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", |
||
563 | RREG32(R_000E40_RBBM_STATUS), |
||
564 | RREG32(R_0007C0_CP_STAT)); |
||
565 | } |
||
566 | /* check if cards are posted or not */ |
||
1321 | serge | 567 | if (radeon_boot_test_post_card(rdev) == false) |
568 | return -EINVAL; |
||
569 | |||
1221 | serge | 570 | /* Initialize clocks */ |
571 | radeon_get_clock_info(rdev->ddev); |
||
1268 | serge | 572 | /* Initialize power management */ |
573 | radeon_pm_init(rdev); |
||
1221 | serge | 574 | /* Get vram informations */ |
575 | rs600_vram_info(rdev); |
||
576 | /* Initialize memory controller (also test AGP) */ |
||
1321 | serge | 577 | r = rs600_mc_init(rdev); |
1221 | serge | 578 | if (r) |
579 | return r; |
||
580 | rs600_debugfs(rdev); |
||
581 | /* Fence driver */ |
||
582 | // r = radeon_fence_driver_init(rdev); |
||
583 | // if (r) |
||
584 | // return r; |
||
585 | // r = radeon_irq_kms_init(rdev); |
||
586 | // if (r) |
||
587 | // return r; |
||
588 | /* Memory manager */ |
||
1321 | serge | 589 | r = radeon_bo_init(rdev); |
1221 | serge | 590 | if (r) |
591 | return r; |
||
592 | r = rs600_gart_init(rdev); |
||
593 | if (r) |
||
594 | return r; |
||
595 | rs600_set_safe_registers(rdev); |
||
596 | rdev->accel_working = true; |
||
597 | r = rs600_startup(rdev); |
||
598 | if (r) { |
||
599 | /* Somethings want wront with the accel init stop accel */ |
||
600 | dev_err(rdev->dev, "Disabling GPU acceleration\n"); |
||
601 | // r100_cp_fini(rdev); |
||
602 | // r100_wb_fini(rdev); |
||
603 | // r100_ib_fini(rdev); |
||
604 | rs600_gart_fini(rdev); |
||
605 | // radeon_irq_kms_fini(rdev); |
||
606 | rdev->accel_working = false; |
||
607 | } |
||
608 | return 0; |
||
1128 | serge | 609 | }>>><>><>><>><>><>>>><> |