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Rev | Author | Line No. | Line |
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1128 | serge | 1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
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3 | * Copyright 2008 Red Hat Inc. |
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4 | * Copyright 2009 Jerome Glisse. |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the "Software"), |
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8 | * to deal in the Software without restriction, including without limitation |
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9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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10 | * and/or sell copies of the Software, and to permit persons to whom the |
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11 | * Software is furnished to do so, subject to the following conditions: |
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12 | * |
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13 | * The above copyright notice and this permission notice shall be included in |
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14 | * all copies or substantial portions of the Software. |
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15 | * |
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16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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22 | * OTHER DEALINGS IN THE SOFTWARE. |
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23 | * |
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24 | * Authors: Dave Airlie |
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25 | * Alex Deucher |
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26 | * Jerome Glisse |
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27 | */ |
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1179 | serge | 28 | #include |
29 | #include |
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1128 | serge | 30 | #include "radeon.h" |
1221 | serge | 31 | #include "rs400d.h" |
1128 | serge | 32 | |
1221 | serge | 33 | /* This files gather functions specifics to : rs400,rs480 */ |
34 | static int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev); |
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1128 | serge | 35 | |
36 | void rs400_gart_adjust_size(struct radeon_device *rdev) |
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37 | { |
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38 | /* Check gart size */ |
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39 | switch (rdev->mc.gtt_size/(1024*1024)) { |
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40 | case 32: |
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41 | case 64: |
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42 | case 128: |
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43 | case 256: |
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44 | case 512: |
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45 | case 1024: |
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46 | case 2048: |
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47 | break; |
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48 | default: |
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49 | DRM_ERROR("Unable to use IGP GART size %uM\n", |
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1179 | serge | 50 | (unsigned)(rdev->mc.gtt_size >> 20)); |
1128 | serge | 51 | DRM_ERROR("Valid GART size for IGP are 32M,64M,128M,256M,512M,1G,2G\n"); |
52 | DRM_ERROR("Forcing to 32M GART size\n"); |
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53 | rdev->mc.gtt_size = 32 * 1024 * 1024; |
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54 | return; |
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55 | } |
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56 | if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) { |
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57 | /* FIXME: RS400 & RS480 seems to have issue with GART size |
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58 | * if 4G of system memory (needs more testing) */ |
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59 | rdev->mc.gtt_size = 32 * 1024 * 1024; |
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60 | DRM_ERROR("Forcing to 32M GART size (because of ASIC bug ?)\n"); |
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61 | } |
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62 | } |
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63 | |||
64 | void rs400_gart_tlb_flush(struct radeon_device *rdev) |
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65 | { |
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66 | uint32_t tmp; |
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67 | unsigned int timeout = rdev->usec_timeout; |
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68 | |||
69 | WREG32_MC(RS480_GART_CACHE_CNTRL, RS480_GART_CACHE_INVALIDATE); |
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70 | do { |
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71 | tmp = RREG32_MC(RS480_GART_CACHE_CNTRL); |
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72 | if ((tmp & RS480_GART_CACHE_INVALIDATE) == 0) |
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73 | break; |
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74 | DRM_UDELAY(1); |
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75 | timeout--; |
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76 | } while (timeout > 0); |
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77 | WREG32_MC(RS480_GART_CACHE_CNTRL, 0); |
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78 | } |
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79 | |||
1179 | serge | 80 | int rs400_gart_init(struct radeon_device *rdev) |
1128 | serge | 81 | { |
82 | int r; |
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83 | |||
1179 | serge | 84 | if (rdev->gart.table.ram.ptr) { |
85 | WARN(1, "RS400 GART already initialized.\n"); |
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86 | return 0; |
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87 | } |
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88 | /* Check gart size */ |
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89 | switch(rdev->mc.gtt_size / (1024 * 1024)) { |
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90 | case 32: |
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91 | case 64: |
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92 | case 128: |
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93 | case 256: |
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94 | case 512: |
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95 | case 1024: |
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96 | case 2048: |
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97 | break; |
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98 | default: |
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99 | return -EINVAL; |
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100 | } |
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1128 | serge | 101 | /* Initialize common gart structure */ |
102 | r = radeon_gart_init(rdev); |
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1179 | serge | 103 | if (r) |
1128 | serge | 104 | return r; |
1179 | serge | 105 | if (rs400_debugfs_pcie_gart_info_init(rdev)) |
1128 | serge | 106 | DRM_ERROR("Failed to register debugfs file for RS400 GART !\n"); |
1179 | serge | 107 | rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; |
108 | return radeon_gart_table_ram_alloc(rdev); |
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109 | } |
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1128 | serge | 110 | |
1179 | serge | 111 | int rs400_gart_enable(struct radeon_device *rdev) |
112 | { |
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113 | uint32_t size_reg; |
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114 | uint32_t tmp; |
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115 | |||
1430 | serge | 116 | radeon_gart_restore(rdev); |
1128 | serge | 117 | tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH); |
118 | tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS; |
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119 | WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp); |
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120 | /* Check gart size */ |
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121 | switch(rdev->mc.gtt_size / (1024 * 1024)) { |
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122 | case 32: |
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123 | size_reg = RS480_VA_SIZE_32MB; |
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124 | break; |
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125 | case 64: |
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126 | size_reg = RS480_VA_SIZE_64MB; |
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127 | break; |
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128 | case 128: |
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129 | size_reg = RS480_VA_SIZE_128MB; |
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130 | break; |
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131 | case 256: |
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132 | size_reg = RS480_VA_SIZE_256MB; |
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133 | break; |
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134 | case 512: |
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135 | size_reg = RS480_VA_SIZE_512MB; |
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136 | break; |
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137 | case 1024: |
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138 | size_reg = RS480_VA_SIZE_1GB; |
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139 | break; |
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140 | case 2048: |
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141 | size_reg = RS480_VA_SIZE_2GB; |
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142 | break; |
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143 | default: |
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144 | return -EINVAL; |
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145 | } |
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146 | /* It should be fine to program it to max value */ |
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147 | if (rdev->family == CHIP_RS690 || (rdev->family == CHIP_RS740)) { |
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148 | WREG32_MC(RS690_MCCFG_AGP_BASE, 0xFFFFFFFF); |
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149 | WREG32_MC(RS690_MCCFG_AGP_BASE_2, 0); |
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150 | } else { |
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151 | WREG32(RADEON_AGP_BASE, 0xFFFFFFFF); |
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152 | WREG32(RS480_AGP_BASE_2, 0); |
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153 | } |
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1430 | serge | 154 | tmp = REG_SET(RS690_MC_AGP_TOP, rdev->mc.gtt_end >> 16); |
155 | tmp |= REG_SET(RS690_MC_AGP_START, rdev->mc.gtt_start >> 16); |
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1128 | serge | 156 | if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) { |
157 | WREG32_MC(RS690_MCCFG_AGP_LOCATION, tmp); |
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158 | tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS; |
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159 | WREG32(RADEON_BUS_CNTL, tmp); |
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160 | } else { |
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161 | WREG32(RADEON_MC_AGP_LOCATION, tmp); |
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162 | tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS; |
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163 | WREG32(RADEON_BUS_CNTL, tmp); |
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164 | } |
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165 | /* Table should be in 32bits address space so ignore bits above. */ |
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1179 | serge | 166 | tmp = (u32)rdev->gart.table_addr & 0xfffff000; |
167 | tmp |= (upper_32_bits(rdev->gart.table_addr) & 0xff) << 4; |
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168 | |||
1128 | serge | 169 | WREG32_MC(RS480_GART_BASE, tmp); |
170 | /* TODO: more tweaking here */ |
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171 | WREG32_MC(RS480_GART_FEATURE_ID, |
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172 | (RS480_TLB_ENABLE | |
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173 | RS480_GTW_LAC_EN | RS480_1LEVEL_GART)); |
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174 | /* Disable snooping */ |
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175 | WREG32_MC(RS480_AGP_MODE_CNTL, |
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176 | (1 << RS480_REQ_TYPE_SNOOP_SHIFT) | RS480_REQ_TYPE_SNOOP_DIS); |
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177 | /* Disable AGP mode */ |
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178 | /* FIXME: according to doc we should set HIDE_MMCFG_BAR=0, |
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179 | * AGPMODE30=0 & AGP30ENHANCED=0 in NB_CNTL */ |
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180 | if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) { |
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181 | WREG32_MC(RS480_MC_MISC_CNTL, |
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182 | (RS480_GART_INDEX_REG_EN | RS690_BLOCK_GFX_D3_EN)); |
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183 | } else { |
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184 | WREG32_MC(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN); |
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185 | } |
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186 | /* Enable gart */ |
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187 | WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN | size_reg)); |
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188 | rs400_gart_tlb_flush(rdev); |
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189 | rdev->gart.ready = true; |
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190 | return 0; |
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191 | } |
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192 | |||
193 | void rs400_gart_disable(struct radeon_device *rdev) |
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194 | { |
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195 | uint32_t tmp; |
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196 | |||
197 | tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH); |
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198 | tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS; |
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199 | WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp); |
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200 | WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, 0); |
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201 | } |
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202 | |||
1179 | serge | 203 | void rs400_gart_fini(struct radeon_device *rdev) |
204 | { |
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205 | rs400_gart_disable(rdev); |
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206 | radeon_gart_table_ram_free(rdev); |
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207 | radeon_gart_fini(rdev); |
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208 | } |
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209 | |||
1128 | serge | 210 | int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) |
211 | { |
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1179 | serge | 212 | uint32_t entry; |
213 | |||
1128 | serge | 214 | if (i < 0 || i > rdev->gart.num_gpu_pages) { |
215 | return -EINVAL; |
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216 | } |
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1179 | serge | 217 | |
218 | entry = (lower_32_bits(addr) & PAGE_MASK) | |
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219 | ((upper_32_bits(addr) & 0xff) << 4) | |
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220 | 0xc; |
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221 | entry = cpu_to_le32(entry); |
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222 | rdev->gart.table.ram.ptr[i] = entry; |
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1128 | serge | 223 | return 0; |
224 | } |
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225 | |||
1404 | serge | 226 | int rs400_mc_wait_for_idle(struct radeon_device *rdev) |
227 | { |
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228 | unsigned i; |
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229 | uint32_t tmp; |
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230 | |||
231 | for (i = 0; i < rdev->usec_timeout; i++) { |
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232 | /* read MC_STATUS */ |
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233 | tmp = RREG32(0x0150); |
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234 | if (tmp & (1 << 2)) { |
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235 | return 0; |
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236 | } |
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237 | DRM_UDELAY(1); |
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238 | } |
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239 | return -1; |
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240 | } |
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241 | |||
1128 | serge | 242 | void rs400_gpu_init(struct radeon_device *rdev) |
243 | { |
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244 | /* FIXME: HDP same place on rs400 ? */ |
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245 | r100_hdp_reset(rdev); |
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246 | /* FIXME: is this correct ? */ |
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247 | r420_pipes_init(rdev); |
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1404 | serge | 248 | if (rs400_mc_wait_for_idle(rdev)) { |
249 | printk(KERN_WARNING "rs400: Failed to wait MC idle while " |
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250 | "programming pipes. Bad things might happen. %08x\n", RREG32(0x150)); |
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1128 | serge | 251 | } |
252 | } |
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253 | |||
1430 | serge | 254 | void rs400_mc_init(struct radeon_device *rdev) |
1128 | serge | 255 | { |
1430 | serge | 256 | u64 base; |
257 | |||
1128 | serge | 258 | rs400_gart_adjust_size(rdev); |
1430 | serge | 259 | rdev->mc.igp_sideport_enabled = radeon_combios_sideport_present(rdev); |
1128 | serge | 260 | /* DDR for all card after R300 & IGP */ |
261 | rdev->mc.vram_is_ddr = true; |
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262 | rdev->mc.vram_width = 128; |
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1179 | serge | 263 | r100_vram_init_sizes(rdev); |
1430 | serge | 264 | base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16; |
265 | radeon_vram_location(rdev, &rdev->mc, base); |
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266 | radeon_gtt_location(rdev, &rdev->mc); |
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1128 | serge | 267 | } |
268 | |||
269 | uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg) |
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270 | { |
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271 | uint32_t r; |
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272 | |||
273 | WREG32(RS480_NB_MC_INDEX, reg & 0xff); |
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274 | r = RREG32(RS480_NB_MC_DATA); |
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275 | WREG32(RS480_NB_MC_INDEX, 0xff); |
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276 | return r; |
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277 | } |
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278 | |||
279 | void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
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280 | { |
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281 | WREG32(RS480_NB_MC_INDEX, ((reg) & 0xff) | RS480_NB_MC_IND_WR_EN); |
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282 | WREG32(RS480_NB_MC_DATA, (v)); |
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283 | WREG32(RS480_NB_MC_INDEX, 0xff); |
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284 | } |
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285 | |||
286 | #if defined(CONFIG_DEBUG_FS) |
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287 | static int rs400_debugfs_gart_info(struct seq_file *m, void *data) |
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288 | { |
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289 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
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290 | struct drm_device *dev = node->minor->dev; |
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291 | struct radeon_device *rdev = dev->dev_private; |
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292 | uint32_t tmp; |
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293 | |||
294 | tmp = RREG32(RADEON_HOST_PATH_CNTL); |
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295 | seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp); |
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296 | tmp = RREG32(RADEON_BUS_CNTL); |
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297 | seq_printf(m, "BUS_CNTL 0x%08x\n", tmp); |
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298 | tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH); |
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299 | seq_printf(m, "AIC_CTRL_SCRATCH 0x%08x\n", tmp); |
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300 | if (rdev->family == CHIP_RS690 || (rdev->family == CHIP_RS740)) { |
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301 | tmp = RREG32_MC(RS690_MCCFG_AGP_BASE); |
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302 | seq_printf(m, "MCCFG_AGP_BASE 0x%08x\n", tmp); |
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303 | tmp = RREG32_MC(RS690_MCCFG_AGP_BASE_2); |
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304 | seq_printf(m, "MCCFG_AGP_BASE_2 0x%08x\n", tmp); |
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305 | tmp = RREG32_MC(RS690_MCCFG_AGP_LOCATION); |
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306 | seq_printf(m, "MCCFG_AGP_LOCATION 0x%08x\n", tmp); |
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307 | tmp = RREG32_MC(0x100); |
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308 | seq_printf(m, "MCCFG_FB_LOCATION 0x%08x\n", tmp); |
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309 | tmp = RREG32(0x134); |
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310 | seq_printf(m, "HDP_FB_LOCATION 0x%08x\n", tmp); |
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311 | } else { |
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312 | tmp = RREG32(RADEON_AGP_BASE); |
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313 | seq_printf(m, "AGP_BASE 0x%08x\n", tmp); |
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314 | tmp = RREG32(RS480_AGP_BASE_2); |
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315 | seq_printf(m, "AGP_BASE_2 0x%08x\n", tmp); |
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316 | tmp = RREG32(RADEON_MC_AGP_LOCATION); |
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317 | seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp); |
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318 | } |
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319 | tmp = RREG32_MC(RS480_GART_BASE); |
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320 | seq_printf(m, "GART_BASE 0x%08x\n", tmp); |
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321 | tmp = RREG32_MC(RS480_GART_FEATURE_ID); |
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322 | seq_printf(m, "GART_FEATURE_ID 0x%08x\n", tmp); |
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323 | tmp = RREG32_MC(RS480_AGP_MODE_CNTL); |
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324 | seq_printf(m, "AGP_MODE_CONTROL 0x%08x\n", tmp); |
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325 | tmp = RREG32_MC(RS480_MC_MISC_CNTL); |
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326 | seq_printf(m, "MC_MISC_CNTL 0x%08x\n", tmp); |
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327 | tmp = RREG32_MC(0x5F); |
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328 | seq_printf(m, "MC_MISC_UMA_CNTL 0x%08x\n", tmp); |
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329 | tmp = RREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE); |
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330 | seq_printf(m, "AGP_ADDRESS_SPACE_SIZE 0x%08x\n", tmp); |
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331 | tmp = RREG32_MC(RS480_GART_CACHE_CNTRL); |
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332 | seq_printf(m, "GART_CACHE_CNTRL 0x%08x\n", tmp); |
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333 | tmp = RREG32_MC(0x3B); |
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334 | seq_printf(m, "MC_GART_ERROR_ADDRESS 0x%08x\n", tmp); |
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335 | tmp = RREG32_MC(0x3C); |
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336 | seq_printf(m, "MC_GART_ERROR_ADDRESS_HI 0x%08x\n", tmp); |
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337 | tmp = RREG32_MC(0x30); |
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338 | seq_printf(m, "GART_ERROR_0 0x%08x\n", tmp); |
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339 | tmp = RREG32_MC(0x31); |
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340 | seq_printf(m, "GART_ERROR_1 0x%08x\n", tmp); |
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341 | tmp = RREG32_MC(0x32); |
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342 | seq_printf(m, "GART_ERROR_2 0x%08x\n", tmp); |
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343 | tmp = RREG32_MC(0x33); |
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344 | seq_printf(m, "GART_ERROR_3 0x%08x\n", tmp); |
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345 | tmp = RREG32_MC(0x34); |
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346 | seq_printf(m, "GART_ERROR_4 0x%08x\n", tmp); |
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347 | tmp = RREG32_MC(0x35); |
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348 | seq_printf(m, "GART_ERROR_5 0x%08x\n", tmp); |
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349 | tmp = RREG32_MC(0x36); |
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350 | seq_printf(m, "GART_ERROR_6 0x%08x\n", tmp); |
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351 | tmp = RREG32_MC(0x37); |
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352 | seq_printf(m, "GART_ERROR_7 0x%08x\n", tmp); |
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353 | return 0; |
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354 | } |
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355 | |||
356 | static struct drm_info_list rs400_gart_info_list[] = { |
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357 | {"rs400_gart_info", rs400_debugfs_gart_info, 0, NULL}, |
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358 | }; |
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359 | #endif |
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360 | |||
1221 | serge | 361 | static int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev) |
1128 | serge | 362 | { |
363 | #if defined(CONFIG_DEBUG_FS) |
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364 | return radeon_debugfs_add_files(rdev, rs400_gart_info_list, 1); |
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365 | #else |
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366 | return 0; |
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367 | #endif |
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368 | } |
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1221 | serge | 369 | |
370 | void rs400_mc_program(struct radeon_device *rdev) |
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371 | { |
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372 | struct r100_mc_save save; |
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373 | |||
374 | /* Stops all mc clients */ |
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375 | r100_mc_stop(rdev, &save); |
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376 | |||
377 | /* Wait for mc idle */ |
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1404 | serge | 378 | if (rs400_mc_wait_for_idle(rdev)) |
379 | dev_warn(rdev->dev, "rs400: Wait MC idle timeout before updating MC.\n"); |
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1221 | serge | 380 | WREG32(R_000148_MC_FB_LOCATION, |
381 | S_000148_MC_FB_START(rdev->mc.vram_start >> 16) | |
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382 | S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16)); |
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383 | |||
384 | r100_mc_resume(rdev, &save); |
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385 | } |
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386 | |||
387 | static int rs400_startup(struct radeon_device *rdev) |
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388 | { |
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389 | int r; |
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390 | |||
391 | rs400_mc_program(rdev); |
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392 | /* Resume clock */ |
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393 | r300_clock_startup(rdev); |
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394 | /* Initialize GPU configuration (# pipes, ...) */ |
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395 | rs400_gpu_init(rdev); |
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1321 | serge | 396 | r100_enable_bm(rdev); |
1221 | serge | 397 | /* Initialize GART (initialize after TTM so we can allocate |
398 | * memory through TTM but finalize after TTM) */ |
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399 | r = rs400_gart_enable(rdev); |
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400 | if (r) |
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401 | return r; |
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402 | /* Enable IRQ */ |
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403 | // r100_irq_set(rdev); |
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1403 | serge | 404 | rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); |
1221 | serge | 405 | /* 1M ring buffer */ |
1413 | serge | 406 | r = r100_cp_init(rdev, 1024 * 1024); |
407 | if (r) { |
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408 | dev_err(rdev->dev, "failled initializing CP (%d).\n", r); |
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409 | return r; |
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410 | } |
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1221 | serge | 411 | // r = r100_wb_init(rdev); |
412 | // if (r) |
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413 | // dev_err(rdev->dev, "failled initializing WB (%d).\n", r); |
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414 | // r = r100_ib_init(rdev); |
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415 | // if (r) { |
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416 | // dev_err(rdev->dev, "failled initializing IB (%d).\n", r); |
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417 | // return r; |
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418 | // } |
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419 | return 0; |
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420 | } |
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421 | |||
422 | |||
423 | |||
424 | |||
425 | int rs400_init(struct radeon_device *rdev) |
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426 | { |
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427 | int r; |
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428 | |||
429 | /* Disable VGA */ |
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430 | r100_vga_render_disable(rdev); |
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431 | /* Initialize scratch registers */ |
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432 | radeon_scratch_init(rdev); |
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433 | /* Initialize surface registers */ |
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434 | radeon_surface_init(rdev); |
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435 | /* TODO: disable VGA need to use VGA request */ |
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436 | /* BIOS*/ |
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437 | if (!radeon_get_bios(rdev)) { |
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438 | if (ASIC_IS_AVIVO(rdev)) |
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439 | return -EINVAL; |
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440 | } |
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441 | if (rdev->is_atom_bios) { |
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442 | dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n"); |
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443 | return -EINVAL; |
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444 | } else { |
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445 | r = radeon_combios_init(rdev); |
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446 | if (r) |
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447 | return r; |
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448 | } |
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449 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ |
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450 | if (radeon_gpu_reset(rdev)) { |
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451 | dev_warn(rdev->dev, |
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452 | "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", |
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453 | RREG32(R_000E40_RBBM_STATUS), |
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454 | RREG32(R_0007C0_CP_STAT)); |
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455 | } |
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456 | /* check if cards are posted or not */ |
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1321 | serge | 457 | if (radeon_boot_test_post_card(rdev) == false) |
458 | return -EINVAL; |
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459 | |||
1221 | serge | 460 | /* Initialize clocks */ |
461 | radeon_get_clock_info(rdev->ddev); |
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1403 | serge | 462 | /* Initialize power management */ |
463 | radeon_pm_init(rdev); |
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1430 | serge | 464 | /* initialize memory controller */ |
465 | rs400_mc_init(rdev); |
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1221 | serge | 466 | /* Fence driver */ |
467 | // r = radeon_fence_driver_init(rdev); |
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468 | // if (r) |
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469 | // return r; |
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470 | // r = radeon_irq_kms_init(rdev); |
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471 | // if (r) |
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472 | // return r; |
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473 | /* Memory manager */ |
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1321 | serge | 474 | r = radeon_bo_init(rdev); |
1221 | serge | 475 | if (r) |
476 | return r; |
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477 | r = rs400_gart_init(rdev); |
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478 | if (r) |
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479 | return r; |
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480 | r300_set_reg_safe(rdev); |
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481 | rdev->accel_working = true; |
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482 | r = rs400_startup(rdev); |
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483 | if (r) { |
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484 | /* Somethings want wront with the accel init stop accel */ |
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485 | dev_err(rdev->dev, "Disabling GPU acceleration\n"); |
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486 | // r100_cp_fini(rdev); |
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487 | // r100_wb_fini(rdev); |
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488 | // r100_ib_fini(rdev); |
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489 | rs400_gart_fini(rdev); |
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490 | // radeon_irq_kms_fini(rdev); |
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491 | rdev->accel_working = false; |
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492 | } |
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493 | return 0; |
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494 | }><>><>>><>>><>><> |