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1117 | serge | 1 | /* |
2 | * Copyright 2007-8 Advanced Micro Devices, Inc. |
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3 | * Copyright 2008 Red Hat Inc. |
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4 | * |
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5 | * Permission is hereby granted, free of charge, to any person obtaining a |
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6 | * copy of this software and associated documentation files (the "Software"), |
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7 | * to deal in the Software without restriction, including without limitation |
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8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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9 | * and/or sell copies of the Software, and to permit persons to whom the |
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10 | * Software is furnished to do so, subject to the following conditions: |
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11 | * |
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12 | * The above copyright notice and this permission notice shall be included in |
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13 | * all copies or substantial portions of the Software. |
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14 | * |
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15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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21 | * OTHER DEALINGS IN THE SOFTWARE. |
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22 | * |
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23 | * Authors: Dave Airlie |
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24 | * Alex Deucher |
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25 | */ |
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1123 | serge | 26 | #include "drmP.h" |
1117 | serge | 27 | #include "radeon_drm.h" |
28 | #include "radeon.h" |
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29 | |||
30 | #include "atom.h" |
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31 | #include "atom-bits.h" |
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32 | |||
33 | /* from radeon_encoder.c */ |
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34 | extern uint32_t |
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35 | radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device, |
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36 | uint8_t dac); |
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37 | extern void radeon_link_encoder_connector(struct drm_device *dev); |
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38 | extern void |
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39 | radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id, |
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40 | uint32_t supported_device); |
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41 | |||
42 | /* from radeon_connector.c */ |
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43 | extern void |
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44 | radeon_add_atom_connector(struct drm_device *dev, |
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45 | uint32_t connector_id, |
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46 | uint32_t supported_device, |
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47 | int connector_type, |
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48 | struct radeon_i2c_bus_rec *i2c_bus, |
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49 | bool linkb, uint32_t igp_lane_info); |
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50 | |||
51 | /* from radeon_legacy_encoder.c */ |
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52 | extern void |
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53 | radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id, |
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54 | uint32_t supported_device); |
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55 | |||
56 | union atom_supported_devices { |
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57 | struct _ATOM_SUPPORTED_DEVICES_INFO info; |
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58 | struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2; |
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59 | struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1; |
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60 | }; |
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61 | |||
62 | static inline struct radeon_i2c_bus_rec radeon_lookup_gpio(struct drm_device |
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63 | *dev, uint8_t id) |
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64 | { |
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65 | struct radeon_device *rdev = dev->dev_private; |
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66 | struct atom_context *ctx = rdev->mode_info.atom_context; |
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67 | ATOM_GPIO_I2C_ASSIGMENT gpio; |
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68 | struct radeon_i2c_bus_rec i2c; |
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69 | int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info); |
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70 | struct _ATOM_GPIO_I2C_INFO *i2c_info; |
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71 | uint16_t data_offset; |
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72 | |||
73 | memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec)); |
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74 | i2c.valid = false; |
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75 | |||
76 | atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset); |
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77 | |||
78 | i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset); |
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79 | |||
80 | gpio = i2c_info->asGPIO_Info[id]; |
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81 | |||
82 | i2c.mask_clk_reg = le16_to_cpu(gpio.usClkMaskRegisterIndex) * 4; |
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83 | i2c.mask_data_reg = le16_to_cpu(gpio.usDataMaskRegisterIndex) * 4; |
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84 | i2c.put_clk_reg = le16_to_cpu(gpio.usClkEnRegisterIndex) * 4; |
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85 | i2c.put_data_reg = le16_to_cpu(gpio.usDataEnRegisterIndex) * 4; |
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86 | i2c.get_clk_reg = le16_to_cpu(gpio.usClkY_RegisterIndex) * 4; |
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87 | i2c.get_data_reg = le16_to_cpu(gpio.usDataY_RegisterIndex) * 4; |
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88 | i2c.a_clk_reg = le16_to_cpu(gpio.usClkA_RegisterIndex) * 4; |
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89 | i2c.a_data_reg = le16_to_cpu(gpio.usDataA_RegisterIndex) * 4; |
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90 | i2c.mask_clk_mask = (1 << gpio.ucClkMaskShift); |
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91 | i2c.mask_data_mask = (1 << gpio.ucDataMaskShift); |
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92 | i2c.put_clk_mask = (1 << gpio.ucClkEnShift); |
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93 | i2c.put_data_mask = (1 << gpio.ucDataEnShift); |
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94 | i2c.get_clk_mask = (1 << gpio.ucClkY_Shift); |
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95 | i2c.get_data_mask = (1 << gpio.ucDataY_Shift); |
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96 | i2c.a_clk_mask = (1 << gpio.ucClkA_Shift); |
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97 | i2c.a_data_mask = (1 << gpio.ucDataA_Shift); |
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98 | i2c.valid = true; |
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99 | |||
100 | return i2c; |
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101 | } |
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102 | |||
103 | static bool radeon_atom_apply_quirks(struct drm_device *dev, |
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104 | uint32_t supported_device, |
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105 | int *connector_type, |
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106 | struct radeon_i2c_bus_rec *i2c_bus) |
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107 | { |
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108 | |||
109 | /* Asus M2A-VM HDMI board lists the DVI port as HDMI */ |
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110 | if ((dev->pdev->device == 0x791e) && |
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111 | (dev->pdev->subsystem_vendor == 0x1043) && |
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112 | (dev->pdev->subsystem_device == 0x826d)) { |
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113 | if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) && |
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114 | (supported_device == ATOM_DEVICE_DFP3_SUPPORT)) |
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115 | *connector_type = DRM_MODE_CONNECTOR_DVID; |
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116 | } |
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117 | |||
118 | /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */ |
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119 | if ((dev->pdev->device == 0x7941) && |
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120 | (dev->pdev->subsystem_vendor == 0x147b) && |
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121 | (dev->pdev->subsystem_device == 0x2412)) { |
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122 | if (*connector_type == DRM_MODE_CONNECTOR_DVII) |
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123 | return false; |
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124 | } |
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125 | |||
126 | /* Falcon NW laptop lists vga ddc line for LVDS */ |
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127 | if ((dev->pdev->device == 0x5653) && |
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128 | (dev->pdev->subsystem_vendor == 0x1462) && |
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129 | (dev->pdev->subsystem_device == 0x0291)) { |
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130 | if (*connector_type == DRM_MODE_CONNECTOR_LVDS) |
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131 | i2c_bus->valid = false; |
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132 | } |
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133 | |||
134 | /* Funky macbooks */ |
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135 | if ((dev->pdev->device == 0x71C5) && |
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136 | (dev->pdev->subsystem_vendor == 0x106b) && |
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137 | (dev->pdev->subsystem_device == 0x0080)) { |
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138 | if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) || |
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139 | (supported_device == ATOM_DEVICE_DFP2_SUPPORT)) |
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140 | return false; |
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141 | } |
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142 | |||
143 | /* some BIOSes seem to report DAC on HDMI - they hurt me with their lies */ |
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144 | if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) || |
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145 | (*connector_type == DRM_MODE_CONNECTOR_HDMIB)) { |
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146 | if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) { |
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147 | return false; |
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148 | } |
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149 | } |
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150 | |||
151 | /* ASUS HD 3600 XT board lists the DVI port as HDMI */ |
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152 | if ((dev->pdev->device == 0x9598) && |
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153 | (dev->pdev->subsystem_vendor == 0x1043) && |
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154 | (dev->pdev->subsystem_device == 0x01da)) { |
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155 | if (*connector_type == DRM_MODE_CONNECTOR_HDMIB) { |
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156 | *connector_type = DRM_MODE_CONNECTOR_DVID; |
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157 | } |
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158 | } |
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159 | |||
160 | return true; |
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161 | } |
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162 | |||
163 | const int supported_devices_connector_convert[] = { |
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164 | DRM_MODE_CONNECTOR_Unknown, |
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165 | DRM_MODE_CONNECTOR_VGA, |
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166 | DRM_MODE_CONNECTOR_DVII, |
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167 | DRM_MODE_CONNECTOR_DVID, |
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168 | DRM_MODE_CONNECTOR_DVIA, |
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169 | DRM_MODE_CONNECTOR_SVIDEO, |
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170 | DRM_MODE_CONNECTOR_Composite, |
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171 | DRM_MODE_CONNECTOR_LVDS, |
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172 | DRM_MODE_CONNECTOR_Unknown, |
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173 | DRM_MODE_CONNECTOR_Unknown, |
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174 | DRM_MODE_CONNECTOR_HDMIA, |
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175 | DRM_MODE_CONNECTOR_HDMIB, |
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176 | DRM_MODE_CONNECTOR_Unknown, |
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177 | DRM_MODE_CONNECTOR_Unknown, |
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178 | DRM_MODE_CONNECTOR_9PinDIN, |
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179 | DRM_MODE_CONNECTOR_DisplayPort |
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180 | }; |
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181 | |||
182 | const int object_connector_convert[] = { |
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183 | DRM_MODE_CONNECTOR_Unknown, |
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184 | DRM_MODE_CONNECTOR_DVII, |
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185 | DRM_MODE_CONNECTOR_DVII, |
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186 | DRM_MODE_CONNECTOR_DVID, |
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187 | DRM_MODE_CONNECTOR_DVID, |
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188 | DRM_MODE_CONNECTOR_VGA, |
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189 | DRM_MODE_CONNECTOR_Composite, |
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190 | DRM_MODE_CONNECTOR_SVIDEO, |
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191 | DRM_MODE_CONNECTOR_Unknown, |
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192 | DRM_MODE_CONNECTOR_9PinDIN, |
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193 | DRM_MODE_CONNECTOR_Unknown, |
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194 | DRM_MODE_CONNECTOR_HDMIA, |
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195 | DRM_MODE_CONNECTOR_HDMIB, |
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196 | DRM_MODE_CONNECTOR_HDMIB, |
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197 | DRM_MODE_CONNECTOR_LVDS, |
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198 | DRM_MODE_CONNECTOR_9PinDIN, |
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199 | DRM_MODE_CONNECTOR_Unknown, |
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200 | DRM_MODE_CONNECTOR_Unknown, |
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201 | DRM_MODE_CONNECTOR_Unknown, |
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202 | DRM_MODE_CONNECTOR_DisplayPort |
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203 | }; |
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204 | |||
205 | bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev) |
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206 | { |
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207 | struct radeon_device *rdev = dev->dev_private; |
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208 | struct radeon_mode_info *mode_info = &rdev->mode_info; |
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209 | struct atom_context *ctx = mode_info->atom_context; |
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210 | int index = GetIndexIntoMasterTable(DATA, Object_Header); |
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211 | uint16_t size, data_offset; |
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212 | uint8_t frev, crev, line_mux = 0; |
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213 | ATOM_CONNECTOR_OBJECT_TABLE *con_obj; |
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214 | ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj; |
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215 | ATOM_OBJECT_HEADER *obj_header; |
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216 | int i, j, path_size, device_support; |
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217 | int connector_type; |
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218 | uint16_t igp_lane_info; |
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219 | bool linkb; |
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220 | struct radeon_i2c_bus_rec ddc_bus; |
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221 | |||
222 | atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset); |
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223 | |||
224 | if (data_offset == 0) |
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225 | return false; |
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226 | |||
227 | if (crev < 2) |
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228 | return false; |
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229 | |||
230 | obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset); |
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231 | path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *) |
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232 | (ctx->bios + data_offset + |
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233 | le16_to_cpu(obj_header->usDisplayPathTableOffset)); |
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234 | con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *) |
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235 | (ctx->bios + data_offset + |
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236 | le16_to_cpu(obj_header->usConnectorObjectTableOffset)); |
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237 | device_support = le16_to_cpu(obj_header->usDeviceSupport); |
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238 | |||
239 | path_size = 0; |
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240 | for (i = 0; i < path_obj->ucNumOfDispPath; i++) { |
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241 | uint8_t *addr = (uint8_t *) path_obj->asDispPath; |
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242 | ATOM_DISPLAY_OBJECT_PATH *path; |
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243 | addr += path_size; |
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244 | path = (ATOM_DISPLAY_OBJECT_PATH *) addr; |
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245 | path_size += le16_to_cpu(path->usSize); |
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246 | linkb = false; |
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247 | |||
248 | if (device_support & le16_to_cpu(path->usDeviceTag)) { |
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249 | uint8_t con_obj_id, con_obj_num, con_obj_type; |
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250 | |||
251 | con_obj_id = |
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252 | (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK) |
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253 | >> OBJECT_ID_SHIFT; |
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254 | con_obj_num = |
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255 | (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK) |
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256 | >> ENUM_ID_SHIFT; |
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257 | con_obj_type = |
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258 | (le16_to_cpu(path->usConnObjectId) & |
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259 | OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT; |
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260 | |||
261 | if ((le16_to_cpu(path->usDeviceTag) == |
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262 | ATOM_DEVICE_TV1_SUPPORT) |
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263 | || (le16_to_cpu(path->usDeviceTag) == |
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264 | ATOM_DEVICE_TV2_SUPPORT) |
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265 | || (le16_to_cpu(path->usDeviceTag) == |
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266 | ATOM_DEVICE_CV_SUPPORT)) |
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267 | continue; |
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268 | |||
269 | if ((rdev->family == CHIP_RS780) && |
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270 | (con_obj_id == |
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271 | CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) { |
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272 | uint16_t igp_offset = 0; |
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273 | ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj; |
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274 | |||
275 | index = |
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276 | GetIndexIntoMasterTable(DATA, |
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277 | IntegratedSystemInfo); |
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278 | |||
279 | atom_parse_data_header(ctx, index, &size, &frev, |
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280 | &crev, &igp_offset); |
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281 | |||
282 | if (crev >= 2) { |
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283 | igp_obj = |
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284 | (ATOM_INTEGRATED_SYSTEM_INFO_V2 |
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285 | *) (ctx->bios + igp_offset); |
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286 | |||
287 | if (igp_obj) { |
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288 | uint32_t slot_config, ct; |
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289 | |||
290 | if (con_obj_num == 1) |
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291 | slot_config = |
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292 | igp_obj-> |
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293 | ulDDISlot1Config; |
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294 | else |
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295 | slot_config = |
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296 | igp_obj-> |
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297 | ulDDISlot2Config; |
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298 | |||
299 | ct = (slot_config >> 16) & 0xff; |
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300 | connector_type = |
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301 | object_connector_convert |
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302 | [ct]; |
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303 | igp_lane_info = |
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304 | slot_config & 0xffff; |
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305 | } else |
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306 | continue; |
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307 | } else |
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308 | continue; |
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309 | } else { |
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310 | igp_lane_info = 0; |
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311 | connector_type = |
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312 | object_connector_convert[con_obj_id]; |
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313 | } |
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314 | |||
315 | if (connector_type == DRM_MODE_CONNECTOR_Unknown) |
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316 | continue; |
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317 | |||
318 | for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); |
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319 | j++) { |
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320 | uint8_t enc_obj_id, enc_obj_num, enc_obj_type; |
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321 | |||
322 | enc_obj_id = |
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323 | (le16_to_cpu(path->usGraphicObjIds[j]) & |
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324 | OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; |
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325 | enc_obj_num = |
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326 | (le16_to_cpu(path->usGraphicObjIds[j]) & |
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327 | ENUM_ID_MASK) >> ENUM_ID_SHIFT; |
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328 | enc_obj_type = |
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329 | (le16_to_cpu(path->usGraphicObjIds[j]) & |
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330 | OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT; |
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331 | |||
332 | /* FIXME: add support for router objects */ |
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333 | if (enc_obj_type == GRAPH_OBJECT_TYPE_ENCODER) { |
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334 | if (enc_obj_num == 2) |
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335 | linkb = true; |
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336 | else |
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337 | linkb = false; |
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338 | |||
1123 | serge | 339 | radeon_add_atom_encoder(dev, |
340 | enc_obj_id, |
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341 | le16_to_cpu |
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342 | (path-> |
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343 | usDeviceTag)); |
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1117 | serge | 344 | |
345 | } |
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346 | } |
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347 | |||
348 | /* look up gpio for ddc */ |
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349 | if ((le16_to_cpu(path->usDeviceTag) & |
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350 | (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) |
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351 | == 0) { |
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352 | for (j = 0; j < con_obj->ucNumberOfObjects; j++) { |
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353 | if (le16_to_cpu(path->usConnObjectId) == |
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354 | le16_to_cpu(con_obj->asObjects[j]. |
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355 | usObjectID)) { |
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356 | ATOM_COMMON_RECORD_HEADER |
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357 | *record = |
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358 | (ATOM_COMMON_RECORD_HEADER |
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359 | *) |
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360 | (ctx->bios + data_offset + |
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361 | le16_to_cpu(con_obj-> |
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362 | asObjects[j]. |
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363 | usRecordOffset)); |
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364 | ATOM_I2C_RECORD *i2c_record; |
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365 | |||
366 | while (record->ucRecordType > 0 |
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367 | && record-> |
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368 | ucRecordType <= |
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369 | ATOM_MAX_OBJECT_RECORD_NUMBER) { |
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370 | DRM_ERROR |
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371 | ("record type %d\n", |
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372 | record-> |
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373 | ucRecordType); |
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374 | switch (record-> |
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375 | ucRecordType) { |
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376 | case ATOM_I2C_RECORD_TYPE: |
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377 | i2c_record = |
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378 | (ATOM_I2C_RECORD |
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379 | *) record; |
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380 | line_mux = |
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381 | i2c_record-> |
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382 | sucI2cId. |
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383 | bfI2C_LineMux; |
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384 | break; |
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385 | } |
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386 | record = |
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387 | (ATOM_COMMON_RECORD_HEADER |
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388 | *) ((char *)record |
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389 | + |
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390 | record-> |
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391 | ucRecordSize); |
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392 | } |
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393 | break; |
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394 | } |
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395 | } |
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396 | } else |
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397 | line_mux = 0; |
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398 | |||
399 | if ((le16_to_cpu(path->usDeviceTag) == |
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400 | ATOM_DEVICE_TV1_SUPPORT) |
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401 | || (le16_to_cpu(path->usDeviceTag) == |
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402 | ATOM_DEVICE_TV2_SUPPORT) |
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403 | || (le16_to_cpu(path->usDeviceTag) == |
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404 | ATOM_DEVICE_CV_SUPPORT)) |
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405 | ddc_bus.valid = false; |
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406 | else |
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407 | ddc_bus = radeon_lookup_gpio(dev, line_mux); |
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408 | |||
1123 | serge | 409 | radeon_add_atom_connector(dev, |
410 | le16_to_cpu(path-> |
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411 | usConnObjectId), |
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412 | le16_to_cpu(path-> |
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413 | usDeviceTag), |
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414 | connector_type, &ddc_bus, |
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415 | linkb, igp_lane_info); |
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1117 | serge | 416 | |
417 | } |
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418 | } |
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419 | |||
1123 | serge | 420 | radeon_link_encoder_connector(dev); |
1117 | serge | 421 | |
422 | return true; |
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423 | } |
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424 | |||
425 | struct bios_connector { |
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426 | bool valid; |
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427 | uint8_t line_mux; |
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428 | uint16_t devices; |
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429 | int connector_type; |
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430 | struct radeon_i2c_bus_rec ddc_bus; |
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431 | }; |
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432 | |||
433 | bool radeon_get_atom_connector_info_from_supported_devices_table(struct |
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434 | drm_device |
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435 | *dev) |
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436 | { |
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437 | struct radeon_device *rdev = dev->dev_private; |
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438 | struct radeon_mode_info *mode_info = &rdev->mode_info; |
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439 | struct atom_context *ctx = mode_info->atom_context; |
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440 | int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo); |
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441 | uint16_t size, data_offset; |
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442 | uint8_t frev, crev; |
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443 | uint16_t device_support; |
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444 | uint8_t dac; |
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445 | union atom_supported_devices *supported_devices; |
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446 | int i, j; |
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447 | struct bios_connector bios_connectors[ATOM_MAX_SUPPORTED_DEVICE]; |
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448 | |||
449 | atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset); |
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1125 | serge | 450 | ENTRY(); |
1117 | serge | 451 | supported_devices = |
452 | (union atom_supported_devices *)(ctx->bios + data_offset); |
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453 | |||
454 | device_support = le16_to_cpu(supported_devices->info.usDeviceSupport); |
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455 | |||
456 | for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) { |
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457 | ATOM_CONNECTOR_INFO_I2C ci = |
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458 | supported_devices->info.asConnInfo[i]; |
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459 | |||
460 | bios_connectors[i].valid = false; |
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461 | |||
462 | if (!(device_support & (1 << i))) { |
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463 | continue; |
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464 | } |
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465 | |||
466 | if (i == ATOM_DEVICE_CV_INDEX) { |
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467 | DRM_DEBUG("Skipping Component Video\n"); |
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468 | continue; |
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469 | } |
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470 | |||
471 | if (i == ATOM_DEVICE_TV1_INDEX) { |
||
472 | DRM_DEBUG("Skipping TV Out\n"); |
||
473 | continue; |
||
474 | } |
||
475 | |||
476 | bios_connectors[i].connector_type = |
||
477 | supported_devices_connector_convert[ci.sucConnectorInfo. |
||
478 | sbfAccess. |
||
479 | bfConnectorType]; |
||
480 | |||
481 | if (bios_connectors[i].connector_type == |
||
482 | DRM_MODE_CONNECTOR_Unknown) |
||
483 | continue; |
||
484 | |||
485 | dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC; |
||
486 | |||
487 | if ((rdev->family == CHIP_RS690) || |
||
488 | (rdev->family == CHIP_RS740)) { |
||
489 | if ((i == ATOM_DEVICE_DFP2_INDEX) |
||
490 | && (ci.sucI2cId.sbfAccess.bfI2C_LineMux == 2)) |
||
491 | bios_connectors[i].line_mux = |
||
492 | ci.sucI2cId.sbfAccess.bfI2C_LineMux + 1; |
||
493 | else if ((i == ATOM_DEVICE_DFP3_INDEX) |
||
494 | && (ci.sucI2cId.sbfAccess.bfI2C_LineMux == 1)) |
||
495 | bios_connectors[i].line_mux = |
||
496 | ci.sucI2cId.sbfAccess.bfI2C_LineMux + 1; |
||
497 | else |
||
498 | bios_connectors[i].line_mux = |
||
499 | ci.sucI2cId.sbfAccess.bfI2C_LineMux; |
||
500 | } else |
||
501 | bios_connectors[i].line_mux = |
||
502 | ci.sucI2cId.sbfAccess.bfI2C_LineMux; |
||
503 | |||
504 | /* give tv unique connector ids */ |
||
505 | if (i == ATOM_DEVICE_TV1_INDEX) { |
||
506 | bios_connectors[i].ddc_bus.valid = false; |
||
507 | bios_connectors[i].line_mux = 50; |
||
508 | } else if (i == ATOM_DEVICE_TV2_INDEX) { |
||
509 | bios_connectors[i].ddc_bus.valid = false; |
||
510 | bios_connectors[i].line_mux = 51; |
||
511 | } else if (i == ATOM_DEVICE_CV_INDEX) { |
||
512 | bios_connectors[i].ddc_bus.valid = false; |
||
513 | bios_connectors[i].line_mux = 52; |
||
514 | } else |
||
515 | bios_connectors[i].ddc_bus = |
||
516 | radeon_lookup_gpio(dev, |
||
517 | bios_connectors[i].line_mux); |
||
518 | |||
519 | /* Always set the connector type to VGA for CRT1/CRT2. if they are |
||
520 | * shared with a DVI port, we'll pick up the DVI connector when we |
||
521 | * merge the outputs. Some bioses incorrectly list VGA ports as DVI. |
||
522 | */ |
||
523 | if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX) |
||
524 | bios_connectors[i].connector_type = |
||
525 | DRM_MODE_CONNECTOR_VGA; |
||
526 | |||
527 | if (!radeon_atom_apply_quirks |
||
528 | (dev, (1 << i), &bios_connectors[i].connector_type, |
||
529 | &bios_connectors[i].ddc_bus)) |
||
530 | continue; |
||
531 | |||
532 | bios_connectors[i].valid = true; |
||
533 | bios_connectors[i].devices = (1 << i); |
||
534 | |||
1123 | serge | 535 | if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom) |
536 | radeon_add_atom_encoder(dev, |
||
537 | radeon_get_encoder_id(dev, |
||
538 | (1 << i), |
||
539 | dac), |
||
540 | (1 << i)); |
||
541 | else |
||
542 | radeon_add_legacy_encoder(dev, |
||
543 | radeon_get_encoder_id(dev, |
||
544 | (1 << |
||
545 | i), |
||
546 | dac), |
||
547 | (1 << i)); |
||
1117 | serge | 548 | } |
549 | |||
550 | /* combine shared connectors */ |
||
551 | for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) { |
||
552 | if (bios_connectors[i].valid) { |
||
553 | for (j = 0; j < ATOM_MAX_SUPPORTED_DEVICE; j++) { |
||
554 | if (bios_connectors[j].valid && (i != j)) { |
||
555 | if (bios_connectors[i].line_mux == |
||
556 | bios_connectors[j].line_mux) { |
||
557 | if (((bios_connectors[i]. |
||
558 | devices & |
||
559 | (ATOM_DEVICE_DFP_SUPPORT)) |
||
560 | && (bios_connectors[j]. |
||
561 | devices & |
||
562 | (ATOM_DEVICE_CRT_SUPPORT))) |
||
563 | || |
||
564 | ((bios_connectors[j]. |
||
565 | devices & |
||
566 | (ATOM_DEVICE_DFP_SUPPORT)) |
||
567 | && (bios_connectors[i]. |
||
568 | devices & |
||
569 | (ATOM_DEVICE_CRT_SUPPORT)))) { |
||
570 | bios_connectors[i]. |
||
571 | devices |= |
||
572 | bios_connectors[j]. |
||
573 | devices; |
||
574 | bios_connectors[i]. |
||
575 | connector_type = |
||
576 | DRM_MODE_CONNECTOR_DVII; |
||
577 | bios_connectors[j]. |
||
578 | valid = false; |
||
579 | } |
||
580 | } |
||
581 | } |
||
582 | } |
||
583 | } |
||
584 | } |
||
585 | |||
586 | /* add the connectors */ |
||
1123 | serge | 587 | for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) { |
588 | if (bios_connectors[i].valid) |
||
589 | radeon_add_atom_connector(dev, |
||
590 | bios_connectors[i].line_mux, |
||
591 | bios_connectors[i].devices, |
||
592 | bios_connectors[i]. |
||
593 | connector_type, |
||
594 | &bios_connectors[i].ddc_bus, |
||
595 | false, 0); |
||
596 | } |
||
1117 | serge | 597 | |
1123 | serge | 598 | radeon_link_encoder_connector(dev); |
1125 | serge | 599 | LEAVE(); |
1117 | serge | 600 | return true; |
601 | } |
||
602 | |||
603 | union firmware_info { |
||
604 | ATOM_FIRMWARE_INFO info; |
||
605 | ATOM_FIRMWARE_INFO_V1_2 info_12; |
||
606 | ATOM_FIRMWARE_INFO_V1_3 info_13; |
||
607 | ATOM_FIRMWARE_INFO_V1_4 info_14; |
||
608 | }; |
||
609 | |||
610 | bool radeon_atom_get_clock_info(struct drm_device *dev) |
||
611 | { |
||
612 | struct radeon_device *rdev = dev->dev_private; |
||
613 | struct radeon_mode_info *mode_info = &rdev->mode_info; |
||
614 | int index = GetIndexIntoMasterTable(DATA, FirmwareInfo); |
||
615 | union firmware_info *firmware_info; |
||
616 | uint8_t frev, crev; |
||
617 | struct radeon_pll *p1pll = &rdev->clock.p1pll; |
||
618 | struct radeon_pll *p2pll = &rdev->clock.p2pll; |
||
619 | struct radeon_pll *spll = &rdev->clock.spll; |
||
620 | struct radeon_pll *mpll = &rdev->clock.mpll; |
||
621 | uint16_t data_offset; |
||
622 | |||
623 | atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, |
||
624 | &crev, &data_offset); |
||
625 | |||
626 | firmware_info = |
||
627 | (union firmware_info *)(mode_info->atom_context->bios + |
||
628 | data_offset); |
||
629 | |||
630 | if (firmware_info) { |
||
631 | /* pixel clocks */ |
||
632 | p1pll->reference_freq = |
||
633 | le16_to_cpu(firmware_info->info.usReferenceClock); |
||
634 | p1pll->reference_div = 0; |
||
635 | |||
636 | p1pll->pll_out_min = |
||
637 | le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output); |
||
638 | p1pll->pll_out_max = |
||
639 | le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output); |
||
640 | |||
641 | if (p1pll->pll_out_min == 0) { |
||
642 | if (ASIC_IS_AVIVO(rdev)) |
||
643 | p1pll->pll_out_min = 64800; |
||
644 | else |
||
645 | p1pll->pll_out_min = 20000; |
||
646 | } |
||
647 | |||
648 | p1pll->pll_in_min = |
||
649 | le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input); |
||
650 | p1pll->pll_in_max = |
||
651 | le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input); |
||
652 | |||
653 | *p2pll = *p1pll; |
||
654 | |||
655 | /* system clock */ |
||
656 | spll->reference_freq = |
||
657 | le16_to_cpu(firmware_info->info.usReferenceClock); |
||
658 | spll->reference_div = 0; |
||
659 | |||
660 | spll->pll_out_min = |
||
661 | le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output); |
||
662 | spll->pll_out_max = |
||
663 | le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output); |
||
664 | |||
665 | /* ??? */ |
||
666 | if (spll->pll_out_min == 0) { |
||
667 | if (ASIC_IS_AVIVO(rdev)) |
||
668 | spll->pll_out_min = 64800; |
||
669 | else |
||
670 | spll->pll_out_min = 20000; |
||
671 | } |
||
672 | |||
673 | spll->pll_in_min = |
||
674 | le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input); |
||
675 | spll->pll_in_max = |
||
676 | le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input); |
||
677 | |||
678 | /* memory clock */ |
||
679 | mpll->reference_freq = |
||
680 | le16_to_cpu(firmware_info->info.usReferenceClock); |
||
681 | mpll->reference_div = 0; |
||
682 | |||
683 | mpll->pll_out_min = |
||
684 | le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output); |
||
685 | mpll->pll_out_max = |
||
686 | le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output); |
||
687 | |||
688 | /* ??? */ |
||
689 | if (mpll->pll_out_min == 0) { |
||
690 | if (ASIC_IS_AVIVO(rdev)) |
||
691 | mpll->pll_out_min = 64800; |
||
692 | else |
||
693 | mpll->pll_out_min = 20000; |
||
694 | } |
||
695 | |||
696 | mpll->pll_in_min = |
||
697 | le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input); |
||
698 | mpll->pll_in_max = |
||
699 | le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input); |
||
700 | |||
701 | rdev->clock.default_sclk = |
||
702 | le32_to_cpu(firmware_info->info.ulDefaultEngineClock); |
||
703 | rdev->clock.default_mclk = |
||
704 | le32_to_cpu(firmware_info->info.ulDefaultMemoryClock); |
||
705 | |||
706 | return true; |
||
707 | } |
||
708 | return false; |
||
709 | } |
||
710 | |||
711 | struct radeon_encoder_int_tmds *radeon_atombios_get_tmds_info(struct |
||
712 | radeon_encoder |
||
713 | *encoder) |
||
714 | { |
||
715 | struct drm_device *dev = encoder->base.dev; |
||
716 | struct radeon_device *rdev = dev->dev_private; |
||
717 | struct radeon_mode_info *mode_info = &rdev->mode_info; |
||
718 | int index = GetIndexIntoMasterTable(DATA, TMDS_Info); |
||
719 | uint16_t data_offset; |
||
720 | struct _ATOM_TMDS_INFO *tmds_info; |
||
721 | uint8_t frev, crev; |
||
722 | uint16_t maxfreq; |
||
723 | int i; |
||
724 | struct radeon_encoder_int_tmds *tmds = NULL; |
||
725 | |||
726 | atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, |
||
727 | &crev, &data_offset); |
||
728 | |||
729 | tmds_info = |
||
730 | (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios + |
||
731 | data_offset); |
||
732 | |||
733 | if (tmds_info) { |
||
734 | tmds = |
||
735 | kzalloc(sizeof(struct radeon_encoder_int_tmds), GFP_KERNEL); |
||
736 | |||
737 | if (!tmds) |
||
738 | return NULL; |
||
739 | |||
740 | maxfreq = le16_to_cpu(tmds_info->usMaxFrequency); |
||
741 | for (i = 0; i < 4; i++) { |
||
742 | tmds->tmds_pll[i].freq = |
||
743 | le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency); |
||
744 | tmds->tmds_pll[i].value = |
||
745 | tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f; |
||
746 | tmds->tmds_pll[i].value |= |
||
747 | (tmds_info->asMiscInfo[i]. |
||
748 | ucPLL_VCO_Gain & 0x3f) << 6; |
||
749 | tmds->tmds_pll[i].value |= |
||
750 | (tmds_info->asMiscInfo[i]. |
||
751 | ucPLL_DutyCycle & 0xf) << 12; |
||
752 | tmds->tmds_pll[i].value |= |
||
753 | (tmds_info->asMiscInfo[i]. |
||
754 | ucPLL_VoltageSwing & 0xf) << 16; |
||
755 | |||
756 | DRM_DEBUG("TMDS PLL From ATOMBIOS %u %x\n", |
||
757 | tmds->tmds_pll[i].freq, |
||
758 | tmds->tmds_pll[i].value); |
||
759 | |||
760 | if (maxfreq == tmds->tmds_pll[i].freq) { |
||
761 | tmds->tmds_pll[i].freq = 0xffffffff; |
||
762 | break; |
||
763 | } |
||
764 | } |
||
765 | } |
||
766 | return tmds; |
||
767 | } |
||
768 | |||
769 | union lvds_info { |
||
770 | struct _ATOM_LVDS_INFO info; |
||
771 | struct _ATOM_LVDS_INFO_V12 info_12; |
||
772 | }; |
||
773 | |||
774 | struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct |
||
775 | radeon_encoder |
||
776 | *encoder) |
||
777 | { |
||
778 | struct drm_device *dev = encoder->base.dev; |
||
779 | struct radeon_device *rdev = dev->dev_private; |
||
780 | struct radeon_mode_info *mode_info = &rdev->mode_info; |
||
781 | int index = GetIndexIntoMasterTable(DATA, LVDS_Info); |
||
782 | uint16_t data_offset; |
||
783 | union lvds_info *lvds_info; |
||
784 | uint8_t frev, crev; |
||
785 | struct radeon_encoder_atom_dig *lvds = NULL; |
||
786 | |||
787 | atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, |
||
788 | &crev, &data_offset); |
||
789 | |||
790 | lvds_info = |
||
791 | (union lvds_info *)(mode_info->atom_context->bios + data_offset); |
||
792 | |||
793 | if (lvds_info) { |
||
794 | lvds = |
||
795 | kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL); |
||
796 | |||
797 | if (!lvds) |
||
798 | return NULL; |
||
799 | |||
800 | lvds->native_mode.dotclock = |
||
801 | le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10; |
||
802 | lvds->native_mode.panel_xres = |
||
803 | le16_to_cpu(lvds_info->info.sLCDTiming.usHActive); |
||
804 | lvds->native_mode.panel_yres = |
||
805 | le16_to_cpu(lvds_info->info.sLCDTiming.usVActive); |
||
806 | lvds->native_mode.hblank = |
||
807 | le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time); |
||
808 | lvds->native_mode.hoverplus = |
||
809 | le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset); |
||
810 | lvds->native_mode.hsync_width = |
||
811 | le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth); |
||
812 | lvds->native_mode.vblank = |
||
813 | le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time); |
||
814 | lvds->native_mode.voverplus = |
||
815 | le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset); |
||
816 | lvds->native_mode.vsync_width = |
||
817 | le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth); |
||
818 | lvds->panel_pwr_delay = |
||
819 | le16_to_cpu(lvds_info->info.usOffDelayInMs); |
||
820 | lvds->lvds_misc = lvds_info->info.ucLVDS_Misc; |
||
821 | |||
822 | encoder->native_mode = lvds->native_mode; |
||
823 | } |
||
824 | return lvds; |
||
825 | } |
||
826 | |||
827 | struct radeon_encoder_primary_dac * |
||
828 | radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder) |
||
829 | { |
||
830 | struct drm_device *dev = encoder->base.dev; |
||
831 | struct radeon_device *rdev = dev->dev_private; |
||
832 | struct radeon_mode_info *mode_info = &rdev->mode_info; |
||
833 | int index = GetIndexIntoMasterTable(DATA, CompassionateData); |
||
834 | uint16_t data_offset; |
||
835 | struct _COMPASSIONATE_DATA *dac_info; |
||
836 | uint8_t frev, crev; |
||
837 | uint8_t bg, dac; |
||
838 | struct radeon_encoder_primary_dac *p_dac = NULL; |
||
839 | |||
840 | atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset); |
||
841 | |||
842 | dac_info = (struct _COMPASSIONATE_DATA *)(mode_info->atom_context->bios + data_offset); |
||
843 | |||
844 | if (dac_info) { |
||
845 | p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL); |
||
846 | |||
847 | if (!p_dac) |
||
848 | return NULL; |
||
849 | |||
850 | bg = dac_info->ucDAC1_BG_Adjustment; |
||
851 | dac = dac_info->ucDAC1_DAC_Adjustment; |
||
852 | p_dac->ps2_pdac_adj = (bg << 8) | (dac); |
||
853 | |||
854 | } |
||
855 | return p_dac; |
||
856 | } |
||
857 | |||
858 | struct radeon_encoder_tv_dac * |
||
859 | radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder) |
||
860 | { |
||
861 | struct drm_device *dev = encoder->base.dev; |
||
862 | struct radeon_device *rdev = dev->dev_private; |
||
863 | struct radeon_mode_info *mode_info = &rdev->mode_info; |
||
864 | int index = GetIndexIntoMasterTable(DATA, CompassionateData); |
||
865 | uint16_t data_offset; |
||
866 | struct _COMPASSIONATE_DATA *dac_info; |
||
867 | uint8_t frev, crev; |
||
868 | uint8_t bg, dac; |
||
869 | struct radeon_encoder_tv_dac *tv_dac = NULL; |
||
870 | |||
871 | atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset); |
||
872 | |||
873 | dac_info = (struct _COMPASSIONATE_DATA *)(mode_info->atom_context->bios + data_offset); |
||
874 | |||
875 | if (dac_info) { |
||
876 | tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL); |
||
877 | |||
878 | if (!tv_dac) |
||
879 | return NULL; |
||
880 | |||
881 | bg = dac_info->ucDAC2_CRT2_BG_Adjustment; |
||
882 | dac = dac_info->ucDAC2_CRT2_DAC_Adjustment; |
||
883 | tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20); |
||
884 | |||
885 | bg = dac_info->ucDAC2_PAL_BG_Adjustment; |
||
886 | dac = dac_info->ucDAC2_PAL_DAC_Adjustment; |
||
887 | tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20); |
||
888 | |||
889 | bg = dac_info->ucDAC2_NTSC_BG_Adjustment; |
||
890 | dac = dac_info->ucDAC2_NTSC_DAC_Adjustment; |
||
891 | tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20); |
||
892 | |||
893 | } |
||
894 | return tv_dac; |
||
895 | } |
||
896 | |||
897 | void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable) |
||
898 | { |
||
899 | DYNAMIC_CLOCK_GATING_PS_ALLOCATION args; |
||
900 | int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating); |
||
901 | |||
902 | args.ucEnable = enable; |
||
903 | |||
904 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
||
905 | } |
||
906 | |||
907 | void radeon_atom_static_pwrmgt_setup(struct radeon_device *rdev, int enable) |
||
908 | { |
||
909 | ENABLE_ASIC_STATIC_PWR_MGT_PS_ALLOCATION args; |
||
910 | int index = GetIndexIntoMasterTable(COMMAND, EnableASIC_StaticPwrMgt); |
||
911 | |||
912 | args.ucEnable = enable; |
||
913 | |||
914 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
||
915 | } |
||
916 | |||
917 | void radeon_atom_set_engine_clock(struct radeon_device *rdev, |
||
918 | uint32_t eng_clock) |
||
919 | { |
||
920 | SET_ENGINE_CLOCK_PS_ALLOCATION args; |
||
921 | int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock); |
||
922 | |||
923 | args.ulTargetEngineClock = eng_clock; /* 10 khz */ |
||
924 | |||
925 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
||
926 | } |
||
927 | |||
928 | void radeon_atom_set_memory_clock(struct radeon_device *rdev, |
||
929 | uint32_t mem_clock) |
||
930 | { |
||
931 | SET_MEMORY_CLOCK_PS_ALLOCATION args; |
||
932 | int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock); |
||
933 | |||
934 | if (rdev->flags & RADEON_IS_IGP) |
||
935 | return; |
||
936 | |||
937 | args.ulTargetMemoryClock = mem_clock; /* 10 khz */ |
||
938 | |||
939 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
||
940 | } |
||
941 | |||
942 | void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev) |
||
943 | { |
||
944 | struct radeon_device *rdev = dev->dev_private; |
||
945 | uint32_t bios_2_scratch, bios_6_scratch; |
||
946 | |||
1120 | serge | 947 | dbgprintf("%s\n",__FUNCTION__); |
1117 | serge | 948 | |
949 | if (rdev->family >= CHIP_R600) { |
||
950 | bios_2_scratch = RREG32(R600_BIOS_0_SCRATCH); |
||
951 | bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH); |
||
952 | } else { |
||
953 | bios_2_scratch = RREG32(RADEON_BIOS_0_SCRATCH); |
||
954 | bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); |
||
955 | } |
||
956 | |||
957 | /* let the bios control the backlight */ |
||
958 | bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE; |
||
959 | |||
960 | /* tell the bios not to handle mode switching */ |
||
961 | bios_6_scratch |= (ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH | ATOM_S6_ACC_MODE); |
||
962 | |||
963 | if (rdev->family >= CHIP_R600) { |
||
964 | WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch); |
||
965 | WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch); |
||
966 | } else { |
||
967 | WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch); |
||
968 | WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); |
||
969 | } |
||
970 | |||
971 | } |
||
972 | |||
973 | void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock) |
||
974 | { |
||
975 | struct drm_device *dev = encoder->dev; |
||
976 | struct radeon_device *rdev = dev->dev_private; |
||
977 | uint32_t bios_6_scratch; |
||
978 | |||
979 | if (rdev->family >= CHIP_R600) |
||
980 | bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH); |
||
981 | else |
||
982 | bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); |
||
983 | |||
984 | if (lock) |
||
985 | bios_6_scratch |= ATOM_S6_CRITICAL_STATE; |
||
986 | else |
||
987 | bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE; |
||
988 | |||
989 | if (rdev->family >= CHIP_R600) |
||
990 | WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch); |
||
991 | else |
||
992 | WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); |
||
993 | } |
||
994 | |||
995 | /* at some point we may want to break this out into individual functions */ |
||
996 | void |
||
997 | radeon_atombios_connected_scratch_regs(struct drm_connector *connector, |
||
998 | struct drm_encoder *encoder, |
||
999 | bool connected) |
||
1000 | { |
||
1001 | struct drm_device *dev = connector->dev; |
||
1002 | struct radeon_device *rdev = dev->dev_private; |
||
1003 | struct radeon_connector *radeon_connector = |
||
1004 | to_radeon_connector(connector); |
||
1005 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
||
1006 | uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch; |
||
1007 | |||
1008 | if (rdev->family >= CHIP_R600) { |
||
1009 | bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH); |
||
1010 | bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH); |
||
1011 | bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH); |
||
1012 | } else { |
||
1013 | bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH); |
||
1014 | bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH); |
||
1015 | bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); |
||
1016 | } |
||
1017 | |||
1018 | if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) && |
||
1019 | (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) { |
||
1020 | if (connected) { |
||
1021 | DRM_DEBUG("TV1 connected\n"); |
||
1022 | bios_3_scratch |= ATOM_S3_TV1_ACTIVE; |
||
1023 | bios_6_scratch |= ATOM_S6_ACC_REQ_TV1; |
||
1024 | } else { |
||
1025 | DRM_DEBUG("TV1 disconnected\n"); |
||
1026 | bios_0_scratch &= ~ATOM_S0_TV1_MASK; |
||
1027 | bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE; |
||
1028 | bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1; |
||
1029 | } |
||
1030 | } |
||
1031 | if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) && |
||
1032 | (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) { |
||
1033 | if (connected) { |
||
1034 | DRM_DEBUG("CV connected\n"); |
||
1035 | bios_3_scratch |= ATOM_S3_CV_ACTIVE; |
||
1036 | bios_6_scratch |= ATOM_S6_ACC_REQ_CV; |
||
1037 | } else { |
||
1038 | DRM_DEBUG("CV disconnected\n"); |
||
1039 | bios_0_scratch &= ~ATOM_S0_CV_MASK; |
||
1040 | bios_3_scratch &= ~ATOM_S3_CV_ACTIVE; |
||
1041 | bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV; |
||
1042 | } |
||
1043 | } |
||
1044 | if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) && |
||
1045 | (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) { |
||
1046 | if (connected) { |
||
1047 | DRM_DEBUG("LCD1 connected\n"); |
||
1048 | bios_0_scratch |= ATOM_S0_LCD1; |
||
1049 | bios_3_scratch |= ATOM_S3_LCD1_ACTIVE; |
||
1050 | bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1; |
||
1051 | } else { |
||
1052 | DRM_DEBUG("LCD1 disconnected\n"); |
||
1053 | bios_0_scratch &= ~ATOM_S0_LCD1; |
||
1054 | bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE; |
||
1055 | bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1; |
||
1056 | } |
||
1057 | } |
||
1058 | if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) && |
||
1059 | (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) { |
||
1060 | if (connected) { |
||
1061 | DRM_DEBUG("CRT1 connected\n"); |
||
1062 | bios_0_scratch |= ATOM_S0_CRT1_COLOR; |
||
1063 | bios_3_scratch |= ATOM_S3_CRT1_ACTIVE; |
||
1064 | bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1; |
||
1065 | } else { |
||
1066 | DRM_DEBUG("CRT1 disconnected\n"); |
||
1067 | bios_0_scratch &= ~ATOM_S0_CRT1_MASK; |
||
1068 | bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE; |
||
1069 | bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1; |
||
1070 | } |
||
1071 | } |
||
1072 | if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) && |
||
1073 | (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) { |
||
1074 | if (connected) { |
||
1075 | DRM_DEBUG("CRT2 connected\n"); |
||
1076 | bios_0_scratch |= ATOM_S0_CRT2_COLOR; |
||
1077 | bios_3_scratch |= ATOM_S3_CRT2_ACTIVE; |
||
1078 | bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2; |
||
1079 | } else { |
||
1080 | DRM_DEBUG("CRT2 disconnected\n"); |
||
1081 | bios_0_scratch &= ~ATOM_S0_CRT2_MASK; |
||
1082 | bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE; |
||
1083 | bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2; |
||
1084 | } |
||
1085 | } |
||
1086 | if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) && |
||
1087 | (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) { |
||
1088 | if (connected) { |
||
1089 | DRM_DEBUG("DFP1 connected\n"); |
||
1090 | bios_0_scratch |= ATOM_S0_DFP1; |
||
1091 | bios_3_scratch |= ATOM_S3_DFP1_ACTIVE; |
||
1092 | bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1; |
||
1093 | } else { |
||
1094 | DRM_DEBUG("DFP1 disconnected\n"); |
||
1095 | bios_0_scratch &= ~ATOM_S0_DFP1; |
||
1096 | bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE; |
||
1097 | bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1; |
||
1098 | } |
||
1099 | } |
||
1100 | if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) && |
||
1101 | (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) { |
||
1102 | if (connected) { |
||
1103 | DRM_DEBUG("DFP2 connected\n"); |
||
1104 | bios_0_scratch |= ATOM_S0_DFP2; |
||
1105 | bios_3_scratch |= ATOM_S3_DFP2_ACTIVE; |
||
1106 | bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2; |
||
1107 | } else { |
||
1108 | DRM_DEBUG("DFP2 disconnected\n"); |
||
1109 | bios_0_scratch &= ~ATOM_S0_DFP2; |
||
1110 | bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE; |
||
1111 | bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2; |
||
1112 | } |
||
1113 | } |
||
1114 | if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) && |
||
1115 | (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) { |
||
1116 | if (connected) { |
||
1117 | DRM_DEBUG("DFP3 connected\n"); |
||
1118 | bios_0_scratch |= ATOM_S0_DFP3; |
||
1119 | bios_3_scratch |= ATOM_S3_DFP3_ACTIVE; |
||
1120 | bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3; |
||
1121 | } else { |
||
1122 | DRM_DEBUG("DFP3 disconnected\n"); |
||
1123 | bios_0_scratch &= ~ATOM_S0_DFP3; |
||
1124 | bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE; |
||
1125 | bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3; |
||
1126 | } |
||
1127 | } |
||
1128 | if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) && |
||
1129 | (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) { |
||
1130 | if (connected) { |
||
1131 | DRM_DEBUG("DFP4 connected\n"); |
||
1132 | bios_0_scratch |= ATOM_S0_DFP4; |
||
1133 | bios_3_scratch |= ATOM_S3_DFP4_ACTIVE; |
||
1134 | bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4; |
||
1135 | } else { |
||
1136 | DRM_DEBUG("DFP4 disconnected\n"); |
||
1137 | bios_0_scratch &= ~ATOM_S0_DFP4; |
||
1138 | bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE; |
||
1139 | bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4; |
||
1140 | } |
||
1141 | } |
||
1142 | if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) && |
||
1143 | (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) { |
||
1144 | if (connected) { |
||
1145 | DRM_DEBUG("DFP5 connected\n"); |
||
1146 | bios_0_scratch |= ATOM_S0_DFP5; |
||
1147 | bios_3_scratch |= ATOM_S3_DFP5_ACTIVE; |
||
1148 | bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5; |
||
1149 | } else { |
||
1150 | DRM_DEBUG("DFP5 disconnected\n"); |
||
1151 | bios_0_scratch &= ~ATOM_S0_DFP5; |
||
1152 | bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE; |
||
1153 | bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5; |
||
1154 | } |
||
1155 | } |
||
1156 | |||
1157 | if (rdev->family >= CHIP_R600) { |
||
1158 | WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch); |
||
1159 | WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch); |
||
1160 | WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch); |
||
1161 | } else { |
||
1162 | WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch); |
||
1163 | WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch); |
||
1164 | WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); |
||
1165 | } |
||
1166 | } |
||
1167 | |||
1168 | void |
||
1169 | radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc) |
||
1170 | { |
||
1171 | struct drm_device *dev = encoder->dev; |
||
1172 | struct radeon_device *rdev = dev->dev_private; |
||
1173 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
||
1174 | uint32_t bios_3_scratch; |
||
1175 | |||
1176 | if (rdev->family >= CHIP_R600) |
||
1177 | bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH); |
||
1178 | else |
||
1179 | bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH); |
||
1180 | |||
1181 | if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) { |
||
1182 | bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE; |
||
1183 | bios_3_scratch |= (crtc << 18); |
||
1184 | } |
||
1185 | if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) { |
||
1186 | bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE; |
||
1187 | bios_3_scratch |= (crtc << 24); |
||
1188 | } |
||
1189 | if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) { |
||
1190 | bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE; |
||
1191 | bios_3_scratch |= (crtc << 16); |
||
1192 | } |
||
1193 | if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) { |
||
1194 | bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE; |
||
1195 | bios_3_scratch |= (crtc << 20); |
||
1196 | } |
||
1197 | if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) { |
||
1198 | bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE; |
||
1199 | bios_3_scratch |= (crtc << 17); |
||
1200 | } |
||
1201 | if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) { |
||
1202 | bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE; |
||
1203 | bios_3_scratch |= (crtc << 19); |
||
1204 | } |
||
1205 | if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) { |
||
1206 | bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE; |
||
1207 | bios_3_scratch |= (crtc << 23); |
||
1208 | } |
||
1209 | if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) { |
||
1210 | bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE; |
||
1211 | bios_3_scratch |= (crtc << 25); |
||
1212 | } |
||
1213 | |||
1214 | if (rdev->family >= CHIP_R600) |
||
1215 | WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch); |
||
1216 | else |
||
1217 | WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch); |
||
1218 | } |
||
1219 | |||
1220 | void |
||
1221 | radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on) |
||
1222 | { |
||
1223 | struct drm_device *dev = encoder->dev; |
||
1224 | struct radeon_device *rdev = dev->dev_private; |
||
1225 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
||
1226 | uint32_t bios_2_scratch; |
||
1227 | |||
1228 | if (rdev->family >= CHIP_R600) |
||
1229 | bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH); |
||
1230 | else |
||
1231 | bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH); |
||
1232 | |||
1233 | if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) { |
||
1234 | if (on) |
||
1235 | bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE; |
||
1236 | else |
||
1237 | bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE; |
||
1238 | } |
||
1239 | if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) { |
||
1240 | if (on) |
||
1241 | bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE; |
||
1242 | else |
||
1243 | bios_2_scratch |= ATOM_S2_CV_DPMS_STATE; |
||
1244 | } |
||
1245 | if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) { |
||
1246 | if (on) |
||
1247 | bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE; |
||
1248 | else |
||
1249 | bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE; |
||
1250 | } |
||
1251 | if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) { |
||
1252 | if (on) |
||
1253 | bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE; |
||
1254 | else |
||
1255 | bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE; |
||
1256 | } |
||
1257 | if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) { |
||
1258 | if (on) |
||
1259 | bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE; |
||
1260 | else |
||
1261 | bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE; |
||
1262 | } |
||
1263 | if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) { |
||
1264 | if (on) |
||
1265 | bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE; |
||
1266 | else |
||
1267 | bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE; |
||
1268 | } |
||
1269 | if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) { |
||
1270 | if (on) |
||
1271 | bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE; |
||
1272 | else |
||
1273 | bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE; |
||
1274 | } |
||
1275 | if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) { |
||
1276 | if (on) |
||
1277 | bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE; |
||
1278 | else |
||
1279 | bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE; |
||
1280 | } |
||
1281 | if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) { |
||
1282 | if (on) |
||
1283 | bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE; |
||
1284 | else |
||
1285 | bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE; |
||
1286 | } |
||
1287 | if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) { |
||
1288 | if (on) |
||
1289 | bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE; |
||
1290 | else |
||
1291 | bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE; |
||
1292 | } |
||
1293 | |||
1294 | if (rdev->family >= CHIP_R600) |
||
1295 | WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch); |
||
1296 | else |
||
1297 | WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch); |
||
1298 | }><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>>>>>><> |