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1117 | serge | 1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
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3 | * Copyright 2008 Red Hat Inc. |
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4 | * Copyright 2009 Jerome Glisse. |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the "Software"), |
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8 | * to deal in the Software without restriction, including without limitation |
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9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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10 | * and/or sell copies of the Software, and to permit persons to whom the |
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11 | * Software is furnished to do so, subject to the following conditions: |
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12 | * |
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13 | * The above copyright notice and this permission notice shall be included in |
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14 | * all copies or substantial portions of the Software. |
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15 | * |
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16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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22 | * OTHER DEALINGS IN THE SOFTWARE. |
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23 | * |
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24 | * Authors: Dave Airlie |
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25 | * Alex Deucher |
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26 | * Jerome Glisse |
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27 | */ |
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28 | #ifndef __RADEON_ASIC_H__ |
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29 | #define __RADEON_ASIC_H__ |
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30 | |||
31 | /* |
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32 | * common functions |
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33 | */ |
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1268 | serge | 34 | uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev); |
1117 | serge | 35 | void radeon_legacy_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock); |
1403 | serge | 36 | uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev); |
1117 | serge | 37 | void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); |
38 | |||
1268 | serge | 39 | uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev); |
1117 | serge | 40 | void radeon_atom_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock); |
1268 | serge | 41 | uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev); |
1117 | serge | 42 | void radeon_atom_set_memory_clock(struct radeon_device *rdev, uint32_t mem_clock); |
43 | void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); |
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44 | |||
2997 | Serge | 45 | void atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level); |
46 | u8 atombios_get_backlight_level(struct radeon_encoder *radeon_encoder); |
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47 | void radeon_legacy_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level); |
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48 | u8 radeon_legacy_get_backlight_level(struct radeon_encoder *radeon_encoder); |
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49 | |||
1117 | serge | 50 | /* |
1430 | serge | 51 | * r100,rv100,rs100,rv200,rs200 |
1117 | serge | 52 | */ |
1963 | serge | 53 | struct r100_mc_save { |
54 | u32 GENMO_WT; |
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55 | u32 CRTC_EXT_CNTL; |
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56 | u32 CRTC_GEN_CNTL; |
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57 | u32 CRTC2_GEN_CNTL; |
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58 | u32 CUR_OFFSET; |
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59 | u32 CUR2_OFFSET; |
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60 | }; |
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61 | int r100_init(struct radeon_device *rdev); |
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62 | void r100_fini(struct radeon_device *rdev); |
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63 | int r100_suspend(struct radeon_device *rdev); |
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64 | int r100_resume(struct radeon_device *rdev); |
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1179 | serge | 65 | void r100_vga_set_state(struct radeon_device *rdev, bool state); |
2997 | Serge | 66 | bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); |
1963 | serge | 67 | int r100_asic_reset(struct radeon_device *rdev); |
1179 | serge | 68 | u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc); |
1117 | serge | 69 | void r100_pci_gart_tlb_flush(struct radeon_device *rdev); |
6104 | serge | 70 | uint64_t r100_pci_gart_get_page_entry(uint64_t addr, uint32_t flags); |
5078 | serge | 71 | void r100_pci_gart_set_page(struct radeon_device *rdev, unsigned i, |
6104 | serge | 72 | uint64_t entry); |
2997 | Serge | 73 | void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring); |
1117 | serge | 74 | int r100_irq_set(struct radeon_device *rdev); |
75 | int r100_irq_process(struct radeon_device *rdev); |
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1128 | serge | 76 | void r100_fence_ring_emit(struct radeon_device *rdev, |
77 | struct radeon_fence *fence); |
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5078 | serge | 78 | bool r100_semaphore_ring_emit(struct radeon_device *rdev, |
2997 | Serge | 79 | struct radeon_ring *cp, |
80 | struct radeon_semaphore *semaphore, |
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81 | bool emit_wait); |
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1128 | serge | 82 | int r100_cs_parse(struct radeon_cs_parser *p); |
1117 | serge | 83 | void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
84 | uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg); |
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5271 | serge | 85 | struct radeon_fence *r100_copy_blit(struct radeon_device *rdev, |
6104 | serge | 86 | uint64_t src_offset, |
87 | uint64_t dst_offset, |
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88 | unsigned num_gpu_pages, |
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5271 | serge | 89 | struct reservation_object *resv); |
1179 | serge | 90 | int r100_set_surface_reg(struct radeon_device *rdev, int reg, |
91 | uint32_t tiling_flags, uint32_t pitch, |
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92 | uint32_t offset, uint32_t obj_size); |
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1963 | serge | 93 | void r100_clear_surface_reg(struct radeon_device *rdev, int reg); |
1179 | serge | 94 | void r100_bandwidth_update(struct radeon_device *rdev); |
95 | void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); |
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2997 | Serge | 96 | int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); |
1321 | serge | 97 | void r100_hpd_init(struct radeon_device *rdev); |
98 | void r100_hpd_fini(struct radeon_device *rdev); |
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99 | bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); |
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100 | void r100_hpd_set_polarity(struct radeon_device *rdev, |
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101 | enum radeon_hpd_id hpd); |
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1963 | serge | 102 | int r100_debugfs_rbbm_init(struct radeon_device *rdev); |
103 | int r100_debugfs_cp_init(struct radeon_device *rdev); |
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104 | void r100_cp_disable(struct radeon_device *rdev); |
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105 | int r100_cp_init(struct radeon_device *rdev, unsigned ring_size); |
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106 | void r100_cp_fini(struct radeon_device *rdev); |
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107 | int r100_pci_gart_init(struct radeon_device *rdev); |
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108 | void r100_pci_gart_fini(struct radeon_device *rdev); |
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109 | int r100_pci_gart_enable(struct radeon_device *rdev); |
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110 | void r100_pci_gart_disable(struct radeon_device *rdev); |
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111 | int r100_debugfs_mc_info_init(struct radeon_device *rdev); |
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112 | int r100_gui_wait_for_idle(struct radeon_device *rdev); |
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2997 | Serge | 113 | int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); |
1963 | serge | 114 | void r100_irq_disable(struct radeon_device *rdev); |
115 | void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save); |
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116 | void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save); |
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117 | void r100_vram_init_sizes(struct radeon_device *rdev); |
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118 | int r100_cp_reset(struct radeon_device *rdev); |
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119 | void r100_vga_render_disable(struct radeon_device *rdev); |
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120 | void r100_restore_sanity(struct radeon_device *rdev); |
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121 | int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p, |
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122 | struct radeon_cs_packet *pkt, |
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123 | struct radeon_bo *robj); |
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124 | int r100_cs_parse_packet0(struct radeon_cs_parser *p, |
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125 | struct radeon_cs_packet *pkt, |
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126 | const unsigned *auth, unsigned n, |
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127 | radeon_packet0_check_t check); |
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128 | int r100_cs_packet_parse(struct radeon_cs_parser *p, |
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129 | struct radeon_cs_packet *pkt, |
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130 | unsigned idx); |
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131 | void r100_enable_bm(struct radeon_device *rdev); |
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132 | void r100_set_common_regs(struct radeon_device *rdev); |
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133 | void r100_bm_disable(struct radeon_device *rdev); |
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134 | extern bool r100_gui_idle(struct radeon_device *rdev); |
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135 | extern void r100_pm_misc(struct radeon_device *rdev); |
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136 | extern void r100_pm_prepare(struct radeon_device *rdev); |
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137 | extern void r100_pm_finish(struct radeon_device *rdev); |
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138 | extern void r100_pm_init_profile(struct radeon_device *rdev); |
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139 | extern void r100_pm_get_dynpm_state(struct radeon_device *rdev); |
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5078 | serge | 140 | extern void r100_page_flip(struct radeon_device *rdev, int crtc, |
141 | u64 crtc_base); |
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142 | extern bool r100_page_flip_pending(struct radeon_device *rdev, int crtc); |
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2997 | Serge | 143 | extern void r100_wait_for_vblank(struct radeon_device *rdev, int crtc); |
144 | extern int r100_mc_wait_for_idle(struct radeon_device *rdev); |
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1117 | serge | 145 | |
5078 | serge | 146 | u32 r100_gfx_get_rptr(struct radeon_device *rdev, |
147 | struct radeon_ring *ring); |
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148 | u32 r100_gfx_get_wptr(struct radeon_device *rdev, |
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149 | struct radeon_ring *ring); |
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150 | void r100_gfx_set_wptr(struct radeon_device *rdev, |
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151 | struct radeon_ring *ring); |
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5139 | serge | 152 | |
1430 | serge | 153 | /* |
154 | * r200,rv250,rs300,rv280 |
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155 | */ |
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5271 | serge | 156 | struct radeon_fence *r200_copy_dma(struct radeon_device *rdev, |
6104 | serge | 157 | uint64_t src_offset, |
158 | uint64_t dst_offset, |
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159 | unsigned num_gpu_pages, |
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5271 | serge | 160 | struct reservation_object *resv); |
1963 | serge | 161 | void r200_set_safe_registers(struct radeon_device *rdev); |
1117 | serge | 162 | |
163 | /* |
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164 | * r300,r350,rv350,rv380 |
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165 | */ |
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1221 | serge | 166 | extern int r300_init(struct radeon_device *rdev); |
167 | extern void r300_fini(struct radeon_device *rdev); |
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168 | extern int r300_suspend(struct radeon_device *rdev); |
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169 | extern int r300_resume(struct radeon_device *rdev); |
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1963 | serge | 170 | extern int r300_asic_reset(struct radeon_device *rdev); |
2997 | Serge | 171 | extern void r300_ring_start(struct radeon_device *rdev, struct radeon_ring *ring); |
1221 | serge | 172 | extern void r300_fence_ring_emit(struct radeon_device *rdev, |
6104 | serge | 173 | struct radeon_fence *fence); |
1221 | serge | 174 | extern int r300_cs_parse(struct radeon_cs_parser *p); |
175 | extern void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev); |
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6104 | serge | 176 | extern uint64_t rv370_pcie_gart_get_page_entry(uint64_t addr, uint32_t flags); |
5078 | serge | 177 | extern void rv370_pcie_gart_set_page(struct radeon_device *rdev, unsigned i, |
6104 | serge | 178 | uint64_t entry); |
1221 | serge | 179 | extern void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes); |
1430 | serge | 180 | extern int rv370_get_pcie_lanes(struct radeon_device *rdev); |
1963 | serge | 181 | extern void r300_set_reg_safe(struct radeon_device *rdev); |
182 | extern void r300_mc_program(struct radeon_device *rdev); |
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183 | extern void r300_mc_init(struct radeon_device *rdev); |
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184 | extern void r300_clock_startup(struct radeon_device *rdev); |
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185 | extern int r300_mc_wait_for_idle(struct radeon_device *rdev); |
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186 | extern int rv370_pcie_gart_init(struct radeon_device *rdev); |
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187 | extern void rv370_pcie_gart_fini(struct radeon_device *rdev); |
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188 | extern int rv370_pcie_gart_enable(struct radeon_device *rdev); |
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189 | extern void rv370_pcie_gart_disable(struct radeon_device *rdev); |
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2997 | Serge | 190 | extern int r300_mc_wait_for_idle(struct radeon_device *rdev); |
1430 | serge | 191 | |
1117 | serge | 192 | /* |
193 | * r420,r423,rv410 |
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194 | */ |
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1179 | serge | 195 | extern int r420_init(struct radeon_device *rdev); |
196 | extern void r420_fini(struct radeon_device *rdev); |
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197 | extern int r420_suspend(struct radeon_device *rdev); |
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198 | extern int r420_resume(struct radeon_device *rdev); |
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1963 | serge | 199 | extern void r420_pm_init_profile(struct radeon_device *rdev); |
200 | extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg); |
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201 | extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v); |
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202 | extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev); |
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203 | extern void r420_pipes_init(struct radeon_device *rdev); |
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1117 | serge | 204 | |
205 | /* |
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206 | * rs400,rs480 |
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207 | */ |
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1221 | serge | 208 | extern int rs400_init(struct radeon_device *rdev); |
209 | extern void rs400_fini(struct radeon_device *rdev); |
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210 | extern int rs400_suspend(struct radeon_device *rdev); |
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211 | extern int rs400_resume(struct radeon_device *rdev); |
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1117 | serge | 212 | void rs400_gart_tlb_flush(struct radeon_device *rdev); |
6104 | serge | 213 | uint64_t rs400_gart_get_page_entry(uint64_t addr, uint32_t flags); |
5078 | serge | 214 | void rs400_gart_set_page(struct radeon_device *rdev, unsigned i, |
6104 | serge | 215 | uint64_t entry); |
1117 | serge | 216 | uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg); |
217 | void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
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1963 | serge | 218 | int rs400_gart_init(struct radeon_device *rdev); |
219 | int rs400_gart_enable(struct radeon_device *rdev); |
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220 | void rs400_gart_adjust_size(struct radeon_device *rdev); |
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221 | void rs400_gart_disable(struct radeon_device *rdev); |
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222 | void rs400_gart_fini(struct radeon_device *rdev); |
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2997 | Serge | 223 | extern int rs400_mc_wait_for_idle(struct radeon_device *rdev); |
1117 | serge | 224 | |
225 | /* |
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226 | * rs600. |
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227 | */ |
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1963 | serge | 228 | extern int rs600_asic_reset(struct radeon_device *rdev); |
1221 | serge | 229 | extern int rs600_init(struct radeon_device *rdev); |
230 | extern void rs600_fini(struct radeon_device *rdev); |
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231 | extern int rs600_suspend(struct radeon_device *rdev); |
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232 | extern int rs600_resume(struct radeon_device *rdev); |
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1117 | serge | 233 | int rs600_irq_set(struct radeon_device *rdev); |
1179 | serge | 234 | int rs600_irq_process(struct radeon_device *rdev); |
1963 | serge | 235 | void rs600_irq_disable(struct radeon_device *rdev); |
1179 | serge | 236 | u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc); |
1117 | serge | 237 | void rs600_gart_tlb_flush(struct radeon_device *rdev); |
6104 | serge | 238 | uint64_t rs600_gart_get_page_entry(uint64_t addr, uint32_t flags); |
5078 | serge | 239 | void rs600_gart_set_page(struct radeon_device *rdev, unsigned i, |
6104 | serge | 240 | uint64_t entry); |
1117 | serge | 241 | uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg); |
242 | void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
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1179 | serge | 243 | void rs600_bandwidth_update(struct radeon_device *rdev); |
1321 | serge | 244 | void rs600_hpd_init(struct radeon_device *rdev); |
245 | void rs600_hpd_fini(struct radeon_device *rdev); |
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246 | bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); |
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247 | void rs600_hpd_set_polarity(struct radeon_device *rdev, |
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248 | enum radeon_hpd_id hpd); |
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1963 | serge | 249 | extern void rs600_pm_misc(struct radeon_device *rdev); |
250 | extern void rs600_pm_prepare(struct radeon_device *rdev); |
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251 | extern void rs600_pm_finish(struct radeon_device *rdev); |
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5078 | serge | 252 | extern void rs600_page_flip(struct radeon_device *rdev, int crtc, |
253 | u64 crtc_base); |
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254 | extern bool rs600_page_flip_pending(struct radeon_device *rdev, int crtc); |
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1963 | serge | 255 | void rs600_set_safe_registers(struct radeon_device *rdev); |
2997 | Serge | 256 | extern void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc); |
257 | extern int rs600_mc_wait_for_idle(struct radeon_device *rdev); |
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1321 | serge | 258 | |
1117 | serge | 259 | /* |
260 | * rs690,rs740 |
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261 | */ |
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1221 | serge | 262 | int rs690_init(struct radeon_device *rdev); |
263 | void rs690_fini(struct radeon_device *rdev); |
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264 | int rs690_resume(struct radeon_device *rdev); |
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265 | int rs690_suspend(struct radeon_device *rdev); |
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1117 | serge | 266 | uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg); |
267 | void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
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1179 | serge | 268 | void rs690_bandwidth_update(struct radeon_device *rdev); |
1963 | serge | 269 | void rs690_line_buffer_adjust(struct radeon_device *rdev, |
270 | struct drm_display_mode *mode1, |
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271 | struct drm_display_mode *mode2); |
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2997 | Serge | 272 | extern int rs690_mc_wait_for_idle(struct radeon_device *rdev); |
1117 | serge | 273 | |
274 | /* |
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275 | * rv515 |
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276 | */ |
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1963 | serge | 277 | struct rv515_mc_save { |
278 | u32 vga_render_control; |
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279 | u32 vga_hdp_control; |
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3192 | Serge | 280 | bool crtc_enabled[2]; |
1963 | serge | 281 | }; |
2997 | Serge | 282 | |
1117 | serge | 283 | int rv515_init(struct radeon_device *rdev); |
1221 | serge | 284 | void rv515_fini(struct radeon_device *rdev); |
1117 | serge | 285 | uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg); |
286 | void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
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2997 | Serge | 287 | void rv515_ring_start(struct radeon_device *rdev, struct radeon_ring *ring); |
1179 | serge | 288 | void rv515_bandwidth_update(struct radeon_device *rdev); |
1221 | serge | 289 | int rv515_resume(struct radeon_device *rdev); |
290 | int rv515_suspend(struct radeon_device *rdev); |
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1963 | serge | 291 | void rv515_bandwidth_avivo_update(struct radeon_device *rdev); |
292 | void rv515_vga_render_disable(struct radeon_device *rdev); |
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293 | void rv515_set_safe_registers(struct radeon_device *rdev); |
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294 | void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save); |
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295 | void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save); |
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296 | void rv515_clock_startup(struct radeon_device *rdev); |
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297 | void rv515_debugfs(struct radeon_device *rdev); |
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2997 | Serge | 298 | int rv515_mc_wait_for_idle(struct radeon_device *rdev); |
1117 | serge | 299 | |
300 | /* |
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301 | * r520,rv530,rv560,rv570,r580 |
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302 | */ |
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1221 | serge | 303 | int r520_init(struct radeon_device *rdev); |
304 | int r520_resume(struct radeon_device *rdev); |
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2997 | Serge | 305 | int r520_mc_wait_for_idle(struct radeon_device *rdev); |
1117 | serge | 306 | |
307 | /* |
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1221 | serge | 308 | * r600,rv610,rv630,rv620,rv635,rv670,rs780,rs880 |
1117 | serge | 309 | */ |
1179 | serge | 310 | int r600_init(struct radeon_device *rdev); |
311 | void r600_fini(struct radeon_device *rdev); |
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312 | int r600_suspend(struct radeon_device *rdev); |
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313 | int r600_resume(struct radeon_device *rdev); |
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314 | void r600_vga_set_state(struct radeon_device *rdev, bool state); |
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315 | int r600_wb_init(struct radeon_device *rdev); |
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316 | void r600_wb_fini(struct radeon_device *rdev); |
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317 | void r600_pcie_gart_tlb_flush(struct radeon_device *rdev); |
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1117 | serge | 318 | uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg); |
319 | void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
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1233 | serge | 320 | int r600_cs_parse(struct radeon_cs_parser *p); |
3192 | Serge | 321 | int r600_dma_cs_parse(struct radeon_cs_parser *p); |
1233 | serge | 322 | void r600_fence_ring_emit(struct radeon_device *rdev, |
323 | struct radeon_fence *fence); |
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5078 | serge | 324 | bool r600_semaphore_ring_emit(struct radeon_device *rdev, |
2997 | Serge | 325 | struct radeon_ring *cp, |
326 | struct radeon_semaphore *semaphore, |
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327 | bool emit_wait); |
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3192 | Serge | 328 | void r600_dma_fence_ring_emit(struct radeon_device *rdev, |
329 | struct radeon_fence *fence); |
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5078 | serge | 330 | bool r600_dma_semaphore_ring_emit(struct radeon_device *rdev, |
3192 | Serge | 331 | struct radeon_ring *ring, |
332 | struct radeon_semaphore *semaphore, |
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333 | bool emit_wait); |
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334 | void r600_dma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); |
||
335 | bool r600_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring); |
||
3764 | Serge | 336 | bool r600_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); |
1963 | serge | 337 | int r600_asic_reset(struct radeon_device *rdev); |
1233 | serge | 338 | int r600_set_surface_reg(struct radeon_device *rdev, int reg, |
339 | uint32_t tiling_flags, uint32_t pitch, |
||
340 | uint32_t offset, uint32_t obj_size); |
||
1963 | serge | 341 | void r600_clear_surface_reg(struct radeon_device *rdev, int reg); |
2997 | Serge | 342 | int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); |
3192 | Serge | 343 | int r600_dma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); |
1233 | serge | 344 | void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); |
2997 | Serge | 345 | int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); |
3192 | Serge | 346 | int r600_dma_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); |
5271 | serge | 347 | struct radeon_fence *r600_copy_cpdma(struct radeon_device *rdev, |
6104 | serge | 348 | uint64_t src_offset, uint64_t dst_offset, |
5271 | serge | 349 | unsigned num_gpu_pages, |
350 | struct reservation_object *resv); |
||
351 | struct radeon_fence *r600_copy_dma(struct radeon_device *rdev, |
||
6104 | serge | 352 | uint64_t src_offset, uint64_t dst_offset, |
5271 | serge | 353 | unsigned num_gpu_pages, |
354 | struct reservation_object *resv); |
||
1321 | serge | 355 | void r600_hpd_init(struct radeon_device *rdev); |
356 | void r600_hpd_fini(struct radeon_device *rdev); |
||
357 | bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); |
||
358 | void r600_hpd_set_polarity(struct radeon_device *rdev, |
||
359 | enum radeon_hpd_id hpd); |
||
5078 | serge | 360 | extern void r600_mmio_hdp_flush(struct radeon_device *rdev); |
1963 | serge | 361 | extern bool r600_gui_idle(struct radeon_device *rdev); |
362 | extern void r600_pm_misc(struct radeon_device *rdev); |
||
363 | extern void r600_pm_init_profile(struct radeon_device *rdev); |
||
364 | extern void rs780_pm_init_profile(struct radeon_device *rdev); |
||
3764 | Serge | 365 | extern uint32_t rs780_mc_rreg(struct radeon_device *rdev, uint32_t reg); |
366 | extern void rs780_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
||
1963 | serge | 367 | extern void r600_pm_get_dynpm_state(struct radeon_device *rdev); |
368 | extern void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes); |
||
369 | extern int r600_get_pcie_lanes(struct radeon_device *rdev); |
||
370 | bool r600_card_posted(struct radeon_device *rdev); |
||
371 | void r600_cp_stop(struct radeon_device *rdev); |
||
372 | int r600_cp_start(struct radeon_device *rdev); |
||
2997 | Serge | 373 | void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size); |
1963 | serge | 374 | int r600_cp_resume(struct radeon_device *rdev); |
375 | void r600_cp_fini(struct radeon_device *rdev); |
||
376 | int r600_count_pipe_bits(uint32_t val); |
||
377 | int r600_mc_wait_for_idle(struct radeon_device *rdev); |
||
378 | int r600_pcie_gart_init(struct radeon_device *rdev); |
||
379 | void r600_scratch_init(struct radeon_device *rdev); |
||
380 | int r600_init_microcode(struct radeon_device *rdev); |
||
5078 | serge | 381 | u32 r600_gfx_get_rptr(struct radeon_device *rdev, |
382 | struct radeon_ring *ring); |
||
383 | u32 r600_gfx_get_wptr(struct radeon_device *rdev, |
||
384 | struct radeon_ring *ring); |
||
385 | void r600_gfx_set_wptr(struct radeon_device *rdev, |
||
386 | struct radeon_ring *ring); |
||
6104 | serge | 387 | int r600_get_allowed_info_register(struct radeon_device *rdev, |
388 | u32 reg, u32 *val); |
||
1963 | serge | 389 | /* r600 irq */ |
390 | int r600_irq_process(struct radeon_device *rdev); |
||
391 | int r600_irq_init(struct radeon_device *rdev); |
||
392 | void r600_irq_fini(struct radeon_device *rdev); |
||
393 | void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size); |
||
394 | int r600_irq_set(struct radeon_device *rdev); |
||
395 | void r600_irq_suspend(struct radeon_device *rdev); |
||
396 | void r600_disable_interrupts(struct radeon_device *rdev); |
||
397 | void r600_rlc_stop(struct radeon_device *rdev); |
||
398 | /* r600 audio */ |
||
399 | void r600_audio_fini(struct radeon_device *rdev); |
||
5078 | serge | 400 | void r600_audio_set_dto(struct drm_encoder *encoder, u32 clock); |
401 | void r600_hdmi_update_avi_infoframe(struct drm_encoder *encoder, void *buffer, |
||
402 | size_t size); |
||
403 | void r600_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock); |
||
404 | void r600_hdmi_audio_workaround(struct drm_encoder *encoder); |
||
1963 | serge | 405 | int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder); |
406 | void r600_hdmi_update_audio_settings(struct drm_encoder *encoder); |
||
2997 | Serge | 407 | int r600_mc_wait_for_idle(struct radeon_device *rdev); |
3764 | Serge | 408 | u32 r600_get_xclk(struct radeon_device *rdev); |
409 | uint64_t r600_get_gpu_clock_counter(struct radeon_device *rdev); |
||
5078 | serge | 410 | int rv6xx_get_temp(struct radeon_device *rdev); |
411 | int r600_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); |
||
412 | int r600_dpm_pre_set_power_state(struct radeon_device *rdev); |
||
413 | void r600_dpm_post_set_power_state(struct radeon_device *rdev); |
||
414 | int r600_dpm_late_enable(struct radeon_device *rdev); |
||
415 | /* r600 dma */ |
||
416 | uint32_t r600_dma_get_rptr(struct radeon_device *rdev, |
||
417 | struct radeon_ring *ring); |
||
418 | uint32_t r600_dma_get_wptr(struct radeon_device *rdev, |
||
419 | struct radeon_ring *ring); |
||
420 | void r600_dma_set_wptr(struct radeon_device *rdev, |
||
421 | struct radeon_ring *ring); |
||
422 | /* rv6xx dpm */ |
||
423 | int rv6xx_dpm_init(struct radeon_device *rdev); |
||
424 | int rv6xx_dpm_enable(struct radeon_device *rdev); |
||
425 | void rv6xx_dpm_disable(struct radeon_device *rdev); |
||
426 | int rv6xx_dpm_set_power_state(struct radeon_device *rdev); |
||
427 | void rv6xx_setup_asic(struct radeon_device *rdev); |
||
428 | void rv6xx_dpm_display_configuration_changed(struct radeon_device *rdev); |
||
429 | void rv6xx_dpm_fini(struct radeon_device *rdev); |
||
430 | u32 rv6xx_dpm_get_sclk(struct radeon_device *rdev, bool low); |
||
431 | u32 rv6xx_dpm_get_mclk(struct radeon_device *rdev, bool low); |
||
432 | void rv6xx_dpm_print_power_state(struct radeon_device *rdev, |
||
433 | struct radeon_ps *ps); |
||
434 | void rv6xx_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, |
||
435 | struct seq_file *m); |
||
436 | int rv6xx_dpm_force_performance_level(struct radeon_device *rdev, |
||
437 | enum radeon_dpm_forced_level level); |
||
6104 | serge | 438 | u32 rv6xx_dpm_get_current_sclk(struct radeon_device *rdev); |
439 | u32 rv6xx_dpm_get_current_mclk(struct radeon_device *rdev); |
||
5078 | serge | 440 | /* rs780 dpm */ |
441 | int rs780_dpm_init(struct radeon_device *rdev); |
||
442 | int rs780_dpm_enable(struct radeon_device *rdev); |
||
443 | void rs780_dpm_disable(struct radeon_device *rdev); |
||
444 | int rs780_dpm_set_power_state(struct radeon_device *rdev); |
||
445 | void rs780_dpm_setup_asic(struct radeon_device *rdev); |
||
446 | void rs780_dpm_display_configuration_changed(struct radeon_device *rdev); |
||
447 | void rs780_dpm_fini(struct radeon_device *rdev); |
||
448 | u32 rs780_dpm_get_sclk(struct radeon_device *rdev, bool low); |
||
449 | u32 rs780_dpm_get_mclk(struct radeon_device *rdev, bool low); |
||
450 | void rs780_dpm_print_power_state(struct radeon_device *rdev, |
||
451 | struct radeon_ps *ps); |
||
452 | void rs780_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, |
||
453 | struct seq_file *m); |
||
454 | int rs780_dpm_force_performance_level(struct radeon_device *rdev, |
||
455 | enum radeon_dpm_forced_level level); |
||
6104 | serge | 456 | u32 rs780_dpm_get_current_sclk(struct radeon_device *rdev); |
457 | u32 rs780_dpm_get_current_mclk(struct radeon_device *rdev); |
||
1117 | serge | 458 | |
1233 | serge | 459 | /* |
460 | * rv770,rv730,rv710,rv740 |
||
461 | */ |
||
462 | int rv770_init(struct radeon_device *rdev); |
||
463 | void rv770_fini(struct radeon_device *rdev); |
||
464 | int rv770_suspend(struct radeon_device *rdev); |
||
465 | int rv770_resume(struct radeon_device *rdev); |
||
1963 | serge | 466 | void rv770_pm_misc(struct radeon_device *rdev); |
5078 | serge | 467 | void rv770_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base); |
468 | bool rv770_page_flip_pending(struct radeon_device *rdev, int crtc); |
||
1963 | serge | 469 | void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); |
470 | void r700_cp_stop(struct radeon_device *rdev); |
||
471 | void r700_cp_fini(struct radeon_device *rdev); |
||
5271 | serge | 472 | struct radeon_fence *rv770_copy_dma(struct radeon_device *rdev, |
6104 | serge | 473 | uint64_t src_offset, uint64_t dst_offset, |
474 | unsigned num_gpu_pages, |
||
5271 | serge | 475 | struct reservation_object *resv); |
3764 | Serge | 476 | u32 rv770_get_xclk(struct radeon_device *rdev); |
477 | int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); |
||
5078 | serge | 478 | int rv770_get_temp(struct radeon_device *rdev); |
479 | /* rv7xx pm */ |
||
480 | int rv770_dpm_init(struct radeon_device *rdev); |
||
481 | int rv770_dpm_enable(struct radeon_device *rdev); |
||
482 | int rv770_dpm_late_enable(struct radeon_device *rdev); |
||
483 | void rv770_dpm_disable(struct radeon_device *rdev); |
||
484 | int rv770_dpm_set_power_state(struct radeon_device *rdev); |
||
485 | void rv770_dpm_setup_asic(struct radeon_device *rdev); |
||
486 | void rv770_dpm_display_configuration_changed(struct radeon_device *rdev); |
||
487 | void rv770_dpm_fini(struct radeon_device *rdev); |
||
488 | u32 rv770_dpm_get_sclk(struct radeon_device *rdev, bool low); |
||
489 | u32 rv770_dpm_get_mclk(struct radeon_device *rdev, bool low); |
||
490 | void rv770_dpm_print_power_state(struct radeon_device *rdev, |
||
491 | struct radeon_ps *ps); |
||
492 | void rv770_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, |
||
493 | struct seq_file *m); |
||
494 | int rv770_dpm_force_performance_level(struct radeon_device *rdev, |
||
495 | enum radeon_dpm_forced_level level); |
||
496 | bool rv770_dpm_vblank_too_short(struct radeon_device *rdev); |
||
6104 | serge | 497 | u32 rv770_dpm_get_current_sclk(struct radeon_device *rdev); |
498 | u32 rv770_dpm_get_current_mclk(struct radeon_device *rdev); |
||
1233 | serge | 499 | |
1430 | serge | 500 | /* |
501 | * evergreen |
||
502 | */ |
||
1963 | serge | 503 | struct evergreen_mc_save { |
504 | u32 vga_render_control; |
||
505 | u32 vga_hdp_control; |
||
2997 | Serge | 506 | bool crtc_enabled[RADEON_MAX_CRTCS]; |
1963 | serge | 507 | }; |
2997 | Serge | 508 | |
1963 | serge | 509 | void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev); |
1430 | serge | 510 | int evergreen_init(struct radeon_device *rdev); |
511 | void evergreen_fini(struct radeon_device *rdev); |
||
512 | int evergreen_suspend(struct radeon_device *rdev); |
||
513 | int evergreen_resume(struct radeon_device *rdev); |
||
3764 | Serge | 514 | bool evergreen_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); |
515 | bool evergreen_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); |
||
1963 | serge | 516 | int evergreen_asic_reset(struct radeon_device *rdev); |
1430 | serge | 517 | void evergreen_bandwidth_update(struct radeon_device *rdev); |
1963 | serge | 518 | void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); |
1430 | serge | 519 | void evergreen_hpd_init(struct radeon_device *rdev); |
520 | void evergreen_hpd_fini(struct radeon_device *rdev); |
||
521 | bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); |
||
522 | void evergreen_hpd_set_polarity(struct radeon_device *rdev, |
||
523 | enum radeon_hpd_id hpd); |
||
1963 | serge | 524 | u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc); |
525 | int evergreen_irq_set(struct radeon_device *rdev); |
||
526 | int evergreen_irq_process(struct radeon_device *rdev); |
||
527 | extern int evergreen_cs_parse(struct radeon_cs_parser *p); |
||
3192 | Serge | 528 | extern int evergreen_dma_cs_parse(struct radeon_cs_parser *p); |
1963 | serge | 529 | extern void evergreen_pm_misc(struct radeon_device *rdev); |
530 | extern void evergreen_pm_prepare(struct radeon_device *rdev); |
||
531 | extern void evergreen_pm_finish(struct radeon_device *rdev); |
||
2997 | Serge | 532 | extern void sumo_pm_init_profile(struct radeon_device *rdev); |
533 | extern void btc_pm_init_profile(struct radeon_device *rdev); |
||
3764 | Serge | 534 | int sumo_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); |
535 | int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); |
||
5078 | serge | 536 | extern void evergreen_page_flip(struct radeon_device *rdev, int crtc, |
537 | u64 crtc_base); |
||
538 | extern bool evergreen_page_flip_pending(struct radeon_device *rdev, int crtc); |
||
2997 | Serge | 539 | extern void dce4_wait_for_vblank(struct radeon_device *rdev, int crtc); |
1963 | serge | 540 | void evergreen_disable_interrupt_state(struct radeon_device *rdev); |
2997 | Serge | 541 | int evergreen_mc_wait_for_idle(struct radeon_device *rdev); |
3192 | Serge | 542 | void evergreen_dma_fence_ring_emit(struct radeon_device *rdev, |
543 | struct radeon_fence *fence); |
||
544 | void evergreen_dma_ring_ib_execute(struct radeon_device *rdev, |
||
545 | struct radeon_ib *ib); |
||
5271 | serge | 546 | struct radeon_fence *evergreen_copy_dma(struct radeon_device *rdev, |
6104 | serge | 547 | uint64_t src_offset, uint64_t dst_offset, |
548 | unsigned num_gpu_pages, |
||
5271 | serge | 549 | struct reservation_object *resv); |
5078 | serge | 550 | int evergreen_get_temp(struct radeon_device *rdev); |
6104 | serge | 551 | int evergreen_get_allowed_info_register(struct radeon_device *rdev, |
552 | u32 reg, u32 *val); |
||
5078 | serge | 553 | int sumo_get_temp(struct radeon_device *rdev); |
554 | int tn_get_temp(struct radeon_device *rdev); |
||
555 | int cypress_dpm_init(struct radeon_device *rdev); |
||
556 | void cypress_dpm_setup_asic(struct radeon_device *rdev); |
||
557 | int cypress_dpm_enable(struct radeon_device *rdev); |
||
558 | void cypress_dpm_disable(struct radeon_device *rdev); |
||
559 | int cypress_dpm_set_power_state(struct radeon_device *rdev); |
||
560 | void cypress_dpm_display_configuration_changed(struct radeon_device *rdev); |
||
561 | void cypress_dpm_fini(struct radeon_device *rdev); |
||
562 | bool cypress_dpm_vblank_too_short(struct radeon_device *rdev); |
||
563 | int btc_dpm_init(struct radeon_device *rdev); |
||
564 | void btc_dpm_setup_asic(struct radeon_device *rdev); |
||
565 | int btc_dpm_enable(struct radeon_device *rdev); |
||
566 | void btc_dpm_disable(struct radeon_device *rdev); |
||
567 | int btc_dpm_pre_set_power_state(struct radeon_device *rdev); |
||
568 | int btc_dpm_set_power_state(struct radeon_device *rdev); |
||
569 | void btc_dpm_post_set_power_state(struct radeon_device *rdev); |
||
570 | void btc_dpm_fini(struct radeon_device *rdev); |
||
571 | u32 btc_dpm_get_sclk(struct radeon_device *rdev, bool low); |
||
572 | u32 btc_dpm_get_mclk(struct radeon_device *rdev, bool low); |
||
573 | bool btc_dpm_vblank_too_short(struct radeon_device *rdev); |
||
574 | void btc_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, |
||
575 | struct seq_file *m); |
||
6104 | serge | 576 | u32 btc_dpm_get_current_sclk(struct radeon_device *rdev); |
577 | u32 btc_dpm_get_current_mclk(struct radeon_device *rdev); |
||
5078 | serge | 578 | int sumo_dpm_init(struct radeon_device *rdev); |
579 | int sumo_dpm_enable(struct radeon_device *rdev); |
||
580 | int sumo_dpm_late_enable(struct radeon_device *rdev); |
||
581 | void sumo_dpm_disable(struct radeon_device *rdev); |
||
582 | int sumo_dpm_pre_set_power_state(struct radeon_device *rdev); |
||
583 | int sumo_dpm_set_power_state(struct radeon_device *rdev); |
||
584 | void sumo_dpm_post_set_power_state(struct radeon_device *rdev); |
||
585 | void sumo_dpm_setup_asic(struct radeon_device *rdev); |
||
586 | void sumo_dpm_display_configuration_changed(struct radeon_device *rdev); |
||
587 | void sumo_dpm_fini(struct radeon_device *rdev); |
||
588 | u32 sumo_dpm_get_sclk(struct radeon_device *rdev, bool low); |
||
589 | u32 sumo_dpm_get_mclk(struct radeon_device *rdev, bool low); |
||
590 | void sumo_dpm_print_power_state(struct radeon_device *rdev, |
||
591 | struct radeon_ps *ps); |
||
592 | void sumo_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, |
||
593 | struct seq_file *m); |
||
594 | int sumo_dpm_force_performance_level(struct radeon_device *rdev, |
||
595 | enum radeon_dpm_forced_level level); |
||
6104 | serge | 596 | u32 sumo_dpm_get_current_sclk(struct radeon_device *rdev); |
597 | u32 sumo_dpm_get_current_mclk(struct radeon_device *rdev); |
||
1430 | serge | 598 | |
1963 | serge | 599 | /* |
600 | * cayman |
||
601 | */ |
||
2997 | Serge | 602 | void cayman_fence_ring_emit(struct radeon_device *rdev, |
603 | struct radeon_fence *fence); |
||
1963 | serge | 604 | void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev); |
605 | int cayman_init(struct radeon_device *rdev); |
||
606 | void cayman_fini(struct radeon_device *rdev); |
||
607 | int cayman_suspend(struct radeon_device *rdev); |
||
608 | int cayman_resume(struct radeon_device *rdev); |
||
609 | int cayman_asic_reset(struct radeon_device *rdev); |
||
2997 | Serge | 610 | void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); |
611 | int cayman_vm_init(struct radeon_device *rdev); |
||
612 | void cayman_vm_fini(struct radeon_device *rdev); |
||
5271 | serge | 613 | void cayman_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring, |
614 | unsigned vm_id, uint64_t pd_addr); |
||
2997 | Serge | 615 | uint32_t cayman_vm_page_flags(struct radeon_device *rdev, uint32_t flags); |
616 | int evergreen_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib); |
||
3192 | Serge | 617 | int evergreen_dma_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib); |
618 | void cayman_dma_ring_ib_execute(struct radeon_device *rdev, |
||
619 | struct radeon_ib *ib); |
||
3764 | Serge | 620 | bool cayman_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring); |
3192 | Serge | 621 | bool cayman_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring); |
5078 | serge | 622 | |
623 | void cayman_dma_vm_copy_pages(struct radeon_device *rdev, |
||
624 | struct radeon_ib *ib, |
||
625 | uint64_t pe, uint64_t src, |
||
626 | unsigned count); |
||
627 | void cayman_dma_vm_write_pages(struct radeon_device *rdev, |
||
628 | struct radeon_ib *ib, |
||
629 | uint64_t pe, |
||
630 | uint64_t addr, unsigned count, |
||
631 | uint32_t incr, uint32_t flags); |
||
632 | void cayman_dma_vm_set_pages(struct radeon_device *rdev, |
||
6104 | serge | 633 | struct radeon_ib *ib, |
634 | uint64_t pe, |
||
635 | uint64_t addr, unsigned count, |
||
636 | uint32_t incr, uint32_t flags); |
||
5078 | serge | 637 | void cayman_dma_vm_pad_ib(struct radeon_ib *ib); |
638 | |||
5271 | serge | 639 | void cayman_dma_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring, |
640 | unsigned vm_id, uint64_t pd_addr); |
||
1430 | serge | 641 | |
5078 | serge | 642 | u32 cayman_gfx_get_rptr(struct radeon_device *rdev, |
643 | struct radeon_ring *ring); |
||
644 | u32 cayman_gfx_get_wptr(struct radeon_device *rdev, |
||
645 | struct radeon_ring *ring); |
||
646 | void cayman_gfx_set_wptr(struct radeon_device *rdev, |
||
647 | struct radeon_ring *ring); |
||
648 | uint32_t cayman_dma_get_rptr(struct radeon_device *rdev, |
||
649 | struct radeon_ring *ring); |
||
650 | uint32_t cayman_dma_get_wptr(struct radeon_device *rdev, |
||
651 | struct radeon_ring *ring); |
||
652 | void cayman_dma_set_wptr(struct radeon_device *rdev, |
||
653 | struct radeon_ring *ring); |
||
6104 | serge | 654 | int cayman_get_allowed_info_register(struct radeon_device *rdev, |
655 | u32 reg, u32 *val); |
||
5078 | serge | 656 | |
657 | int ni_dpm_init(struct radeon_device *rdev); |
||
658 | void ni_dpm_setup_asic(struct radeon_device *rdev); |
||
659 | int ni_dpm_enable(struct radeon_device *rdev); |
||
660 | void ni_dpm_disable(struct radeon_device *rdev); |
||
661 | int ni_dpm_pre_set_power_state(struct radeon_device *rdev); |
||
662 | int ni_dpm_set_power_state(struct radeon_device *rdev); |
||
663 | void ni_dpm_post_set_power_state(struct radeon_device *rdev); |
||
664 | void ni_dpm_fini(struct radeon_device *rdev); |
||
665 | u32 ni_dpm_get_sclk(struct radeon_device *rdev, bool low); |
||
666 | u32 ni_dpm_get_mclk(struct radeon_device *rdev, bool low); |
||
667 | void ni_dpm_print_power_state(struct radeon_device *rdev, |
||
668 | struct radeon_ps *ps); |
||
669 | void ni_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, |
||
670 | struct seq_file *m); |
||
671 | int ni_dpm_force_performance_level(struct radeon_device *rdev, |
||
672 | enum radeon_dpm_forced_level level); |
||
673 | bool ni_dpm_vblank_too_short(struct radeon_device *rdev); |
||
6104 | serge | 674 | u32 ni_dpm_get_current_sclk(struct radeon_device *rdev); |
675 | u32 ni_dpm_get_current_mclk(struct radeon_device *rdev); |
||
5078 | serge | 676 | int trinity_dpm_init(struct radeon_device *rdev); |
677 | int trinity_dpm_enable(struct radeon_device *rdev); |
||
678 | int trinity_dpm_late_enable(struct radeon_device *rdev); |
||
679 | void trinity_dpm_disable(struct radeon_device *rdev); |
||
680 | int trinity_dpm_pre_set_power_state(struct radeon_device *rdev); |
||
681 | int trinity_dpm_set_power_state(struct radeon_device *rdev); |
||
682 | void trinity_dpm_post_set_power_state(struct radeon_device *rdev); |
||
683 | void trinity_dpm_setup_asic(struct radeon_device *rdev); |
||
684 | void trinity_dpm_display_configuration_changed(struct radeon_device *rdev); |
||
685 | void trinity_dpm_fini(struct radeon_device *rdev); |
||
686 | u32 trinity_dpm_get_sclk(struct radeon_device *rdev, bool low); |
||
687 | u32 trinity_dpm_get_mclk(struct radeon_device *rdev, bool low); |
||
688 | void trinity_dpm_print_power_state(struct radeon_device *rdev, |
||
689 | struct radeon_ps *ps); |
||
690 | void trinity_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, |
||
691 | struct seq_file *m); |
||
692 | int trinity_dpm_force_performance_level(struct radeon_device *rdev, |
||
693 | enum radeon_dpm_forced_level level); |
||
694 | void trinity_dpm_enable_bapm(struct radeon_device *rdev, bool enable); |
||
6104 | serge | 695 | u32 trinity_dpm_get_current_sclk(struct radeon_device *rdev); |
696 | u32 trinity_dpm_get_current_mclk(struct radeon_device *rdev); |
||
697 | int tn_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk); |
||
5078 | serge | 698 | |
2997 | Serge | 699 | /* DCE6 - SI */ |
700 | void dce6_bandwidth_update(struct radeon_device *rdev); |
||
5078 | serge | 701 | void dce6_audio_fini(struct radeon_device *rdev); |
2997 | Serge | 702 | |
703 | /* |
||
704 | * si |
||
705 | */ |
||
706 | void si_fence_ring_emit(struct radeon_device *rdev, |
||
707 | struct radeon_fence *fence); |
||
708 | void si_pcie_gart_tlb_flush(struct radeon_device *rdev); |
||
709 | int si_init(struct radeon_device *rdev); |
||
710 | void si_fini(struct radeon_device *rdev); |
||
711 | int si_suspend(struct radeon_device *rdev); |
||
712 | int si_resume(struct radeon_device *rdev); |
||
3764 | Serge | 713 | bool si_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); |
714 | bool si_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); |
||
2997 | Serge | 715 | int si_asic_reset(struct radeon_device *rdev); |
716 | void si_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); |
||
717 | int si_irq_set(struct radeon_device *rdev); |
||
718 | int si_irq_process(struct radeon_device *rdev); |
||
719 | int si_vm_init(struct radeon_device *rdev); |
||
720 | void si_vm_fini(struct radeon_device *rdev); |
||
5271 | serge | 721 | void si_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring, |
722 | unsigned vm_id, uint64_t pd_addr); |
||
2997 | Serge | 723 | int si_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib); |
5271 | serge | 724 | struct radeon_fence *si_copy_dma(struct radeon_device *rdev, |
6104 | serge | 725 | uint64_t src_offset, uint64_t dst_offset, |
726 | unsigned num_gpu_pages, |
||
5271 | serge | 727 | struct reservation_object *resv); |
5078 | serge | 728 | |
729 | void si_dma_vm_copy_pages(struct radeon_device *rdev, |
||
730 | struct radeon_ib *ib, |
||
731 | uint64_t pe, uint64_t src, |
||
732 | unsigned count); |
||
733 | void si_dma_vm_write_pages(struct radeon_device *rdev, |
||
6104 | serge | 734 | struct radeon_ib *ib, |
735 | uint64_t pe, |
||
736 | uint64_t addr, unsigned count, |
||
737 | uint32_t incr, uint32_t flags); |
||
5078 | serge | 738 | void si_dma_vm_set_pages(struct radeon_device *rdev, |
739 | struct radeon_ib *ib, |
||
740 | uint64_t pe, |
||
741 | uint64_t addr, unsigned count, |
||
742 | uint32_t incr, uint32_t flags); |
||
743 | |||
5271 | serge | 744 | void si_dma_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring, |
745 | unsigned vm_id, uint64_t pd_addr); |
||
3764 | Serge | 746 | u32 si_get_xclk(struct radeon_device *rdev); |
747 | uint64_t si_get_gpu_clock_counter(struct radeon_device *rdev); |
||
748 | int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); |
||
6104 | serge | 749 | int si_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk); |
5078 | serge | 750 | int si_get_temp(struct radeon_device *rdev); |
6104 | serge | 751 | int si_get_allowed_info_register(struct radeon_device *rdev, |
752 | u32 reg, u32 *val); |
||
5078 | serge | 753 | int si_dpm_init(struct radeon_device *rdev); |
754 | void si_dpm_setup_asic(struct radeon_device *rdev); |
||
755 | int si_dpm_enable(struct radeon_device *rdev); |
||
756 | int si_dpm_late_enable(struct radeon_device *rdev); |
||
757 | void si_dpm_disable(struct radeon_device *rdev); |
||
758 | int si_dpm_pre_set_power_state(struct radeon_device *rdev); |
||
759 | int si_dpm_set_power_state(struct radeon_device *rdev); |
||
760 | void si_dpm_post_set_power_state(struct radeon_device *rdev); |
||
761 | void si_dpm_fini(struct radeon_device *rdev); |
||
762 | void si_dpm_display_configuration_changed(struct radeon_device *rdev); |
||
763 | void si_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, |
||
764 | struct seq_file *m); |
||
765 | int si_dpm_force_performance_level(struct radeon_device *rdev, |
||
766 | enum radeon_dpm_forced_level level); |
||
6104 | serge | 767 | int si_fan_ctrl_get_fan_speed_percent(struct radeon_device *rdev, |
768 | u32 *speed); |
||
769 | int si_fan_ctrl_set_fan_speed_percent(struct radeon_device *rdev, |
||
770 | u32 speed); |
||
771 | u32 si_fan_ctrl_get_mode(struct radeon_device *rdev); |
||
772 | void si_fan_ctrl_set_mode(struct radeon_device *rdev, u32 mode); |
||
773 | u32 si_dpm_get_current_sclk(struct radeon_device *rdev); |
||
774 | u32 si_dpm_get_current_mclk(struct radeon_device *rdev); |
||
2997 | Serge | 775 | |
5078 | serge | 776 | /* DCE8 - CIK */ |
777 | void dce8_bandwidth_update(struct radeon_device *rdev); |
||
778 | |||
779 | /* |
||
780 | * cik |
||
781 | */ |
||
782 | uint64_t cik_get_gpu_clock_counter(struct radeon_device *rdev); |
||
783 | u32 cik_get_xclk(struct radeon_device *rdev); |
||
784 | uint32_t cik_pciep_rreg(struct radeon_device *rdev, uint32_t reg); |
||
785 | void cik_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
||
786 | int cik_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); |
||
787 | int cik_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk); |
||
788 | void cik_sdma_fence_ring_emit(struct radeon_device *rdev, |
||
789 | struct radeon_fence *fence); |
||
790 | bool cik_sdma_semaphore_ring_emit(struct radeon_device *rdev, |
||
791 | struct radeon_ring *ring, |
||
792 | struct radeon_semaphore *semaphore, |
||
793 | bool emit_wait); |
||
794 | void cik_sdma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); |
||
5271 | serge | 795 | struct radeon_fence *cik_copy_dma(struct radeon_device *rdev, |
6104 | serge | 796 | uint64_t src_offset, uint64_t dst_offset, |
797 | unsigned num_gpu_pages, |
||
5271 | serge | 798 | struct reservation_object *resv); |
799 | struct radeon_fence *cik_copy_cpdma(struct radeon_device *rdev, |
||
6104 | serge | 800 | uint64_t src_offset, uint64_t dst_offset, |
801 | unsigned num_gpu_pages, |
||
5271 | serge | 802 | struct reservation_object *resv); |
5078 | serge | 803 | int cik_sdma_ring_test(struct radeon_device *rdev, struct radeon_ring *ring); |
804 | int cik_sdma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); |
||
805 | bool cik_sdma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring); |
||
806 | void cik_fence_gfx_ring_emit(struct radeon_device *rdev, |
||
807 | struct radeon_fence *fence); |
||
808 | void cik_fence_compute_ring_emit(struct radeon_device *rdev, |
||
809 | struct radeon_fence *fence); |
||
810 | bool cik_semaphore_ring_emit(struct radeon_device *rdev, |
||
811 | struct radeon_ring *cp, |
||
812 | struct radeon_semaphore *semaphore, |
||
813 | bool emit_wait); |
||
814 | void cik_pcie_gart_tlb_flush(struct radeon_device *rdev); |
||
815 | int cik_init(struct radeon_device *rdev); |
||
816 | void cik_fini(struct radeon_device *rdev); |
||
817 | int cik_suspend(struct radeon_device *rdev); |
||
818 | int cik_resume(struct radeon_device *rdev); |
||
819 | bool cik_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); |
||
820 | int cik_asic_reset(struct radeon_device *rdev); |
||
821 | void cik_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); |
||
822 | int cik_ring_test(struct radeon_device *rdev, struct radeon_ring *ring); |
||
823 | int cik_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); |
||
824 | int cik_irq_set(struct radeon_device *rdev); |
||
825 | int cik_irq_process(struct radeon_device *rdev); |
||
826 | int cik_vm_init(struct radeon_device *rdev); |
||
827 | void cik_vm_fini(struct radeon_device *rdev); |
||
5271 | serge | 828 | void cik_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring, |
829 | unsigned vm_id, uint64_t pd_addr); |
||
5078 | serge | 830 | |
831 | void cik_sdma_vm_copy_pages(struct radeon_device *rdev, |
||
832 | struct radeon_ib *ib, |
||
833 | uint64_t pe, uint64_t src, |
||
834 | unsigned count); |
||
835 | void cik_sdma_vm_write_pages(struct radeon_device *rdev, |
||
6104 | serge | 836 | struct radeon_ib *ib, |
837 | uint64_t pe, |
||
838 | uint64_t addr, unsigned count, |
||
839 | uint32_t incr, uint32_t flags); |
||
5078 | serge | 840 | void cik_sdma_vm_set_pages(struct radeon_device *rdev, |
841 | struct radeon_ib *ib, |
||
842 | uint64_t pe, |
||
843 | uint64_t addr, unsigned count, |
||
844 | uint32_t incr, uint32_t flags); |
||
845 | void cik_sdma_vm_pad_ib(struct radeon_ib *ib); |
||
846 | |||
5271 | serge | 847 | void cik_dma_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring, |
848 | unsigned vm_id, uint64_t pd_addr); |
||
5078 | serge | 849 | int cik_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib); |
850 | u32 cik_gfx_get_rptr(struct radeon_device *rdev, |
||
6104 | serge | 851 | struct radeon_ring *ring); |
5078 | serge | 852 | u32 cik_gfx_get_wptr(struct radeon_device *rdev, |
6104 | serge | 853 | struct radeon_ring *ring); |
5078 | serge | 854 | void cik_gfx_set_wptr(struct radeon_device *rdev, |
855 | struct radeon_ring *ring); |
||
856 | u32 cik_compute_get_rptr(struct radeon_device *rdev, |
||
857 | struct radeon_ring *ring); |
||
858 | u32 cik_compute_get_wptr(struct radeon_device *rdev, |
||
859 | struct radeon_ring *ring); |
||
860 | void cik_compute_set_wptr(struct radeon_device *rdev, |
||
861 | struct radeon_ring *ring); |
||
862 | u32 cik_sdma_get_rptr(struct radeon_device *rdev, |
||
863 | struct radeon_ring *ring); |
||
864 | u32 cik_sdma_get_wptr(struct radeon_device *rdev, |
||
865 | struct radeon_ring *ring); |
||
866 | void cik_sdma_set_wptr(struct radeon_device *rdev, |
||
6104 | serge | 867 | struct radeon_ring *ring); |
5078 | serge | 868 | int ci_get_temp(struct radeon_device *rdev); |
869 | int kv_get_temp(struct radeon_device *rdev); |
||
6104 | serge | 870 | int cik_get_allowed_info_register(struct radeon_device *rdev, |
871 | u32 reg, u32 *val); |
||
5078 | serge | 872 | |
873 | int ci_dpm_init(struct radeon_device *rdev); |
||
874 | int ci_dpm_enable(struct radeon_device *rdev); |
||
875 | int ci_dpm_late_enable(struct radeon_device *rdev); |
||
876 | void ci_dpm_disable(struct radeon_device *rdev); |
||
877 | int ci_dpm_pre_set_power_state(struct radeon_device *rdev); |
||
878 | int ci_dpm_set_power_state(struct radeon_device *rdev); |
||
879 | void ci_dpm_post_set_power_state(struct radeon_device *rdev); |
||
880 | void ci_dpm_setup_asic(struct radeon_device *rdev); |
||
881 | void ci_dpm_display_configuration_changed(struct radeon_device *rdev); |
||
882 | void ci_dpm_fini(struct radeon_device *rdev); |
||
883 | u32 ci_dpm_get_sclk(struct radeon_device *rdev, bool low); |
||
884 | u32 ci_dpm_get_mclk(struct radeon_device *rdev, bool low); |
||
885 | void ci_dpm_print_power_state(struct radeon_device *rdev, |
||
886 | struct radeon_ps *ps); |
||
887 | void ci_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, |
||
888 | struct seq_file *m); |
||
889 | int ci_dpm_force_performance_level(struct radeon_device *rdev, |
||
890 | enum radeon_dpm_forced_level level); |
||
891 | bool ci_dpm_vblank_too_short(struct radeon_device *rdev); |
||
892 | void ci_dpm_powergate_uvd(struct radeon_device *rdev, bool gate); |
||
6104 | serge | 893 | u32 ci_dpm_get_current_sclk(struct radeon_device *rdev); |
894 | u32 ci_dpm_get_current_mclk(struct radeon_device *rdev); |
||
5078 | serge | 895 | |
6104 | serge | 896 | int ci_fan_ctrl_get_fan_speed_percent(struct radeon_device *rdev, |
897 | u32 *speed); |
||
898 | int ci_fan_ctrl_set_fan_speed_percent(struct radeon_device *rdev, |
||
899 | u32 speed); |
||
900 | u32 ci_fan_ctrl_get_mode(struct radeon_device *rdev); |
||
901 | void ci_fan_ctrl_set_mode(struct radeon_device *rdev, u32 mode); |
||
902 | |||
5078 | serge | 903 | int kv_dpm_init(struct radeon_device *rdev); |
904 | int kv_dpm_enable(struct radeon_device *rdev); |
||
905 | int kv_dpm_late_enable(struct radeon_device *rdev); |
||
906 | void kv_dpm_disable(struct radeon_device *rdev); |
||
907 | int kv_dpm_pre_set_power_state(struct radeon_device *rdev); |
||
908 | int kv_dpm_set_power_state(struct radeon_device *rdev); |
||
909 | void kv_dpm_post_set_power_state(struct radeon_device *rdev); |
||
910 | void kv_dpm_setup_asic(struct radeon_device *rdev); |
||
911 | void kv_dpm_display_configuration_changed(struct radeon_device *rdev); |
||
912 | void kv_dpm_fini(struct radeon_device *rdev); |
||
913 | u32 kv_dpm_get_sclk(struct radeon_device *rdev, bool low); |
||
914 | u32 kv_dpm_get_mclk(struct radeon_device *rdev, bool low); |
||
915 | void kv_dpm_print_power_state(struct radeon_device *rdev, |
||
916 | struct radeon_ps *ps); |
||
917 | void kv_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, |
||
918 | struct seq_file *m); |
||
919 | int kv_dpm_force_performance_level(struct radeon_device *rdev, |
||
920 | enum radeon_dpm_forced_level level); |
||
921 | void kv_dpm_powergate_uvd(struct radeon_device *rdev, bool gate); |
||
922 | void kv_dpm_enable_bapm(struct radeon_device *rdev, bool enable); |
||
6104 | serge | 923 | u32 kv_dpm_get_current_sclk(struct radeon_device *rdev); |
924 | u32 kv_dpm_get_current_mclk(struct radeon_device *rdev); |
||
5078 | serge | 925 | |
926 | /* uvd v1.0 */ |
||
927 | uint32_t uvd_v1_0_get_rptr(struct radeon_device *rdev, |
||
928 | struct radeon_ring *ring); |
||
929 | uint32_t uvd_v1_0_get_wptr(struct radeon_device *rdev, |
||
930 | struct radeon_ring *ring); |
||
931 | void uvd_v1_0_set_wptr(struct radeon_device *rdev, |
||
932 | struct radeon_ring *ring); |
||
5271 | serge | 933 | int uvd_v1_0_resume(struct radeon_device *rdev); |
5078 | serge | 934 | |
935 | int uvd_v1_0_init(struct radeon_device *rdev); |
||
936 | void uvd_v1_0_fini(struct radeon_device *rdev); |
||
937 | int uvd_v1_0_start(struct radeon_device *rdev); |
||
938 | void uvd_v1_0_stop(struct radeon_device *rdev); |
||
939 | |||
940 | int uvd_v1_0_ring_test(struct radeon_device *rdev, struct radeon_ring *ring); |
||
5271 | serge | 941 | void uvd_v1_0_fence_emit(struct radeon_device *rdev, |
942 | struct radeon_fence *fence); |
||
5078 | serge | 943 | int uvd_v1_0_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); |
944 | bool uvd_v1_0_semaphore_emit(struct radeon_device *rdev, |
||
945 | struct radeon_ring *ring, |
||
946 | struct radeon_semaphore *semaphore, |
||
947 | bool emit_wait); |
||
948 | void uvd_v1_0_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); |
||
949 | |||
950 | /* uvd v2.2 */ |
||
951 | int uvd_v2_2_resume(struct radeon_device *rdev); |
||
952 | void uvd_v2_2_fence_emit(struct radeon_device *rdev, |
||
953 | struct radeon_fence *fence); |
||
6104 | serge | 954 | bool uvd_v2_2_semaphore_emit(struct radeon_device *rdev, |
955 | struct radeon_ring *ring, |
||
956 | struct radeon_semaphore *semaphore, |
||
957 | bool emit_wait); |
||
5078 | serge | 958 | |
959 | /* uvd v3.1 */ |
||
960 | bool uvd_v3_1_semaphore_emit(struct radeon_device *rdev, |
||
961 | struct radeon_ring *ring, |
||
962 | struct radeon_semaphore *semaphore, |
||
963 | bool emit_wait); |
||
964 | |||
965 | /* uvd v4.2 */ |
||
966 | int uvd_v4_2_resume(struct radeon_device *rdev); |
||
967 | |||
968 | /* vce v1.0 */ |
||
969 | uint32_t vce_v1_0_get_rptr(struct radeon_device *rdev, |
||
970 | struct radeon_ring *ring); |
||
971 | uint32_t vce_v1_0_get_wptr(struct radeon_device *rdev, |
||
972 | struct radeon_ring *ring); |
||
973 | void vce_v1_0_set_wptr(struct radeon_device *rdev, |
||
974 | struct radeon_ring *ring); |
||
6104 | serge | 975 | int vce_v1_0_load_fw(struct radeon_device *rdev, uint32_t *data); |
976 | unsigned vce_v1_0_bo_size(struct radeon_device *rdev); |
||
977 | int vce_v1_0_resume(struct radeon_device *rdev); |
||
5078 | serge | 978 | int vce_v1_0_init(struct radeon_device *rdev); |
979 | int vce_v1_0_start(struct radeon_device *rdev); |
||
980 | |||
981 | /* vce v2.0 */ |
||
6104 | serge | 982 | unsigned vce_v2_0_bo_size(struct radeon_device *rdev); |
5078 | serge | 983 | int vce_v2_0_resume(struct radeon_device *rdev); |
984 | |||
1117 | serge | 985 | #endif |