WebSVN – Kolibri OS – Blame – /drivers/video/drm/radeon/radeon_asic.c

Rev	Author	Line No.	Line
1963	serge	1	/*
		2	* Copyright 2008 Advanced Micro Devices, Inc.
		3	* Copyright 2008 Red Hat Inc.
		4	* Copyright 2009 Jerome Glisse.
		5	*
		6	* Permission is hereby granted, free of charge, to any person obtaining a
		7	* copy of this software and associated documentation files (the "Software"),
		8	* to deal in the Software without restriction, including without limitation
		9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		10	* and/or sell copies of the Software, and to permit persons to whom the
		11	* Software is furnished to do so, subject to the following conditions:
		12	*
		13	* The above copyright notice and this permission notice shall be included in
		14	* all copies or substantial portions of the Software.
		15	*
		16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
		20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
		21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
		22	* OTHER DEALINGS IN THE SOFTWARE.
		23	*
		24	* Authors: Dave Airlie
		25	* Alex Deucher
		26	* Jerome Glisse
		27	*/
		28
		29	//#include
		30	#include
		31	#include
		32	#include
		33	//#include
		34	//#include
		35	#include "radeon_reg.h"
		36	#include "radeon.h"
		37	#include "radeon_asic.h"
		38	#include "atom.h"
		39
		40	/*
		41	* Registers accessors functions.
		42	*/
2997	Serge	43	/**
		44	* radeon_invalid_rreg - dummy reg read function
		45	*
		46	* @rdev: radeon device pointer
		47	* @reg: offset of register
		48	*
		49	* Dummy register read function. Used for register blocks
		50	* that certain asics don't have (all asics).
		51	* Returns the value in the register.
		52	*/
1963	serge	53	static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
		54	{
		55	DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
		56	BUG_ON(1);
		57	return 0;
		58	}
		59
2997	Serge	60	/**
		61	* radeon_invalid_wreg - dummy reg write function
		62	*
		63	* @rdev: radeon device pointer
		64	* @reg: offset of register
		65	* @v: value to write to the register
		66	*
		67	* Dummy register read function. Used for register blocks
		68	* that certain asics don't have (all asics).
		69	*/
1963	serge	70	static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
		71	{
		72	DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
		73	reg, v);
		74	BUG_ON(1);
		75	}
		76
2997	Serge	77	/**
		78	* radeon_register_accessor_init - sets up the register accessor callbacks
		79	*
		80	* @rdev: radeon device pointer
		81	*
		82	* Sets up the register accessor callbacks for various register
		83	* apertures. Not all asics have all apertures (all asics).
		84	*/
1963	serge	85	static void radeon_register_accessor_init(struct radeon_device *rdev)
		86	{
		87	rdev->mc_rreg = &radeon_invalid_rreg;
		88	rdev->mc_wreg = &radeon_invalid_wreg;
		89	rdev->pll_rreg = &radeon_invalid_rreg;
		90	rdev->pll_wreg = &radeon_invalid_wreg;
		91	rdev->pciep_rreg = &radeon_invalid_rreg;
		92	rdev->pciep_wreg = &radeon_invalid_wreg;
		93
		94	/* Don't change order as we are overridding accessor. */
		95	if (rdev->family < CHIP_RV515) {
		96	rdev->pcie_reg_mask = 0xff;
		97	} else {
		98	rdev->pcie_reg_mask = 0x7ff;
		99	}
		100	/* FIXME: not sure here */
		101	if (rdev->family <= CHIP_R580) {
		102	rdev->pll_rreg = &r100_pll_rreg;
		103	rdev->pll_wreg = &r100_pll_wreg;
		104	}
		105	if (rdev->family >= CHIP_R420) {
		106	rdev->mc_rreg = &r420_mc_rreg;
		107	rdev->mc_wreg = &r420_mc_wreg;
		108	}
		109	if (rdev->family >= CHIP_RV515) {
		110	rdev->mc_rreg = &rv515_mc_rreg;
		111	rdev->mc_wreg = &rv515_mc_wreg;
		112	}
		113	if (rdev->family == CHIP_RS400 \|\| rdev->family == CHIP_RS480) {
		114	rdev->mc_rreg = &rs400_mc_rreg;
		115	rdev->mc_wreg = &rs400_mc_wreg;
		116	}
		117	if (rdev->family == CHIP_RS690 \|\| rdev->family == CHIP_RS740) {
		118	rdev->mc_rreg = &rs690_mc_rreg;
		119	rdev->mc_wreg = &rs690_mc_wreg;
		120	}
		121	if (rdev->family == CHIP_RS600) {
		122	rdev->mc_rreg = &rs600_mc_rreg;
		123	rdev->mc_wreg = &rs600_mc_wreg;
		124	}
3764	Serge	125	if (rdev->family == CHIP_RS780 \|\| rdev->family == CHIP_RS880) {
		126	rdev->mc_rreg = &rs780_mc_rreg;
		127	rdev->mc_wreg = &rs780_mc_wreg;
		128	}
5078	serge	129
		130	if (rdev->family >= CHIP_BONAIRE) {
		131	rdev->pciep_rreg = &cik_pciep_rreg;
		132	rdev->pciep_wreg = &cik_pciep_wreg;
		133	} else if (rdev->family >= CHIP_R600) {
1963	serge	134	rdev->pciep_rreg = &r600_pciep_rreg;
		135	rdev->pciep_wreg = &r600_pciep_wreg;
		136	}
		137	}
		138
		139
		140	/* helper to disable agp */
2997	Serge	141	/**
		142	* radeon_agp_disable - AGP disable helper function
		143	*
		144	* @rdev: radeon device pointer
		145	*
		146	* Removes AGP flags and changes the gart callbacks on AGP
		147	* cards when using the internal gart rather than AGP (all asics).
		148	*/
1963	serge	149	void radeon_agp_disable(struct radeon_device *rdev)
		150	{
		151	rdev->flags &= ~RADEON_IS_AGP;
		152	if (rdev->family >= CHIP_R600) {
		153	DRM_INFO("Forcing AGP to PCIE mode\n");
		154	rdev->flags \|= RADEON_IS_PCIE;
		155	} else if (rdev->family >= CHIP_RV515 \|\|
		156	rdev->family == CHIP_RV380 \|\|
		157	rdev->family == CHIP_RV410 \|\|
		158	rdev->family == CHIP_R423) {
		159	DRM_INFO("Forcing AGP to PCIE mode\n");
		160	rdev->flags \|= RADEON_IS_PCIE;
2997	Serge	161	rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush;
		162	rdev->asic->gart.set_page = &rv370_pcie_gart_set_page;
1963	serge	163	} else {
		164	DRM_INFO("Forcing AGP to PCI mode\n");
		165	rdev->flags \|= RADEON_IS_PCI;
2997	Serge	166	rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
		167	rdev->asic->gart.set_page = &r100_pci_gart_set_page;
1963	serge	168	}
		169	rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
		170	}
		171
		172	/*
		173	* ASIC
		174	*/
5078	serge	175
		176	static struct radeon_asic_ring r100_gfx_ring = {
		177	.ib_execute = &r100_ring_ib_execute,
		178	.emit_fence = &r100_fence_ring_emit,
		179	.emit_semaphore = &r100_semaphore_ring_emit,
		180	.cs_parse = &r100_cs_parse,
		181	.ring_start = &r100_ring_start,
		182	.ring_test = &r100_ring_test,
		183	.ib_test = &r100_ib_test,
		184	.is_lockup = &r100_gpu_is_lockup,
		185	.get_rptr = &r100_gfx_get_rptr,
		186	.get_wptr = &r100_gfx_get_wptr,
		187	.set_wptr = &r100_gfx_set_wptr,
		188	.hdp_flush = &r100_ring_hdp_flush,
		189	};
		190
1963	serge	191	static struct radeon_asic r100_asic = {
		192	.init = &r100_init,
		193	// .fini = &r100_fini,
		194	// .suspend = &r100_suspend,
		195	// .resume = &r100_resume,
		196	// .vga_set_state = &r100_vga_set_state,
		197	.asic_reset = &r100_asic_reset,
5078	serge	198	.mmio_hdp_flush = NULL,
2997	Serge	199	.gui_idle = &r100_gui_idle,
		200	.mc_wait_for_idle = &r100_mc_wait_for_idle,
		201	.gart = {
		202	.tlb_flush = &r100_pci_gart_tlb_flush,
		203	.set_page = &r100_pci_gart_set_page,
		204	},
		205	.ring = {
5078	serge	206	[RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring
2997	Serge	207	},
		208	.irq = {
		209	.set = &r100_irq_set,
		210	.process = &r100_irq_process,
		211	},
		212	.display = {
		213	.bandwidth_update = &r100_bandwidth_update,
		214	.get_vblank_counter = &r100_get_vblank_counter,
		215	.wait_for_vblank = &r100_wait_for_vblank,
5078	serge	216	.set_backlight_level = &radeon_legacy_set_backlight_level,
		217	.get_backlight_level = &radeon_legacy_get_backlight_level,
2997	Serge	218	},
		219	.copy = {
		220	.blit = &r100_copy_blit,
		221	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		222	.dma = NULL,
		223	.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
2005	serge	224	.copy = &r100_copy_blit,
2997	Serge	225	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		226	},
		227	.surface = {
		228	.set_reg = r100_set_surface_reg,
		229	.clear_reg = r100_clear_surface_reg,
		230	},
		231	.hpd = {
5078	serge	232	.init = &r100_hpd_init,
		233	.fini = &r100_hpd_fini,
		234	.sense = &r100_hpd_sense,
		235	.set_polarity = &r100_hpd_set_polarity,
2997	Serge	236	},
		237	.pm = {
5078	serge	238	.misc = &r100_pm_misc,
		239	.prepare = &r100_pm_prepare,
		240	.finish = &r100_pm_finish,
		241	.init_profile = &r100_pm_init_profile,
		242	.get_dynpm_state = &r100_pm_get_dynpm_state,
		243	.get_engine_clock = &radeon_legacy_get_engine_clock,
		244	.set_engine_clock = &radeon_legacy_set_engine_clock,
		245	.get_memory_clock = &radeon_legacy_get_memory_clock,
3192	Serge	246	.set_memory_clock = NULL,
		247	.get_pcie_lanes = NULL,
		248	.set_pcie_lanes = NULL,
5078	serge	249	.set_clock_gating = &radeon_legacy_set_clock_gating,
2997	Serge	250	},
		251	.pflip = {
		252	// .pre_page_flip = &r100_pre_page_flip,
		253	// .page_flip = &r100_page_flip,
		254	},
1963	serge	255	};
		256
		257	static struct radeon_asic r200_asic = {
		258	.init = &r100_init,
		259	// .fini = &r100_fini,
		260	// .suspend = &r100_suspend,
		261	// .resume = &r100_resume,
		262	// .vga_set_state = &r100_vga_set_state,
		263	.asic_reset = &r100_asic_reset,
5078	serge	264	.mmio_hdp_flush = NULL,
2007	serge	265	.gui_idle = &r100_gui_idle,
2997	Serge	266	.mc_wait_for_idle = &r100_mc_wait_for_idle,
		267	.gart = {
		268	.tlb_flush = &r100_pci_gart_tlb_flush,
		269	.set_page = &r100_pci_gart_set_page,
		270	},
		271	.ring = {
5078	serge	272	[RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring
2997	Serge	273	},
		274	.irq = {
		275	.set = &r100_irq_set,
		276	.process = &r100_irq_process,
		277	},
		278	.display = {
		279	.bandwidth_update = &r100_bandwidth_update,
		280	.get_vblank_counter = &r100_get_vblank_counter,
		281	.wait_for_vblank = &r100_wait_for_vblank,
5078	serge	282	.set_backlight_level = &radeon_legacy_set_backlight_level,
		283	.get_backlight_level = &radeon_legacy_get_backlight_level,
2997	Serge	284	},
		285	.copy = {
		286	.blit = &r100_copy_blit,
		287	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		288	.dma = &r200_copy_dma,
		289	.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		290	.copy = &r100_copy_blit,
		291	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		292	},
		293	.surface = {
		294	.set_reg = r100_set_surface_reg,
		295	.clear_reg = r100_clear_surface_reg,
		296	},
		297	.hpd = {
5078	serge	298	.init = &r100_hpd_init,
		299	.fini = &r100_hpd_fini,
		300	.sense = &r100_hpd_sense,
		301	.set_polarity = &r100_hpd_set_polarity,
2997	Serge	302	},
		303	.pm = {
5078	serge	304	.misc = &r100_pm_misc,
		305	.prepare = &r100_pm_prepare,
		306	.finish = &r100_pm_finish,
		307	.init_profile = &r100_pm_init_profile,
		308	.get_dynpm_state = &r100_pm_get_dynpm_state,
		309	.get_engine_clock = &radeon_legacy_get_engine_clock,
		310	.set_engine_clock = &radeon_legacy_set_engine_clock,
		311	.get_memory_clock = &radeon_legacy_get_memory_clock,
3192	Serge	312	.set_memory_clock = NULL,
		313	.get_pcie_lanes = NULL,
		314	.set_pcie_lanes = NULL,
5078	serge	315	.set_clock_gating = &radeon_legacy_set_clock_gating,
2997	Serge	316	},
		317	.pflip = {
		318	// .pre_page_flip = &r100_pre_page_flip,
		319	// .page_flip = &r100_page_flip,
		320	},
1963	serge	321	};
		322
5078	serge	323	static struct radeon_asic_ring r300_gfx_ring = {
		324	.ib_execute = &r100_ring_ib_execute,
		325	.emit_fence = &r300_fence_ring_emit,
		326	.emit_semaphore = &r100_semaphore_ring_emit,
		327	.cs_parse = &r300_cs_parse,
		328	.ring_start = &r300_ring_start,
		329	.ring_test = &r100_ring_test,
		330	.ib_test = &r100_ib_test,
		331	.is_lockup = &r100_gpu_is_lockup,
		332	.get_rptr = &r100_gfx_get_rptr,
		333	.get_wptr = &r100_gfx_get_wptr,
		334	.set_wptr = &r100_gfx_set_wptr,
		335	.hdp_flush = &r100_ring_hdp_flush,
		336	};
		337
1963	serge	338	static struct radeon_asic r300_asic = {
		339	.init = &r300_init,
		340	// .fini = &r300_fini,
		341	// .suspend = &r300_suspend,
		342	// .resume = &r300_resume,
		343	// .vga_set_state = &r100_vga_set_state,
		344	.asic_reset = &r300_asic_reset,
5078	serge	345	.mmio_hdp_flush = NULL,
2007	serge	346	.gui_idle = &r100_gui_idle,
2997	Serge	347	.mc_wait_for_idle = &r300_mc_wait_for_idle,
		348	.gart = {
		349	.tlb_flush = &r100_pci_gart_tlb_flush,
		350	.set_page = &r100_pci_gart_set_page,
		351	},
		352	.ring = {
5078	serge	353	[RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
2997	Serge	354	},
		355	.irq = {
		356	.set = &r100_irq_set,
		357	.process = &r100_irq_process,
		358	},
		359	.display = {
		360	.bandwidth_update = &r100_bandwidth_update,
		361	.get_vblank_counter = &r100_get_vblank_counter,
		362	.wait_for_vblank = &r100_wait_for_vblank,
5078	serge	363	.set_backlight_level = &radeon_legacy_set_backlight_level,
		364	.get_backlight_level = &radeon_legacy_get_backlight_level,
2997	Serge	365	},
		366	.copy = {
		367	.blit = &r100_copy_blit,
		368	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		369	.dma = &r200_copy_dma,
		370	.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		371	.copy = &r100_copy_blit,
		372	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		373	},
		374	.surface = {
		375	.set_reg = r100_set_surface_reg,
		376	.clear_reg = r100_clear_surface_reg,
		377	},
		378	.hpd = {
5078	serge	379	.init = &r100_hpd_init,
		380	.fini = &r100_hpd_fini,
		381	.sense = &r100_hpd_sense,
		382	.set_polarity = &r100_hpd_set_polarity,
2997	Serge	383	},
		384	.pm = {
5078	serge	385	.misc = &r100_pm_misc,
		386	.prepare = &r100_pm_prepare,
		387	.finish = &r100_pm_finish,
		388	.init_profile = &r100_pm_init_profile,
		389	.get_dynpm_state = &r100_pm_get_dynpm_state,
		390	.get_engine_clock = &radeon_legacy_get_engine_clock,
		391	.set_engine_clock = &radeon_legacy_set_engine_clock,
		392	.get_memory_clock = &radeon_legacy_get_memory_clock,
		393	.set_memory_clock = NULL,
		394	.get_pcie_lanes = &rv370_get_pcie_lanes,
		395	.set_pcie_lanes = &rv370_set_pcie_lanes,
		396	.set_clock_gating = &radeon_legacy_set_clock_gating,
2997	Serge	397	},
		398	.pflip = {
		399	// .pre_page_flip = &r100_pre_page_flip,
		400	// .page_flip = &r100_page_flip,
		401	},
1963	serge	402	};
		403
		404	static struct radeon_asic r300_asic_pcie = {
		405	.init = &r300_init,
		406	// .fini = &r300_fini,
		407	// .suspend = &r300_suspend,
		408	// .resume = &r300_resume,
		409	// .vga_set_state = &r100_vga_set_state,
		410	.asic_reset = &r300_asic_reset,
5078	serge	411	.mmio_hdp_flush = NULL,
2007	serge	412	.gui_idle = &r100_gui_idle,
2997	Serge	413	.mc_wait_for_idle = &r300_mc_wait_for_idle,
		414	.gart = {
		415	.tlb_flush = &rv370_pcie_gart_tlb_flush,
		416	.set_page = &rv370_pcie_gart_set_page,
		417	},
		418	.ring = {
5078	serge	419	[RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
2997	Serge	420	},
		421	.irq = {
		422	.set = &r100_irq_set,
		423	.process = &r100_irq_process,
		424	},
		425	.display = {
		426	.bandwidth_update = &r100_bandwidth_update,
		427	.get_vblank_counter = &r100_get_vblank_counter,
		428	.wait_for_vblank = &r100_wait_for_vblank,
5078	serge	429	.set_backlight_level = &radeon_legacy_set_backlight_level,
		430	.get_backlight_level = &radeon_legacy_get_backlight_level,
2997	Serge	431	},
		432	.copy = {
		433	.blit = &r100_copy_blit,
		434	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		435	.dma = &r200_copy_dma,
		436	.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		437	.copy = &r100_copy_blit,
		438	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		439	},
		440	.surface = {
		441	.set_reg = r100_set_surface_reg,
		442	.clear_reg = r100_clear_surface_reg,
		443	},
		444	.hpd = {
		445	.init = &r100_hpd_init,
		446	.fini = &r100_hpd_fini,
		447	.sense = &r100_hpd_sense,
		448	.set_polarity = &r100_hpd_set_polarity,
		449	},
		450	.pm = {
5078	serge	451	.misc = &r100_pm_misc,
		452	.prepare = &r100_pm_prepare,
		453	.finish = &r100_pm_finish,
		454	.init_profile = &r100_pm_init_profile,
		455	.get_dynpm_state = &r100_pm_get_dynpm_state,
		456	.get_engine_clock = &radeon_legacy_get_engine_clock,
		457	.set_engine_clock = &radeon_legacy_set_engine_clock,
		458	.get_memory_clock = &radeon_legacy_get_memory_clock,
		459	.set_memory_clock = NULL,
		460	.get_pcie_lanes = &rv370_get_pcie_lanes,
		461	.set_pcie_lanes = &rv370_set_pcie_lanes,
		462	.set_clock_gating = &radeon_legacy_set_clock_gating,
2997	Serge	463	},
		464	.pflip = {
		465	// .pre_page_flip = &r100_pre_page_flip,
		466	// .page_flip = &r100_page_flip,
		467	},
1963	serge	468	};
		469
		470	static struct radeon_asic r420_asic = {
		471	.init = &r420_init,
		472	// .fini = &r420_fini,
		473	// .suspend = &r420_suspend,
		474	// .resume = &r420_resume,
		475	// .vga_set_state = &r100_vga_set_state,
		476	.asic_reset = &r300_asic_reset,
5078	serge	477	.mmio_hdp_flush = NULL,
2160	serge	478	.gui_idle = &r100_gui_idle,
2997	Serge	479	.mc_wait_for_idle = &r300_mc_wait_for_idle,
		480	.gart = {
		481	.tlb_flush = &rv370_pcie_gart_tlb_flush,
		482	.set_page = &rv370_pcie_gart_set_page,
		483	},
		484	.ring = {
5078	serge	485	[RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
2997	Serge	486	},
		487	.irq = {
		488	.set = &r100_irq_set,
		489	.process = &r100_irq_process,
		490	},
		491	.display = {
		492	.bandwidth_update = &r100_bandwidth_update,
		493	.get_vblank_counter = &r100_get_vblank_counter,
		494	.wait_for_vblank = &r100_wait_for_vblank,
5078	serge	495	.set_backlight_level = &atombios_set_backlight_level,
		496	.get_backlight_level = &atombios_get_backlight_level,
2997	Serge	497	},
		498	.copy = {
		499	.blit = &r100_copy_blit,
		500	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		501	.dma = &r200_copy_dma,
		502	.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		503	.copy = &r100_copy_blit,
		504	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		505	},
		506	.surface = {
		507	.set_reg = r100_set_surface_reg,
		508	.clear_reg = r100_clear_surface_reg,
		509	},
		510	.hpd = {
5078	serge	511	.init = &r100_hpd_init,
		512	.fini = &r100_hpd_fini,
		513	.sense = &r100_hpd_sense,
		514	.set_polarity = &r100_hpd_set_polarity,
2997	Serge	515	},
		516	.pm = {
5078	serge	517	.misc = &r100_pm_misc,
		518	.prepare = &r100_pm_prepare,
		519	.finish = &r100_pm_finish,
		520	.init_profile = &r420_pm_init_profile,
		521	.get_dynpm_state = &r100_pm_get_dynpm_state,
		522	.get_engine_clock = &radeon_atom_get_engine_clock,
		523	.set_engine_clock = &radeon_atom_set_engine_clock,
		524	.get_memory_clock = &radeon_atom_get_memory_clock,
		525	.set_memory_clock = &radeon_atom_set_memory_clock,
		526	.get_pcie_lanes = &rv370_get_pcie_lanes,
		527	.set_pcie_lanes = &rv370_set_pcie_lanes,
		528	.set_clock_gating = &radeon_atom_set_clock_gating,
2997	Serge	529	},
		530	.pflip = {
		531	// .pre_page_flip = &r100_pre_page_flip,
		532	// .page_flip = &r100_page_flip,
		533	},
1963	serge	534	};
		535
		536	static struct radeon_asic rs400_asic = {
		537	.init = &rs400_init,
		538	// .fini = &rs400_fini,
		539	// .suspend = &rs400_suspend,
		540	// .resume = &rs400_resume,
		541	// .vga_set_state = &r100_vga_set_state,
		542	.asic_reset = &r300_asic_reset,
5078	serge	543	.mmio_hdp_flush = NULL,
2160	serge	544	.gui_idle = &r100_gui_idle,
2997	Serge	545	.mc_wait_for_idle = &rs400_mc_wait_for_idle,
		546	.gart = {
		547	.tlb_flush = &rs400_gart_tlb_flush,
		548	.set_page = &rs400_gart_set_page,
		549	},
		550	.ring = {
5078	serge	551	[RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
2997	Serge	552	},
		553	.irq = {
		554	.set = &r100_irq_set,
		555	.process = &r100_irq_process,
		556	},
		557	.display = {
		558	.bandwidth_update = &r100_bandwidth_update,
		559	.get_vblank_counter = &r100_get_vblank_counter,
		560	.wait_for_vblank = &r100_wait_for_vblank,
5078	serge	561	.set_backlight_level = &radeon_legacy_set_backlight_level,
		562	.get_backlight_level = &radeon_legacy_get_backlight_level,
2997	Serge	563	},
		564	.copy = {
		565	.blit = &r100_copy_blit,
		566	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		567	.dma = &r200_copy_dma,
		568	.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		569	.copy = &r100_copy_blit,
		570	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		571	},
		572	.surface = {
		573	.set_reg = r100_set_surface_reg,
		574	.clear_reg = r100_clear_surface_reg,
		575	},
		576	.hpd = {
5078	serge	577	.init = &r100_hpd_init,
		578	.fini = &r100_hpd_fini,
		579	.sense = &r100_hpd_sense,
		580	.set_polarity = &r100_hpd_set_polarity,
2997	Serge	581	},
		582	.pm = {
5078	serge	583	.misc = &r100_pm_misc,
		584	.prepare = &r100_pm_prepare,
		585	.finish = &r100_pm_finish,
		586	.init_profile = &r100_pm_init_profile,
		587	.get_dynpm_state = &r100_pm_get_dynpm_state,
		588	.get_engine_clock = &radeon_legacy_get_engine_clock,
		589	.set_engine_clock = &radeon_legacy_set_engine_clock,
		590	.get_memory_clock = &radeon_legacy_get_memory_clock,
		591	.set_memory_clock = NULL,
		592	.get_pcie_lanes = NULL,
		593	.set_pcie_lanes = NULL,
		594	.set_clock_gating = &radeon_legacy_set_clock_gating,
2997	Serge	595	},
		596	.pflip = {
		597	// .pre_page_flip = &r100_pre_page_flip,
		598	// .page_flip = &r100_page_flip,
		599	},
1963	serge	600	};
		601
		602	static struct radeon_asic rs600_asic = {
		603	.init = &rs600_init,
		604	// .fini = &rs600_fini,
		605	// .suspend = &rs600_suspend,
		606	// .resume = &rs600_resume,
		607	// .vga_set_state = &r100_vga_set_state,
		608	.asic_reset = &rs600_asic_reset,
5078	serge	609	.mmio_hdp_flush = NULL,
2160	serge	610	.gui_idle = &r100_gui_idle,
2997	Serge	611	.mc_wait_for_idle = &rs600_mc_wait_for_idle,
		612	.gart = {
		613	.tlb_flush = &rs600_gart_tlb_flush,
		614	.set_page = &rs600_gart_set_page,
		615	},
		616	.ring = {
5078	serge	617	[RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
2997	Serge	618	},
		619	.irq = {
		620	.set = &rs600_irq_set,
		621	.process = &rs600_irq_process,
		622	},
		623	.display = {
		624	.bandwidth_update = &rs600_bandwidth_update,
		625	.get_vblank_counter = &rs600_get_vblank_counter,
		626	.wait_for_vblank = &avivo_wait_for_vblank,
5078	serge	627	.set_backlight_level = &atombios_set_backlight_level,
		628	.get_backlight_level = &atombios_get_backlight_level,
		629	.hdmi_enable = &r600_hdmi_enable,
		630	.hdmi_setmode = &r600_hdmi_setmode,
2997	Serge	631	},
		632	.copy = {
		633	.blit = &r100_copy_blit,
		634	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		635	.dma = &r200_copy_dma,
		636	.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		637	.copy = &r100_copy_blit,
		638	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		639	},
		640	.surface = {
		641	.set_reg = r100_set_surface_reg,
		642	.clear_reg = r100_clear_surface_reg,
		643	},
		644	.hpd = {
5078	serge	645	.init = &rs600_hpd_init,
		646	.fini = &rs600_hpd_fini,
		647	.sense = &rs600_hpd_sense,
		648	.set_polarity = &rs600_hpd_set_polarity,
2997	Serge	649	},
		650	.pm = {
5078	serge	651	.misc = &rs600_pm_misc,
		652	.prepare = &rs600_pm_prepare,
		653	.finish = &rs600_pm_finish,
		654	.init_profile = &r420_pm_init_profile,
		655	.get_dynpm_state = &r100_pm_get_dynpm_state,
		656	.get_engine_clock = &radeon_atom_get_engine_clock,
		657	.set_engine_clock = &radeon_atom_set_engine_clock,
		658	.get_memory_clock = &radeon_atom_get_memory_clock,
		659	.set_memory_clock = &radeon_atom_set_memory_clock,
3120	serge	660	.get_pcie_lanes = NULL,
		661	.set_pcie_lanes = NULL,
5078	serge	662	.set_clock_gating = &radeon_atom_set_clock_gating,
2997	Serge	663	},
		664	.pflip = {
		665	// .pre_page_flip = &rs600_pre_page_flip,
		666	// .page_flip = &rs600_page_flip,
		667	},
1963	serge	668	};
		669
		670	static struct radeon_asic rs690_asic = {
		671	.init = &rs690_init,
		672	// .fini = &rs690_fini,
		673	// .suspend = &rs690_suspend,
		674	// .resume = &rs690_resume,
		675	// .vga_set_state = &r100_vga_set_state,
		676	.asic_reset = &rs600_asic_reset,
5078	serge	677	.mmio_hdp_flush = NULL,
2160	serge	678	.gui_idle = &r100_gui_idle,
2997	Serge	679	.mc_wait_for_idle = &rs690_mc_wait_for_idle,
		680	.gart = {
		681	.tlb_flush = &rs400_gart_tlb_flush,
		682	.set_page = &rs400_gart_set_page,
		683	},
		684	.ring = {
5078	serge	685	[RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
2997	Serge	686	},
		687	.irq = {
		688	.set = &rs600_irq_set,
		689	.process = &rs600_irq_process,
		690	},
		691	.display = {
		692	.get_vblank_counter = &rs600_get_vblank_counter,
		693	.bandwidth_update = &rs690_bandwidth_update,
		694	.wait_for_vblank = &avivo_wait_for_vblank,
5078	serge	695	.set_backlight_level = &atombios_set_backlight_level,
		696	.get_backlight_level = &atombios_get_backlight_level,
		697	.hdmi_enable = &r600_hdmi_enable,
		698	.hdmi_setmode = &r600_hdmi_setmode,
2997	Serge	699	},
		700	.copy = {
		701	.blit = &r100_copy_blit,
		702	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		703	.dma = &r200_copy_dma,
		704	.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		705	.copy = &r200_copy_dma,
		706	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		707	},
		708	.surface = {
		709	.set_reg = r100_set_surface_reg,
		710	.clear_reg = r100_clear_surface_reg,
		711	},
		712	.hpd = {
5078	serge	713	.init = &rs600_hpd_init,
		714	.fini = &rs600_hpd_fini,
2997	Serge	715	.sense = &rs600_hpd_sense,
		716	.set_polarity = &rs600_hpd_set_polarity,
		717	},
		718	.pm = {
5078	serge	719	.misc = &rs600_pm_misc,
		720	.prepare = &rs600_pm_prepare,
		721	.finish = &rs600_pm_finish,
		722	.init_profile = &r420_pm_init_profile,
		723	.get_dynpm_state = &r100_pm_get_dynpm_state,
		724	.get_engine_clock = &radeon_atom_get_engine_clock,
		725	.set_engine_clock = &radeon_atom_set_engine_clock,
		726	.get_memory_clock = &radeon_atom_get_memory_clock,
		727	.set_memory_clock = &radeon_atom_set_memory_clock,
3120	serge	728	.get_pcie_lanes = NULL,
		729	.set_pcie_lanes = NULL,
5078	serge	730	.set_clock_gating = &radeon_atom_set_clock_gating,
2997	Serge	731	},
		732	.pflip = {
		733	// .pre_page_flip = &rs600_pre_page_flip,
		734	// .page_flip = &rs600_page_flip,
		735	},
1963	serge	736	};
		737
		738	static struct radeon_asic rv515_asic = {
		739	.init = &rv515_init,
		740	// .fini = &rv515_fini,
		741	// .suspend = &rv515_suspend,
		742	// .resume = &rv515_resume,
		743	// .vga_set_state = &r100_vga_set_state,
		744	.asic_reset = &rs600_asic_reset,
5078	serge	745	.mmio_hdp_flush = NULL,
2160	serge	746	.gui_idle = &r100_gui_idle,
2997	Serge	747	.mc_wait_for_idle = &rv515_mc_wait_for_idle,
		748	.gart = {
		749	.tlb_flush = &rv370_pcie_gart_tlb_flush,
		750	.set_page = &rv370_pcie_gart_set_page,
		751	},
		752	.ring = {
5078	serge	753	[RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
2997	Serge	754	},
		755	.irq = {
		756	.set = &rs600_irq_set,
		757	.process = &rs600_irq_process,
		758	},
		759	.display = {
		760	.get_vblank_counter = &rs600_get_vblank_counter,
		761	.bandwidth_update = &rv515_bandwidth_update,
		762	.wait_for_vblank = &avivo_wait_for_vblank,
5078	serge	763	.set_backlight_level = &atombios_set_backlight_level,
		764	.get_backlight_level = &atombios_get_backlight_level,
2997	Serge	765	},
		766	.copy = {
		767	.blit = &r100_copy_blit,
		768	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		769	.dma = &r200_copy_dma,
		770	.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		771	.copy = &r100_copy_blit,
		772	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		773	},
		774	.surface = {
		775	.set_reg = r100_set_surface_reg,
		776	.clear_reg = r100_clear_surface_reg,
		777	},
		778	.hpd = {
5078	serge	779	.init = &rs600_hpd_init,
		780	.fini = &rs600_hpd_fini,
		781	.sense = &rs600_hpd_sense,
		782	.set_polarity = &rs600_hpd_set_polarity,
2997	Serge	783	},
		784	.pm = {
5078	serge	785	.misc = &rs600_pm_misc,
		786	.prepare = &rs600_pm_prepare,
		787	.finish = &rs600_pm_finish,
		788	.init_profile = &r420_pm_init_profile,
		789	.get_dynpm_state = &r100_pm_get_dynpm_state,
		790	.get_engine_clock = &radeon_atom_get_engine_clock,
		791	.set_engine_clock = &radeon_atom_set_engine_clock,
		792	.get_memory_clock = &radeon_atom_get_memory_clock,
		793	.set_memory_clock = &radeon_atom_set_memory_clock,
		794	.get_pcie_lanes = &rv370_get_pcie_lanes,
		795	.set_pcie_lanes = &rv370_set_pcie_lanes,
		796	.set_clock_gating = &radeon_atom_set_clock_gating,
2997	Serge	797	},
		798	.pflip = {
		799	// .pre_page_flip = &rs600_pre_page_flip,
		800	// .page_flip = &rs600_page_flip,
		801	},
1963	serge	802	};
		803
		804	static struct radeon_asic r520_asic = {
		805	.init = &r520_init,
		806	// .fini = &rv515_fini,
		807	// .suspend = &rv515_suspend,
		808	// .resume = &r520_resume,
		809	// .vga_set_state = &r100_vga_set_state,
		810	.asic_reset = &rs600_asic_reset,
5078	serge	811	.mmio_hdp_flush = NULL,
2160	serge	812	.gui_idle = &r100_gui_idle,
2997	Serge	813	.mc_wait_for_idle = &r520_mc_wait_for_idle,
		814	.gart = {
		815	.tlb_flush = &rv370_pcie_gart_tlb_flush,
		816	.set_page = &rv370_pcie_gart_set_page,
		817	},
		818	.ring = {
5078	serge	819	[RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
2997	Serge	820	},
		821	.irq = {
		822	.set = &rs600_irq_set,
		823	.process = &rs600_irq_process,
		824	},
		825	.display = {
		826	.bandwidth_update = &rv515_bandwidth_update,
		827	.get_vblank_counter = &rs600_get_vblank_counter,
		828	.wait_for_vblank = &avivo_wait_for_vblank,
5078	serge	829	.set_backlight_level = &atombios_set_backlight_level,
		830	.get_backlight_level = &atombios_get_backlight_level,
2997	Serge	831	},
		832	.copy = {
		833	.blit = &r100_copy_blit,
		834	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		835	.dma = &r200_copy_dma,
		836	.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		837	.copy = &r100_copy_blit,
		838	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		839	},
		840	.surface = {
		841	.set_reg = r100_set_surface_reg,
		842	.clear_reg = r100_clear_surface_reg,
		843	},
		844	.hpd = {
5078	serge	845	.init = &rs600_hpd_init,
		846	.fini = &rs600_hpd_fini,
		847	.sense = &rs600_hpd_sense,
		848	.set_polarity = &rs600_hpd_set_polarity,
2997	Serge	849	},
		850	.pm = {
5078	serge	851	.misc = &rs600_pm_misc,
		852	.prepare = &rs600_pm_prepare,
		853	.finish = &rs600_pm_finish,
		854	.init_profile = &r420_pm_init_profile,
		855	.get_dynpm_state = &r100_pm_get_dynpm_state,
		856	.get_engine_clock = &radeon_atom_get_engine_clock,
		857	.set_engine_clock = &radeon_atom_set_engine_clock,
		858	.get_memory_clock = &radeon_atom_get_memory_clock,
		859	.set_memory_clock = &radeon_atom_set_memory_clock,
		860	.get_pcie_lanes = &rv370_get_pcie_lanes,
		861	.set_pcie_lanes = &rv370_set_pcie_lanes,
		862	.set_clock_gating = &radeon_atom_set_clock_gating,
2997	Serge	863	},
		864	.pflip = {
		865	// .pre_page_flip = &rs600_pre_page_flip,
		866	// .page_flip = &rs600_page_flip,
		867	},
1963	serge	868	};
		869
5078	serge	870	static struct radeon_asic_ring r600_gfx_ring = {
		871	.ib_execute = &r600_ring_ib_execute,
		872	.emit_fence = &r600_fence_ring_emit,
		873	.emit_semaphore = &r600_semaphore_ring_emit,
		874	.cs_parse = &r600_cs_parse,
		875	.ring_test = &r600_ring_test,
		876	.ib_test = &r600_ib_test,
		877	.is_lockup = &r600_gfx_is_lockup,
		878	.get_rptr = &r600_gfx_get_rptr,
		879	.get_wptr = &r600_gfx_get_wptr,
		880	.set_wptr = &r600_gfx_set_wptr,
		881	};
		882
		883	static struct radeon_asic_ring r600_dma_ring = {
		884	.ib_execute = &r600_dma_ring_ib_execute,
		885	.emit_fence = &r600_dma_fence_ring_emit,
		886	.emit_semaphore = &r600_dma_semaphore_ring_emit,
		887	.cs_parse = &r600_dma_cs_parse,
		888	.ring_test = &r600_dma_ring_test,
		889	.ib_test = &r600_dma_ib_test,
		890	.is_lockup = &r600_dma_is_lockup,
		891	.get_rptr = &r600_dma_get_rptr,
		892	.get_wptr = &r600_dma_get_wptr,
		893	.set_wptr = &r600_dma_set_wptr,
		894	};
		895
1963	serge	896	static struct radeon_asic r600_asic = {
		897	.init = &r600_init,
		898	// .fini = &r600_fini,
		899	// .suspend = &r600_suspend,
		900	// .resume = &r600_resume,
2997	Serge	901	// .vga_set_state = &r600_vga_set_state,
1963	serge	902	.asic_reset = &r600_asic_reset,
5078	serge	903	.mmio_hdp_flush = r600_mmio_hdp_flush,
2997	Serge	904	.gui_idle = &r600_gui_idle,
		905	.mc_wait_for_idle = &r600_mc_wait_for_idle,
3764	Serge	906	.get_xclk = &r600_get_xclk,
		907	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,
2997	Serge	908	.gart = {
		909	.tlb_flush = &r600_pcie_gart_tlb_flush,
		910	.set_page = &rs600_gart_set_page,
		911	},
		912	.ring = {
5078	serge	913	[RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
		914	[R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
2997	Serge	915	},
		916	.irq = {
		917	.set = &r600_irq_set,
		918	.process = &r600_irq_process,
		919	},
		920	.display = {
		921	.bandwidth_update = &rv515_bandwidth_update,
		922	.get_vblank_counter = &rs600_get_vblank_counter,
		923	.wait_for_vblank = &avivo_wait_for_vblank,
5078	serge	924	.set_backlight_level = &atombios_set_backlight_level,
		925	.get_backlight_level = &atombios_get_backlight_level,
		926	.hdmi_enable = &r600_hdmi_enable,
		927	.hdmi_setmode = &r600_hdmi_setmode,
2997	Serge	928	},
		929	.copy = {
5078	serge	930	.blit = &r600_copy_cpdma,
2997	Serge	931	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
3192	Serge	932	.dma = &r600_copy_dma,
		933	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
5078	serge	934	.copy = &r600_copy_cpdma,
		935	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
2997	Serge	936	},
		937	.surface = {
		938	.set_reg = r600_set_surface_reg,
		939	.clear_reg = r600_clear_surface_reg,
		940	},
		941	.hpd = {
5078	serge	942	.init = &r600_hpd_init,
		943	.fini = &r600_hpd_fini,
		944	.sense = &r600_hpd_sense,
		945	.set_polarity = &r600_hpd_set_polarity,
2997	Serge	946	},
		947	.pm = {
5078	serge	948	.misc = &r600_pm_misc,
		949	.prepare = &rs600_pm_prepare,
		950	.finish = &rs600_pm_finish,
		951	.init_profile = &r600_pm_init_profile,
		952	.get_dynpm_state = &r600_pm_get_dynpm_state,
		953	.get_engine_clock = &radeon_atom_get_engine_clock,
		954	.set_engine_clock = &radeon_atom_set_engine_clock,
		955	.get_memory_clock = &radeon_atom_get_memory_clock,
		956	.set_memory_clock = &radeon_atom_set_memory_clock,
		957	.get_pcie_lanes = &r600_get_pcie_lanes,
		958	.set_pcie_lanes = &r600_set_pcie_lanes,
3120	serge	959	.set_clock_gating = NULL,
5078	serge	960	.get_temperature = &rv6xx_get_temp,
2997	Serge	961	},
		962	.pflip = {
		963	// .pre_page_flip = &rs600_pre_page_flip,
		964	// .page_flip = &rs600_page_flip,
		965	},
1963	serge	966	};
		967
5078	serge	968	static struct radeon_asic rv6xx_asic = {
		969	.init = &r600_init,
		970	// .fini = &r600_fini,
		971	// .suspend = &r600_suspend,
		972	// .resume = &r600_resume,
		973	// .vga_set_state = &r600_vga_set_state,
		974	.asic_reset = &r600_asic_reset,
		975	.mmio_hdp_flush = r600_mmio_hdp_flush,
		976	.gui_idle = &r600_gui_idle,
		977	.mc_wait_for_idle = &r600_mc_wait_for_idle,
		978	.get_xclk = &r600_get_xclk,
		979	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,
		980	.gart = {
		981	.tlb_flush = &r600_pcie_gart_tlb_flush,
		982	.set_page = &rs600_gart_set_page,
		983	},
		984	.ring = {
		985	[RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
		986	[R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
		987	},
		988	.irq = {
		989	.set = &r600_irq_set,
		990	.process = &r600_irq_process,
		991	},
		992	.display = {
		993	.bandwidth_update = &rv515_bandwidth_update,
		994	.get_vblank_counter = &rs600_get_vblank_counter,
		995	.wait_for_vblank = &avivo_wait_for_vblank,
		996	.set_backlight_level = &atombios_set_backlight_level,
		997	.get_backlight_level = &atombios_get_backlight_level,
		998	.hdmi_enable = &r600_hdmi_enable,
		999	.hdmi_setmode = &r600_hdmi_setmode,
		1000	},
		1001	.copy = {
		1002	.blit = &r600_copy_cpdma,
		1003	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		1004	.dma = &r600_copy_dma,
		1005	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
		1006	.copy = &r600_copy_cpdma,
		1007	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		1008	},
		1009	.surface = {
		1010	.set_reg = r600_set_surface_reg,
		1011	.clear_reg = r600_clear_surface_reg,
		1012	},
		1013	.hpd = {
		1014	.init = &r600_hpd_init,
		1015	.fini = &r600_hpd_fini,
		1016	.sense = &r600_hpd_sense,
		1017	.set_polarity = &r600_hpd_set_polarity,
		1018	},
		1019	.pm = {
		1020	.misc = &r600_pm_misc,
		1021	.prepare = &rs600_pm_prepare,
		1022	.finish = &rs600_pm_finish,
		1023	.init_profile = &r600_pm_init_profile,
		1024	.get_dynpm_state = &r600_pm_get_dynpm_state,
		1025	.get_engine_clock = &radeon_atom_get_engine_clock,
		1026	.set_engine_clock = &radeon_atom_set_engine_clock,
		1027	.get_memory_clock = &radeon_atom_get_memory_clock,
		1028	.set_memory_clock = &radeon_atom_set_memory_clock,
		1029	.get_pcie_lanes = &r600_get_pcie_lanes,
		1030	.set_pcie_lanes = &r600_set_pcie_lanes,
		1031	.set_clock_gating = NULL,
		1032	.get_temperature = &rv6xx_get_temp,
		1033	.set_uvd_clocks = &r600_set_uvd_clocks,
		1034	},
		1035	.dpm = {
		1036	.init = &rv6xx_dpm_init,
		1037	.setup_asic = &rv6xx_setup_asic,
		1038	.enable = &rv6xx_dpm_enable,
		1039	.late_enable = &r600_dpm_late_enable,
		1040	.disable = &rv6xx_dpm_disable,
		1041	.pre_set_power_state = &r600_dpm_pre_set_power_state,
		1042	.set_power_state = &rv6xx_dpm_set_power_state,
		1043	.post_set_power_state = &r600_dpm_post_set_power_state,
		1044	.display_configuration_changed = &rv6xx_dpm_display_configuration_changed,
		1045	.fini = &rv6xx_dpm_fini,
		1046	.get_sclk = &rv6xx_dpm_get_sclk,
		1047	.get_mclk = &rv6xx_dpm_get_mclk,
		1048	.print_power_state = &rv6xx_dpm_print_power_state,
		1049	.debugfs_print_current_performance_level = &rv6xx_dpm_debugfs_print_current_performance_level,
		1050	.force_performance_level = &rv6xx_dpm_force_performance_level,
		1051	},
		1052	.pflip = {
		1053	// .pre_page_flip = &rs600_pre_page_flip,
		1054	// .page_flip = &rs600_page_flip,
		1055	},
		1056	};
		1057
1963	serge	1058	static struct radeon_asic rs780_asic = {
		1059	.init = &r600_init,
		1060	// .fini = &r600_fini,
		1061	// .suspend = &r600_suspend,
		1062	// .resume = &r600_resume,
2997	Serge	1063	// .vga_set_state = &r600_vga_set_state,
1963	serge	1064	.asic_reset = &r600_asic_reset,
5078	serge	1065	.mmio_hdp_flush = r600_mmio_hdp_flush,
2997	Serge	1066	.gui_idle = &r600_gui_idle,
		1067	.mc_wait_for_idle = &r600_mc_wait_for_idle,
3764	Serge	1068	.get_xclk = &r600_get_xclk,
		1069	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,
2997	Serge	1070	.gart = {
		1071	.tlb_flush = &r600_pcie_gart_tlb_flush,
		1072	.set_page = &rs600_gart_set_page,
		1073	},
		1074	.ring = {
5078	serge	1075	[RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
		1076	[R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
2997	Serge	1077	},
		1078	.irq = {
		1079	.set = &r600_irq_set,
		1080	.process = &r600_irq_process,
		1081	},
		1082	.display = {
		1083	.bandwidth_update = &rs690_bandwidth_update,
		1084	.get_vblank_counter = &rs600_get_vblank_counter,
		1085	.wait_for_vblank = &avivo_wait_for_vblank,
5078	serge	1086	.set_backlight_level = &atombios_set_backlight_level,
		1087	.get_backlight_level = &atombios_get_backlight_level,
		1088	.hdmi_enable = &r600_hdmi_enable,
		1089	.hdmi_setmode = &r600_hdmi_setmode,
2997	Serge	1090	},
		1091	.copy = {
5078	serge	1092	.blit = &r600_copy_cpdma,
2997	Serge	1093	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
3192	Serge	1094	.dma = &r600_copy_dma,
		1095	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
5078	serge	1096	.copy = &r600_copy_cpdma,
		1097	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
2997	Serge	1098	},
		1099	.surface = {
		1100	.set_reg = r600_set_surface_reg,
		1101	.clear_reg = r600_clear_surface_reg,
		1102	},
		1103	.hpd = {
5078	serge	1104	.init = &r600_hpd_init,
		1105	.fini = &r600_hpd_fini,
		1106	.sense = &r600_hpd_sense,
		1107	.set_polarity = &r600_hpd_set_polarity,
2997	Serge	1108	},
		1109	.pm = {
5078	serge	1110	.misc = &r600_pm_misc,
		1111	.prepare = &rs600_pm_prepare,
		1112	.finish = &rs600_pm_finish,
		1113	.init_profile = &rs780_pm_init_profile,
		1114	.get_dynpm_state = &r600_pm_get_dynpm_state,
		1115	.get_engine_clock = &radeon_atom_get_engine_clock,
		1116	.set_engine_clock = &radeon_atom_set_engine_clock,
3120	serge	1117	.get_memory_clock = NULL,
		1118	.set_memory_clock = NULL,
		1119	.get_pcie_lanes = NULL,
		1120	.set_pcie_lanes = NULL,
		1121	.set_clock_gating = NULL,
5078	serge	1122	.get_temperature = &rv6xx_get_temp,
		1123	.set_uvd_clocks = &r600_set_uvd_clocks,
2997	Serge	1124	},
5078	serge	1125	.dpm = {
		1126	.init = &rs780_dpm_init,
		1127	.setup_asic = &rs780_dpm_setup_asic,
		1128	.enable = &rs780_dpm_enable,
		1129	.late_enable = &r600_dpm_late_enable,
		1130	.disable = &rs780_dpm_disable,
		1131	.pre_set_power_state = &r600_dpm_pre_set_power_state,
		1132	.set_power_state = &rs780_dpm_set_power_state,
		1133	.post_set_power_state = &r600_dpm_post_set_power_state,
		1134	.display_configuration_changed = &rs780_dpm_display_configuration_changed,
		1135	.fini = &rs780_dpm_fini,
		1136	.get_sclk = &rs780_dpm_get_sclk,
		1137	.get_mclk = &rs780_dpm_get_mclk,
		1138	.print_power_state = &rs780_dpm_print_power_state,
		1139	.debugfs_print_current_performance_level = &rs780_dpm_debugfs_print_current_performance_level,
		1140	.force_performance_level = &rs780_dpm_force_performance_level,
		1141	},
2997	Serge	1142	.pflip = {
		1143	// .pre_page_flip = &rs600_pre_page_flip,
		1144	// .page_flip = &rs600_page_flip,
		1145	},
1963	serge	1146	};
		1147
5078	serge	1148	static struct radeon_asic_ring rv770_uvd_ring = {
		1149	.ib_execute = &uvd_v1_0_ib_execute,
		1150	.emit_fence = &uvd_v2_2_fence_emit,
		1151	.emit_semaphore = &uvd_v1_0_semaphore_emit,
		1152	.cs_parse = &radeon_uvd_cs_parse,
		1153	.ring_test = &uvd_v1_0_ring_test,
		1154	.ib_test = &uvd_v1_0_ib_test,
		1155	.is_lockup = &radeon_ring_test_lockup,
		1156	.get_rptr = &uvd_v1_0_get_rptr,
		1157	.get_wptr = &uvd_v1_0_get_wptr,
		1158	.set_wptr = &uvd_v1_0_set_wptr,
		1159	};
		1160
1963	serge	1161	static struct radeon_asic rv770_asic = {
		1162	.init = &rv770_init,
		1163	// .fini = &rv770_fini,
		1164	// .suspend = &rv770_suspend,
		1165	// .resume = &rv770_resume,
		1166	.asic_reset = &r600_asic_reset,
2997	Serge	1167	// .vga_set_state = &r600_vga_set_state,
5078	serge	1168	.mmio_hdp_flush = r600_mmio_hdp_flush,
2997	Serge	1169	.gui_idle = &r600_gui_idle,
		1170	.mc_wait_for_idle = &r600_mc_wait_for_idle,
3764	Serge	1171	.get_xclk = &rv770_get_xclk,
		1172	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,
2997	Serge	1173	.gart = {
		1174	.tlb_flush = &r600_pcie_gart_tlb_flush,
		1175	.set_page = &rs600_gart_set_page,
		1176	},
		1177	.ring = {
5078	serge	1178	[RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
		1179	[R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
		1180	[R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
2997	Serge	1181	},
		1182	.irq = {
		1183	.set = &r600_irq_set,
		1184	.process = &r600_irq_process,
		1185	},
		1186	.display = {
		1187	.bandwidth_update = &rv515_bandwidth_update,
		1188	.get_vblank_counter = &rs600_get_vblank_counter,
		1189	.wait_for_vblank = &avivo_wait_for_vblank,
5078	serge	1190	.set_backlight_level = &atombios_set_backlight_level,
		1191	.get_backlight_level = &atombios_get_backlight_level,
		1192	.hdmi_enable = &r600_hdmi_enable,
		1193	.hdmi_setmode = &dce3_1_hdmi_setmode,
2997	Serge	1194	},
		1195	.copy = {
5078	serge	1196	.blit = &r600_copy_cpdma,
2997	Serge	1197	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
3764	Serge	1198	.dma = &rv770_copy_dma,
3192	Serge	1199	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
3764	Serge	1200	.copy = &rv770_copy_dma,
3192	Serge	1201	.copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2997	Serge	1202	},
		1203	.surface = {
		1204	.set_reg = r600_set_surface_reg,
		1205	.clear_reg = r600_clear_surface_reg,
		1206	},
		1207	.hpd = {
5078	serge	1208	.init = &r600_hpd_init,
		1209	.fini = &r600_hpd_fini,
		1210	.sense = &r600_hpd_sense,
		1211	.set_polarity = &r600_hpd_set_polarity,
2997	Serge	1212	},
		1213	.pm = {
5078	serge	1214	.misc = &rv770_pm_misc,
		1215	.prepare = &rs600_pm_prepare,
		1216	.finish = &rs600_pm_finish,
		1217	.init_profile = &r600_pm_init_profile,
		1218	.get_dynpm_state = &r600_pm_get_dynpm_state,
		1219	.get_engine_clock = &radeon_atom_get_engine_clock,
		1220	.set_engine_clock = &radeon_atom_set_engine_clock,
		1221	.get_memory_clock = &radeon_atom_get_memory_clock,
		1222	.set_memory_clock = &radeon_atom_set_memory_clock,
		1223	.get_pcie_lanes = &r600_get_pcie_lanes,
		1224	.set_pcie_lanes = &r600_set_pcie_lanes,
		1225	.set_clock_gating = &radeon_atom_set_clock_gating,
3764	Serge	1226	.set_uvd_clocks = &rv770_set_uvd_clocks,
5078	serge	1227	.get_temperature = &rv770_get_temp,
2997	Serge	1228	},
5078	serge	1229	.dpm = {
		1230	.init = &rv770_dpm_init,
		1231	.setup_asic = &rv770_dpm_setup_asic,
		1232	.enable = &rv770_dpm_enable,
		1233	.late_enable = &rv770_dpm_late_enable,
		1234	.disable = &rv770_dpm_disable,
		1235	.pre_set_power_state = &r600_dpm_pre_set_power_state,
		1236	.set_power_state = &rv770_dpm_set_power_state,
		1237	.post_set_power_state = &r600_dpm_post_set_power_state,
		1238	.display_configuration_changed = &rv770_dpm_display_configuration_changed,
		1239	.fini = &rv770_dpm_fini,
		1240	.get_sclk = &rv770_dpm_get_sclk,
		1241	.get_mclk = &rv770_dpm_get_mclk,
		1242	.print_power_state = &rv770_dpm_print_power_state,
		1243	.debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level,
		1244	.force_performance_level = &rv770_dpm_force_performance_level,
		1245	.vblank_too_short = &rv770_dpm_vblank_too_short,
		1246	},
2997	Serge	1247	.pflip = {
		1248	// .pre_page_flip = &rs600_pre_page_flip,
		1249	// .page_flip = &rv770_page_flip,
		1250	},
1963	serge	1251	};
1986	serge	1252
5078	serge	1253	static struct radeon_asic_ring evergreen_gfx_ring = {
		1254	.ib_execute = &evergreen_ring_ib_execute,
		1255	.emit_fence = &r600_fence_ring_emit,
		1256	.emit_semaphore = &r600_semaphore_ring_emit,
		1257	.cs_parse = &evergreen_cs_parse,
		1258	.ring_test = &r600_ring_test,
		1259	.ib_test = &r600_ib_test,
		1260	.is_lockup = &evergreen_gfx_is_lockup,
		1261	.get_rptr = &r600_gfx_get_rptr,
		1262	.get_wptr = &r600_gfx_get_wptr,
		1263	.set_wptr = &r600_gfx_set_wptr,
		1264	};
		1265
		1266	static struct radeon_asic_ring evergreen_dma_ring = {
		1267	.ib_execute = &evergreen_dma_ring_ib_execute,
		1268	.emit_fence = &evergreen_dma_fence_ring_emit,
		1269	.emit_semaphore = &r600_dma_semaphore_ring_emit,
		1270	.cs_parse = &evergreen_dma_cs_parse,
		1271	.ring_test = &r600_dma_ring_test,
		1272	.ib_test = &r600_dma_ib_test,
		1273	.is_lockup = &evergreen_dma_is_lockup,
		1274	.get_rptr = &r600_dma_get_rptr,
		1275	.get_wptr = &r600_dma_get_wptr,
		1276	.set_wptr = &r600_dma_set_wptr,
		1277	};
		1278
1963	serge	1279	static struct radeon_asic evergreen_asic = {
		1280	.init = &evergreen_init,
		1281	// .fini = &evergreen_fini,
		1282	// .suspend = &evergreen_suspend,
		1283	// .resume = &evergreen_resume,
		1284	.asic_reset = &evergreen_asic_reset,
2997	Serge	1285	// .vga_set_state = &r600_vga_set_state,
5078	serge	1286	.mmio_hdp_flush = r600_mmio_hdp_flush,
2997	Serge	1287	.gui_idle = &r600_gui_idle,
		1288	.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
3764	Serge	1289	.get_xclk = &rv770_get_xclk,
		1290	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,
2997	Serge	1291	.gart = {
		1292	.tlb_flush = &evergreen_pcie_gart_tlb_flush,
		1293	.set_page = &rs600_gart_set_page,
		1294	},
		1295	.ring = {
5078	serge	1296	[RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,
		1297	[R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring,
		1298	[R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
2997	Serge	1299	},
		1300	.irq = {
		1301	.set = &evergreen_irq_set,
		1302	.process = &evergreen_irq_process,
		1303	},
		1304	.display = {
		1305	.bandwidth_update = &evergreen_bandwidth_update,
		1306	.get_vblank_counter = &evergreen_get_vblank_counter,
		1307	.wait_for_vblank = &dce4_wait_for_vblank,
5078	serge	1308	.set_backlight_level = &atombios_set_backlight_level,
		1309	.get_backlight_level = &atombios_get_backlight_level,
		1310	.hdmi_enable = &evergreen_hdmi_enable,
		1311	.hdmi_setmode = &evergreen_hdmi_setmode,
2997	Serge	1312	},
		1313	.copy = {
5078	serge	1314	.blit = &r600_copy_cpdma,
2997	Serge	1315	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
3192	Serge	1316	.dma = &evergreen_copy_dma,
		1317	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
		1318	.copy = &evergreen_copy_dma,
		1319	.copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2997	Serge	1320	},
		1321	.surface = {
		1322	.set_reg = r600_set_surface_reg,
		1323	.clear_reg = r600_clear_surface_reg,
		1324	},
		1325	.hpd = {
5078	serge	1326	.init = &evergreen_hpd_init,
		1327	.fini = &evergreen_hpd_fini,
		1328	.sense = &evergreen_hpd_sense,
		1329	.set_polarity = &evergreen_hpd_set_polarity,
2997	Serge	1330	},
		1331	.pm = {
5078	serge	1332	.misc = &evergreen_pm_misc,
		1333	.prepare = &evergreen_pm_prepare,
		1334	.finish = &evergreen_pm_finish,
		1335	.init_profile = &r600_pm_init_profile,
		1336	.get_dynpm_state = &r600_pm_get_dynpm_state,
		1337	.get_engine_clock = &radeon_atom_get_engine_clock,
		1338	.set_engine_clock = &radeon_atom_set_engine_clock,
		1339	.get_memory_clock = &radeon_atom_get_memory_clock,
		1340	.set_memory_clock = &radeon_atom_set_memory_clock,
		1341	.get_pcie_lanes = &r600_get_pcie_lanes,
		1342	.set_pcie_lanes = &r600_set_pcie_lanes,
		1343	.set_clock_gating = NULL,
3764	Serge	1344	.set_uvd_clocks = &evergreen_set_uvd_clocks,
5078	serge	1345	.get_temperature = &evergreen_get_temp,
2997	Serge	1346	},
5078	serge	1347	.dpm = {
		1348	.init = &cypress_dpm_init,
		1349	.setup_asic = &cypress_dpm_setup_asic,
		1350	.enable = &cypress_dpm_enable,
		1351	.late_enable = &rv770_dpm_late_enable,
		1352	.disable = &cypress_dpm_disable,
		1353	.pre_set_power_state = &r600_dpm_pre_set_power_state,
		1354	.set_power_state = &cypress_dpm_set_power_state,
		1355	.post_set_power_state = &r600_dpm_post_set_power_state,
		1356	.display_configuration_changed = &cypress_dpm_display_configuration_changed,
		1357	.fini = &cypress_dpm_fini,
		1358	.get_sclk = &rv770_dpm_get_sclk,
		1359	.get_mclk = &rv770_dpm_get_mclk,
		1360	.print_power_state = &rv770_dpm_print_power_state,
		1361	.debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level,
		1362	.force_performance_level = &rv770_dpm_force_performance_level,
		1363	.vblank_too_short = &cypress_dpm_vblank_too_short,
		1364	},
2997	Serge	1365	.pflip = {
		1366	},
1986	serge	1367	};
1990	serge	1368
1986	serge	1369	static struct radeon_asic sumo_asic = {
		1370	.init = &evergreen_init,
1990	serge	1371	// .fini = &evergreen_fini,
		1372	// .suspend = &evergreen_suspend,
		1373	// .resume = &evergreen_resume,
1986	serge	1374	.asic_reset = &evergreen_asic_reset,
2997	Serge	1375	// .vga_set_state = &r600_vga_set_state,
5078	serge	1376	.mmio_hdp_flush = r600_mmio_hdp_flush,
2997	Serge	1377	.gui_idle = &r600_gui_idle,
		1378	.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
3764	Serge	1379	.get_xclk = &r600_get_xclk,
		1380	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,
2997	Serge	1381	.gart = {
		1382	.tlb_flush = &evergreen_pcie_gart_tlb_flush,
		1383	.set_page = &rs600_gart_set_page,
		1384	},
		1385	.ring = {
5078	serge	1386	[RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,
		1387	[R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring,
		1388	[R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
2997	Serge	1389	},
		1390	.irq = {
		1391	.set = &evergreen_irq_set,
		1392	.process = &evergreen_irq_process,
		1393	},
		1394	.display = {
		1395	.bandwidth_update = &evergreen_bandwidth_update,
		1396	.get_vblank_counter = &evergreen_get_vblank_counter,
		1397	.wait_for_vblank = &dce4_wait_for_vblank,
5078	serge	1398	.set_backlight_level = &atombios_set_backlight_level,
		1399	.get_backlight_level = &atombios_get_backlight_level,
		1400	.hdmi_enable = &evergreen_hdmi_enable,
		1401	.hdmi_setmode = &evergreen_hdmi_setmode,
2997	Serge	1402	},
		1403	.copy = {
5078	serge	1404	.blit = &r600_copy_cpdma,
2997	Serge	1405	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
3192	Serge	1406	.dma = &evergreen_copy_dma,
		1407	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
		1408	.copy = &evergreen_copy_dma,
		1409	.copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2997	Serge	1410	},
		1411	.surface = {
		1412	.set_reg = r600_set_surface_reg,
		1413	.clear_reg = r600_clear_surface_reg,
		1414	},
		1415	.hpd = {
5078	serge	1416	.init = &evergreen_hpd_init,
		1417	.fini = &evergreen_hpd_fini,
		1418	.sense = &evergreen_hpd_sense,
		1419	.set_polarity = &evergreen_hpd_set_polarity,
2997	Serge	1420	},
		1421	.pm = {
5078	serge	1422	.misc = &evergreen_pm_misc,
		1423	.prepare = &evergreen_pm_prepare,
		1424	.finish = &evergreen_pm_finish,
		1425	.init_profile = &sumo_pm_init_profile,
		1426	.get_dynpm_state = &r600_pm_get_dynpm_state,
		1427	.get_engine_clock = &radeon_atom_get_engine_clock,
		1428	.set_engine_clock = &radeon_atom_set_engine_clock,
3120	serge	1429	.get_memory_clock = NULL,
		1430	.set_memory_clock = NULL,
		1431	.get_pcie_lanes = NULL,
		1432	.set_pcie_lanes = NULL,
		1433	.set_clock_gating = NULL,
3764	Serge	1434	.set_uvd_clocks = &sumo_set_uvd_clocks,
5078	serge	1435	.get_temperature = &sumo_get_temp,
2997	Serge	1436	},
5078	serge	1437	.dpm = {
		1438	.init = &sumo_dpm_init,
		1439	.setup_asic = &sumo_dpm_setup_asic,
		1440	.enable = &sumo_dpm_enable,
		1441	.late_enable = &sumo_dpm_late_enable,
		1442	.disable = &sumo_dpm_disable,
		1443	.pre_set_power_state = &sumo_dpm_pre_set_power_state,
		1444	.set_power_state = &sumo_dpm_set_power_state,
		1445	.post_set_power_state = &sumo_dpm_post_set_power_state,
		1446	.display_configuration_changed = &sumo_dpm_display_configuration_changed,
		1447	.fini = &sumo_dpm_fini,
		1448	.get_sclk = &sumo_dpm_get_sclk,
		1449	.get_mclk = &sumo_dpm_get_mclk,
		1450	.print_power_state = &sumo_dpm_print_power_state,
		1451	.debugfs_print_current_performance_level = &sumo_dpm_debugfs_print_current_performance_level,
		1452	.force_performance_level = &sumo_dpm_force_performance_level,
		1453	},
2997	Serge	1454	.pflip = {
		1455	// .pre_page_flip = &evergreen_pre_page_flip,
		1456	// .page_flip = &evergreen_page_flip,
		1457	},
1986	serge	1458	};
		1459
		1460	static struct radeon_asic btc_asic = {
		1461	.init = &evergreen_init,
1990	serge	1462	// .fini = &evergreen_fini,
		1463	// .suspend = &evergreen_suspend,
		1464	// .resume = &evergreen_resume,
1986	serge	1465	.asic_reset = &evergreen_asic_reset,
2997	Serge	1466	// .vga_set_state = &r600_vga_set_state,
5078	serge	1467	.mmio_hdp_flush = r600_mmio_hdp_flush,
2997	Serge	1468	.gui_idle = &r600_gui_idle,
		1469	.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
3764	Serge	1470	.get_xclk = &rv770_get_xclk,
		1471	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,
2997	Serge	1472	.gart = {
		1473	.tlb_flush = &evergreen_pcie_gart_tlb_flush,
		1474	.set_page = &rs600_gart_set_page,
		1475	},
		1476	.ring = {
5078	serge	1477	[RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,
		1478	[R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring,
		1479	[R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
2997	Serge	1480	},
		1481	.irq = {
		1482	.set = &evergreen_irq_set,
		1483	.process = &evergreen_irq_process,
		1484	},
		1485	.display = {
		1486	.bandwidth_update = &evergreen_bandwidth_update,
		1487	.get_vblank_counter = &evergreen_get_vblank_counter,
		1488	.wait_for_vblank = &dce4_wait_for_vblank,
5078	serge	1489	.set_backlight_level = &atombios_set_backlight_level,
		1490	.get_backlight_level = &atombios_get_backlight_level,
		1491	.hdmi_enable = &evergreen_hdmi_enable,
		1492	.hdmi_setmode = &evergreen_hdmi_setmode,
2997	Serge	1493	},
		1494	.copy = {
5078	serge	1495	.blit = &r600_copy_cpdma,
2997	Serge	1496	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
3192	Serge	1497	.dma = &evergreen_copy_dma,
		1498	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
		1499	.copy = &evergreen_copy_dma,
		1500	.copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2997	Serge	1501	},
		1502	.surface = {
		1503	.set_reg = r600_set_surface_reg,
		1504	.clear_reg = r600_clear_surface_reg,
		1505	},
		1506	.hpd = {
5078	serge	1507	.init = &evergreen_hpd_init,
		1508	.fini = &evergreen_hpd_fini,
		1509	.sense = &evergreen_hpd_sense,
		1510	.set_polarity = &evergreen_hpd_set_polarity,
2997	Serge	1511	},
		1512	.pm = {
5078	serge	1513	.misc = &evergreen_pm_misc,
		1514	.prepare = &evergreen_pm_prepare,
		1515	.finish = &evergreen_pm_finish,
		1516	.init_profile = &btc_pm_init_profile,
		1517	.get_dynpm_state = &r600_pm_get_dynpm_state,
		1518	.get_engine_clock = &radeon_atom_get_engine_clock,
		1519	.set_engine_clock = &radeon_atom_set_engine_clock,
		1520	.get_memory_clock = &radeon_atom_get_memory_clock,
		1521	.set_memory_clock = &radeon_atom_set_memory_clock,
		1522	.get_pcie_lanes = &r600_get_pcie_lanes,
		1523	.set_pcie_lanes = &r600_set_pcie_lanes,
3120	serge	1524	.set_clock_gating = NULL,
3764	Serge	1525	.set_uvd_clocks = &evergreen_set_uvd_clocks,
5078	serge	1526	.get_temperature = &evergreen_get_temp,
2997	Serge	1527	},
5078	serge	1528	.dpm = {
		1529	.init = &btc_dpm_init,
		1530	.setup_asic = &btc_dpm_setup_asic,
		1531	.enable = &btc_dpm_enable,
		1532	.late_enable = &rv770_dpm_late_enable,
		1533	.disable = &btc_dpm_disable,
		1534	.pre_set_power_state = &btc_dpm_pre_set_power_state,
		1535	.set_power_state = &btc_dpm_set_power_state,
		1536	.post_set_power_state = &btc_dpm_post_set_power_state,
		1537	.display_configuration_changed = &cypress_dpm_display_configuration_changed,
		1538	.fini = &btc_dpm_fini,
		1539	.get_sclk = &btc_dpm_get_sclk,
		1540	.get_mclk = &btc_dpm_get_mclk,
		1541	.print_power_state = &rv770_dpm_print_power_state,
		1542	.debugfs_print_current_performance_level = &btc_dpm_debugfs_print_current_performance_level,
		1543	.force_performance_level = &rv770_dpm_force_performance_level,
		1544	.vblank_too_short = &btc_dpm_vblank_too_short,
		1545	},
2997	Serge	1546	.pflip = {
		1547	// .pre_page_flip = &evergreen_pre_page_flip,
		1548	// .page_flip = &evergreen_page_flip,
		1549	},
1986	serge	1550	};
		1551
5078	serge	1552	static struct radeon_asic_ring cayman_gfx_ring = {
		1553	.ib_execute = &cayman_ring_ib_execute,
		1554	.ib_parse = &evergreen_ib_parse,
		1555	.emit_fence = &cayman_fence_ring_emit,
		1556	.emit_semaphore = &r600_semaphore_ring_emit,
		1557	.cs_parse = &evergreen_cs_parse,
		1558	.ring_test = &r600_ring_test,
		1559	.ib_test = &r600_ib_test,
		1560	.is_lockup = &cayman_gfx_is_lockup,
		1561	.vm_flush = &cayman_vm_flush,
		1562	.get_rptr = &cayman_gfx_get_rptr,
		1563	.get_wptr = &cayman_gfx_get_wptr,
		1564	.set_wptr = &cayman_gfx_set_wptr,
		1565	};
		1566
		1567	static struct radeon_asic_ring cayman_dma_ring = {
		1568	.ib_execute = &cayman_dma_ring_ib_execute,
		1569	.ib_parse = &evergreen_dma_ib_parse,
		1570	.emit_fence = &evergreen_dma_fence_ring_emit,
		1571	.emit_semaphore = &r600_dma_semaphore_ring_emit,
		1572	.cs_parse = &evergreen_dma_cs_parse,
		1573	.ring_test = &r600_dma_ring_test,
		1574	.ib_test = &r600_dma_ib_test,
		1575	.is_lockup = &cayman_dma_is_lockup,
		1576	.vm_flush = &cayman_dma_vm_flush,
		1577	.get_rptr = &cayman_dma_get_rptr,
		1578	.get_wptr = &cayman_dma_get_wptr,
		1579	.set_wptr = &cayman_dma_set_wptr
		1580	};
		1581
		1582	static struct radeon_asic_ring cayman_uvd_ring = {
		1583	.ib_execute = &uvd_v1_0_ib_execute,
		1584	.emit_fence = &uvd_v2_2_fence_emit,
		1585	.emit_semaphore = &uvd_v3_1_semaphore_emit,
		1586	.cs_parse = &radeon_uvd_cs_parse,
		1587	.ring_test = &uvd_v1_0_ring_test,
		1588	.ib_test = &uvd_v1_0_ib_test,
		1589	.is_lockup = &radeon_ring_test_lockup,
		1590	.get_rptr = &uvd_v1_0_get_rptr,
		1591	.get_wptr = &uvd_v1_0_get_wptr,
		1592	.set_wptr = &uvd_v1_0_set_wptr,
		1593	};
		1594
1986	serge	1595	static struct radeon_asic cayman_asic = {
		1596	.init = &cayman_init,
2997	Serge	1597	// .fini = &cayman_fini,
		1598	// .suspend = &cayman_suspend,
		1599	// .resume = &cayman_resume,
1986	serge	1600	.asic_reset = &cayman_asic_reset,
2997	Serge	1601	// .vga_set_state = &r600_vga_set_state,
5078	serge	1602	.mmio_hdp_flush = r600_mmio_hdp_flush,
2997	Serge	1603	.gui_idle = &r600_gui_idle,
		1604	.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
3764	Serge	1605	.get_xclk = &rv770_get_xclk,
		1606	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,
2997	Serge	1607	.gart = {
		1608	.tlb_flush = &cayman_pcie_gart_tlb_flush,
		1609	.set_page = &rs600_gart_set_page,
		1610	},
		1611	.vm = {
		1612	.init = &cayman_vm_init,
		1613	.fini = &cayman_vm_fini,
5078	serge	1614	.copy_pages = &cayman_dma_vm_copy_pages,
		1615	.write_pages = &cayman_dma_vm_write_pages,
		1616	.set_pages = &cayman_dma_vm_set_pages,
		1617	.pad_ib = &cayman_dma_vm_pad_ib,
2997	Serge	1618	},
		1619	.ring = {
5078	serge	1620	[RADEON_RING_TYPE_GFX_INDEX] = &cayman_gfx_ring,
		1621	[CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring,
		1622	[CAYMAN_RING_TYPE_CP2_INDEX] = &cayman_gfx_ring,
		1623	[R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring,
		1624	[CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring,
		1625	[R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
2997	Serge	1626	},
		1627	.irq = {
		1628	.set = &evergreen_irq_set,
		1629	.process = &evergreen_irq_process,
		1630	},
		1631	.display = {
		1632	.bandwidth_update = &evergreen_bandwidth_update,
		1633	.get_vblank_counter = &evergreen_get_vblank_counter,
		1634	.wait_for_vblank = &dce4_wait_for_vblank,
5078	serge	1635	.set_backlight_level = &atombios_set_backlight_level,
		1636	.get_backlight_level = &atombios_get_backlight_level,
		1637	.hdmi_enable = &evergreen_hdmi_enable,
		1638	.hdmi_setmode = &evergreen_hdmi_setmode,
2997	Serge	1639	},
		1640	.copy = {
5078	serge	1641	.blit = &r600_copy_cpdma,
2997	Serge	1642	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
3192	Serge	1643	.dma = &evergreen_copy_dma,
		1644	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
		1645	.copy = &evergreen_copy_dma,
		1646	.copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2997	Serge	1647	},
		1648	.surface = {
		1649	.set_reg = r600_set_surface_reg,
		1650	.clear_reg = r600_clear_surface_reg,
		1651	},
		1652	.hpd = {
5078	serge	1653	.init = &evergreen_hpd_init,
		1654	.fini = &evergreen_hpd_fini,
		1655	.sense = &evergreen_hpd_sense,
		1656	.set_polarity = &evergreen_hpd_set_polarity,
2997	Serge	1657	},
		1658	.pm = {
5078	serge	1659	.misc = &evergreen_pm_misc,
		1660	.prepare = &evergreen_pm_prepare,
		1661	.finish = &evergreen_pm_finish,
		1662	.init_profile = &btc_pm_init_profile,
		1663	.get_dynpm_state = &r600_pm_get_dynpm_state,
		1664	.get_engine_clock = &radeon_atom_get_engine_clock,
		1665	.set_engine_clock = &radeon_atom_set_engine_clock,
		1666	.get_memory_clock = &radeon_atom_get_memory_clock,
		1667	.set_memory_clock = &radeon_atom_set_memory_clock,
		1668	.get_pcie_lanes = &r600_get_pcie_lanes,
		1669	.set_pcie_lanes = &r600_set_pcie_lanes,
3120	serge	1670	.set_clock_gating = NULL,
3764	Serge	1671	.set_uvd_clocks = &evergreen_set_uvd_clocks,
5078	serge	1672	.get_temperature = &evergreen_get_temp,
2997	Serge	1673	},
5078	serge	1674	.dpm = {
		1675	.init = &ni_dpm_init,
		1676	.setup_asic = &ni_dpm_setup_asic,
		1677	.enable = &ni_dpm_enable,
		1678	.late_enable = &rv770_dpm_late_enable,
		1679	.disable = &ni_dpm_disable,
		1680	.pre_set_power_state = &ni_dpm_pre_set_power_state,
		1681	.set_power_state = &ni_dpm_set_power_state,
		1682	.post_set_power_state = &ni_dpm_post_set_power_state,
		1683	.display_configuration_changed = &cypress_dpm_display_configuration_changed,
		1684	.fini = &ni_dpm_fini,
		1685	.get_sclk = &ni_dpm_get_sclk,
		1686	.get_mclk = &ni_dpm_get_mclk,
		1687	.print_power_state = &ni_dpm_print_power_state,
		1688	.debugfs_print_current_performance_level = &ni_dpm_debugfs_print_current_performance_level,
		1689	.force_performance_level = &ni_dpm_force_performance_level,
		1690	.vblank_too_short = &ni_dpm_vblank_too_short,
		1691	},
2997	Serge	1692	.pflip = {
		1693	// .pre_page_flip = &evergreen_pre_page_flip,
		1694	// .page_flip = &evergreen_page_flip,
		1695	},
1963	serge	1696	};
		1697
2997	Serge	1698	static struct radeon_asic trinity_asic = {
		1699	.init = &cayman_init,
		1700	// .fini = &cayman_fini,
		1701	// .suspend = &cayman_suspend,
		1702	// .resume = &cayman_resume,
		1703	.asic_reset = &cayman_asic_reset,
		1704	// .vga_set_state = &r600_vga_set_state,
5078	serge	1705	.mmio_hdp_flush = r600_mmio_hdp_flush,
2997	Serge	1706	.gui_idle = &r600_gui_idle,
		1707	.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
3764	Serge	1708	.get_xclk = &r600_get_xclk,
		1709	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,
2997	Serge	1710	.gart = {
		1711	.tlb_flush = &cayman_pcie_gart_tlb_flush,
		1712	.set_page = &rs600_gart_set_page,
		1713	},
		1714	.vm = {
		1715	.init = &cayman_vm_init,
		1716	.fini = &cayman_vm_fini,
5078	serge	1717	.copy_pages = &cayman_dma_vm_copy_pages,
		1718	.write_pages = &cayman_dma_vm_write_pages,
		1719	.set_pages = &cayman_dma_vm_set_pages,
		1720	.pad_ib = &cayman_dma_vm_pad_ib,
2997	Serge	1721	},
		1722	.ring = {
5078	serge	1723	[RADEON_RING_TYPE_GFX_INDEX] = &cayman_gfx_ring,
		1724	[CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring,
		1725	[CAYMAN_RING_TYPE_CP2_INDEX] = &cayman_gfx_ring,
		1726	[R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring,
		1727	[CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring,
		1728	[R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
2997	Serge	1729	},
		1730	.irq = {
		1731	.set = &evergreen_irq_set,
		1732	.process = &evergreen_irq_process,
		1733	},
		1734	.display = {
		1735	.bandwidth_update = &dce6_bandwidth_update,
		1736	.get_vblank_counter = &evergreen_get_vblank_counter,
		1737	.wait_for_vblank = &dce4_wait_for_vblank,
5078	serge	1738	.set_backlight_level = &atombios_set_backlight_level,
		1739	.get_backlight_level = &atombios_get_backlight_level,
		1740	.hdmi_enable = &evergreen_hdmi_enable,
		1741	.hdmi_setmode = &evergreen_hdmi_setmode,
2997	Serge	1742	},
		1743	.copy = {
5078	serge	1744	.blit = &r600_copy_cpdma,
2997	Serge	1745	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
3192	Serge	1746	.dma = &evergreen_copy_dma,
		1747	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
		1748	.copy = &evergreen_copy_dma,
		1749	.copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2997	Serge	1750	},
		1751	.surface = {
		1752	.set_reg = r600_set_surface_reg,
		1753	.clear_reg = r600_clear_surface_reg,
		1754	},
		1755	.hpd = {
5078	serge	1756	.init = &evergreen_hpd_init,
		1757	.fini = &evergreen_hpd_fini,
		1758	.sense = &evergreen_hpd_sense,
		1759	.set_polarity = &evergreen_hpd_set_polarity,
2997	Serge	1760	},
		1761	.pm = {
5078	serge	1762	.misc = &evergreen_pm_misc,
		1763	.prepare = &evergreen_pm_prepare,
		1764	.finish = &evergreen_pm_finish,
		1765	.init_profile = &sumo_pm_init_profile,
		1766	.get_dynpm_state = &r600_pm_get_dynpm_state,
		1767	.get_engine_clock = &radeon_atom_get_engine_clock,
		1768	.set_engine_clock = &radeon_atom_set_engine_clock,
3120	serge	1769	.get_memory_clock = NULL,
		1770	.set_memory_clock = NULL,
		1771	.get_pcie_lanes = NULL,
		1772	.set_pcie_lanes = NULL,
		1773	.set_clock_gating = NULL,
3764	Serge	1774	.set_uvd_clocks = &sumo_set_uvd_clocks,
5078	serge	1775	.get_temperature = &tn_get_temp,
2997	Serge	1776	},
5078	serge	1777	.dpm = {
		1778	.init = &trinity_dpm_init,
		1779	.setup_asic = &trinity_dpm_setup_asic,
		1780	.enable = &trinity_dpm_enable,
		1781	.late_enable = &trinity_dpm_late_enable,
		1782	.disable = &trinity_dpm_disable,
		1783	.pre_set_power_state = &trinity_dpm_pre_set_power_state,
		1784	.set_power_state = &trinity_dpm_set_power_state,
		1785	.post_set_power_state = &trinity_dpm_post_set_power_state,
		1786	.display_configuration_changed = &trinity_dpm_display_configuration_changed,
		1787	.fini = &trinity_dpm_fini,
		1788	.get_sclk = &trinity_dpm_get_sclk,
		1789	.get_mclk = &trinity_dpm_get_mclk,
		1790	.print_power_state = &trinity_dpm_print_power_state,
		1791	.debugfs_print_current_performance_level = &trinity_dpm_debugfs_print_current_performance_level,
		1792	.force_performance_level = &trinity_dpm_force_performance_level,
		1793	.enable_bapm = &trinity_dpm_enable_bapm,
		1794	},
2997	Serge	1795	.pflip = {
		1796	// .pre_page_flip = &evergreen_pre_page_flip,
		1797	// .page_flip = &evergreen_page_flip,
		1798	},
		1799	};
		1800
5078	serge	1801	static struct radeon_asic_ring si_gfx_ring = {
		1802	.ib_execute = &si_ring_ib_execute,
		1803	.ib_parse = &si_ib_parse,
		1804	.emit_fence = &si_fence_ring_emit,
		1805	.emit_semaphore = &r600_semaphore_ring_emit,
		1806	.cs_parse = NULL,
		1807	.ring_test = &r600_ring_test,
		1808	.ib_test = &r600_ib_test,
		1809	.is_lockup = &si_gfx_is_lockup,
		1810	.vm_flush = &si_vm_flush,
		1811	.get_rptr = &cayman_gfx_get_rptr,
		1812	.get_wptr = &cayman_gfx_get_wptr,
		1813	.set_wptr = &cayman_gfx_set_wptr,
		1814	};
		1815
		1816	static struct radeon_asic_ring si_dma_ring = {
		1817	.ib_execute = &cayman_dma_ring_ib_execute,
		1818	.ib_parse = &evergreen_dma_ib_parse,
		1819	.emit_fence = &evergreen_dma_fence_ring_emit,
		1820	.emit_semaphore = &r600_dma_semaphore_ring_emit,
		1821	.cs_parse = NULL,
		1822	.ring_test = &r600_dma_ring_test,
		1823	.ib_test = &r600_dma_ib_test,
		1824	.is_lockup = &si_dma_is_lockup,
		1825	.vm_flush = &si_dma_vm_flush,
		1826	.get_rptr = &cayman_dma_get_rptr,
		1827	.get_wptr = &cayman_dma_get_wptr,
		1828	.set_wptr = &cayman_dma_set_wptr,
		1829	};
		1830
2997	Serge	1831	static struct radeon_asic si_asic = {
		1832	.init = &si_init,
		1833	// .fini = &si_fini,
		1834	// .suspend = &si_suspend,
		1835	// .resume = &si_resume,
		1836	.asic_reset = &si_asic_reset,
		1837	// .vga_set_state = &r600_vga_set_state,
5078	serge	1838	.mmio_hdp_flush = r600_mmio_hdp_flush,
2997	Serge	1839	.gui_idle = &r600_gui_idle,
		1840	.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
3764	Serge	1841	.get_xclk = &si_get_xclk,
		1842	.get_gpu_clock_counter = &si_get_gpu_clock_counter,
2997	Serge	1843	.gart = {
		1844	.tlb_flush = &si_pcie_gart_tlb_flush,
		1845	.set_page = &rs600_gart_set_page,
		1846	},
		1847	.vm = {
		1848	.init = &si_vm_init,
		1849	.fini = &si_vm_fini,
5078	serge	1850	.copy_pages = &si_dma_vm_copy_pages,
		1851	.write_pages = &si_dma_vm_write_pages,
		1852	.set_pages = &si_dma_vm_set_pages,
		1853	.pad_ib = &cayman_dma_vm_pad_ib,
2997	Serge	1854	},
		1855	.ring = {
5078	serge	1856	[RADEON_RING_TYPE_GFX_INDEX] = &si_gfx_ring,
		1857	[CAYMAN_RING_TYPE_CP1_INDEX] = &si_gfx_ring,
		1858	[CAYMAN_RING_TYPE_CP2_INDEX] = &si_gfx_ring,
		1859	[R600_RING_TYPE_DMA_INDEX] = &si_dma_ring,
		1860	[CAYMAN_RING_TYPE_DMA1_INDEX] = &si_dma_ring,
		1861	[R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
2997	Serge	1862	},
		1863	.irq = {
		1864	.set = &si_irq_set,
		1865	.process = &si_irq_process,
		1866	},
		1867	.display = {
		1868	.bandwidth_update = &dce6_bandwidth_update,
		1869	.get_vblank_counter = &evergreen_get_vblank_counter,
		1870	.wait_for_vblank = &dce4_wait_for_vblank,
5078	serge	1871	.set_backlight_level = &atombios_set_backlight_level,
		1872	.get_backlight_level = &atombios_get_backlight_level,
		1873	.hdmi_enable = &evergreen_hdmi_enable,
		1874	.hdmi_setmode = &evergreen_hdmi_setmode,
2997	Serge	1875	},
		1876	.copy = {
5078	serge	1877	.blit = &r600_copy_cpdma,
2997	Serge	1878	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
3192	Serge	1879	.dma = &si_copy_dma,
		1880	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
		1881	.copy = &si_copy_dma,
		1882	.copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2997	Serge	1883	},
		1884	.surface = {
		1885	.set_reg = r600_set_surface_reg,
		1886	.clear_reg = r600_clear_surface_reg,
		1887	},
		1888	.hpd = {
		1889	.init = &evergreen_hpd_init,
		1890	.fini = &evergreen_hpd_fini,
		1891	.sense = &evergreen_hpd_sense,
		1892	.set_polarity = &evergreen_hpd_set_polarity,
		1893	},
		1894	.pm = {
5078	serge	1895	.misc = &evergreen_pm_misc,
		1896	.prepare = &evergreen_pm_prepare,
		1897	.finish = &evergreen_pm_finish,
		1898	.init_profile = &sumo_pm_init_profile,
		1899	.get_dynpm_state = &r600_pm_get_dynpm_state,
		1900	.get_engine_clock = &radeon_atom_get_engine_clock,
		1901	.set_engine_clock = &radeon_atom_set_engine_clock,
		1902	.get_memory_clock = &radeon_atom_get_memory_clock,
		1903	.set_memory_clock = &radeon_atom_set_memory_clock,
		1904	.get_pcie_lanes = &r600_get_pcie_lanes,
		1905	.set_pcie_lanes = &r600_set_pcie_lanes,
		1906	.set_clock_gating = NULL,
		1907	.set_uvd_clocks = &si_set_uvd_clocks,
		1908	.get_temperature = &si_get_temp,
		1909	},
		1910	.dpm = {
		1911	.init = &si_dpm_init,
		1912	.setup_asic = &si_dpm_setup_asic,
		1913	.enable = &si_dpm_enable,
		1914	.late_enable = &si_dpm_late_enable,
		1915	.disable = &si_dpm_disable,
		1916	.pre_set_power_state = &si_dpm_pre_set_power_state,
		1917	.set_power_state = &si_dpm_set_power_state,
		1918	.post_set_power_state = &si_dpm_post_set_power_state,
		1919	.display_configuration_changed = &si_dpm_display_configuration_changed,
		1920	.fini = &si_dpm_fini,
		1921	.get_sclk = &ni_dpm_get_sclk,
		1922	.get_mclk = &ni_dpm_get_mclk,
		1923	.print_power_state = &ni_dpm_print_power_state,
		1924	.debugfs_print_current_performance_level = &si_dpm_debugfs_print_current_performance_level,
		1925	.force_performance_level = &si_dpm_force_performance_level,
		1926	.vblank_too_short = &ni_dpm_vblank_too_short,
		1927	},
		1928	.pflip = {
		1929	// .pre_page_flip = &evergreen_pre_page_flip,
		1930	// .page_flip = &evergreen_page_flip,
		1931	},
		1932	};
		1933
		1934	static struct radeon_asic_ring ci_gfx_ring = {
		1935	.ib_execute = &cik_ring_ib_execute,
		1936	.ib_parse = &cik_ib_parse,
		1937	.emit_fence = &cik_fence_gfx_ring_emit,
		1938	.emit_semaphore = &cik_semaphore_ring_emit,
		1939	.cs_parse = NULL,
		1940	.ring_test = &cik_ring_test,
		1941	.ib_test = &cik_ib_test,
		1942	.is_lockup = &cik_gfx_is_lockup,
		1943	.vm_flush = &cik_vm_flush,
		1944	.get_rptr = &cik_gfx_get_rptr,
		1945	.get_wptr = &cik_gfx_get_wptr,
		1946	.set_wptr = &cik_gfx_set_wptr,
		1947	};
		1948
		1949	static struct radeon_asic_ring ci_cp_ring = {
		1950	.ib_execute = &cik_ring_ib_execute,
		1951	.ib_parse = &cik_ib_parse,
		1952	.emit_fence = &cik_fence_compute_ring_emit,
		1953	.emit_semaphore = &cik_semaphore_ring_emit,
		1954	.cs_parse = NULL,
		1955	.ring_test = &cik_ring_test,
		1956	.ib_test = &cik_ib_test,
		1957	.is_lockup = &cik_gfx_is_lockup,
		1958	.vm_flush = &cik_vm_flush,
		1959	.get_rptr = &cik_compute_get_rptr,
		1960	.get_wptr = &cik_compute_get_wptr,
		1961	.set_wptr = &cik_compute_set_wptr,
		1962	};
		1963
		1964	static struct radeon_asic_ring ci_dma_ring = {
		1965	.ib_execute = &cik_sdma_ring_ib_execute,
		1966	.ib_parse = &cik_ib_parse,
		1967	.emit_fence = &cik_sdma_fence_ring_emit,
		1968	.emit_semaphore = &cik_sdma_semaphore_ring_emit,
		1969	.cs_parse = NULL,
		1970	.ring_test = &cik_sdma_ring_test,
		1971	.ib_test = &cik_sdma_ib_test,
		1972	.is_lockup = &cik_sdma_is_lockup,
		1973	.vm_flush = &cik_dma_vm_flush,
		1974	.get_rptr = &cik_sdma_get_rptr,
		1975	.get_wptr = &cik_sdma_get_wptr,
		1976	.set_wptr = &cik_sdma_set_wptr,
		1977	};
		1978
		1979	static struct radeon_asic_ring ci_vce_ring = {
		1980	.ib_execute = &radeon_vce_ib_execute,
		1981	.emit_fence = &radeon_vce_fence_emit,
		1982	.emit_semaphore = &radeon_vce_semaphore_emit,
		1983	.cs_parse = &radeon_vce_cs_parse,
		1984	.ring_test = &radeon_vce_ring_test,
		1985	.ib_test = &radeon_vce_ib_test,
		1986	.is_lockup = &radeon_ring_test_lockup,
		1987	.get_rptr = &vce_v1_0_get_rptr,
		1988	.get_wptr = &vce_v1_0_get_wptr,
		1989	.set_wptr = &vce_v1_0_set_wptr,
		1990	};
		1991
		1992	static struct radeon_asic ci_asic = {
		1993	.init = &cik_init,
		1994	// .fini = &si_fini,
		1995	// .suspend = &si_suspend,
		1996	// .resume = &si_resume,
		1997	.asic_reset = &cik_asic_reset,
		1998	// .vga_set_state = &r600_vga_set_state,
		1999	.mmio_hdp_flush = &r600_mmio_hdp_flush,
		2000	.gui_idle = &r600_gui_idle,
		2001	.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
		2002	.get_xclk = &cik_get_xclk,
		2003	.get_gpu_clock_counter = &cik_get_gpu_clock_counter,
		2004	.gart = {
		2005	.tlb_flush = &cik_pcie_gart_tlb_flush,
		2006	.set_page = &rs600_gart_set_page,
		2007	},
		2008	.vm = {
		2009	.init = &cik_vm_init,
		2010	.fini = &cik_vm_fini,
		2011	.copy_pages = &cik_sdma_vm_copy_pages,
		2012	.write_pages = &cik_sdma_vm_write_pages,
		2013	.set_pages = &cik_sdma_vm_set_pages,
		2014	.pad_ib = &cik_sdma_vm_pad_ib,
		2015	},
		2016	.ring = {
		2017	[RADEON_RING_TYPE_GFX_INDEX] = &ci_gfx_ring,
		2018	[CAYMAN_RING_TYPE_CP1_INDEX] = &ci_cp_ring,
		2019	[CAYMAN_RING_TYPE_CP2_INDEX] = &ci_cp_ring,
		2020	[R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring,
		2021	[CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring,
		2022	[R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
		2023	[TN_RING_TYPE_VCE1_INDEX] = &ci_vce_ring,
		2024	[TN_RING_TYPE_VCE2_INDEX] = &ci_vce_ring,
		2025	},
		2026	.irq = {
		2027	.set = &cik_irq_set,
		2028	.process = &cik_irq_process,
		2029	},
		2030	.display = {
		2031	.bandwidth_update = &dce8_bandwidth_update,
		2032	.get_vblank_counter = &evergreen_get_vblank_counter,
		2033	.wait_for_vblank = &dce4_wait_for_vblank,
		2034	.set_backlight_level = &atombios_set_backlight_level,
		2035	.get_backlight_level = &atombios_get_backlight_level,
		2036	.hdmi_enable = &evergreen_hdmi_enable,
		2037	.hdmi_setmode = &evergreen_hdmi_setmode,
		2038	},
		2039	.copy = {
		2040	.blit = &cik_copy_cpdma,
		2041	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		2042	.dma = &cik_copy_dma,
		2043	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
		2044	.copy = &cik_copy_dma,
		2045	.copy_ring_index = R600_RING_TYPE_DMA_INDEX,
		2046	},
		2047	.surface = {
		2048	.set_reg = r600_set_surface_reg,
		2049	.clear_reg = r600_clear_surface_reg,
		2050	},
		2051	.hpd = {
		2052	.init = &evergreen_hpd_init,
		2053	.fini = &evergreen_hpd_fini,
		2054	.sense = &evergreen_hpd_sense,
		2055	.set_polarity = &evergreen_hpd_set_polarity,
		2056	},
		2057	.pm = {
		2058	.misc = &evergreen_pm_misc,
		2059	.prepare = &evergreen_pm_prepare,
		2060	.finish = &evergreen_pm_finish,
		2061	.init_profile = &sumo_pm_init_profile,
		2062	.get_dynpm_state = &r600_pm_get_dynpm_state,
		2063	.get_engine_clock = &radeon_atom_get_engine_clock,
		2064	.set_engine_clock = &radeon_atom_set_engine_clock,
		2065	.get_memory_clock = &radeon_atom_get_memory_clock,
		2066	.set_memory_clock = &radeon_atom_set_memory_clock,
3120	serge	2067	.get_pcie_lanes = NULL,
		2068	.set_pcie_lanes = NULL,
		2069	.set_clock_gating = NULL,
5078	serge	2070	.set_uvd_clocks = &cik_set_uvd_clocks,
		2071	.set_vce_clocks = &cik_set_vce_clocks,
		2072	.get_temperature = &ci_get_temp,
2997	Serge	2073	},
5078	serge	2074	.dpm = {
		2075	.init = &ci_dpm_init,
		2076	.setup_asic = &ci_dpm_setup_asic,
		2077	.enable = &ci_dpm_enable,
		2078	.late_enable = &ci_dpm_late_enable,
		2079	.disable = &ci_dpm_disable,
		2080	.pre_set_power_state = &ci_dpm_pre_set_power_state,
		2081	.set_power_state = &ci_dpm_set_power_state,
		2082	.post_set_power_state = &ci_dpm_post_set_power_state,
		2083	.display_configuration_changed = &ci_dpm_display_configuration_changed,
		2084	.fini = &ci_dpm_fini,
		2085	.get_sclk = &ci_dpm_get_sclk,
		2086	.get_mclk = &ci_dpm_get_mclk,
		2087	.print_power_state = &ci_dpm_print_power_state,
		2088	.debugfs_print_current_performance_level = &ci_dpm_debugfs_print_current_performance_level,
		2089	.force_performance_level = &ci_dpm_force_performance_level,
		2090	.vblank_too_short = &ci_dpm_vblank_too_short,
		2091	.powergate_uvd = &ci_dpm_powergate_uvd,
		2092	},
2997	Serge	2093	.pflip = {
		2094	// .pre_page_flip = &evergreen_pre_page_flip,
		2095	// .page_flip = &evergreen_page_flip,
		2096	},
		2097	};
		2098
5078	serge	2099	static struct radeon_asic kv_asic = {
		2100	.init = &cik_init,
		2101	// .fini = &si_fini,
		2102	// .suspend = &si_suspend,
		2103	// .resume = &si_resume,
		2104	.asic_reset = &cik_asic_reset,
		2105	// .vga_set_state = &r600_vga_set_state,
		2106	.mmio_hdp_flush = &r600_mmio_hdp_flush,
		2107	.gui_idle = &r600_gui_idle,
		2108	.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
		2109	.get_xclk = &cik_get_xclk,
		2110	.get_gpu_clock_counter = &cik_get_gpu_clock_counter,
		2111	.gart = {
		2112	.tlb_flush = &cik_pcie_gart_tlb_flush,
		2113	.set_page = &rs600_gart_set_page,
		2114	},
		2115	.vm = {
		2116	.init = &cik_vm_init,
		2117	.fini = &cik_vm_fini,
		2118	.copy_pages = &cik_sdma_vm_copy_pages,
		2119	.write_pages = &cik_sdma_vm_write_pages,
		2120	.set_pages = &cik_sdma_vm_set_pages,
		2121	.pad_ib = &cik_sdma_vm_pad_ib,
		2122	},
		2123	.ring = {
		2124	[RADEON_RING_TYPE_GFX_INDEX] = &ci_gfx_ring,
		2125	[CAYMAN_RING_TYPE_CP1_INDEX] = &ci_cp_ring,
		2126	[CAYMAN_RING_TYPE_CP2_INDEX] = &ci_cp_ring,
		2127	[R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring,
		2128	[CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring,
		2129	[R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
		2130	[TN_RING_TYPE_VCE1_INDEX] = &ci_vce_ring,
		2131	[TN_RING_TYPE_VCE2_INDEX] = &ci_vce_ring,
		2132	},
		2133	.irq = {
		2134	.set = &cik_irq_set,
		2135	.process = &cik_irq_process,
		2136	},
		2137	.display = {
		2138	.bandwidth_update = &dce8_bandwidth_update,
		2139	.get_vblank_counter = &evergreen_get_vblank_counter,
		2140	.wait_for_vblank = &dce4_wait_for_vblank,
		2141	.set_backlight_level = &atombios_set_backlight_level,
		2142	.get_backlight_level = &atombios_get_backlight_level,
		2143	.hdmi_enable = &evergreen_hdmi_enable,
		2144	.hdmi_setmode = &evergreen_hdmi_setmode,
		2145	},
		2146	.copy = {
		2147	.blit = &cik_copy_cpdma,
		2148	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		2149	.dma = &cik_copy_dma,
		2150	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
		2151	.copy = &cik_copy_dma,
		2152	.copy_ring_index = R600_RING_TYPE_DMA_INDEX,
		2153	},
		2154	.surface = {
		2155	.set_reg = r600_set_surface_reg,
		2156	.clear_reg = r600_clear_surface_reg,
		2157	},
		2158	.hpd = {
		2159	.init = &evergreen_hpd_init,
		2160	.fini = &evergreen_hpd_fini,
		2161	.sense = &evergreen_hpd_sense,
		2162	.set_polarity = &evergreen_hpd_set_polarity,
		2163	},
		2164	.pm = {
		2165	.misc = &evergreen_pm_misc,
		2166	.prepare = &evergreen_pm_prepare,
		2167	.finish = &evergreen_pm_finish,
		2168	.init_profile = &sumo_pm_init_profile,
		2169	.get_dynpm_state = &r600_pm_get_dynpm_state,
		2170	.get_engine_clock = &radeon_atom_get_engine_clock,
		2171	.set_engine_clock = &radeon_atom_set_engine_clock,
		2172	.get_memory_clock = &radeon_atom_get_memory_clock,
		2173	.set_memory_clock = &radeon_atom_set_memory_clock,
		2174	.get_pcie_lanes = NULL,
		2175	.set_pcie_lanes = NULL,
		2176	.set_clock_gating = NULL,
		2177	.set_uvd_clocks = &cik_set_uvd_clocks,
		2178	.set_vce_clocks = &cik_set_vce_clocks,
		2179	.get_temperature = &kv_get_temp,
		2180	},
		2181	.dpm = {
		2182	.init = &kv_dpm_init,
		2183	.setup_asic = &kv_dpm_setup_asic,
		2184	.enable = &kv_dpm_enable,
		2185	.late_enable = &kv_dpm_late_enable,
		2186	.disable = &kv_dpm_disable,
		2187	.pre_set_power_state = &kv_dpm_pre_set_power_state,
		2188	.set_power_state = &kv_dpm_set_power_state,
		2189	.post_set_power_state = &kv_dpm_post_set_power_state,
		2190	.display_configuration_changed = &kv_dpm_display_configuration_changed,
		2191	.fini = &kv_dpm_fini,
		2192	.get_sclk = &kv_dpm_get_sclk,
		2193	.get_mclk = &kv_dpm_get_mclk,
		2194	.print_power_state = &kv_dpm_print_power_state,
		2195	.debugfs_print_current_performance_level = &kv_dpm_debugfs_print_current_performance_level,
		2196	.force_performance_level = &kv_dpm_force_performance_level,
		2197	.powergate_uvd = &kv_dpm_powergate_uvd,
		2198	.enable_bapm = &kv_dpm_enable_bapm,
		2199	},
		2200	.pflip = {
		2201	// .pre_page_flip = &evergreen_pre_page_flip,
		2202	// .page_flip = &evergreen_page_flip,
		2203	},
		2204	};
		2205
2997	Serge	2206	/**
		2207	* radeon_asic_init - register asic specific callbacks
		2208	*
		2209	* @rdev: radeon device pointer
		2210	*
		2211	* Registers the appropriate asic specific callbacks for each
		2212	* chip family. Also sets other asics specific info like the number
		2213	* of crtcs and the register aperture accessors (all asics).
		2214	* Returns 0 for success.
		2215	*/
1963	serge	2216	int radeon_asic_init(struct radeon_device *rdev)
		2217	{
		2218	radeon_register_accessor_init(rdev);
1986	serge	2219
		2220	/* set the number of crtcs */
		2221	if (rdev->flags & RADEON_SINGLE_CRTC)
		2222	rdev->num_crtc = 1;
		2223	else
		2224	rdev->num_crtc = 2;
		2225
3764	Serge	2226	rdev->has_uvd = false;
		2227
1963	serge	2228	switch (rdev->family) {
		2229	case CHIP_R100:
		2230	case CHIP_RV100:
		2231	case CHIP_RS100:
		2232	case CHIP_RV200:
		2233	case CHIP_RS200:
		2234	rdev->asic = &r100_asic;
		2235	break;
		2236	case CHIP_R200:
		2237	case CHIP_RV250:
		2238	case CHIP_RS300:
		2239	case CHIP_RV280:
		2240	rdev->asic = &r200_asic;
		2241	break;
		2242	case CHIP_R300:
		2243	case CHIP_R350:
		2244	case CHIP_RV350:
		2245	case CHIP_RV380:
		2246	if (rdev->flags & RADEON_IS_PCIE)
		2247	rdev->asic = &r300_asic_pcie;
		2248	else
		2249	rdev->asic = &r300_asic;
		2250	break;
		2251	case CHIP_R420:
		2252	case CHIP_R423:
		2253	case CHIP_RV410:
		2254	rdev->asic = &r420_asic;
		2255	/* handle macs */
		2256	if (rdev->bios == NULL) {
2997	Serge	2257	rdev->asic->pm.get_engine_clock = &radeon_legacy_get_engine_clock;
		2258	rdev->asic->pm.set_engine_clock = &radeon_legacy_set_engine_clock;
		2259	rdev->asic->pm.get_memory_clock = &radeon_legacy_get_memory_clock;
		2260	rdev->asic->pm.set_memory_clock = NULL;
		2261	rdev->asic->display.set_backlight_level = &radeon_legacy_set_backlight_level;
1963	serge	2262	}
		2263	break;
		2264	case CHIP_RS400:
		2265	case CHIP_RS480:
		2266	rdev->asic = &rs400_asic;
		2267	break;
		2268	case CHIP_RS600:
		2269	rdev->asic = &rs600_asic;
		2270	break;
		2271	case CHIP_RS690:
		2272	case CHIP_RS740:
		2273	rdev->asic = &rs690_asic;
		2274	break;
		2275	case CHIP_RV515:
		2276	rdev->asic = &rv515_asic;
		2277	break;
		2278	case CHIP_R520:
		2279	case CHIP_RV530:
		2280	case CHIP_RV560:
		2281	case CHIP_RV570:
		2282	case CHIP_R580:
		2283	rdev->asic = &r520_asic;
		2284	break;
		2285	case CHIP_R600:
5078	serge	2286	rdev->asic = &r600_asic;
		2287	break;
1963	serge	2288	case CHIP_RV610:
		2289	case CHIP_RV630:
		2290	case CHIP_RV620:
		2291	case CHIP_RV635:
		2292	case CHIP_RV670:
5078	serge	2293	rdev->asic = &rv6xx_asic;
3764	Serge	2294	rdev->has_uvd = true;
1963	serge	2295	break;
		2296	case CHIP_RS780:
		2297	case CHIP_RS880:
		2298	rdev->asic = &rs780_asic;
3764	Serge	2299	rdev->has_uvd = true;
1963	serge	2300	break;
		2301	case CHIP_RV770:
		2302	case CHIP_RV730:
		2303	case CHIP_RV710:
		2304	case CHIP_RV740:
		2305	rdev->asic = &rv770_asic;
3764	Serge	2306	rdev->has_uvd = true;
1963	serge	2307	break;
1986	serge	2308	case CHIP_CEDAR:
		2309	case CHIP_REDWOOD:
		2310	case CHIP_JUNIPER:
		2311	case CHIP_CYPRESS:
		2312	case CHIP_HEMLOCK:
		2313	/* set num crtcs */
		2314	if (rdev->family == CHIP_CEDAR)
		2315	rdev->num_crtc = 4;
		2316	else
		2317	rdev->num_crtc = 6;
		2318	rdev->asic = &evergreen_asic;
3764	Serge	2319	rdev->has_uvd = true;
1986	serge	2320	break;
1990	serge	2321	case CHIP_PALM:
		2322	case CHIP_SUMO:
		2323	case CHIP_SUMO2:
		2324	rdev->asic = &sumo_asic;
3764	Serge	2325	rdev->has_uvd = true;
1990	serge	2326	break;
		2327	case CHIP_BARTS:
		2328	case CHIP_TURKS:
		2329	case CHIP_CAICOS:
		2330	/* set num crtcs */
		2331	if (rdev->family == CHIP_CAICOS)
		2332	rdev->num_crtc = 4;
		2333	else
		2334	rdev->num_crtc = 6;
		2335	rdev->asic = &btc_asic;
3764	Serge	2336	rdev->has_uvd = true;
1990	serge	2337	break;
2004	serge	2338	case CHIP_CAYMAN:
		2339	rdev->asic = &cayman_asic;
		2340	/* set num crtcs */
		2341	rdev->num_crtc = 6;
3764	Serge	2342	rdev->has_uvd = true;
2004	serge	2343	break;
2997	Serge	2344	case CHIP_ARUBA:
		2345	rdev->asic = &trinity_asic;
		2346	/* set num crtcs */
		2347	rdev->num_crtc = 4;
3764	Serge	2348	rdev->has_uvd = true;
2997	Serge	2349	break;
		2350	case CHIP_TAHITI:
		2351	case CHIP_PITCAIRN:
		2352	case CHIP_VERDE:
3764	Serge	2353	case CHIP_OLAND:
		2354	case CHIP_HAINAN:
2997	Serge	2355	rdev->asic = &si_asic;
		2356	/* set num crtcs */
3764	Serge	2357	if (rdev->family == CHIP_HAINAN)
		2358	rdev->num_crtc = 0;
		2359	else if (rdev->family == CHIP_OLAND)
		2360	rdev->num_crtc = 2;
		2361	else
2997	Serge	2362	rdev->num_crtc = 6;
3764	Serge	2363	if (rdev->family == CHIP_HAINAN)
		2364	rdev->has_uvd = false;
		2365	else
		2366	rdev->has_uvd = true;
5078	serge	2367	switch (rdev->family) {
		2368	case CHIP_TAHITI:
		2369	rdev->cg_flags =
		2370	RADEON_CG_SUPPORT_GFX_MGCG \|
		2371	RADEON_CG_SUPPORT_GFX_MGLS \|
		2372	/RADEON_CG_SUPPORT_GFX_CGCG \|/
		2373	RADEON_CG_SUPPORT_GFX_CGLS \|
		2374	RADEON_CG_SUPPORT_GFX_CGTS \|
		2375	RADEON_CG_SUPPORT_GFX_CP_LS \|
		2376	RADEON_CG_SUPPORT_MC_MGCG \|
		2377	RADEON_CG_SUPPORT_SDMA_MGCG \|
		2378	RADEON_CG_SUPPORT_BIF_LS \|
		2379	RADEON_CG_SUPPORT_VCE_MGCG \|
		2380	RADEON_CG_SUPPORT_UVD_MGCG \|
		2381	RADEON_CG_SUPPORT_HDP_LS \|
		2382	RADEON_CG_SUPPORT_HDP_MGCG;
		2383	rdev->pg_flags = 0;
		2384	break;
		2385	case CHIP_PITCAIRN:
		2386	rdev->cg_flags =
		2387	RADEON_CG_SUPPORT_GFX_MGCG \|
		2388	RADEON_CG_SUPPORT_GFX_MGLS \|
		2389	/RADEON_CG_SUPPORT_GFX_CGCG \|/
		2390	RADEON_CG_SUPPORT_GFX_CGLS \|
		2391	RADEON_CG_SUPPORT_GFX_CGTS \|
		2392	RADEON_CG_SUPPORT_GFX_CP_LS \|
		2393	RADEON_CG_SUPPORT_GFX_RLC_LS \|
		2394	RADEON_CG_SUPPORT_MC_LS \|
		2395	RADEON_CG_SUPPORT_MC_MGCG \|
		2396	RADEON_CG_SUPPORT_SDMA_MGCG \|
		2397	RADEON_CG_SUPPORT_BIF_LS \|
		2398	RADEON_CG_SUPPORT_VCE_MGCG \|
		2399	RADEON_CG_SUPPORT_UVD_MGCG \|
		2400	RADEON_CG_SUPPORT_HDP_LS \|
		2401	RADEON_CG_SUPPORT_HDP_MGCG;
		2402	rdev->pg_flags = 0;
		2403	break;
		2404	case CHIP_VERDE:
		2405	rdev->cg_flags =
		2406	RADEON_CG_SUPPORT_GFX_MGCG \|
		2407	RADEON_CG_SUPPORT_GFX_MGLS \|
		2408	/RADEON_CG_SUPPORT_GFX_CGCG \|/
		2409	RADEON_CG_SUPPORT_GFX_CGLS \|
		2410	RADEON_CG_SUPPORT_GFX_CGTS \|
		2411	RADEON_CG_SUPPORT_GFX_CP_LS \|
		2412	RADEON_CG_SUPPORT_GFX_RLC_LS \|
		2413	RADEON_CG_SUPPORT_MC_LS \|
		2414	RADEON_CG_SUPPORT_MC_MGCG \|
		2415	RADEON_CG_SUPPORT_SDMA_MGCG \|
		2416	RADEON_CG_SUPPORT_BIF_LS \|
		2417	RADEON_CG_SUPPORT_VCE_MGCG \|
		2418	RADEON_CG_SUPPORT_UVD_MGCG \|
		2419	RADEON_CG_SUPPORT_HDP_LS \|
		2420	RADEON_CG_SUPPORT_HDP_MGCG;
		2421	rdev->pg_flags = 0 \|
		2422	/RADEON_PG_SUPPORT_GFX_PG \| /
		2423	RADEON_PG_SUPPORT_SDMA;
		2424	break;
		2425	case CHIP_OLAND:
		2426	rdev->cg_flags =
		2427	RADEON_CG_SUPPORT_GFX_MGCG \|
		2428	RADEON_CG_SUPPORT_GFX_MGLS \|
		2429	/RADEON_CG_SUPPORT_GFX_CGCG \|/
		2430	RADEON_CG_SUPPORT_GFX_CGLS \|
		2431	RADEON_CG_SUPPORT_GFX_CGTS \|
		2432	RADEON_CG_SUPPORT_GFX_CP_LS \|
		2433	RADEON_CG_SUPPORT_GFX_RLC_LS \|
		2434	RADEON_CG_SUPPORT_MC_LS \|
		2435	RADEON_CG_SUPPORT_MC_MGCG \|
		2436	RADEON_CG_SUPPORT_SDMA_MGCG \|
		2437	RADEON_CG_SUPPORT_BIF_LS \|
		2438	RADEON_CG_SUPPORT_UVD_MGCG \|
		2439	RADEON_CG_SUPPORT_HDP_LS \|
		2440	RADEON_CG_SUPPORT_HDP_MGCG;
		2441	rdev->pg_flags = 0;
		2442	break;
		2443	case CHIP_HAINAN:
		2444	rdev->cg_flags =
		2445	RADEON_CG_SUPPORT_GFX_MGCG \|
		2446	RADEON_CG_SUPPORT_GFX_MGLS \|
		2447	/RADEON_CG_SUPPORT_GFX_CGCG \|/
		2448	RADEON_CG_SUPPORT_GFX_CGLS \|
		2449	RADEON_CG_SUPPORT_GFX_CGTS \|
		2450	RADEON_CG_SUPPORT_GFX_CP_LS \|
		2451	RADEON_CG_SUPPORT_GFX_RLC_LS \|
		2452	RADEON_CG_SUPPORT_MC_LS \|
		2453	RADEON_CG_SUPPORT_MC_MGCG \|
		2454	RADEON_CG_SUPPORT_SDMA_MGCG \|
		2455	RADEON_CG_SUPPORT_BIF_LS \|
		2456	RADEON_CG_SUPPORT_HDP_LS \|
		2457	RADEON_CG_SUPPORT_HDP_MGCG;
		2458	rdev->pg_flags = 0;
		2459	break;
		2460	default:
		2461	rdev->cg_flags = 0;
		2462	rdev->pg_flags = 0;
		2463	break;
		2464	}
2997	Serge	2465	break;
5078	serge	2466	case CHIP_BONAIRE:
		2467	case CHIP_HAWAII:
		2468	rdev->asic = &ci_asic;
		2469	rdev->num_crtc = 6;
		2470	rdev->has_uvd = true;
		2471	if (rdev->family == CHIP_BONAIRE) {
		2472	rdev->cg_flags =
		2473	RADEON_CG_SUPPORT_GFX_MGCG \|
		2474	RADEON_CG_SUPPORT_GFX_MGLS \|
		2475	/RADEON_CG_SUPPORT_GFX_CGCG \|/
		2476	RADEON_CG_SUPPORT_GFX_CGLS \|
		2477	RADEON_CG_SUPPORT_GFX_CGTS \|
		2478	RADEON_CG_SUPPORT_GFX_CGTS_LS \|
		2479	RADEON_CG_SUPPORT_GFX_CP_LS \|
		2480	RADEON_CG_SUPPORT_MC_LS \|
		2481	RADEON_CG_SUPPORT_MC_MGCG \|
		2482	RADEON_CG_SUPPORT_SDMA_MGCG \|
		2483	RADEON_CG_SUPPORT_SDMA_LS \|
		2484	RADEON_CG_SUPPORT_BIF_LS \|
		2485	RADEON_CG_SUPPORT_VCE_MGCG \|
		2486	RADEON_CG_SUPPORT_UVD_MGCG \|
		2487	RADEON_CG_SUPPORT_HDP_LS \|
		2488	RADEON_CG_SUPPORT_HDP_MGCG;
		2489	rdev->pg_flags = 0;
		2490	} else {
		2491	rdev->cg_flags =
		2492	RADEON_CG_SUPPORT_GFX_MGCG \|
		2493	RADEON_CG_SUPPORT_GFX_MGLS \|
		2494	/RADEON_CG_SUPPORT_GFX_CGCG \|/
		2495	RADEON_CG_SUPPORT_GFX_CGLS \|
		2496	RADEON_CG_SUPPORT_GFX_CGTS \|
		2497	RADEON_CG_SUPPORT_GFX_CP_LS \|
		2498	RADEON_CG_SUPPORT_MC_LS \|
		2499	RADEON_CG_SUPPORT_MC_MGCG \|
		2500	RADEON_CG_SUPPORT_SDMA_MGCG \|
		2501	RADEON_CG_SUPPORT_SDMA_LS \|
		2502	RADEON_CG_SUPPORT_BIF_LS \|
		2503	RADEON_CG_SUPPORT_VCE_MGCG \|
		2504	RADEON_CG_SUPPORT_UVD_MGCG \|
		2505	RADEON_CG_SUPPORT_HDP_LS \|
		2506	RADEON_CG_SUPPORT_HDP_MGCG;
		2507	rdev->pg_flags = 0;
		2508	}
		2509	break;
		2510	case CHIP_KAVERI:
		2511	case CHIP_KABINI:
		2512	case CHIP_MULLINS:
		2513	rdev->asic = &kv_asic;
		2514	/* set num crtcs */
		2515	if (rdev->family == CHIP_KAVERI) {
		2516	rdev->num_crtc = 4;
		2517	rdev->cg_flags =
		2518	RADEON_CG_SUPPORT_GFX_MGCG \|
		2519	RADEON_CG_SUPPORT_GFX_MGLS \|
		2520	/RADEON_CG_SUPPORT_GFX_CGCG \|/
		2521	RADEON_CG_SUPPORT_GFX_CGLS \|
		2522	RADEON_CG_SUPPORT_GFX_CGTS \|
		2523	RADEON_CG_SUPPORT_GFX_CGTS_LS \|
		2524	RADEON_CG_SUPPORT_GFX_CP_LS \|
		2525	RADEON_CG_SUPPORT_SDMA_MGCG \|
		2526	RADEON_CG_SUPPORT_SDMA_LS \|
		2527	RADEON_CG_SUPPORT_BIF_LS \|
		2528	RADEON_CG_SUPPORT_VCE_MGCG \|
		2529	RADEON_CG_SUPPORT_UVD_MGCG \|
		2530	RADEON_CG_SUPPORT_HDP_LS \|
		2531	RADEON_CG_SUPPORT_HDP_MGCG;
		2532	rdev->pg_flags = 0;
		2533	/*RADEON_PG_SUPPORT_GFX_PG \|
		2534	RADEON_PG_SUPPORT_GFX_SMG \|
		2535	RADEON_PG_SUPPORT_GFX_DMG \|
		2536	RADEON_PG_SUPPORT_UVD \|
		2537	RADEON_PG_SUPPORT_VCE \|
		2538	RADEON_PG_SUPPORT_CP \|
		2539	RADEON_PG_SUPPORT_GDS \|
		2540	RADEON_PG_SUPPORT_RLC_SMU_HS \|
		2541	RADEON_PG_SUPPORT_ACP \|
		2542	RADEON_PG_SUPPORT_SAMU;*/
		2543	} else {
		2544	rdev->num_crtc = 2;
		2545	rdev->cg_flags =
		2546	RADEON_CG_SUPPORT_GFX_MGCG \|
		2547	RADEON_CG_SUPPORT_GFX_MGLS \|
		2548	/RADEON_CG_SUPPORT_GFX_CGCG \|/
		2549	RADEON_CG_SUPPORT_GFX_CGLS \|
		2550	RADEON_CG_SUPPORT_GFX_CGTS \|
		2551	RADEON_CG_SUPPORT_GFX_CGTS_LS \|
		2552	RADEON_CG_SUPPORT_GFX_CP_LS \|
		2553	RADEON_CG_SUPPORT_SDMA_MGCG \|
		2554	RADEON_CG_SUPPORT_SDMA_LS \|
		2555	RADEON_CG_SUPPORT_BIF_LS \|
		2556	RADEON_CG_SUPPORT_VCE_MGCG \|
		2557	RADEON_CG_SUPPORT_UVD_MGCG \|
		2558	RADEON_CG_SUPPORT_HDP_LS \|
		2559	RADEON_CG_SUPPORT_HDP_MGCG;
		2560	rdev->pg_flags = 0;
		2561	/*RADEON_PG_SUPPORT_GFX_PG \|
		2562	RADEON_PG_SUPPORT_GFX_SMG \|
		2563	RADEON_PG_SUPPORT_UVD \|
		2564	RADEON_PG_SUPPORT_VCE \|
		2565	RADEON_PG_SUPPORT_CP \|
		2566	RADEON_PG_SUPPORT_GDS \|
		2567	RADEON_PG_SUPPORT_RLC_SMU_HS \|
		2568	RADEON_PG_SUPPORT_SAMU;*/
		2569	}
		2570	rdev->has_uvd = true;
		2571	break;
1963	serge	2572	default:
		2573	/* FIXME: not supported yet */
		2574	return -EINVAL;
		2575	}
		2576
		2577	if (rdev->flags & RADEON_IS_IGP) {
2997	Serge	2578	rdev->asic->pm.get_memory_clock = NULL;
		2579	rdev->asic->pm.set_memory_clock = NULL;
1963	serge	2580	}
		2581
		2582	return 0;
		2583	}
		2584

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/radeon/radeon_asic.c – Rev 5097