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1117 | serge | 1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
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3 | * Copyright 2008 Red Hat Inc. |
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4 | * Copyright 2009 Jerome Glisse. |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the "Software"), |
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8 | * to deal in the Software without restriction, including without limitation |
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9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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10 | * and/or sell copies of the Software, and to permit persons to whom the |
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11 | * Software is furnished to do so, subject to the following conditions: |
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12 | * |
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13 | * The above copyright notice and this permission notice shall be included in |
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14 | * all copies or substantial portions of the Software. |
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15 | * |
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16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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22 | * OTHER DEALINGS IN THE SOFTWARE. |
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23 | * |
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24 | * Authors: Dave Airlie |
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25 | * Alex Deucher |
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26 | * Jerome Glisse |
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27 | */ |
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28 | #ifndef __RADEON_H__ |
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29 | #define __RADEON_H__ |
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30 | |||
31 | /* TODO: Here are things that needs to be done : |
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32 | * - surface allocator & initializer : (bit like scratch reg) should |
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33 | * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings |
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34 | * related to surface |
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35 | * - WB : write back stuff (do it bit like scratch reg things) |
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36 | * - Vblank : look at Jesse's rework and what we should do |
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37 | * - r600/r700: gart & cp |
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38 | * - cs : clean cs ioctl use bitmap & things like that. |
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39 | * - power management stuff |
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40 | * - Barrier in gart code |
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41 | * - Unmappabled vram ? |
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42 | * - TESTING, TESTING, TESTING |
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43 | */ |
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44 | |||
1221 | serge | 45 | /* Initialization path: |
46 | * We expect that acceleration initialization might fail for various |
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47 | * reasons even thought we work hard to make it works on most |
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48 | * configurations. In order to still have a working userspace in such |
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49 | * situation the init path must succeed up to the memory controller |
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50 | * initialization point. Failure before this point are considered as |
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51 | * fatal error. Here is the init callchain : |
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52 | * radeon_device_init perform common structure, mutex initialization |
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53 | * asic_init setup the GPU memory layout and perform all |
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54 | * one time initialization (failure in this |
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55 | * function are considered fatal) |
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56 | * asic_startup setup the GPU acceleration, in order to |
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57 | * follow guideline the first thing this |
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58 | * function should do is setting the GPU |
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59 | * memory controller (only MC setup failure |
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60 | * are considered as fatal) |
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61 | */ |
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62 | |||
1321 | serge | 63 | #include |
2997 | Serge | 64 | #include |
1321 | serge | 65 | #include |
66 | #include |
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2997 | Serge | 67 | #include |
1221 | serge | 68 | |
1321 | serge | 69 | #include |
70 | #include |
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71 | #include |
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72 | #include |
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1221 | serge | 73 | |
2004 | serge | 74 | #include |
1120 | serge | 75 | #include |
1117 | serge | 76 | |
1120 | serge | 77 | #include |
1179 | serge | 78 | |
79 | #include "radeon_family.h" |
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1117 | serge | 80 | #include "radeon_mode.h" |
81 | #include "radeon_reg.h" |
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82 | |||
83 | #include |
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84 | |||
1179 | serge | 85 | /* |
86 | * Modules parameters. |
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87 | */ |
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88 | extern int radeon_no_wb; |
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1123 | serge | 89 | extern int radeon_modeset; |
1117 | serge | 90 | extern int radeon_dynclks; |
1123 | serge | 91 | extern int radeon_r4xx_atom; |
1128 | serge | 92 | extern int radeon_agpmode; |
93 | extern int radeon_vram_limit; |
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1117 | serge | 94 | extern int radeon_gart_size; |
1128 | serge | 95 | extern int radeon_benchmarking; |
1179 | serge | 96 | extern int radeon_testing; |
1123 | serge | 97 | extern int radeon_connector_table; |
1179 | serge | 98 | extern int radeon_tv; |
1403 | serge | 99 | extern int radeon_audio; |
1963 | serge | 100 | extern int radeon_disp_priority; |
101 | extern int radeon_hw_i2c; |
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102 | extern int radeon_pcie_gen2; |
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2997 | Serge | 103 | extern int radeon_msi; |
104 | extern int radeon_lockup_timeout; |
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3764 | Serge | 105 | extern int radeon_fastfb; |
2997 | Serge | 106 | |
107 | |||
1430 | serge | 108 | typedef struct pm_message { |
109 | int event; |
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110 | } pm_message_t; |
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111 | |||
1233 | serge | 112 | typedef struct |
113 | { |
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114 | int width; |
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115 | int height; |
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116 | int bpp; |
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117 | int freq; |
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1321 | serge | 118 | }videomode_t; |
1179 | serge | 119 | |
120 | |||
121 | |||
1963 | serge | 122 | static inline u32 ioread32(const volatile void __iomem *addr) |
123 | { |
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124 | return in32((u32)addr); |
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125 | } |
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126 | |||
3764 | Serge | 127 | //static inline void iowrite32(uint32_t b, volatile void __iomem *addr) |
128 | //{ |
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129 | // out32((u32)addr, b); |
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130 | //} |
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1963 | serge | 131 | |
132 | |||
1117 | serge | 133 | /* |
134 | * Copy from radeon_drv.h so we don't have to include both and have conflicting |
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135 | * symbol; |
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136 | */ |
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1120 | serge | 137 | #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ |
1963 | serge | 138 | #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2) |
1428 | serge | 139 | /* RADEON_IB_POOL_SIZE must be a power of 2 */ |
1120 | serge | 140 | #define RADEON_IB_POOL_SIZE 16 |
2997 | Serge | 141 | #define RADEON_DEBUGFS_MAX_COMPONENTS 32 |
1120 | serge | 142 | #define RADEONFB_CONN_LIMIT 4 |
1179 | serge | 143 | #define RADEON_BIOS_NUM_SCRATCH 8 |
1117 | serge | 144 | |
2997 | Serge | 145 | /* max number of rings */ |
3764 | Serge | 146 | #define RADEON_NUM_RINGS 6 |
2997 | Serge | 147 | |
148 | /* fence seq are set to this number when signaled */ |
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149 | #define RADEON_FENCE_SIGNALED_SEQ 0LL |
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150 | |||
151 | /* internal ring indices */ |
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152 | /* r1xx+ has gfx CP ring */ |
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153 | #define RADEON_RING_TYPE_GFX_INDEX 0 |
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154 | |||
155 | /* cayman has 2 compute CP rings */ |
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156 | #define CAYMAN_RING_TYPE_CP1_INDEX 1 |
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157 | #define CAYMAN_RING_TYPE_CP2_INDEX 2 |
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158 | |||
3192 | Serge | 159 | /* R600+ has an async dma ring */ |
160 | #define R600_RING_TYPE_DMA_INDEX 3 |
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161 | /* cayman add a second async dma ring */ |
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162 | #define CAYMAN_RING_TYPE_DMA1_INDEX 4 |
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163 | |||
3764 | Serge | 164 | /* R600+ */ |
165 | #define R600_RING_TYPE_UVD_INDEX 5 |
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166 | |||
2997 | Serge | 167 | /* hardcode those limit for now */ |
168 | #define RADEON_VA_IB_OFFSET (1 << 20) |
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169 | #define RADEON_VA_RESERVED_SIZE (8 << 20) |
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170 | #define RADEON_IB_VM_MAX_SIZE (64 << 10) |
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171 | |||
3192 | Serge | 172 | /* reset flags */ |
173 | #define RADEON_RESET_GFX (1 << 0) |
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174 | #define RADEON_RESET_COMPUTE (1 << 1) |
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175 | #define RADEON_RESET_DMA (1 << 2) |
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3764 | Serge | 176 | #define RADEON_RESET_CP (1 << 3) |
177 | #define RADEON_RESET_GRBM (1 << 4) |
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178 | #define RADEON_RESET_DMA1 (1 << 5) |
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179 | #define RADEON_RESET_RLC (1 << 6) |
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180 | #define RADEON_RESET_SEM (1 << 7) |
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181 | #define RADEON_RESET_IH (1 << 8) |
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182 | #define RADEON_RESET_VMC (1 << 9) |
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183 | #define RADEON_RESET_MC (1 << 10) |
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184 | #define RADEON_RESET_DISPLAY (1 << 11) |
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3192 | Serge | 185 | |
1117 | serge | 186 | /* |
187 | * Errata workarounds. |
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188 | */ |
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189 | enum radeon_pll_errata { |
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190 | CHIP_ERRATA_R300_CG = 0x00000001, |
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191 | CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, |
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192 | CHIP_ERRATA_PLL_DELAY = 0x00000004 |
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193 | }; |
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194 | |||
195 | |||
196 | struct radeon_device; |
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197 | |||
198 | |||
199 | /* |
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200 | * BIOS. |
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201 | */ |
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202 | bool radeon_get_bios(struct radeon_device *rdev); |
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203 | |||
204 | /* |
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1179 | serge | 205 | * Dummy page |
206 | */ |
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207 | struct radeon_dummy_page { |
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208 | struct page *page; |
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209 | dma_addr_t addr; |
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210 | }; |
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211 | int radeon_dummy_page_init(struct radeon_device *rdev); |
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212 | void radeon_dummy_page_fini(struct radeon_device *rdev); |
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213 | |||
214 | |||
215 | /* |
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1117 | serge | 216 | * Clocks |
217 | */ |
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218 | struct radeon_clock { |
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219 | struct radeon_pll p1pll; |
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220 | struct radeon_pll p2pll; |
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1430 | serge | 221 | struct radeon_pll dcpll; |
1117 | serge | 222 | struct radeon_pll spll; |
223 | struct radeon_pll mpll; |
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224 | /* 10 Khz units */ |
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225 | uint32_t default_mclk; |
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226 | uint32_t default_sclk; |
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1430 | serge | 227 | uint32_t default_dispclk; |
228 | uint32_t dp_extclk; |
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1963 | serge | 229 | uint32_t max_pixel_clock; |
1117 | serge | 230 | }; |
231 | |||
1268 | serge | 232 | /* |
233 | * Power management |
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234 | */ |
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235 | int radeon_pm_init(struct radeon_device *rdev); |
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1963 | serge | 236 | void radeon_pm_fini(struct radeon_device *rdev); |
1430 | serge | 237 | void radeon_pm_compute_clocks(struct radeon_device *rdev); |
1963 | serge | 238 | void radeon_pm_suspend(struct radeon_device *rdev); |
239 | void radeon_pm_resume(struct radeon_device *rdev); |
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1430 | serge | 240 | void radeon_combios_get_power_modes(struct radeon_device *rdev); |
241 | void radeon_atombios_get_power_modes(struct radeon_device *rdev); |
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3764 | Serge | 242 | int radeon_atom_get_clock_dividers(struct radeon_device *rdev, |
243 | u8 clock_type, |
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244 | u32 clock, |
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245 | bool strobe_mode, |
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246 | struct atom_clock_dividers *dividers); |
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1963 | serge | 247 | void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type); |
248 | void rs690_pm_info(struct radeon_device *rdev); |
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249 | extern int rv6xx_get_temp(struct radeon_device *rdev); |
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250 | extern int rv770_get_temp(struct radeon_device *rdev); |
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251 | extern int evergreen_get_temp(struct radeon_device *rdev); |
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252 | extern int sumo_get_temp(struct radeon_device *rdev); |
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2997 | Serge | 253 | extern int si_get_temp(struct radeon_device *rdev); |
254 | extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw, |
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255 | unsigned *bankh, unsigned *mtaspect, |
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256 | unsigned *tile_split); |
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1179 | serge | 257 | |
1117 | serge | 258 | /* |
259 | * Fences. |
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260 | */ |
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261 | struct radeon_fence_driver { |
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262 | uint32_t scratch_reg; |
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2997 | Serge | 263 | uint64_t gpu_addr; |
264 | volatile uint32_t *cpu_addr; |
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265 | /* sync_seq is protected by ring emission lock */ |
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266 | uint64_t sync_seq[RADEON_NUM_RINGS]; |
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267 | atomic64_t last_seq; |
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268 | unsigned long last_activity; |
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1403 | serge | 269 | bool initialized; |
1117 | serge | 270 | }; |
271 | |||
272 | struct radeon_fence { |
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2997 | Serge | 273 | struct radeon_device *rdev; |
274 | struct kref kref; |
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1117 | serge | 275 | /* protected by radeon_fence.lock */ |
2997 | Serge | 276 | uint64_t seq; |
277 | /* RB, DMA, etc. */ |
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278 | unsigned ring; |
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1117 | serge | 279 | }; |
280 | |||
2997 | Serge | 281 | int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring); |
1117 | serge | 282 | int radeon_fence_driver_init(struct radeon_device *rdev); |
283 | void radeon_fence_driver_fini(struct radeon_device *rdev); |
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3192 | Serge | 284 | void radeon_fence_driver_force_completion(struct radeon_device *rdev); |
2997 | Serge | 285 | int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring); |
286 | void radeon_fence_process(struct radeon_device *rdev, int ring); |
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1117 | serge | 287 | bool radeon_fence_signaled(struct radeon_fence *fence); |
288 | int radeon_fence_wait(struct radeon_fence *fence, bool interruptible); |
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2997 | Serge | 289 | int radeon_fence_wait_next_locked(struct radeon_device *rdev, int ring); |
3192 | Serge | 290 | int radeon_fence_wait_empty_locked(struct radeon_device *rdev, int ring); |
2997 | Serge | 291 | int radeon_fence_wait_any(struct radeon_device *rdev, |
292 | struct radeon_fence **fences, |
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293 | bool intr); |
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1117 | serge | 294 | struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence); |
295 | void radeon_fence_unref(struct radeon_fence **fence); |
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2997 | Serge | 296 | unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring); |
297 | bool radeon_fence_need_sync(struct radeon_fence *fence, int ring); |
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298 | void radeon_fence_note_sync(struct radeon_fence *fence, int ring); |
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299 | static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a, |
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300 | struct radeon_fence *b) |
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301 | { |
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302 | if (!a) { |
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303 | return b; |
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304 | } |
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1117 | serge | 305 | |
2997 | Serge | 306 | if (!b) { |
307 | return a; |
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308 | } |
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309 | |||
310 | BUG_ON(a->ring != b->ring); |
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311 | |||
312 | if (a->seq > b->seq) { |
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313 | return a; |
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314 | } else { |
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315 | return b; |
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316 | } |
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317 | } |
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318 | |||
319 | static inline bool radeon_fence_is_earlier(struct radeon_fence *a, |
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320 | struct radeon_fence *b) |
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321 | { |
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322 | if (!a) { |
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323 | return false; |
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324 | } |
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325 | |||
326 | if (!b) { |
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327 | return true; |
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328 | } |
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329 | |||
330 | BUG_ON(a->ring != b->ring); |
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331 | |||
332 | return a->seq < b->seq; |
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333 | } |
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334 | |||
1179 | serge | 335 | /* |
336 | * Tiling registers |
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337 | */ |
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338 | struct radeon_surface_reg { |
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1321 | serge | 339 | struct radeon_bo *bo; |
1179 | serge | 340 | }; |
1117 | serge | 341 | |
1179 | serge | 342 | #define RADEON_GEM_MAX_SURFACES 8 |
343 | |||
1117 | serge | 344 | /* |
1321 | serge | 345 | * TTM. |
1117 | serge | 346 | */ |
1321 | serge | 347 | struct radeon_mman { |
348 | struct ttm_bo_global_ref bo_global_ref; |
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3764 | Serge | 349 | struct drm_global_reference mem_global_ref; |
1403 | serge | 350 | struct ttm_bo_device bdev; |
1321 | serge | 351 | bool mem_global_referenced; |
1403 | serge | 352 | bool initialized; |
1321 | serge | 353 | }; |
1117 | serge | 354 | |
2997 | Serge | 355 | /* bo virtual address in a specific vm */ |
356 | struct radeon_bo_va { |
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357 | /* protected by bo being reserved */ |
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358 | struct list_head bo_list; |
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359 | uint64_t soffset; |
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360 | uint64_t eoffset; |
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361 | uint32_t flags; |
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362 | bool valid; |
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363 | unsigned ref_count; |
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364 | |||
365 | /* protected by vm mutex */ |
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366 | struct list_head vm_list; |
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367 | |||
368 | /* constant after initialization */ |
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369 | struct radeon_vm *vm; |
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370 | struct radeon_bo *bo; |
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371 | }; |
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372 | |||
1321 | serge | 373 | struct radeon_bo { |
374 | /* Protected by gem.mutex */ |
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375 | struct list_head list; |
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376 | /* Protected by tbo.reserved */ |
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377 | u32 placements[3]; |
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3764 | Serge | 378 | u32 domain; |
1321 | serge | 379 | struct ttm_placement placement; |
380 | struct ttm_buffer_object tbo; |
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381 | struct ttm_bo_kmap_obj kmap; |
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1404 | serge | 382 | unsigned pin_count; |
383 | void *kptr; |
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2007 | serge | 384 | void *uptr; |
1404 | serge | 385 | u32 cpu_addr; |
386 | u32 tiling_flags; |
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387 | u32 pitch; |
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388 | int surface_reg; |
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2997 | Serge | 389 | /* list of all virtual address to which this bo |
390 | * is associated to |
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391 | */ |
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392 | struct list_head va; |
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1321 | serge | 393 | /* Constant after initialization */ |
394 | struct radeon_device *rdev; |
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1963 | serge | 395 | struct drm_gem_object gem_base; |
3120 | serge | 396 | |
3764 | Serge | 397 | struct ttm_bo_kmap_obj dma_buf_vmap; |
1321 | serge | 398 | }; |
1963 | serge | 399 | #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base) |
1321 | serge | 400 | |
401 | struct radeon_bo_list { |
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402 | struct radeon_bo *bo; |
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1117 | serge | 403 | uint64_t gpu_offset; |
404 | unsigned rdomain; |
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405 | unsigned wdomain; |
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1321 | serge | 406 | u32 tiling_flags; |
1117 | serge | 407 | }; |
408 | |||
3764 | Serge | 409 | int radeon_gem_debugfs_init(struct radeon_device *rdev); |
410 | |||
2997 | Serge | 411 | /* sub-allocation manager, it has to be protected by another lock. |
412 | * By conception this is an helper for other part of the driver |
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413 | * like the indirect buffer or semaphore, which both have their |
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414 | * locking. |
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415 | * |
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416 | * Principe is simple, we keep a list of sub allocation in offset |
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417 | * order (first entry has offset == 0, last entry has the highest |
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418 | * offset). |
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419 | * |
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420 | * When allocating new object we first check if there is room at |
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421 | * the end total_size - (last_object_offset + last_object_size) >= |
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422 | * alloc_size. If so we allocate new object there. |
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423 | * |
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424 | * When there is not enough room at the end, we start waiting for |
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425 | * each sub object until we reach object_offset+object_size >= |
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426 | * alloc_size, this object then become the sub object we return. |
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427 | * |
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428 | * Alignment can't be bigger than page size. |
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429 | * |
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430 | * Hole are not considered for allocation to keep things simple. |
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431 | * Assumption is that there won't be hole (all object on same |
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432 | * alignment). |
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433 | */ |
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434 | struct radeon_sa_manager { |
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435 | wait_queue_head_t wq; |
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436 | struct radeon_bo *bo; |
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437 | struct list_head *hole; |
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438 | struct list_head flist[RADEON_NUM_RINGS]; |
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439 | struct list_head olist; |
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440 | unsigned size; |
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441 | uint64_t gpu_addr; |
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442 | void *cpu_ptr; |
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443 | uint32_t domain; |
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444 | }; |
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445 | |||
446 | struct radeon_sa_bo; |
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447 | |||
448 | /* sub-allocation buffer */ |
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449 | struct radeon_sa_bo { |
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450 | struct list_head olist; |
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451 | struct list_head flist; |
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452 | struct radeon_sa_manager *manager; |
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453 | unsigned soffset; |
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454 | unsigned eoffset; |
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455 | struct radeon_fence *fence; |
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456 | }; |
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457 | |||
1123 | serge | 458 | /* |
459 | * GEM objects. |
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460 | */ |
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461 | struct radeon_gem { |
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1630 | serge | 462 | struct mutex mutex; |
1123 | serge | 463 | struct list_head objects; |
464 | }; |
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1117 | serge | 465 | |
1126 | serge | 466 | int radeon_gem_init(struct radeon_device *rdev); |
467 | void radeon_gem_fini(struct radeon_device *rdev); |
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468 | int radeon_gem_object_create(struct radeon_device *rdev, int size, |
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469 | int alignment, int initial_domain, |
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470 | bool discardable, bool kernel, |
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471 | struct drm_gem_object **obj); |
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1117 | serge | 472 | |
2004 | serge | 473 | int radeon_mode_dumb_create(struct drm_file *file_priv, |
474 | struct drm_device *dev, |
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475 | struct drm_mode_create_dumb *args); |
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476 | int radeon_mode_dumb_mmap(struct drm_file *filp, |
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477 | struct drm_device *dev, |
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478 | uint32_t handle, uint64_t *offset_p); |
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479 | int radeon_mode_dumb_destroy(struct drm_file *file_priv, |
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480 | struct drm_device *dev, |
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481 | uint32_t handle); |
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1117 | serge | 482 | |
483 | /* |
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2997 | Serge | 484 | * Semaphores. |
1117 | serge | 485 | */ |
2997 | Serge | 486 | /* everything here is constant */ |
487 | struct radeon_semaphore { |
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488 | struct radeon_sa_bo *sa_bo; |
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489 | signed waiters; |
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490 | uint64_t gpu_addr; |
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1117 | serge | 491 | }; |
492 | |||
2997 | Serge | 493 | int radeon_semaphore_create(struct radeon_device *rdev, |
494 | struct radeon_semaphore **semaphore); |
||
495 | void radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring, |
||
496 | struct radeon_semaphore *semaphore); |
||
497 | void radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring, |
||
498 | struct radeon_semaphore *semaphore); |
||
499 | int radeon_semaphore_sync_rings(struct radeon_device *rdev, |
||
500 | struct radeon_semaphore *semaphore, |
||
501 | int signaler, int waiter); |
||
502 | void radeon_semaphore_free(struct radeon_device *rdev, |
||
503 | struct radeon_semaphore **semaphore, |
||
504 | struct radeon_fence *fence); |
||
1117 | serge | 505 | |
2997 | Serge | 506 | /* |
507 | * GART structures, functions & helpers |
||
508 | */ |
||
509 | struct radeon_mc; |
||
1117 | serge | 510 | |
1268 | serge | 511 | #define RADEON_GPU_PAGE_SIZE 4096 |
1430 | serge | 512 | #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1) |
2997 | Serge | 513 | #define RADEON_GPU_PAGE_SHIFT 12 |
514 | #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK) |
||
1268 | serge | 515 | |
1117 | serge | 516 | struct radeon_gart { |
517 | dma_addr_t table_addr; |
||
2997 | Serge | 518 | struct radeon_bo *robj; |
519 | void *ptr; |
||
1117 | serge | 520 | unsigned num_gpu_pages; |
521 | unsigned num_cpu_pages; |
||
522 | unsigned table_size; |
||
523 | struct page **pages; |
||
524 | dma_addr_t *pages_addr; |
||
525 | bool ready; |
||
526 | }; |
||
527 | |||
528 | int radeon_gart_table_ram_alloc(struct radeon_device *rdev); |
||
529 | void radeon_gart_table_ram_free(struct radeon_device *rdev); |
||
530 | int radeon_gart_table_vram_alloc(struct radeon_device *rdev); |
||
531 | void radeon_gart_table_vram_free(struct radeon_device *rdev); |
||
2997 | Serge | 532 | int radeon_gart_table_vram_pin(struct radeon_device *rdev); |
533 | void radeon_gart_table_vram_unpin(struct radeon_device *rdev); |
||
1117 | serge | 534 | int radeon_gart_init(struct radeon_device *rdev); |
535 | void radeon_gart_fini(struct radeon_device *rdev); |
||
536 | void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, |
||
537 | int pages); |
||
1120 | serge | 538 | int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, |
2997 | Serge | 539 | int pages, u32 *pagelist, |
540 | dma_addr_t *dma_addr); |
||
541 | void radeon_gart_restore(struct radeon_device *rdev); |
||
1117 | serge | 542 | |
543 | |||
544 | /* |
||
545 | * GPU MC structures, functions & helpers |
||
546 | */ |
||
547 | struct radeon_mc { |
||
548 | resource_size_t aper_size; |
||
549 | resource_size_t aper_base; |
||
550 | resource_size_t agp_base; |
||
1179 | serge | 551 | /* for some chips with <= 32MB we need to lie |
552 | * about vram size near mc fb location */ |
||
553 | u64 mc_vram_size; |
||
1430 | serge | 554 | u64 visible_vram_size; |
1179 | serge | 555 | u64 gtt_size; |
556 | u64 gtt_start; |
||
557 | u64 gtt_end; |
||
558 | u64 vram_start; |
||
559 | u64 vram_end; |
||
1117 | serge | 560 | unsigned vram_width; |
1179 | serge | 561 | u64 real_vram_size; |
1117 | serge | 562 | int vram_mtrr; |
563 | bool vram_is_ddr; |
||
1403 | serge | 564 | bool igp_sideport_enabled; |
1963 | serge | 565 | u64 gtt_base_align; |
3764 | Serge | 566 | u64 mc_mask; |
1117 | serge | 567 | }; |
568 | |||
1403 | serge | 569 | bool radeon_combios_sideport_present(struct radeon_device *rdev); |
570 | bool radeon_atombios_sideport_present(struct radeon_device *rdev); |
||
1117 | serge | 571 | |
572 | /* |
||
573 | * GPU scratch registers structures, functions & helpers |
||
574 | */ |
||
575 | struct radeon_scratch { |
||
576 | unsigned num_reg; |
||
1963 | serge | 577 | uint32_t reg_base; |
1117 | serge | 578 | bool free[32]; |
579 | uint32_t reg[32]; |
||
580 | }; |
||
581 | |||
582 | int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg); |
||
583 | void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg); |
||
584 | |||
585 | |||
586 | /* |
||
587 | * IRQS. |
||
588 | */ |
||
1963 | serge | 589 | struct r500_irq_stat_regs { |
590 | u32 disp_int; |
||
2997 | Serge | 591 | u32 hdmi0_status; |
1963 | serge | 592 | }; |
593 | |||
594 | struct r600_irq_stat_regs { |
||
595 | u32 disp_int; |
||
596 | u32 disp_int_cont; |
||
597 | u32 disp_int_cont2; |
||
598 | u32 d1grph_int; |
||
599 | u32 d2grph_int; |
||
2997 | Serge | 600 | u32 hdmi0_status; |
601 | u32 hdmi1_status; |
||
1963 | serge | 602 | }; |
603 | |||
604 | struct evergreen_irq_stat_regs { |
||
605 | u32 disp_int; |
||
606 | u32 disp_int_cont; |
||
607 | u32 disp_int_cont2; |
||
608 | u32 disp_int_cont3; |
||
609 | u32 disp_int_cont4; |
||
610 | u32 disp_int_cont5; |
||
611 | u32 d1grph_int; |
||
612 | u32 d2grph_int; |
||
613 | u32 d3grph_int; |
||
614 | u32 d4grph_int; |
||
615 | u32 d5grph_int; |
||
616 | u32 d6grph_int; |
||
2997 | Serge | 617 | u32 afmt_status1; |
618 | u32 afmt_status2; |
||
619 | u32 afmt_status3; |
||
620 | u32 afmt_status4; |
||
621 | u32 afmt_status5; |
||
622 | u32 afmt_status6; |
||
1963 | serge | 623 | }; |
624 | |||
625 | union radeon_irq_stat_regs { |
||
626 | struct r500_irq_stat_regs r500; |
||
627 | struct r600_irq_stat_regs r600; |
||
628 | struct evergreen_irq_stat_regs evergreen; |
||
629 | }; |
||
630 | |||
2997 | Serge | 631 | #define RADEON_MAX_HPD_PINS 6 |
632 | #define RADEON_MAX_CRTCS 6 |
||
633 | #define RADEON_MAX_AFMT_BLOCKS 6 |
||
634 | |||
1117 | serge | 635 | struct radeon_irq { |
636 | bool installed; |
||
2997 | Serge | 637 | spinlock_t lock; |
638 | atomic_t ring_int[RADEON_NUM_RINGS]; |
||
639 | bool crtc_vblank_int[RADEON_MAX_CRTCS]; |
||
640 | atomic_t pflip[RADEON_MAX_CRTCS]; |
||
1963 | serge | 641 | wait_queue_head_t vblank_queue; |
2997 | Serge | 642 | bool hpd[RADEON_MAX_HPD_PINS]; |
643 | bool afmt[RADEON_MAX_AFMT_BLOCKS]; |
||
1963 | serge | 644 | union radeon_irq_stat_regs stat_regs; |
1117 | serge | 645 | }; |
646 | |||
647 | int radeon_irq_kms_init(struct radeon_device *rdev); |
||
648 | void radeon_irq_kms_fini(struct radeon_device *rdev); |
||
2997 | Serge | 649 | void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring); |
650 | void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring); |
||
2004 | serge | 651 | void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc); |
652 | void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc); |
||
2997 | Serge | 653 | void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block); |
654 | void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block); |
||
655 | void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask); |
||
656 | void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask); |
||
1117 | serge | 657 | |
658 | /* |
||
2997 | Serge | 659 | * CP & rings. |
1117 | serge | 660 | */ |
2997 | Serge | 661 | |
1117 | serge | 662 | struct radeon_ib { |
2997 | Serge | 663 | struct radeon_sa_bo *sa_bo; |
664 | uint32_t length_dw; |
||
1403 | serge | 665 | uint64_t gpu_addr; |
2997 | Serge | 666 | uint32_t *ptr; |
667 | int ring; |
||
1117 | serge | 668 | struct radeon_fence *fence; |
2997 | Serge | 669 | struct radeon_vm *vm; |
670 | bool is_const_ib; |
||
671 | struct radeon_fence *sync_to[RADEON_NUM_RINGS]; |
||
672 | struct radeon_semaphore *semaphore; |
||
1117 | serge | 673 | }; |
674 | |||
2997 | Serge | 675 | struct radeon_ring { |
1321 | serge | 676 | struct radeon_bo *ring_obj; |
1117 | serge | 677 | volatile uint32_t *ring; |
1403 | serge | 678 | unsigned rptr; |
2997 | Serge | 679 | unsigned rptr_offs; |
680 | unsigned rptr_reg; |
||
681 | unsigned rptr_save_reg; |
||
682 | u64 next_rptr_gpu_addr; |
||
683 | volatile u32 *next_rptr_cpu_addr; |
||
1403 | serge | 684 | unsigned wptr; |
685 | unsigned wptr_old; |
||
2997 | Serge | 686 | unsigned wptr_reg; |
1403 | serge | 687 | unsigned ring_size; |
688 | unsigned ring_free_dw; |
||
689 | int count_dw; |
||
2997 | Serge | 690 | unsigned long last_activity; |
691 | unsigned last_rptr; |
||
1403 | serge | 692 | uint64_t gpu_addr; |
693 | uint32_t align_mask; |
||
694 | uint32_t ptr_mask; |
||
695 | bool ready; |
||
2997 | Serge | 696 | u32 ptr_reg_shift; |
697 | u32 ptr_reg_mask; |
||
698 | u32 nop; |
||
699 | u32 idx; |
||
3764 | Serge | 700 | u64 last_semaphore_signal_addr; |
701 | u64 last_semaphore_wait_addr; |
||
1117 | serge | 702 | }; |
703 | |||
1321 | serge | 704 | /* |
2997 | Serge | 705 | * VM |
706 | */ |
||
707 | |||
708 | /* maximum number of VMIDs */ |
||
709 | #define RADEON_NUM_VM 16 |
||
710 | |||
711 | /* defines number of bits in page table versus page directory, |
||
712 | * a page is 4KB so we have 12 bits offset, 9 bits in the page |
||
713 | * table and the remaining 19 bits are in the page directory */ |
||
714 | #define RADEON_VM_BLOCK_SIZE 9 |
||
715 | |||
716 | /* number of entries in page table */ |
||
717 | #define RADEON_VM_PTE_COUNT (1 << RADEON_VM_BLOCK_SIZE) |
||
718 | |||
719 | struct radeon_vm { |
||
720 | struct list_head list; |
||
721 | struct list_head va; |
||
722 | unsigned id; |
||
723 | |||
724 | /* contains the page directory */ |
||
725 | struct radeon_sa_bo *page_directory; |
||
726 | uint64_t pd_gpu_addr; |
||
727 | |||
728 | /* array of page tables, one for each page directory entry */ |
||
729 | struct radeon_sa_bo **page_tables; |
||
730 | |||
731 | struct mutex mutex; |
||
732 | /* last fence for cs using this vm */ |
||
733 | struct radeon_fence *fence; |
||
734 | /* last flush or NULL if we still need to flush */ |
||
735 | struct radeon_fence *last_flush; |
||
736 | }; |
||
737 | |||
738 | struct radeon_vm_manager { |
||
739 | struct mutex lock; |
||
740 | struct list_head lru_vm; |
||
741 | struct radeon_fence *active[RADEON_NUM_VM]; |
||
742 | struct radeon_sa_manager sa_manager; |
||
743 | uint32_t max_pfn; |
||
744 | /* number of VMIDs */ |
||
745 | unsigned nvm; |
||
746 | /* vram base address for page table entry */ |
||
747 | u64 vram_base_offset; |
||
748 | /* is vm enabled? */ |
||
749 | bool enabled; |
||
750 | }; |
||
751 | |||
752 | /* |
||
753 | * file private structure |
||
754 | */ |
||
755 | struct radeon_fpriv { |
||
756 | struct radeon_vm vm; |
||
757 | }; |
||
758 | |||
759 | /* |
||
1321 | serge | 760 | * R6xx+ IH ring |
761 | */ |
||
762 | struct r600_ih { |
||
763 | struct radeon_bo *ring_obj; |
||
764 | volatile uint32_t *ring; |
||
765 | unsigned rptr; |
||
766 | unsigned ring_size; |
||
767 | uint64_t gpu_addr; |
||
768 | uint32_t ptr_mask; |
||
2997 | Serge | 769 | atomic_t lock; |
1321 | serge | 770 | bool enabled; |
771 | }; |
||
772 | |||
2997 | Serge | 773 | struct r600_blit_cp_primitives { |
774 | void (*set_render_target)(struct radeon_device *rdev, int format, |
||
775 | int w, int h, u64 gpu_addr); |
||
776 | void (*cp_set_surface_sync)(struct radeon_device *rdev, |
||
777 | u32 sync_type, u32 size, |
||
778 | u64 mc_addr); |
||
779 | void (*set_shaders)(struct radeon_device *rdev); |
||
780 | void (*set_vtx_resource)(struct radeon_device *rdev, u64 gpu_addr); |
||
781 | void (*set_tex_resource)(struct radeon_device *rdev, |
||
782 | int format, int w, int h, int pitch, |
||
783 | u64 gpu_addr, u32 size); |
||
784 | void (*set_scissors)(struct radeon_device *rdev, int x1, int y1, |
||
785 | int x2, int y2); |
||
786 | void (*draw_auto)(struct radeon_device *rdev); |
||
787 | void (*set_default_state)(struct radeon_device *rdev); |
||
788 | }; |
||
789 | |||
1179 | serge | 790 | struct r600_blit { |
1321 | serge | 791 | struct radeon_bo *shader_obj; |
2997 | Serge | 792 | struct r600_blit_cp_primitives primitives; |
793 | int max_dim; |
||
794 | int ring_size_common; |
||
795 | int ring_size_per_loop; |
||
1179 | serge | 796 | u64 shader_gpu_addr; |
797 | u32 vs_offset, ps_offset; |
||
798 | u32 state_offset; |
||
799 | u32 state_len; |
||
800 | }; |
||
801 | |||
2997 | Serge | 802 | /* |
803 | * SI RLC stuff |
||
804 | */ |
||
805 | struct si_rlc { |
||
806 | /* for power gating */ |
||
807 | struct radeon_bo *save_restore_obj; |
||
808 | uint64_t save_restore_gpu_addr; |
||
809 | /* for clear state */ |
||
810 | struct radeon_bo *clear_state_obj; |
||
811 | uint64_t clear_state_gpu_addr; |
||
812 | }; |
||
813 | |||
814 | int radeon_ib_get(struct radeon_device *rdev, int ring, |
||
815 | struct radeon_ib *ib, struct radeon_vm *vm, |
||
816 | unsigned size); |
||
817 | void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib); |
||
3764 | Serge | 818 | void radeon_ib_sync_to(struct radeon_ib *ib, struct radeon_fence *fence); |
2997 | Serge | 819 | int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib, |
820 | struct radeon_ib *const_ib); |
||
1117 | serge | 821 | int radeon_ib_pool_init(struct radeon_device *rdev); |
822 | void radeon_ib_pool_fini(struct radeon_device *rdev); |
||
2997 | Serge | 823 | int radeon_ib_ring_tests(struct radeon_device *rdev); |
1117 | serge | 824 | /* Ring access between begin & end cannot sleep */ |
2997 | Serge | 825 | bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev, |
826 | struct radeon_ring *ring); |
||
827 | void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp); |
||
828 | int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); |
||
829 | int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); |
||
830 | void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp); |
||
831 | void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp); |
||
832 | void radeon_ring_undo(struct radeon_ring *ring); |
||
833 | void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp); |
||
834 | int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); |
||
835 | void radeon_ring_force_activity(struct radeon_device *rdev, struct radeon_ring *ring); |
||
836 | void radeon_ring_lockup_update(struct radeon_ring *ring); |
||
837 | bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring); |
||
838 | unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring, |
||
839 | uint32_t **data); |
||
840 | int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring, |
||
841 | unsigned size, uint32_t *data); |
||
842 | int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size, |
||
843 | unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg, |
||
844 | u32 ptr_reg_shift, u32 ptr_reg_mask, u32 nop); |
||
845 | void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp); |
||
1117 | serge | 846 | |
847 | |||
3192 | Serge | 848 | /* r600 async dma */ |
849 | void r600_dma_stop(struct radeon_device *rdev); |
||
850 | int r600_dma_resume(struct radeon_device *rdev); |
||
851 | void r600_dma_fini(struct radeon_device *rdev); |
||
852 | |||
853 | void cayman_dma_stop(struct radeon_device *rdev); |
||
854 | int cayman_dma_resume(struct radeon_device *rdev); |
||
855 | void cayman_dma_fini(struct radeon_device *rdev); |
||
856 | |||
1117 | serge | 857 | /* |
858 | * CS. |
||
859 | */ |
||
860 | struct radeon_cs_reloc { |
||
861 | // struct drm_gem_object *gobj; |
||
1321 | serge | 862 | struct radeon_bo *robj; |
1630 | serge | 863 | struct radeon_bo_list lobj; |
1403 | serge | 864 | uint32_t handle; |
865 | uint32_t flags; |
||
1117 | serge | 866 | }; |
867 | |||
868 | struct radeon_cs_chunk { |
||
869 | uint32_t chunk_id; |
||
870 | uint32_t length_dw; |
||
1221 | serge | 871 | int kpage_idx[2]; |
872 | uint32_t *kpage[2]; |
||
1117 | serge | 873 | uint32_t *kdata; |
1221 | serge | 874 | void __user *user_ptr; |
875 | int last_copied_page; |
||
876 | int last_page_index; |
||
1117 | serge | 877 | }; |
878 | |||
879 | struct radeon_cs_parser { |
||
1430 | serge | 880 | struct device *dev; |
1117 | serge | 881 | struct radeon_device *rdev; |
2004 | serge | 882 | struct drm_file *filp; |
1117 | serge | 883 | /* chunks */ |
884 | unsigned nchunks; |
||
885 | struct radeon_cs_chunk *chunks; |
||
886 | uint64_t *chunks_array; |
||
887 | /* IB */ |
||
888 | unsigned idx; |
||
889 | /* relocations */ |
||
890 | unsigned nrelocs; |
||
891 | struct radeon_cs_reloc *relocs; |
||
892 | struct radeon_cs_reloc **relocs_ptr; |
||
1120 | serge | 893 | struct list_head validated; |
3192 | Serge | 894 | unsigned dma_reloc_idx; |
1117 | serge | 895 | /* indices of various chunks */ |
896 | int chunk_ib_idx; |
||
897 | int chunk_relocs_idx; |
||
2997 | Serge | 898 | int chunk_flags_idx; |
899 | int chunk_const_ib_idx; |
||
900 | struct radeon_ib ib; |
||
901 | struct radeon_ib const_ib; |
||
1117 | serge | 902 | void *track; |
1179 | serge | 903 | unsigned family; |
1221 | serge | 904 | int parser_error; |
2997 | Serge | 905 | u32 cs_flags; |
906 | u32 ring; |
||
907 | s32 priority; |
||
1117 | serge | 908 | }; |
909 | |||
1221 | serge | 910 | extern int radeon_cs_finish_pages(struct radeon_cs_parser *p); |
2997 | Serge | 911 | extern u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx); |
1221 | serge | 912 | |
1117 | serge | 913 | struct radeon_cs_packet { |
914 | unsigned idx; |
||
915 | unsigned type; |
||
916 | unsigned reg; |
||
917 | unsigned opcode; |
||
918 | int count; |
||
919 | unsigned one_reg_wr; |
||
920 | }; |
||
921 | |||
922 | typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p, |
||
923 | struct radeon_cs_packet *pkt, |
||
924 | unsigned idx, unsigned reg); |
||
925 | typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p, |
||
926 | struct radeon_cs_packet *pkt); |
||
927 | |||
928 | |||
929 | /* |
||
930 | * AGP |
||
931 | */ |
||
932 | int radeon_agp_init(struct radeon_device *rdev); |
||
1321 | serge | 933 | void radeon_agp_resume(struct radeon_device *rdev); |
1963 | serge | 934 | void radeon_agp_suspend(struct radeon_device *rdev); |
1117 | serge | 935 | void radeon_agp_fini(struct radeon_device *rdev); |
936 | |||
937 | |||
938 | /* |
||
939 | * Writeback |
||
940 | */ |
||
941 | struct radeon_wb { |
||
1321 | serge | 942 | struct radeon_bo *wb_obj; |
1117 | serge | 943 | volatile uint32_t *wb; |
944 | uint64_t gpu_addr; |
||
1963 | serge | 945 | bool enabled; |
946 | bool use_event; |
||
1117 | serge | 947 | }; |
948 | |||
1963 | serge | 949 | #define RADEON_WB_SCRATCH_OFFSET 0 |
2997 | Serge | 950 | #define RADEON_WB_RING0_NEXT_RPTR 256 |
1963 | serge | 951 | #define RADEON_WB_CP_RPTR_OFFSET 1024 |
952 | #define RADEON_WB_CP1_RPTR_OFFSET 1280 |
||
953 | #define RADEON_WB_CP2_RPTR_OFFSET 1536 |
||
3192 | Serge | 954 | #define R600_WB_DMA_RPTR_OFFSET 1792 |
1963 | serge | 955 | #define R600_WB_IH_WPTR_OFFSET 2048 |
3192 | Serge | 956 | #define CAYMAN_WB_DMA1_RPTR_OFFSET 2304 |
3764 | Serge | 957 | #define R600_WB_UVD_RPTR_OFFSET 2560 |
1963 | serge | 958 | #define R600_WB_EVENT_OFFSET 3072 |
959 | |||
1179 | serge | 960 | /** |
961 | * struct radeon_pm - power management datas |
||
962 | * @max_bandwidth: maximum bandwidth the gpu has (MByte/s) |
||
963 | * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880) |
||
964 | * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880) |
||
965 | * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880) |
||
966 | * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880) |
||
967 | * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP) |
||
968 | * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP) |
||
969 | * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP) |
||
970 | * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP) |
||
1963 | serge | 971 | * @sclk: GPU clock Mhz (core bandwidth depends of this clock) |
1179 | serge | 972 | * @needed_bandwidth: current bandwidth needs |
973 | * |
||
974 | * It keeps track of various data needed to take powermanagement decision. |
||
1963 | serge | 975 | * Bandwidth need is used to determine minimun clock of the GPU and memory. |
1179 | serge | 976 | * Equation between gpu/memory clock and available bandwidth is hw dependent |
977 | * (type of memory, bus size, efficiency, ...) |
||
978 | */ |
||
1963 | serge | 979 | |
980 | enum radeon_pm_method { |
||
981 | PM_METHOD_PROFILE, |
||
982 | PM_METHOD_DYNPM, |
||
1430 | serge | 983 | }; |
1963 | serge | 984 | |
985 | enum radeon_dynpm_state { |
||
986 | DYNPM_STATE_DISABLED, |
||
987 | DYNPM_STATE_MINIMUM, |
||
988 | DYNPM_STATE_PAUSED, |
||
989 | DYNPM_STATE_ACTIVE, |
||
990 | DYNPM_STATE_SUSPENDED, |
||
1430 | serge | 991 | }; |
1963 | serge | 992 | enum radeon_dynpm_action { |
993 | DYNPM_ACTION_NONE, |
||
994 | DYNPM_ACTION_MINIMUM, |
||
995 | DYNPM_ACTION_DOWNCLOCK, |
||
996 | DYNPM_ACTION_UPCLOCK, |
||
997 | DYNPM_ACTION_DEFAULT |
||
998 | }; |
||
1430 | serge | 999 | |
1000 | enum radeon_voltage_type { |
||
1001 | VOLTAGE_NONE = 0, |
||
1002 | VOLTAGE_GPIO, |
||
1003 | VOLTAGE_VDDC, |
||
1004 | VOLTAGE_SW |
||
1005 | }; |
||
1006 | |||
1007 | enum radeon_pm_state_type { |
||
1008 | POWER_STATE_TYPE_DEFAULT, |
||
1009 | POWER_STATE_TYPE_POWERSAVE, |
||
1010 | POWER_STATE_TYPE_BATTERY, |
||
1011 | POWER_STATE_TYPE_BALANCED, |
||
1012 | POWER_STATE_TYPE_PERFORMANCE, |
||
1013 | }; |
||
1014 | |||
1963 | serge | 1015 | enum radeon_pm_profile_type { |
1016 | PM_PROFILE_DEFAULT, |
||
1017 | PM_PROFILE_AUTO, |
||
1018 | PM_PROFILE_LOW, |
||
1019 | PM_PROFILE_MID, |
||
1020 | PM_PROFILE_HIGH, |
||
1430 | serge | 1021 | }; |
1022 | |||
1963 | serge | 1023 | #define PM_PROFILE_DEFAULT_IDX 0 |
1024 | #define PM_PROFILE_LOW_SH_IDX 1 |
||
1025 | #define PM_PROFILE_MID_SH_IDX 2 |
||
1026 | #define PM_PROFILE_HIGH_SH_IDX 3 |
||
1027 | #define PM_PROFILE_LOW_MH_IDX 4 |
||
1028 | #define PM_PROFILE_MID_MH_IDX 5 |
||
1029 | #define PM_PROFILE_HIGH_MH_IDX 6 |
||
1030 | #define PM_PROFILE_MAX 7 |
||
1031 | |||
1032 | struct radeon_pm_profile { |
||
1033 | int dpms_off_ps_idx; |
||
1034 | int dpms_on_ps_idx; |
||
1035 | int dpms_off_cm_idx; |
||
1036 | int dpms_on_cm_idx; |
||
1037 | }; |
||
1038 | |||
1039 | enum radeon_int_thermal_type { |
||
1040 | THERMAL_TYPE_NONE, |
||
1041 | THERMAL_TYPE_RV6XX, |
||
1042 | THERMAL_TYPE_RV770, |
||
1043 | THERMAL_TYPE_EVERGREEN, |
||
1044 | THERMAL_TYPE_SUMO, |
||
1045 | THERMAL_TYPE_NI, |
||
2997 | Serge | 1046 | THERMAL_TYPE_SI, |
1963 | serge | 1047 | }; |
1048 | |||
1430 | serge | 1049 | struct radeon_voltage { |
1050 | enum radeon_voltage_type type; |
||
1051 | /* gpio voltage */ |
||
1052 | struct radeon_gpio_rec gpio; |
||
1053 | u32 delay; /* delay in usec from voltage drop to sclk change */ |
||
1054 | bool active_high; /* voltage drop is active when bit is high */ |
||
1055 | /* VDDC voltage */ |
||
1056 | u8 vddc_id; /* index into vddc voltage table */ |
||
1057 | u8 vddci_id; /* index into vddci voltage table */ |
||
1058 | bool vddci_enabled; |
||
1059 | /* r6xx+ sw */ |
||
1963 | serge | 1060 | u16 voltage; |
1061 | /* evergreen+ vddci */ |
||
1062 | u16 vddci; |
||
1430 | serge | 1063 | }; |
1064 | |||
1963 | serge | 1065 | /* clock mode flags */ |
1066 | #define RADEON_PM_MODE_NO_DISPLAY (1 << 0) |
||
1430 | serge | 1067 | |
1068 | struct radeon_pm_clock_info { |
||
1069 | /* memory clock */ |
||
1070 | u32 mclk; |
||
1071 | /* engine clock */ |
||
1072 | u32 sclk; |
||
1073 | /* voltage info */ |
||
1074 | struct radeon_voltage voltage; |
||
1963 | serge | 1075 | /* standardized clock flags */ |
1430 | serge | 1076 | u32 flags; |
1077 | }; |
||
1078 | |||
1963 | serge | 1079 | /* state flags */ |
1080 | #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0) |
||
1081 | |||
1430 | serge | 1082 | struct radeon_power_state { |
1083 | enum radeon_pm_state_type type; |
||
2997 | Serge | 1084 | struct radeon_pm_clock_info *clock_info; |
1430 | serge | 1085 | /* number of valid clock modes in this power state */ |
1086 | int num_clock_modes; |
||
1087 | struct radeon_pm_clock_info *default_clock_mode; |
||
1963 | serge | 1088 | /* standardized state flags */ |
1089 | u32 flags; |
||
1090 | u32 misc; /* vbios specific flags */ |
||
1091 | u32 misc2; /* vbios specific flags */ |
||
1092 | int pcie_lanes; /* pcie lanes */ |
||
1430 | serge | 1093 | }; |
1094 | |||
1095 | /* |
||
1096 | * Some modes are overclocked by very low value, accept them |
||
1097 | */ |
||
1098 | #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */ |
||
1099 | |||
1179 | serge | 1100 | struct radeon_pm { |
1630 | serge | 1101 | struct mutex mutex; |
2997 | Serge | 1102 | /* write locked while reprogramming mclk */ |
1103 | struct rw_semaphore mclk_lock; |
||
1963 | serge | 1104 | u32 active_crtcs; |
1105 | int active_crtc_count; |
||
1430 | serge | 1106 | int req_vblank; |
1963 | serge | 1107 | bool vblank_sync; |
1179 | serge | 1108 | fixed20_12 max_bandwidth; |
1109 | fixed20_12 igp_sideport_mclk; |
||
1110 | fixed20_12 igp_system_mclk; |
||
1111 | fixed20_12 igp_ht_link_clk; |
||
1112 | fixed20_12 igp_ht_link_width; |
||
1113 | fixed20_12 k8_bandwidth; |
||
1114 | fixed20_12 sideport_bandwidth; |
||
1115 | fixed20_12 ht_bandwidth; |
||
1116 | fixed20_12 core_bandwidth; |
||
1117 | fixed20_12 sclk; |
||
1963 | serge | 1118 | fixed20_12 mclk; |
1179 | serge | 1119 | fixed20_12 needed_bandwidth; |
1963 | serge | 1120 | struct radeon_power_state *power_state; |
1430 | serge | 1121 | /* number of valid power states */ |
1122 | int num_power_states; |
||
1963 | serge | 1123 | int current_power_state_index; |
1124 | int current_clock_mode_index; |
||
1125 | int requested_power_state_index; |
||
1126 | int requested_clock_mode_index; |
||
1127 | int default_power_state_index; |
||
1128 | u32 current_sclk; |
||
1129 | u32 current_mclk; |
||
1130 | u16 current_vddc; |
||
1131 | u16 current_vddci; |
||
1132 | u32 default_sclk; |
||
1133 | u32 default_mclk; |
||
1134 | u16 default_vddc; |
||
1135 | u16 default_vddci; |
||
1136 | struct radeon_i2c_chan *i2c_bus; |
||
1137 | /* selected pm method */ |
||
1138 | enum radeon_pm_method pm_method; |
||
1139 | /* dynpm power management */ |
||
1140 | // struct delayed_work dynpm_idle_work; |
||
1141 | enum radeon_dynpm_state dynpm_state; |
||
1142 | enum radeon_dynpm_action dynpm_planned_action; |
||
1143 | unsigned long dynpm_action_timeout; |
||
1144 | bool dynpm_can_upclock; |
||
1145 | bool dynpm_can_downclock; |
||
1146 | /* profile-based power management */ |
||
1147 | enum radeon_pm_profile_type profile; |
||
1148 | int profile_index; |
||
1149 | struct radeon_pm_profile profiles[PM_PROFILE_MAX]; |
||
1150 | /* internal thermal controller on rv6xx+ */ |
||
1151 | enum radeon_int_thermal_type int_thermal_type; |
||
1152 | struct device *int_hwmon_dev; |
||
1179 | serge | 1153 | }; |
1117 | serge | 1154 | |
2997 | Serge | 1155 | int radeon_pm_get_type_index(struct radeon_device *rdev, |
1156 | enum radeon_pm_state_type ps_type, |
||
1157 | int instance); |
||
3764 | Serge | 1158 | /* |
1159 | * UVD |
||
1160 | */ |
||
1161 | #define RADEON_MAX_UVD_HANDLES 10 |
||
1162 | #define RADEON_UVD_STACK_SIZE (1024*1024) |
||
1163 | #define RADEON_UVD_HEAP_SIZE (1024*1024) |
||
2997 | Serge | 1164 | |
3764 | Serge | 1165 | struct radeon_uvd { |
1166 | struct radeon_bo *vcpu_bo; |
||
1167 | void *cpu_addr; |
||
1168 | uint64_t gpu_addr; |
||
1169 | atomic_t handles[RADEON_MAX_UVD_HANDLES]; |
||
1170 | struct drm_file *filp[RADEON_MAX_UVD_HANDLES]; |
||
1171 | struct delayed_work idle_work; |
||
1172 | }; |
||
1173 | |||
1174 | int radeon_uvd_init(struct radeon_device *rdev); |
||
1175 | void radeon_uvd_fini(struct radeon_device *rdev); |
||
1176 | int radeon_uvd_suspend(struct radeon_device *rdev); |
||
1177 | int radeon_uvd_resume(struct radeon_device *rdev); |
||
1178 | int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring, |
||
1179 | uint32_t handle, struct radeon_fence **fence); |
||
1180 | int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring, |
||
1181 | uint32_t handle, struct radeon_fence **fence); |
||
1182 | void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo); |
||
1183 | void radeon_uvd_free_handles(struct radeon_device *rdev, |
||
1184 | struct drm_file *filp); |
||
1185 | int radeon_uvd_cs_parse(struct radeon_cs_parser *parser); |
||
1186 | void radeon_uvd_note_usage(struct radeon_device *rdev); |
||
1187 | int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev, |
||
1188 | unsigned vclk, unsigned dclk, |
||
1189 | unsigned vco_min, unsigned vco_max, |
||
1190 | unsigned fb_factor, unsigned fb_mask, |
||
1191 | unsigned pd_min, unsigned pd_max, |
||
1192 | unsigned pd_even, |
||
1193 | unsigned *optimal_fb_div, |
||
1194 | unsigned *optimal_vclk_div, |
||
1195 | unsigned *optimal_dclk_div); |
||
1196 | int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev, |
||
1197 | unsigned cg_upll_func_cntl); |
||
1198 | |||
2997 | Serge | 1199 | struct r600_audio { |
1200 | int channels; |
||
1201 | int rate; |
||
1202 | int bits_per_sample; |
||
1203 | u8 status_bits; |
||
1204 | u8 category_code; |
||
1205 | }; |
||
1117 | serge | 1206 | /* |
1207 | * ASIC specific functions. |
||
1208 | */ |
||
1209 | struct radeon_asic { |
||
1210 | int (*init)(struct radeon_device *rdev); |
||
1179 | serge | 1211 | void (*fini)(struct radeon_device *rdev); |
1212 | int (*resume)(struct radeon_device *rdev); |
||
1213 | int (*suspend)(struct radeon_device *rdev); |
||
1214 | void (*vga_set_state)(struct radeon_device *rdev, bool state); |
||
1963 | serge | 1215 | int (*asic_reset)(struct radeon_device *rdev); |
2997 | Serge | 1216 | /* ioctl hw specific callback. Some hw might want to perform special |
1217 | * operation on specific ioctl. For instance on wait idle some hw |
||
1218 | * might want to perform and HDP flush through MMIO as it seems that |
||
1219 | * some R6XX/R7XX hw doesn't take HDP flush into account if programmed |
||
1220 | * through ring. |
||
1221 | */ |
||
1222 | void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo); |
||
1223 | /* check if 3D engine is idle */ |
||
1224 | bool (*gui_idle)(struct radeon_device *rdev); |
||
1225 | /* wait for mc_idle */ |
||
1226 | int (*mc_wait_for_idle)(struct radeon_device *rdev); |
||
3764 | Serge | 1227 | /* get the reference clock */ |
1228 | u32 (*get_xclk)(struct radeon_device *rdev); |
||
1229 | /* get the gpu clock counter */ |
||
1230 | uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev); |
||
2997 | Serge | 1231 | /* gart */ |
1232 | struct { |
||
1233 | void (*tlb_flush)(struct radeon_device *rdev); |
||
1234 | int (*set_page)(struct radeon_device *rdev, int i, uint64_t addr); |
||
1235 | } gart; |
||
1236 | struct { |
||
1237 | int (*init)(struct radeon_device *rdev); |
||
1238 | void (*fini)(struct radeon_device *rdev); |
||
1239 | |||
1240 | u32 pt_ring_index; |
||
3764 | Serge | 1241 | void (*set_page)(struct radeon_device *rdev, |
1242 | struct radeon_ib *ib, |
||
1243 | uint64_t pe, |
||
2997 | Serge | 1244 | uint64_t addr, unsigned count, |
1245 | uint32_t incr, uint32_t flags); |
||
1246 | } vm; |
||
1247 | /* ring specific callbacks */ |
||
1248 | struct { |
||
1249 | void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib); |
||
1250 | int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib); |
||
1251 | void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence); |
||
1252 | void (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp, |
||
1253 | struct radeon_semaphore *semaphore, bool emit_wait); |
||
1254 | int (*cs_parse)(struct radeon_cs_parser *p); |
||
1255 | void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp); |
||
1256 | int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp); |
||
1257 | int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp); |
||
1258 | bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp); |
||
1259 | void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); |
||
1260 | } ring[RADEON_NUM_RINGS]; |
||
1261 | /* irqs */ |
||
1262 | struct { |
||
1263 | int (*set)(struct radeon_device *rdev); |
||
1264 | int (*process)(struct radeon_device *rdev); |
||
1265 | } irq; |
||
1266 | /* displays */ |
||
1267 | struct { |
||
1268 | /* display watermarks */ |
||
1269 | void (*bandwidth_update)(struct radeon_device *rdev); |
||
1270 | /* get frame count */ |
||
1179 | serge | 1271 | u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc); |
2997 | Serge | 1272 | /* wait for vblank */ |
1273 | void (*wait_for_vblank)(struct radeon_device *rdev, int crtc); |
||
1274 | /* set backlight level */ |
||
1275 | void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level); |
||
1276 | /* get backlight level */ |
||
1277 | u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder); |
||
3764 | Serge | 1278 | /* audio callbacks */ |
1279 | void (*hdmi_enable)(struct drm_encoder *encoder, bool enable); |
||
1280 | void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode); |
||
2997 | Serge | 1281 | } display; |
1282 | /* copy functions for bo handling */ |
||
1283 | struct { |
||
1284 | int (*blit)(struct radeon_device *rdev, |
||
1117 | serge | 1285 | uint64_t src_offset, |
1286 | uint64_t dst_offset, |
||
2997 | Serge | 1287 | unsigned num_gpu_pages, |
1288 | struct radeon_fence **fence); |
||
1289 | u32 blit_ring_index; |
||
1290 | int (*dma)(struct radeon_device *rdev, |
||
1117 | serge | 1291 | uint64_t src_offset, |
1292 | uint64_t dst_offset, |
||
2997 | Serge | 1293 | unsigned num_gpu_pages, |
1294 | struct radeon_fence **fence); |
||
1295 | u32 dma_ring_index; |
||
1296 | /* method used for bo copy */ |
||
1117 | serge | 1297 | int (*copy)(struct radeon_device *rdev, |
1298 | uint64_t src_offset, |
||
1299 | uint64_t dst_offset, |
||
2997 | Serge | 1300 | unsigned num_gpu_pages, |
1301 | struct radeon_fence **fence); |
||
1302 | /* ring used for bo copies */ |
||
1303 | u32 copy_ring_index; |
||
1304 | } copy; |
||
1305 | /* surfaces */ |
||
1306 | struct { |
||
1307 | int (*set_reg)(struct radeon_device *rdev, int reg, |
||
1308 | uint32_t tiling_flags, uint32_t pitch, |
||
1309 | uint32_t offset, uint32_t obj_size); |
||
1310 | void (*clear_reg)(struct radeon_device *rdev, int reg); |
||
1311 | } surface; |
||
1312 | /* hotplug detect */ |
||
1313 | struct { |
||
1314 | void (*init)(struct radeon_device *rdev); |
||
1315 | void (*fini)(struct radeon_device *rdev); |
||
1316 | bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd); |
||
1317 | void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd); |
||
1318 | } hpd; |
||
1319 | /* power management */ |
||
1320 | struct { |
||
1321 | void (*misc)(struct radeon_device *rdev); |
||
1322 | void (*prepare)(struct radeon_device *rdev); |
||
1323 | void (*finish)(struct radeon_device *rdev); |
||
1324 | void (*init_profile)(struct radeon_device *rdev); |
||
1325 | void (*get_dynpm_state)(struct radeon_device *rdev); |
||
1268 | serge | 1326 | uint32_t (*get_engine_clock)(struct radeon_device *rdev); |
1117 | serge | 1327 | void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); |
1268 | serge | 1328 | uint32_t (*get_memory_clock)(struct radeon_device *rdev); |
1117 | serge | 1329 | void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock); |
1430 | serge | 1330 | int (*get_pcie_lanes)(struct radeon_device *rdev); |
1117 | serge | 1331 | void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); |
1332 | void (*set_clock_gating)(struct radeon_device *rdev, int enable); |
||
3764 | Serge | 1333 | int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk); |
2997 | Serge | 1334 | } pm; |
1963 | serge | 1335 | /* pageflipping */ |
2997 | Serge | 1336 | struct { |
1963 | serge | 1337 | void (*pre_page_flip)(struct radeon_device *rdev, int crtc); |
1338 | u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base); |
||
1339 | void (*post_page_flip)(struct radeon_device *rdev, int crtc); |
||
2997 | Serge | 1340 | } pflip; |
1117 | serge | 1341 | }; |
1342 | |||
1179 | serge | 1343 | /* |
1344 | * Asic structures |
||
1345 | */ |
||
1346 | struct r100_asic { |
||
1347 | const unsigned *reg_safe_bm; |
||
1348 | unsigned reg_safe_bm_size; |
||
1403 | serge | 1349 | u32 hdp_cntl; |
1179 | serge | 1350 | }; |
1351 | |||
1352 | struct r300_asic { |
||
1353 | const unsigned *reg_safe_bm; |
||
1354 | unsigned reg_safe_bm_size; |
||
1403 | serge | 1355 | u32 resync_scratch; |
1356 | u32 hdp_cntl; |
||
1179 | serge | 1357 | }; |
1358 | |||
1359 | struct r600_asic { |
||
1360 | unsigned max_pipes; |
||
1361 | unsigned max_tile_pipes; |
||
1362 | unsigned max_simds; |
||
1363 | unsigned max_backends; |
||
1364 | unsigned max_gprs; |
||
1365 | unsigned max_threads; |
||
1366 | unsigned max_stack_entries; |
||
1367 | unsigned max_hw_contexts; |
||
1368 | unsigned max_gs_threads; |
||
1369 | unsigned sx_max_export_size; |
||
1370 | unsigned sx_max_export_pos_size; |
||
1371 | unsigned sx_max_export_smx_size; |
||
1372 | unsigned sq_num_cf_insts; |
||
1430 | serge | 1373 | unsigned tiling_nbanks; |
1374 | unsigned tiling_npipes; |
||
1375 | unsigned tiling_group_size; |
||
1963 | serge | 1376 | unsigned tile_config; |
2160 | serge | 1377 | unsigned backend_map; |
1179 | serge | 1378 | }; |
1379 | |||
1380 | struct rv770_asic { |
||
1381 | unsigned max_pipes; |
||
1382 | unsigned max_tile_pipes; |
||
1383 | unsigned max_simds; |
||
1384 | unsigned max_backends; |
||
1385 | unsigned max_gprs; |
||
1386 | unsigned max_threads; |
||
1387 | unsigned max_stack_entries; |
||
1388 | unsigned max_hw_contexts; |
||
1389 | unsigned max_gs_threads; |
||
1390 | unsigned sx_max_export_size; |
||
1391 | unsigned sx_max_export_pos_size; |
||
1392 | unsigned sx_max_export_smx_size; |
||
1393 | unsigned sq_num_cf_insts; |
||
1394 | unsigned sx_num_of_sets; |
||
1395 | unsigned sc_prim_fifo_size; |
||
1396 | unsigned sc_hiz_tile_fifo_size; |
||
1397 | unsigned sc_earlyz_tile_fifo_fize; |
||
1430 | serge | 1398 | unsigned tiling_nbanks; |
1399 | unsigned tiling_npipes; |
||
1400 | unsigned tiling_group_size; |
||
1963 | serge | 1401 | unsigned tile_config; |
2160 | serge | 1402 | unsigned backend_map; |
1179 | serge | 1403 | }; |
1404 | |||
1963 | serge | 1405 | struct evergreen_asic { |
1406 | unsigned num_ses; |
||
1407 | unsigned max_pipes; |
||
1408 | unsigned max_tile_pipes; |
||
1409 | unsigned max_simds; |
||
1410 | unsigned max_backends; |
||
1411 | unsigned max_gprs; |
||
1412 | unsigned max_threads; |
||
1413 | unsigned max_stack_entries; |
||
1414 | unsigned max_hw_contexts; |
||
1415 | unsigned max_gs_threads; |
||
1416 | unsigned sx_max_export_size; |
||
1417 | unsigned sx_max_export_pos_size; |
||
1418 | unsigned sx_max_export_smx_size; |
||
1419 | unsigned sq_num_cf_insts; |
||
1420 | unsigned sx_num_of_sets; |
||
1421 | unsigned sc_prim_fifo_size; |
||
1422 | unsigned sc_hiz_tile_fifo_size; |
||
1423 | unsigned sc_earlyz_tile_fifo_size; |
||
1424 | unsigned tiling_nbanks; |
||
1425 | unsigned tiling_npipes; |
||
1426 | unsigned tiling_group_size; |
||
1427 | unsigned tile_config; |
||
2160 | serge | 1428 | unsigned backend_map; |
1963 | serge | 1429 | }; |
1430 | |||
1431 | struct cayman_asic { |
||
1432 | unsigned max_shader_engines; |
||
1433 | unsigned max_pipes_per_simd; |
||
1434 | unsigned max_tile_pipes; |
||
1435 | unsigned max_simds_per_se; |
||
1436 | unsigned max_backends_per_se; |
||
1437 | unsigned max_texture_channel_caches; |
||
1438 | unsigned max_gprs; |
||
1439 | unsigned max_threads; |
||
1440 | unsigned max_gs_threads; |
||
1441 | unsigned max_stack_entries; |
||
1442 | unsigned sx_num_of_sets; |
||
1443 | unsigned sx_max_export_size; |
||
1444 | unsigned sx_max_export_pos_size; |
||
1445 | unsigned sx_max_export_smx_size; |
||
1446 | unsigned max_hw_contexts; |
||
1447 | unsigned sq_num_cf_insts; |
||
1448 | unsigned sc_prim_fifo_size; |
||
1449 | unsigned sc_hiz_tile_fifo_size; |
||
1450 | unsigned sc_earlyz_tile_fifo_size; |
||
1451 | |||
1452 | unsigned num_shader_engines; |
||
1453 | unsigned num_shader_pipes_per_simd; |
||
1454 | unsigned num_tile_pipes; |
||
1455 | unsigned num_simds_per_se; |
||
1456 | unsigned num_backends_per_se; |
||
1457 | unsigned backend_disable_mask_per_asic; |
||
1458 | unsigned backend_map; |
||
1459 | unsigned num_texture_channel_caches; |
||
1460 | unsigned mem_max_burst_length_bytes; |
||
1461 | unsigned mem_row_size_in_kb; |
||
1462 | unsigned shader_engine_tile_size; |
||
1463 | unsigned num_gpus; |
||
1464 | unsigned multi_gpu_tile_size; |
||
1465 | |||
1466 | unsigned tile_config; |
||
1467 | }; |
||
1468 | |||
2997 | Serge | 1469 | struct si_asic { |
1470 | unsigned max_shader_engines; |
||
1471 | unsigned max_tile_pipes; |
||
1472 | unsigned max_cu_per_sh; |
||
1473 | unsigned max_sh_per_se; |
||
1474 | unsigned max_backends_per_se; |
||
1475 | unsigned max_texture_channel_caches; |
||
1476 | unsigned max_gprs; |
||
1477 | unsigned max_gs_threads; |
||
1478 | unsigned max_hw_contexts; |
||
1479 | unsigned sc_prim_fifo_size_frontend; |
||
1480 | unsigned sc_prim_fifo_size_backend; |
||
1481 | unsigned sc_hiz_tile_fifo_size; |
||
1482 | unsigned sc_earlyz_tile_fifo_size; |
||
1483 | |||
1484 | unsigned num_tile_pipes; |
||
1485 | unsigned num_backends_per_se; |
||
1486 | unsigned backend_disable_mask_per_asic; |
||
1487 | unsigned backend_map; |
||
1488 | unsigned num_texture_channel_caches; |
||
1489 | unsigned mem_max_burst_length_bytes; |
||
1490 | unsigned mem_row_size_in_kb; |
||
1491 | unsigned shader_engine_tile_size; |
||
1492 | unsigned num_gpus; |
||
1493 | unsigned multi_gpu_tile_size; |
||
1494 | |||
1495 | unsigned tile_config; |
||
3764 | Serge | 1496 | uint32_t tile_mode_array[32]; |
2997 | Serge | 1497 | }; |
1498 | |||
1117 | serge | 1499 | union radeon_asic_config { |
1500 | struct r300_asic r300; |
||
1179 | serge | 1501 | struct r100_asic r100; |
1502 | struct r600_asic r600; |
||
1503 | struct rv770_asic rv770; |
||
1963 | serge | 1504 | struct evergreen_asic evergreen; |
1505 | struct cayman_asic cayman; |
||
2997 | Serge | 1506 | struct si_asic si; |
1117 | serge | 1507 | }; |
1508 | |||
1509 | /* |
||
1963 | serge | 1510 | * asic initizalization from radeon_asic.c |
1511 | */ |
||
1512 | void radeon_agp_disable(struct radeon_device *rdev); |
||
1513 | int radeon_asic_init(struct radeon_device *rdev); |
||
1179 | serge | 1514 | |
1515 | |||
1516 | |||
2997 | Serge | 1517 | /* VRAM scratch page for HDP bug, default vram page */ |
1518 | struct r600_vram_scratch { |
||
1963 | serge | 1519 | struct radeon_bo *robj; |
1520 | volatile uint32_t *ptr; |
||
2997 | Serge | 1521 | u64 gpu_addr; |
1963 | serge | 1522 | }; |
1179 | serge | 1523 | |
2997 | Serge | 1524 | |
1117 | serge | 1525 | /* |
1526 | * Core structure, functions and helpers. |
||
1527 | */ |
||
1528 | typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t); |
||
1529 | typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t); |
||
1530 | |||
1531 | struct radeon_device { |
||
2997 | Serge | 1532 | struct device *dev; |
1117 | serge | 1533 | struct drm_device *ddev; |
1534 | struct pci_dev *pdev; |
||
2997 | Serge | 1535 | struct rw_semaphore exclusive_lock; |
1117 | serge | 1536 | /* ASIC */ |
1537 | union radeon_asic_config config; |
||
1538 | enum radeon_family family; |
||
1539 | unsigned long flags; |
||
1540 | int usec_timeout; |
||
1541 | enum radeon_pll_errata pll_errata; |
||
1542 | int num_gb_pipes; |
||
1413 | serge | 1543 | int num_z_pipes; |
1117 | serge | 1544 | int disp_priority; |
1545 | /* BIOS */ |
||
1546 | uint8_t *bios; |
||
1547 | bool is_atom_bios; |
||
1548 | uint16_t bios_header_start; |
||
1413 | serge | 1549 | struct radeon_bo *stollen_vga_memory; |
1117 | serge | 1550 | /* Register mmio */ |
1963 | serge | 1551 | resource_size_t rmmio_base; |
1552 | resource_size_t rmmio_size; |
||
3192 | Serge | 1553 | /* protects concurrent MM_INDEX/DATA based register access */ |
1554 | spinlock_t mmio_idx_lock; |
||
2997 | Serge | 1555 | void __iomem *rmmio; |
1120 | serge | 1556 | radeon_rreg_t mc_rreg; |
1557 | radeon_wreg_t mc_wreg; |
||
1558 | radeon_rreg_t pll_rreg; |
||
1559 | radeon_wreg_t pll_wreg; |
||
1179 | serge | 1560 | uint32_t pcie_reg_mask; |
1120 | serge | 1561 | radeon_rreg_t pciep_rreg; |
1562 | radeon_wreg_t pciep_wreg; |
||
1963 | serge | 1563 | /* io port */ |
1564 | void __iomem *rio_mem; |
||
1565 | resource_size_t rio_mem_size; |
||
1120 | serge | 1566 | struct radeon_clock clock; |
1117 | serge | 1567 | struct radeon_mc mc; |
1568 | struct radeon_gart gart; |
||
1569 | struct radeon_mode_info mode_info; |
||
1570 | struct radeon_scratch scratch; |
||
1321 | serge | 1571 | struct radeon_mman mman; |
2997 | Serge | 1572 | struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS]; |
1573 | wait_queue_head_t fence_queue; |
||
1574 | struct mutex ring_lock; |
||
1575 | struct radeon_ring ring[RADEON_NUM_RINGS]; |
||
1576 | bool ib_pool_ready; |
||
1577 | struct radeon_sa_manager ring_tmp_bo; |
||
1963 | serge | 1578 | struct radeon_irq irq; |
1117 | serge | 1579 | struct radeon_asic *asic; |
1126 | serge | 1580 | struct radeon_gem gem; |
1179 | serge | 1581 | struct radeon_pm pm; |
3764 | Serge | 1582 | struct radeon_uvd uvd; |
1179 | serge | 1583 | uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH]; |
1117 | serge | 1584 | struct radeon_wb wb; |
1179 | serge | 1585 | struct radeon_dummy_page dummy_page; |
1117 | serge | 1586 | bool shutdown; |
1587 | bool suspend; |
||
1179 | serge | 1588 | bool need_dma32; |
1589 | bool accel_working; |
||
3764 | Serge | 1590 | bool fastfb_working; /* IGP feature*/ |
1179 | serge | 1591 | struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; |
1592 | const struct firmware *me_fw; /* all family ME firmware */ |
||
1593 | const struct firmware *pfp_fw; /* r6/700 PFP firmware */ |
||
1403 | serge | 1594 | const struct firmware *rlc_fw; /* r6/700 RLC firmware */ |
1963 | serge | 1595 | const struct firmware *mc_fw; /* NI MC firmware */ |
2997 | Serge | 1596 | const struct firmware *ce_fw; /* SI CE firmware */ |
3764 | Serge | 1597 | const struct firmware *uvd_fw; /* UVD firmware */ |
1179 | serge | 1598 | struct r600_blit r600_blit; |
2997 | Serge | 1599 | struct r600_vram_scratch vram_scratch; |
1268 | serge | 1600 | int msi_enabled; /* msi enabled */ |
2004 | serge | 1601 | struct r600_ih ih; /* r6/700 interrupt ring */ |
2997 | Serge | 1602 | struct si_rlc rlc; |
1963 | serge | 1603 | // struct work_struct hotplug_work; |
2997 | Serge | 1604 | // struct work_struct audio_work; |
1430 | serge | 1605 | int num_crtc; /* number of crtcs */ |
1630 | serge | 1606 | struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */ |
1963 | serge | 1607 | bool audio_enabled; |
3764 | Serge | 1608 | bool has_uvd; |
2997 | Serge | 1609 | // struct r600_audio audio_status; /* audio stuff */ |
1610 | // struct notifier_block acpi_nb; |
||
1611 | /* only one userspace can use Hyperz features or CMASK at a time */ |
||
1612 | // struct drm_file *hyperz_filp; |
||
1613 | // struct drm_file *cmask_filp; |
||
1963 | serge | 1614 | /* i2c buses */ |
1615 | struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS]; |
||
2997 | Serge | 1616 | /* debugfs */ |
1617 | // struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS]; |
||
1618 | unsigned debugfs_count; |
||
1619 | /* virtual memory */ |
||
1620 | struct radeon_vm_manager vm_manager; |
||
1621 | struct mutex gpu_clock_mutex; |
||
1622 | /* ACPI interface */ |
||
1623 | // struct radeon_atif atif; |
||
1624 | // struct radeon_atcs atcs; |
||
1117 | serge | 1625 | }; |
1626 | |||
1627 | int radeon_device_init(struct radeon_device *rdev, |
||
1628 | struct drm_device *ddev, |
||
1629 | struct pci_dev *pdev, |
||
1630 | uint32_t flags); |
||
1631 | void radeon_device_fini(struct radeon_device *rdev); |
||
1632 | int radeon_gpu_wait_for_idle(struct radeon_device *rdev); |
||
1633 | |||
3192 | Serge | 1634 | uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg, |
1635 | bool always_indirect); |
||
1636 | void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v, |
||
1637 | bool always_indirect); |
||
2997 | Serge | 1638 | u32 r100_io_rreg(struct radeon_device *rdev, u32 reg); |
1639 | void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v); |
||
1117 | serge | 1640 | |
1321 | serge | 1641 | /* |
1642 | * Cast helper |
||
1643 | */ |
||
1644 | #define to_radeon_fence(p) ((struct radeon_fence *)(p)) |
||
1117 | serge | 1645 | |
1646 | /* |
||
1647 | * Registers read & write functions. |
||
1648 | */ |
||
2997 | Serge | 1649 | #define RREG8(reg) readb((rdev->rmmio) + (reg)) |
1650 | #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg)) |
||
1651 | #define RREG16(reg) readw((rdev->rmmio) + (reg)) |
||
1652 | #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg)) |
||
3192 | Serge | 1653 | #define RREG32(reg) r100_mm_rreg(rdev, (reg), false) |
1654 | #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true) |
||
1655 | #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false)) |
||
1656 | #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false) |
||
1657 | #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true) |
||
1117 | serge | 1658 | #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) |
1659 | #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) |
||
1660 | #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg)) |
||
1661 | #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v)) |
||
1662 | #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg)) |
||
1663 | #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) |
||
1179 | serge | 1664 | #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) |
1665 | #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) |
||
3764 | Serge | 1666 | #define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg)) |
1667 | #define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v)) |
||
1117 | serge | 1668 | #define WREG32_P(reg, val, mask) \ |
1669 | do { \ |
||
1670 | uint32_t tmp_ = RREG32(reg); \ |
||
1671 | tmp_ &= (mask); \ |
||
1672 | tmp_ |= ((val) & ~(mask)); \ |
||
1673 | WREG32(reg, tmp_); \ |
||
1674 | } while (0) |
||
3764 | Serge | 1675 | #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) |
1676 | #define WREG32_OR(reg, or) WREG32_P(reg, or, ~or) |
||
1117 | serge | 1677 | #define WREG32_PLL_P(reg, val, mask) \ |
1678 | do { \ |
||
1679 | uint32_t tmp_ = RREG32_PLL(reg); \ |
||
1680 | tmp_ &= (mask); \ |
||
1681 | tmp_ |= ((val) & ~(mask)); \ |
||
1682 | WREG32_PLL(reg, tmp_); \ |
||
1683 | } while (0) |
||
1963 | serge | 1684 | #define RREG32_IO(reg) r100_io_rreg(rdev, (reg)) |
1685 | #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v)) |
||
1117 | serge | 1686 | |
1179 | serge | 1687 | /* |
1688 | * Indirect registers accessor |
||
1689 | */ |
||
1690 | static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg) |
||
1691 | { |
||
1692 | uint32_t r; |
||
1117 | serge | 1693 | |
1179 | serge | 1694 | WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); |
1695 | r = RREG32(RADEON_PCIE_DATA); |
||
1696 | return r; |
||
1697 | } |
||
1698 | |||
1699 | static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
||
1700 | { |
||
1701 | WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); |
||
1702 | WREG32(RADEON_PCIE_DATA, (v)); |
||
1703 | } |
||
1704 | |||
1705 | void r100_pll_errata_after_index(struct radeon_device *rdev); |
||
1706 | |||
1707 | |||
1117 | serge | 1708 | /* |
1709 | * ASICs helpers. |
||
1710 | */ |
||
1179 | serge | 1711 | #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \ |
1712 | (rdev->pdev->device == 0x5969)) |
||
1117 | serge | 1713 | #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \ |
1714 | (rdev->family == CHIP_RV200) || \ |
||
1715 | (rdev->family == CHIP_RS100) || \ |
||
1716 | (rdev->family == CHIP_RS200) || \ |
||
1717 | (rdev->family == CHIP_RV250) || \ |
||
1718 | (rdev->family == CHIP_RV280) || \ |
||
1719 | (rdev->family == CHIP_RS300)) |
||
1720 | #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \ |
||
1721 | (rdev->family == CHIP_RV350) || \ |
||
1722 | (rdev->family == CHIP_R350) || \ |
||
1723 | (rdev->family == CHIP_RV380) || \ |
||
1724 | (rdev->family == CHIP_R420) || \ |
||
1725 | (rdev->family == CHIP_R423) || \ |
||
1726 | (rdev->family == CHIP_RV410) || \ |
||
1727 | (rdev->family == CHIP_RS400) || \ |
||
1728 | (rdev->family == CHIP_RS480)) |
||
1963 | serge | 1729 | #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \ |
1730 | (rdev->ddev->pdev->device == 0x9443) || \ |
||
1731 | (rdev->ddev->pdev->device == 0x944B) || \ |
||
1732 | (rdev->ddev->pdev->device == 0x9506) || \ |
||
1733 | (rdev->ddev->pdev->device == 0x9509) || \ |
||
1734 | (rdev->ddev->pdev->device == 0x950F) || \ |
||
1735 | (rdev->ddev->pdev->device == 0x689C) || \ |
||
1736 | (rdev->ddev->pdev->device == 0x689D)) |
||
1117 | serge | 1737 | #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) |
1963 | serge | 1738 | #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \ |
1739 | (rdev->family == CHIP_RS690) || \ |
||
1740 | (rdev->family == CHIP_RS740) || \ |
||
1741 | (rdev->family >= CHIP_R600)) |
||
1117 | serge | 1742 | #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) |
1743 | #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) |
||
1430 | serge | 1744 | #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR)) |
1963 | serge | 1745 | #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \ |
1746 | (rdev->flags & RADEON_IS_IGP)) |
||
1747 | #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS)) |
||
2997 | Serge | 1748 | #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA)) |
1749 | #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \ |
||
1750 | (rdev->flags & RADEON_IS_IGP)) |
||
3764 | Serge | 1751 | #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND)) |
1752 | #define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN)) |
||
1117 | serge | 1753 | |
1754 | /* |
||
1755 | * BIOS helpers. |
||
1756 | */ |
||
1757 | #define RBIOS8(i) (rdev->bios[i]) |
||
1758 | #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) |
||
1759 | #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) |
||
1760 | |||
1761 | int radeon_combios_init(struct radeon_device *rdev); |
||
1762 | void radeon_combios_fini(struct radeon_device *rdev); |
||
1763 | int radeon_atombios_init(struct radeon_device *rdev); |
||
1764 | void radeon_atombios_fini(struct radeon_device *rdev); |
||
1765 | |||
1766 | |||
1767 | /* |
||
1768 | * RING helpers. |
||
1769 | */ |
||
2997 | Serge | 1770 | #if DRM_DEBUG_CODE == 0 |
1771 | static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v) |
||
1117 | serge | 1772 | { |
2997 | Serge | 1773 | ring->ring[ring->wptr++] = v; |
1774 | ring->wptr &= ring->ptr_mask; |
||
1775 | ring->count_dw--; |
||
1776 | ring->ring_free_dw--; |
||
1777 | } |
||
1778 | #else |
||
1779 | /* With debugging this is just too big to inline */ |
||
1780 | void radeon_ring_write(struct radeon_ring *ring, uint32_t v); |
||
1117 | serge | 1781 | #endif |
1782 | |||
1783 | /* |
||
1784 | * ASICs macro. |
||
1785 | */ |
||
1786 | #define radeon_init(rdev) (rdev)->asic->init((rdev)) |
||
1179 | serge | 1787 | #define radeon_fini(rdev) (rdev)->asic->fini((rdev)) |
1788 | #define radeon_resume(rdev) (rdev)->asic->resume((rdev)) |
||
1789 | #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) |
||
2997 | Serge | 1790 | #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)].cs_parse((p)) |
1179 | serge | 1791 | #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state)) |
1963 | serge | 1792 | #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev)) |
2997 | Serge | 1793 | #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev)) |
1794 | #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p)) |
||
1795 | #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev)) |
||
1796 | #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev)) |
||
3764 | Serge | 1797 | #define radeon_asic_vm_set_page(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_page((rdev), (ib), (pe), (addr), (count), (incr), (flags))) |
2997 | Serge | 1798 | #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)].ring_start((rdev), (cp)) |
1799 | #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)].ring_test((rdev), (cp)) |
||
1800 | #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)].ib_test((rdev), (cp)) |
||
1801 | #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)].ib_execute((rdev), (ib)) |
||
1802 | #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)].ib_parse((rdev), (ib)) |
||
1803 | #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)].is_lockup((rdev), (cp)) |
||
1804 | #define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)].vm_flush((rdev), (r), (vm)) |
||
1805 | #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev)) |
||
1806 | #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev)) |
||
1807 | #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc)) |
||
1808 | #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l)) |
||
1809 | #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e)) |
||
3764 | Serge | 1810 | #define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b)) |
1811 | #define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m)) |
||
2997 | Serge | 1812 | #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)].emit_fence((rdev), (fence)) |
1813 | #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)].emit_semaphore((rdev), (cp), (semaphore), (emit_wait)) |
||
1814 | #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f)) |
||
1815 | #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f)) |
||
1816 | #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f)) |
||
1817 | #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index |
||
1818 | #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index |
||
1819 | #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index |
||
1820 | #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev)) |
||
1821 | #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e)) |
||
1822 | #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev)) |
||
1823 | #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e)) |
||
1824 | #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev)) |
||
1825 | #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l)) |
||
1826 | #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e)) |
||
3764 | Serge | 1827 | #define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d)) |
2997 | Serge | 1828 | #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s))) |
1829 | #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r))) |
||
1830 | #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev)) |
||
1831 | #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev)) |
||
1832 | #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev)) |
||
1833 | #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h)) |
||
1834 | #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h)) |
||
1963 | serge | 1835 | #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev)) |
2997 | Serge | 1836 | #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev)) |
1837 | #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev)) |
||
1838 | #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev)) |
||
1839 | #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev)) |
||
1840 | #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev)) |
||
1841 | #define radeon_pre_page_flip(rdev, crtc) (rdev)->asic->pflip.pre_page_flip((rdev), (crtc)) |
||
1842 | #define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base)) |
||
1843 | #define radeon_post_page_flip(rdev, crtc) (rdev)->asic->pflip.post_page_flip((rdev), (crtc)) |
||
1844 | #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc)) |
||
1845 | #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev)) |
||
3764 | Serge | 1846 | #define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev)) |
1847 | #define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev)) |
||
1117 | serge | 1848 | |
1179 | serge | 1849 | /* Common functions */ |
1403 | serge | 1850 | /* AGP */ |
1963 | serge | 1851 | extern int radeon_gpu_reset(struct radeon_device *rdev); |
3764 | Serge | 1852 | extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung); |
1403 | serge | 1853 | extern void radeon_agp_disable(struct radeon_device *rdev); |
1179 | serge | 1854 | extern int radeon_modeset_init(struct radeon_device *rdev); |
1855 | extern void radeon_modeset_fini(struct radeon_device *rdev); |
||
1856 | extern bool radeon_card_posted(struct radeon_device *rdev); |
||
1963 | serge | 1857 | extern void radeon_update_bandwidth_info(struct radeon_device *rdev); |
1858 | extern void radeon_update_display_priority(struct radeon_device *rdev); |
||
1321 | serge | 1859 | extern bool radeon_boot_test_post_card(struct radeon_device *rdev); |
1179 | serge | 1860 | extern void radeon_scratch_init(struct radeon_device *rdev); |
1963 | serge | 1861 | extern void radeon_wb_fini(struct radeon_device *rdev); |
1862 | extern int radeon_wb_init(struct radeon_device *rdev); |
||
1863 | extern void radeon_wb_disable(struct radeon_device *rdev); |
||
1179 | serge | 1864 | extern void radeon_surface_init(struct radeon_device *rdev); |
1865 | extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); |
||
1221 | serge | 1866 | extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); |
1867 | extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); |
||
1321 | serge | 1868 | extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain); |
1403 | serge | 1869 | extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo); |
1430 | serge | 1870 | extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base); |
1871 | extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); |
||
1872 | extern int radeon_resume_kms(struct drm_device *dev); |
||
1873 | extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state); |
||
1963 | serge | 1874 | extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size); |
3764 | Serge | 1875 | extern void radeon_program_register_sequence(struct radeon_device *rdev, |
1876 | const u32 *registers, |
||
1877 | const u32 array_size); |
||
1117 | serge | 1878 | |
1963 | serge | 1879 | /* |
2997 | Serge | 1880 | * vm |
1881 | */ |
||
1882 | int radeon_vm_manager_init(struct radeon_device *rdev); |
||
1883 | void radeon_vm_manager_fini(struct radeon_device *rdev); |
||
1884 | void radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm); |
||
1885 | void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm); |
||
1886 | int radeon_vm_alloc_pt(struct radeon_device *rdev, struct radeon_vm *vm); |
||
1887 | void radeon_vm_add_to_lru(struct radeon_device *rdev, struct radeon_vm *vm); |
||
1888 | struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev, |
||
1889 | struct radeon_vm *vm, int ring); |
||
1890 | void radeon_vm_fence(struct radeon_device *rdev, |
||
1891 | struct radeon_vm *vm, |
||
1892 | struct radeon_fence *fence); |
||
1893 | uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr); |
||
1894 | int radeon_vm_bo_update_pte(struct radeon_device *rdev, |
||
1895 | struct radeon_vm *vm, |
||
1896 | struct radeon_bo *bo, |
||
1897 | struct ttm_mem_reg *mem); |
||
1898 | void radeon_vm_bo_invalidate(struct radeon_device *rdev, |
||
1899 | struct radeon_bo *bo); |
||
1900 | struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm, |
||
1901 | struct radeon_bo *bo); |
||
1902 | struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev, |
||
1903 | struct radeon_vm *vm, |
||
1904 | struct radeon_bo *bo); |
||
1905 | int radeon_vm_bo_set_addr(struct radeon_device *rdev, |
||
1906 | struct radeon_bo_va *bo_va, |
||
1907 | uint64_t offset, |
||
1908 | uint32_t flags); |
||
1909 | int radeon_vm_bo_rmv(struct radeon_device *rdev, |
||
1910 | struct radeon_bo_va *bo_va); |
||
1911 | |||
1912 | /* audio */ |
||
1913 | void r600_audio_update_hdmi(struct work_struct *work); |
||
1914 | |||
1915 | /* |
||
1916 | * R600 vram scratch functions |
||
1917 | */ |
||
1918 | int r600_vram_scratch_init(struct radeon_device *rdev); |
||
1919 | void r600_vram_scratch_fini(struct radeon_device *rdev); |
||
1920 | |||
1921 | /* |
||
1922 | * r600 cs checking helper |
||
1923 | */ |
||
1924 | unsigned r600_mip_minify(unsigned size, unsigned level); |
||
1925 | bool r600_fmt_is_valid_color(u32 format); |
||
1926 | bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family); |
||
1927 | int r600_fmt_get_blocksize(u32 format); |
||
1928 | int r600_fmt_get_nblocksx(u32 format, u32 w); |
||
1929 | int r600_fmt_get_nblocksy(u32 format, u32 h); |
||
1930 | |||
1931 | /* |
||
1963 | serge | 1932 | * r600 functions used by radeon_encoder.c |
1933 | */ |
||
2997 | Serge | 1934 | struct radeon_hdmi_acr { |
1935 | u32 clock; |
||
1936 | |||
1937 | int n_32khz; |
||
1938 | int cts_32khz; |
||
1939 | |||
1940 | int n_44_1khz; |
||
1941 | int cts_44_1khz; |
||
1942 | |||
1943 | int n_48khz; |
||
1944 | int cts_48khz; |
||
1945 | |||
1946 | }; |
||
1947 | |||
1948 | extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock); |
||
1949 | |||
1950 | extern u32 r6xx_remap_render_backend(struct radeon_device *rdev, |
||
1951 | u32 tiling_pipe_num, |
||
1952 | u32 max_rb_num, |
||
1953 | u32 total_max_rb_num, |
||
1954 | u32 enabled_rb_mask); |
||
1179 | serge | 1955 | |
2997 | Serge | 1956 | /* |
1957 | * evergreen functions used by radeon_encoder.c |
||
1958 | */ |
||
1959 | |||
1963 | serge | 1960 | extern int ni_init_microcode(struct radeon_device *rdev); |
1961 | extern int ni_mc_load_microcode(struct radeon_device *rdev); |
||
1221 | serge | 1962 | |
1963 | serge | 1963 | /* radeon_acpi.c */ |
1964 | #if defined(CONFIG_ACPI) |
||
1965 | extern int radeon_acpi_init(struct radeon_device *rdev); |
||
2997 | Serge | 1966 | extern void radeon_acpi_fini(struct radeon_device *rdev); |
1963 | serge | 1967 | #else |
1968 | static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; } |
||
2997 | Serge | 1969 | static inline void radeon_acpi_fini(struct radeon_device *rdev) { } |
1963 | serge | 1970 | #endif |
1179 | serge | 1971 | |
1321 | serge | 1972 | #include "radeon_object.h" |
1179 | serge | 1973 | |
1117 | serge | 1974 | #define DRM_UDELAY(d) udelay(d) |
1975 | |||
1976 | resource_size_t |
||
1977 | drm_get_resource_start(struct drm_device *dev, unsigned int resource); |
||
1978 | resource_size_t |
||
1979 | drm_get_resource_len(struct drm_device *dev, unsigned int resource); |
||
1980 | |||
1239 | serge | 1981 | bool set_mode(struct drm_device *dev, struct drm_connector *connector, |
1403 | serge | 1982 | videomode_t *mode, bool strict); |
1117 | serge | 1983 | |
1179 | serge | 1984 | |
3764 | Serge | 1985 | #ifndef __TTM__ |
3192 | Serge | 1986 | #define radeon_ttm_set_active_vram_size(a, b) |
3764 | Serge | 1987 | #endif |
3192 | Serge | 1988 | |
1117 | serge | 1989 | #endif><>><>><>><>><>><>><>=>>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><> |