Rev 1129 | Rev 1221 | Go to most recent revision | Details | Compare with Previous | Last modification | View Log | RSS feed
Rev | Author | Line No. | Line |
---|---|---|---|
1117 | serge | 1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
||
3 | * Copyright 2008 Red Hat Inc. |
||
4 | * Copyright 2009 Jerome Glisse. |
||
5 | * |
||
6 | * Permission is hereby granted, free of charge, to any person obtaining a |
||
7 | * copy of this software and associated documentation files (the "Software"), |
||
8 | * to deal in the Software without restriction, including without limitation |
||
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
||
10 | * and/or sell copies of the Software, and to permit persons to whom the |
||
11 | * Software is furnished to do so, subject to the following conditions: |
||
12 | * |
||
13 | * The above copyright notice and this permission notice shall be included in |
||
14 | * all copies or substantial portions of the Software. |
||
15 | * |
||
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
||
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
||
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
||
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
||
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
||
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
||
22 | * OTHER DEALINGS IN THE SOFTWARE. |
||
23 | * |
||
24 | * Authors: Dave Airlie |
||
25 | * Alex Deucher |
||
26 | * Jerome Glisse |
||
27 | */ |
||
1125 | serge | 28 | #include "drmP.h" |
1117 | serge | 29 | #include "radeon_reg.h" |
30 | #include "radeon.h" |
||
31 | |||
32 | /* r520,rv530,rv560,rv570,r580 depends on : */ |
||
33 | void r100_hdp_reset(struct radeon_device *rdev); |
||
34 | void r420_pipes_init(struct radeon_device *rdev); |
||
35 | void rs600_mc_disable_clients(struct radeon_device *rdev); |
||
36 | void rs600_disable_vga(struct radeon_device *rdev); |
||
37 | int rv515_debugfs_pipes_info_init(struct radeon_device *rdev); |
||
38 | int rv515_debugfs_ga_info_init(struct radeon_device *rdev); |
||
39 | |||
40 | /* This files gather functions specifics to: |
||
41 | * r520,rv530,rv560,rv570,r580 |
||
42 | * |
||
43 | * Some of these functions might be used by newer ASICs. |
||
44 | */ |
||
45 | void r520_gpu_init(struct radeon_device *rdev); |
||
46 | int r520_mc_wait_for_idle(struct radeon_device *rdev); |
||
47 | |||
1179 | serge | 48 | |
1117 | serge | 49 | /* |
50 | * MC |
||
51 | */ |
||
52 | int r520_mc_init(struct radeon_device *rdev) |
||
53 | { |
||
54 | uint32_t tmp; |
||
55 | int r; |
||
56 | |||
1179 | serge | 57 | ENTER(); |
1117 | serge | 58 | |
1129 | serge | 59 | if (r100_debugfs_rbbm_init(rdev)) { |
60 | DRM_ERROR("Failed to register debugfs file for RBBM !\n"); |
||
61 | } |
||
62 | if (rv515_debugfs_pipes_info_init(rdev)) { |
||
63 | DRM_ERROR("Failed to register debugfs file for pipes !\n"); |
||
64 | } |
||
65 | if (rv515_debugfs_ga_info_init(rdev)) { |
||
66 | DRM_ERROR("Failed to register debugfs file for pipes !\n"); |
||
67 | } |
||
1119 | serge | 68 | |
1117 | serge | 69 | r520_gpu_init(rdev); |
70 | rv370_pcie_gart_disable(rdev); |
||
71 | |||
72 | /* Setup GPU memory space */ |
||
73 | rdev->mc.vram_location = 0xFFFFFFFFUL; |
||
74 | rdev->mc.gtt_location = 0xFFFFFFFFUL; |
||
75 | r = radeon_mc_setup(rdev); |
||
76 | if (r) { |
||
77 | return r; |
||
78 | } |
||
79 | |||
80 | /* Program GPU memory space */ |
||
1119 | serge | 81 | rs600_mc_disable_clients(rdev); |
82 | if (r520_mc_wait_for_idle(rdev)) { |
||
83 | printk(KERN_WARNING "Failed to wait MC idle while " |
||
1117 | serge | 84 | "programming pipes. Bad things might happen.\n"); |
85 | } |
||
86 | /* Write VRAM size in case we are limiting it */ |
||
1179 | serge | 87 | WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size); |
88 | tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1; |
||
1117 | serge | 89 | tmp = REG_SET(R520_MC_FB_TOP, tmp >> 16); |
90 | tmp |= REG_SET(R520_MC_FB_START, rdev->mc.vram_location >> 16); |
||
91 | WREG32_MC(R520_MC_FB_LOCATION, tmp); |
||
92 | WREG32(RS690_HDP_FB_LOCATION, rdev->mc.vram_location >> 16); |
||
93 | WREG32(0x310, rdev->mc.vram_location); |
||
94 | if (rdev->flags & RADEON_IS_AGP) { |
||
95 | tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1; |
||
96 | tmp = REG_SET(R520_MC_AGP_TOP, tmp >> 16); |
||
97 | tmp |= REG_SET(R520_MC_AGP_START, rdev->mc.gtt_location >> 16); |
||
98 | WREG32_MC(R520_MC_AGP_LOCATION, tmp); |
||
99 | WREG32_MC(R520_MC_AGP_BASE, rdev->mc.agp_base); |
||
100 | WREG32_MC(R520_MC_AGP_BASE_2, 0); |
||
101 | } else { |
||
102 | WREG32_MC(R520_MC_AGP_LOCATION, 0x0FFFFFFF); |
||
103 | WREG32_MC(R520_MC_AGP_BASE, 0); |
||
104 | WREG32_MC(R520_MC_AGP_BASE_2, 0); |
||
105 | } |
||
1119 | serge | 106 | |
1179 | serge | 107 | LEAVE(); |
1119 | serge | 108 | |
1117 | serge | 109 | return 0; |
110 | } |
||
111 | |||
112 | void r520_mc_fini(struct radeon_device *rdev) |
||
113 | { |
||
114 | } |
||
115 | |||
116 | |||
117 | /* |
||
118 | * Global GPU functions |
||
119 | */ |
||
120 | void r520_errata(struct radeon_device *rdev) |
||
121 | { |
||
122 | rdev->pll_errata = 0; |
||
123 | } |
||
124 | |||
125 | int r520_mc_wait_for_idle(struct radeon_device *rdev) |
||
126 | { |
||
127 | unsigned i; |
||
128 | uint32_t tmp; |
||
129 | |||
130 | for (i = 0; i < rdev->usec_timeout; i++) { |
||
131 | /* read MC_STATUS */ |
||
132 | tmp = RREG32_MC(R520_MC_STATUS); |
||
133 | if (tmp & R520_MC_STATUS_IDLE) { |
||
134 | return 0; |
||
135 | } |
||
136 | DRM_UDELAY(1); |
||
137 | } |
||
138 | return -1; |
||
139 | } |
||
140 | |||
141 | void r520_gpu_init(struct radeon_device *rdev) |
||
142 | { |
||
143 | unsigned pipe_select_current, gb_pipe_select, tmp; |
||
1179 | serge | 144 | ENTER(); |
1117 | serge | 145 | |
146 | r100_hdp_reset(rdev); |
||
147 | rs600_disable_vga(rdev); |
||
148 | /* |
||
149 | * DST_PIPE_CONFIG 0x170C |
||
150 | * GB_TILE_CONFIG 0x4018 |
||
151 | * GB_FIFO_SIZE 0x4024 |
||
152 | * GB_PIPE_SELECT 0x402C |
||
153 | * GB_PIPE_SELECT2 0x4124 |
||
154 | * Z_PIPE_SHIFT 0 |
||
155 | * Z_PIPE_MASK 0x000000003 |
||
156 | * GB_FIFO_SIZE2 0x4128 |
||
157 | * SC_SFIFO_SIZE_SHIFT 0 |
||
158 | * SC_SFIFO_SIZE_MASK 0x000000003 |
||
159 | * SC_MFIFO_SIZE_SHIFT 2 |
||
160 | * SC_MFIFO_SIZE_MASK 0x00000000C |
||
161 | * FG_SFIFO_SIZE_SHIFT 4 |
||
162 | * FG_SFIFO_SIZE_MASK 0x000000030 |
||
163 | * ZB_MFIFO_SIZE_SHIFT 6 |
||
164 | * ZB_MFIFO_SIZE_MASK 0x0000000C0 |
||
165 | * GA_ENHANCE 0x4274 |
||
166 | * SU_REG_DEST 0x42C8 |
||
167 | */ |
||
168 | /* workaround for RV530 */ |
||
169 | if (rdev->family == CHIP_RV530) { |
||
170 | WREG32(0x4128, 0xFF); |
||
171 | } |
||
172 | r420_pipes_init(rdev); |
||
173 | gb_pipe_select = RREG32(0x402C); |
||
174 | tmp = RREG32(0x170C); |
||
175 | pipe_select_current = (tmp >> 2) & 3; |
||
176 | tmp = (1 << pipe_select_current) | |
||
177 | (((gb_pipe_select >> 8) & 0xF) << 4); |
||
178 | WREG32_PLL(0x000D, tmp); |
||
179 | if (r520_mc_wait_for_idle(rdev)) { |
||
180 | printk(KERN_WARNING "Failed to wait MC idle while " |
||
181 | "programming pipes. Bad things might happen.\n"); |
||
182 | } |
||
183 | } |
||
184 | |||
185 | |||
186 | /* |
||
187 | * VRAM info |
||
188 | */ |
||
189 | static void r520_vram_get_type(struct radeon_device *rdev) |
||
190 | { |
||
191 | uint32_t tmp; |
||
1179 | serge | 192 | ENTER(); |
1117 | serge | 193 | |
194 | rdev->mc.vram_width = 128; |
||
195 | rdev->mc.vram_is_ddr = true; |
||
196 | tmp = RREG32_MC(R520_MC_CNTL0); |
||
197 | switch ((tmp & R520_MEM_NUM_CHANNELS_MASK) >> R520_MEM_NUM_CHANNELS_SHIFT) { |
||
198 | case 0: |
||
199 | rdev->mc.vram_width = 32; |
||
200 | break; |
||
201 | case 1: |
||
202 | rdev->mc.vram_width = 64; |
||
203 | break; |
||
204 | case 2: |
||
205 | rdev->mc.vram_width = 128; |
||
206 | break; |
||
207 | case 3: |
||
208 | rdev->mc.vram_width = 256; |
||
209 | break; |
||
210 | default: |
||
211 | rdev->mc.vram_width = 128; |
||
212 | break; |
||
213 | } |
||
214 | if (tmp & R520_MC_CHANNEL_SIZE) |
||
215 | rdev->mc.vram_width *= 2; |
||
216 | } |
||
217 | |||
218 | void r520_vram_info(struct radeon_device *rdev) |
||
219 | { |
||
1179 | serge | 220 | fixed20_12 a; |
221 | |||
1117 | serge | 222 | r520_vram_get_type(rdev); |
223 | |||
1179 | serge | 224 | r100_vram_init_sizes(rdev); |
225 | /* FIXME: we should enforce default clock in case GPU is not in |
||
226 | * default setup |
||
227 | */ |
||
228 | a.full = rfixed_const(100); |
||
229 | rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk); |
||
230 | rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a); |
||
1117 | serge | 231 | } |
232 | |||
1179 | serge | 233 | void r520_bandwidth_update(struct radeon_device *rdev) |
1119 | serge | 234 | { |
1179 | serge | 235 | rv515_bandwidth_avivo_update(rdev); |
1119 | serge | 236 | }><>><>> |