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1117 | serge | 1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
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3 | * Copyright 2008 Red Hat Inc. |
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4 | * Copyright 2009 Jerome Glisse. |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the "Software"), |
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8 | * to deal in the Software without restriction, including without limitation |
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9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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10 | * and/or sell copies of the Software, and to permit persons to whom the |
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11 | * Software is furnished to do so, subject to the following conditions: |
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12 | * |
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13 | * The above copyright notice and this permission notice shall be included in |
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14 | * all copies or substantial portions of the Software. |
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15 | * |
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16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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22 | * OTHER DEALINGS IN THE SOFTWARE. |
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23 | * |
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24 | * Authors: Dave Airlie |
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25 | * Alex Deucher |
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26 | * Jerome Glisse |
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27 | */ |
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28 | //#include "drmP.h" |
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29 | #include "radeon_reg.h" |
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30 | #include "radeon.h" |
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31 | |||
32 | /* r520,rv530,rv560,rv570,r580 depends on : */ |
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33 | void r100_hdp_reset(struct radeon_device *rdev); |
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34 | int rv370_pcie_gart_enable(struct radeon_device *rdev); |
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35 | void rv370_pcie_gart_disable(struct radeon_device *rdev); |
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36 | void r420_pipes_init(struct radeon_device *rdev); |
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37 | void rs600_mc_disable_clients(struct radeon_device *rdev); |
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38 | void rs600_disable_vga(struct radeon_device *rdev); |
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39 | int rv515_debugfs_pipes_info_init(struct radeon_device *rdev); |
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40 | int rv515_debugfs_ga_info_init(struct radeon_device *rdev); |
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41 | |||
42 | /* This files gather functions specifics to: |
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43 | * r520,rv530,rv560,rv570,r580 |
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44 | * |
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45 | * Some of these functions might be used by newer ASICs. |
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46 | */ |
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47 | void r520_gpu_init(struct radeon_device *rdev); |
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48 | int r520_mc_wait_for_idle(struct radeon_device *rdev); |
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49 | |||
50 | #if 0 |
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51 | /* |
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52 | * MC |
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53 | */ |
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54 | int r520_mc_init(struct radeon_device *rdev) |
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55 | { |
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56 | uint32_t tmp; |
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57 | int r; |
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58 | |||
59 | if (r100_debugfs_rbbm_init(rdev)) { |
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60 | DRM_ERROR("Failed to register debugfs file for RBBM !\n"); |
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61 | } |
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62 | if (rv515_debugfs_pipes_info_init(rdev)) { |
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63 | DRM_ERROR("Failed to register debugfs file for pipes !\n"); |
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64 | } |
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65 | if (rv515_debugfs_ga_info_init(rdev)) { |
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66 | DRM_ERROR("Failed to register debugfs file for pipes !\n"); |
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67 | } |
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68 | |||
69 | r520_gpu_init(rdev); |
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70 | rv370_pcie_gart_disable(rdev); |
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71 | |||
72 | /* Setup GPU memory space */ |
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73 | rdev->mc.vram_location = 0xFFFFFFFFUL; |
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74 | rdev->mc.gtt_location = 0xFFFFFFFFUL; |
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75 | if (rdev->flags & RADEON_IS_AGP) { |
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76 | r = radeon_agp_init(rdev); |
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77 | if (r) { |
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78 | printk(KERN_WARNING "[drm] Disabling AGP\n"); |
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79 | rdev->flags &= ~RADEON_IS_AGP; |
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80 | rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; |
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81 | } else { |
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82 | rdev->mc.gtt_location = rdev->mc.agp_base; |
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83 | } |
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84 | } |
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85 | r = radeon_mc_setup(rdev); |
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86 | if (r) { |
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87 | return r; |
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88 | } |
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89 | |||
90 | /* Program GPU memory space */ |
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91 | rs600_mc_disable_clients(rdev); |
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92 | if (r520_mc_wait_for_idle(rdev)) { |
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93 | printk(KERN_WARNING "Failed to wait MC idle while " |
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94 | "programming pipes. Bad things might happen.\n"); |
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95 | } |
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96 | /* Write VRAM size in case we are limiting it */ |
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97 | WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.vram_size); |
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98 | tmp = rdev->mc.vram_location + rdev->mc.vram_size - 1; |
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99 | tmp = REG_SET(R520_MC_FB_TOP, tmp >> 16); |
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100 | tmp |= REG_SET(R520_MC_FB_START, rdev->mc.vram_location >> 16); |
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101 | WREG32_MC(R520_MC_FB_LOCATION, tmp); |
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102 | WREG32(RS690_HDP_FB_LOCATION, rdev->mc.vram_location >> 16); |
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103 | WREG32(0x310, rdev->mc.vram_location); |
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104 | if (rdev->flags & RADEON_IS_AGP) { |
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105 | tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1; |
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106 | tmp = REG_SET(R520_MC_AGP_TOP, tmp >> 16); |
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107 | tmp |= REG_SET(R520_MC_AGP_START, rdev->mc.gtt_location >> 16); |
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108 | WREG32_MC(R520_MC_AGP_LOCATION, tmp); |
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109 | WREG32_MC(R520_MC_AGP_BASE, rdev->mc.agp_base); |
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110 | WREG32_MC(R520_MC_AGP_BASE_2, 0); |
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111 | } else { |
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112 | WREG32_MC(R520_MC_AGP_LOCATION, 0x0FFFFFFF); |
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113 | WREG32_MC(R520_MC_AGP_BASE, 0); |
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114 | WREG32_MC(R520_MC_AGP_BASE_2, 0); |
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115 | } |
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116 | return 0; |
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117 | } |
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118 | |||
119 | void r520_mc_fini(struct radeon_device *rdev) |
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120 | { |
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121 | rv370_pcie_gart_disable(rdev); |
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122 | radeon_gart_table_vram_free(rdev); |
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123 | radeon_gart_fini(rdev); |
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124 | } |
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125 | |||
126 | #endif |
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127 | |||
128 | /* |
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129 | * Global GPU functions |
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130 | */ |
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131 | void r520_errata(struct radeon_device *rdev) |
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132 | { |
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133 | rdev->pll_errata = 0; |
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134 | } |
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135 | |||
136 | #if 0 |
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137 | int r520_mc_wait_for_idle(struct radeon_device *rdev) |
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138 | { |
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139 | unsigned i; |
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140 | uint32_t tmp; |
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141 | |||
142 | for (i = 0; i < rdev->usec_timeout; i++) { |
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143 | /* read MC_STATUS */ |
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144 | tmp = RREG32_MC(R520_MC_STATUS); |
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145 | if (tmp & R520_MC_STATUS_IDLE) { |
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146 | return 0; |
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147 | } |
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148 | DRM_UDELAY(1); |
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149 | } |
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150 | return -1; |
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151 | } |
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152 | |||
153 | void r520_gpu_init(struct radeon_device *rdev) |
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154 | { |
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155 | unsigned pipe_select_current, gb_pipe_select, tmp; |
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156 | |||
157 | r100_hdp_reset(rdev); |
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158 | rs600_disable_vga(rdev); |
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159 | /* |
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160 | * DST_PIPE_CONFIG 0x170C |
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161 | * GB_TILE_CONFIG 0x4018 |
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162 | * GB_FIFO_SIZE 0x4024 |
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163 | * GB_PIPE_SELECT 0x402C |
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164 | * GB_PIPE_SELECT2 0x4124 |
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165 | * Z_PIPE_SHIFT 0 |
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166 | * Z_PIPE_MASK 0x000000003 |
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167 | * GB_FIFO_SIZE2 0x4128 |
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168 | * SC_SFIFO_SIZE_SHIFT 0 |
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169 | * SC_SFIFO_SIZE_MASK 0x000000003 |
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170 | * SC_MFIFO_SIZE_SHIFT 2 |
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171 | * SC_MFIFO_SIZE_MASK 0x00000000C |
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172 | * FG_SFIFO_SIZE_SHIFT 4 |
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173 | * FG_SFIFO_SIZE_MASK 0x000000030 |
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174 | * ZB_MFIFO_SIZE_SHIFT 6 |
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175 | * ZB_MFIFO_SIZE_MASK 0x0000000C0 |
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176 | * GA_ENHANCE 0x4274 |
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177 | * SU_REG_DEST 0x42C8 |
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178 | */ |
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179 | /* workaround for RV530 */ |
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180 | if (rdev->family == CHIP_RV530) { |
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181 | WREG32(0x4124, 1); |
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182 | WREG32(0x4128, 0xFF); |
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183 | } |
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184 | r420_pipes_init(rdev); |
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185 | gb_pipe_select = RREG32(0x402C); |
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186 | tmp = RREG32(0x170C); |
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187 | pipe_select_current = (tmp >> 2) & 3; |
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188 | tmp = (1 << pipe_select_current) | |
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189 | (((gb_pipe_select >> 8) & 0xF) << 4); |
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190 | WREG32_PLL(0x000D, tmp); |
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191 | if (r520_mc_wait_for_idle(rdev)) { |
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192 | printk(KERN_WARNING "Failed to wait MC idle while " |
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193 | "programming pipes. Bad things might happen.\n"); |
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194 | } |
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195 | } |
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196 | |||
197 | #endif |
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198 | |||
199 | |||
200 | /* |
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201 | * VRAM info |
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202 | */ |
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203 | static void r520_vram_get_type(struct radeon_device *rdev) |
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204 | { |
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205 | uint32_t tmp; |
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206 | |||
207 | rdev->mc.vram_width = 128; |
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208 | rdev->mc.vram_is_ddr = true; |
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209 | tmp = RREG32_MC(R520_MC_CNTL0); |
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210 | switch ((tmp & R520_MEM_NUM_CHANNELS_MASK) >> R520_MEM_NUM_CHANNELS_SHIFT) { |
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211 | case 0: |
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212 | rdev->mc.vram_width = 32; |
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213 | break; |
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214 | case 1: |
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215 | rdev->mc.vram_width = 64; |
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216 | break; |
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217 | case 2: |
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218 | rdev->mc.vram_width = 128; |
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219 | break; |
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220 | case 3: |
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221 | rdev->mc.vram_width = 256; |
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222 | break; |
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223 | default: |
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224 | rdev->mc.vram_width = 128; |
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225 | break; |
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226 | } |
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227 | if (tmp & R520_MC_CHANNEL_SIZE) |
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228 | rdev->mc.vram_width *= 2; |
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229 | } |
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230 | |||
231 | void r520_vram_info(struct radeon_device *rdev) |
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232 | { |
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233 | r520_vram_get_type(rdev); |
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234 | rdev->mc.vram_size = RREG32(RADEON_CONFIG_MEMSIZE); |
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235 | |||
236 | rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); |
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237 | rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); |
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238 | }><>><>> |
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239 |