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Rev | Author | Line No. | Line |
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1120 | serge | 1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
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3 | * Copyright 2008 Red Hat Inc. |
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4 | * Copyright 2009 Jerome Glisse. |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the "Software"), |
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8 | * to deal in the Software without restriction, including without limitation |
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9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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10 | * and/or sell copies of the Software, and to permit persons to whom the |
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11 | * Software is furnished to do so, subject to the following conditions: |
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12 | * |
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13 | * The above copyright notice and this permission notice shall be included in |
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14 | * all copies or substantial portions of the Software. |
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15 | * |
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16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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22 | * OTHER DEALINGS IN THE SOFTWARE. |
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23 | * |
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24 | * Authors: Dave Airlie |
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25 | * Alex Deucher |
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26 | * Jerome Glisse |
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27 | */ |
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1179 | serge | 28 | #include |
1963 | serge | 29 | #include |
30 | #include |
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31 | #include |
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32 | #include |
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1120 | serge | 33 | #include "radeon_reg.h" |
34 | #include "radeon.h" |
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1963 | serge | 35 | #include "radeon_asic.h" |
1179 | serge | 36 | #include "radeon_drm.h" |
1120 | serge | 37 | |
1179 | serge | 38 | #include "r300d.h" |
1221 | serge | 39 | #include "rv350d.h" |
1179 | serge | 40 | #include "r300_reg_safe.h" |
41 | |||
1403 | serge | 42 | /* This files gather functions specifics to: r300,r350,rv350,rv370,rv380 |
43 | * |
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44 | * GPU Errata: |
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45 | * - HOST_PATH_CNTL: r300 family seems to dislike write to HOST_PATH_CNTL |
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46 | * using MMIO to flush host path read cache, this lead to HARDLOCKUP. |
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47 | * However, scheduling such write to the ring seems harmless, i suspect |
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48 | * the CP read collide with the flush somehow, or maybe the MC, hard to |
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49 | * tell. (Jerome Glisse) |
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50 | */ |
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1120 | serge | 51 | |
52 | /* |
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53 | * rv370,rv380 PCIE GART |
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54 | */ |
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1221 | serge | 55 | static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev); |
56 | |||
1120 | serge | 57 | void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev) |
58 | { |
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59 | uint32_t tmp; |
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60 | int i; |
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61 | |||
62 | /* Workaround HW bug do flush 2 times */ |
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63 | for (i = 0; i < 2; i++) { |
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64 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); |
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65 | WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp | RADEON_PCIE_TX_GART_INVALIDATE_TLB); |
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66 | (void)RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); |
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67 | WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); |
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1179 | serge | 68 | } |
1120 | serge | 69 | mb(); |
1179 | serge | 70 | } |
71 | |||
1963 | serge | 72 | #define R300_PTE_WRITEABLE (1 << 2) |
73 | #define R300_PTE_READABLE (1 << 3) |
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74 | |||
1179 | serge | 75 | int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) |
76 | { |
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77 | void __iomem *ptr = (void *)rdev->gart.table.vram.ptr; |
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78 | |||
79 | if (i < 0 || i > rdev->gart.num_gpu_pages) { |
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80 | return -EINVAL; |
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1120 | serge | 81 | } |
1179 | serge | 82 | addr = (lower_32_bits(addr) >> 8) | |
83 | ((upper_32_bits(addr) & 0xff) << 24) | |
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1963 | serge | 84 | R300_PTE_WRITEABLE | R300_PTE_READABLE; |
1179 | serge | 85 | /* on x86 we want this to be CPU endian, on powerpc |
86 | * on powerpc without HW swappers, it'll get swapped on way |
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87 | * into VRAM - so no need for cpu_to_le32 on VRAM tables */ |
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88 | writel(addr, ((void __iomem *)ptr) + (i * 4)); |
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89 | return 0; |
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1120 | serge | 90 | } |
91 | |||
1179 | serge | 92 | int rv370_pcie_gart_init(struct radeon_device *rdev) |
1120 | serge | 93 | { |
94 | int r; |
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95 | |||
1179 | serge | 96 | if (rdev->gart.table.vram.robj) { |
1963 | serge | 97 | WARN(1, "RV370 PCIE GART already initialized\n"); |
1179 | serge | 98 | return 0; |
99 | } |
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1120 | serge | 100 | /* Initialize common gart structure */ |
101 | r = radeon_gart_init(rdev); |
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1179 | serge | 102 | if (r) |
1120 | serge | 103 | return r; |
1129 | serge | 104 | r = rv370_debugfs_pcie_gart_info_init(rdev); |
1179 | serge | 105 | if (r) |
1129 | serge | 106 | DRM_ERROR("Failed to register debugfs file for PCIE gart !\n"); |
1179 | serge | 107 | rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; |
108 | rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush; |
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109 | rdev->asic->gart_set_page = &rv370_pcie_gart_set_page; |
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110 | return radeon_gart_table_vram_alloc(rdev); |
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111 | } |
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112 | |||
113 | int rv370_pcie_gart_enable(struct radeon_device *rdev) |
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114 | { |
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115 | uint32_t table_addr; |
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116 | uint32_t tmp; |
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117 | int r; |
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118 | |||
119 | if (rdev->gart.table.vram.robj == NULL) { |
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120 | dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); |
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121 | return -EINVAL; |
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1129 | serge | 122 | } |
1179 | serge | 123 | r = radeon_gart_table_vram_pin(rdev); |
124 | if (r) |
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1120 | serge | 125 | return r; |
1430 | serge | 126 | radeon_gart_restore(rdev); |
1120 | serge | 127 | /* discard memory request outside of configured range */ |
128 | tmp = RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD; |
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129 | WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); |
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1430 | serge | 130 | WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, rdev->mc.gtt_start); |
131 | tmp = rdev->mc.gtt_end & ~RADEON_GPU_PAGE_MASK; |
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1120 | serge | 132 | WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, tmp); |
133 | WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0); |
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134 | WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0); |
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135 | table_addr = rdev->gart.table_addr; |
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136 | WREG32_PCIE(RADEON_PCIE_TX_GART_BASE, table_addr); |
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137 | /* FIXME: setup default page */ |
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1430 | serge | 138 | WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_start); |
1120 | serge | 139 | WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_HI, 0); |
140 | /* Clear error */ |
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1963 | serge | 141 | WREG32_PCIE(RADEON_PCIE_TX_GART_ERROR, 0); |
1120 | serge | 142 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); |
143 | tmp |= RADEON_PCIE_TX_GART_EN; |
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144 | tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD; |
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145 | WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); |
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146 | rv370_pcie_gart_tlb_flush(rdev); |
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147 | DRM_INFO("PCIE GART of %uM enabled (table at 0x%08X).\n", |
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1179 | serge | 148 | (unsigned)(rdev->mc.gtt_size >> 20), table_addr); |
1120 | serge | 149 | rdev->gart.ready = true; |
150 | return 0; |
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151 | } |
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152 | |||
153 | void rv370_pcie_gart_disable(struct radeon_device *rdev) |
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154 | { |
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1321 | serge | 155 | u32 tmp; |
156 | int r; |
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1120 | serge | 157 | |
1963 | serge | 158 | WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, 0); |
159 | WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, 0); |
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160 | WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0); |
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161 | WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0); |
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1120 | serge | 162 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); |
163 | tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD; |
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164 | WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp & ~RADEON_PCIE_TX_GART_EN); |
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165 | if (rdev->gart.table.vram.robj) { |
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1404 | serge | 166 | r = radeon_bo_reserve(rdev->gart.table.vram.robj, false); |
167 | if (likely(r == 0)) { |
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168 | radeon_bo_kunmap(rdev->gart.table.vram.robj); |
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169 | radeon_bo_unpin(rdev->gart.table.vram.robj); |
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170 | radeon_bo_unreserve(rdev->gart.table.vram.robj); |
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171 | } |
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1120 | serge | 172 | } |
173 | } |
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174 | |||
1179 | serge | 175 | void rv370_pcie_gart_fini(struct radeon_device *rdev) |
1120 | serge | 176 | { |
1963 | serge | 177 | radeon_gart_fini(rdev); |
1120 | serge | 178 | rv370_pcie_gart_disable(rdev); |
1179 | serge | 179 | radeon_gart_table_vram_free(rdev); |
1120 | serge | 180 | } |
181 | |||
182 | void r300_fence_ring_emit(struct radeon_device *rdev, |
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183 | struct radeon_fence *fence) |
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184 | { |
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185 | /* Who ever call radeon_fence_emit should call ring_lock and ask |
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186 | * for enough space (today caller are ib schedule and buffer move) */ |
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187 | /* Write SC register so SC & US assert idle */ |
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1430 | serge | 188 | radeon_ring_write(rdev, PACKET0(R300_RE_SCISSORS_TL, 0)); |
1120 | serge | 189 | radeon_ring_write(rdev, 0); |
1430 | serge | 190 | radeon_ring_write(rdev, PACKET0(R300_RE_SCISSORS_BR, 0)); |
1120 | serge | 191 | radeon_ring_write(rdev, 0); |
192 | /* Flush 3D cache */ |
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1430 | serge | 193 | radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); |
194 | radeon_ring_write(rdev, R300_RB3D_DC_FLUSH); |
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195 | radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); |
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196 | radeon_ring_write(rdev, R300_ZC_FLUSH); |
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1120 | serge | 197 | /* Wait until IDLE & CLEAN */ |
1430 | serge | 198 | radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0)); |
199 | radeon_ring_write(rdev, (RADEON_WAIT_3D_IDLECLEAN | |
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200 | RADEON_WAIT_2D_IDLECLEAN | |
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201 | RADEON_WAIT_DMA_GUI_IDLE)); |
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1403 | serge | 202 | radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0)); |
203 | radeon_ring_write(rdev, rdev->config.r300.hdp_cntl | |
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204 | RADEON_HDP_READ_BUFFER_INVALIDATE); |
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205 | radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0)); |
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206 | radeon_ring_write(rdev, rdev->config.r300.hdp_cntl); |
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1120 | serge | 207 | /* Emit fence sequence & fire IRQ */ |
208 | radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0)); |
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209 | radeon_ring_write(rdev, fence->seq); |
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210 | radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0)); |
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211 | radeon_ring_write(rdev, RADEON_SW_INT_FIRE); |
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212 | } |
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213 | |||
214 | void r300_ring_start(struct radeon_device *rdev) |
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215 | { |
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216 | unsigned gb_tile_config; |
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217 | int r; |
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218 | |||
219 | /* Sub pixel 1/12 so we can have 4K rendering according to doc */ |
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220 | gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16); |
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221 | switch(rdev->num_gb_pipes) { |
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222 | case 2: |
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223 | gb_tile_config |= R300_PIPE_COUNT_R300; |
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224 | break; |
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225 | case 3: |
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226 | gb_tile_config |= R300_PIPE_COUNT_R420_3P; |
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227 | break; |
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228 | case 4: |
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229 | gb_tile_config |= R300_PIPE_COUNT_R420; |
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230 | break; |
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231 | case 1: |
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232 | default: |
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233 | gb_tile_config |= R300_PIPE_COUNT_RV350; |
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234 | break; |
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235 | } |
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236 | |||
237 | r = radeon_ring_lock(rdev, 64); |
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238 | if (r) { |
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239 | return; |
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240 | } |
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241 | radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0)); |
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242 | radeon_ring_write(rdev, |
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243 | RADEON_ISYNC_ANY2D_IDLE3D | |
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244 | RADEON_ISYNC_ANY3D_IDLE2D | |
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245 | RADEON_ISYNC_WAIT_IDLEGUI | |
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246 | RADEON_ISYNC_CPSCRATCH_IDLEGUI); |
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247 | radeon_ring_write(rdev, PACKET0(R300_GB_TILE_CONFIG, 0)); |
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248 | radeon_ring_write(rdev, gb_tile_config); |
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249 | radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0)); |
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250 | radeon_ring_write(rdev, |
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251 | RADEON_WAIT_2D_IDLECLEAN | |
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252 | RADEON_WAIT_3D_IDLECLEAN); |
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1430 | serge | 253 | radeon_ring_write(rdev, PACKET0(R300_DST_PIPE_CONFIG, 0)); |
254 | radeon_ring_write(rdev, R300_PIPE_AUTO_CONFIG); |
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1120 | serge | 255 | radeon_ring_write(rdev, PACKET0(R300_GB_SELECT, 0)); |
256 | radeon_ring_write(rdev, 0); |
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257 | radeon_ring_write(rdev, PACKET0(R300_GB_ENABLE, 0)); |
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258 | radeon_ring_write(rdev, 0); |
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259 | radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); |
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260 | radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE); |
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261 | radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); |
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262 | radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE); |
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263 | radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0)); |
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264 | radeon_ring_write(rdev, |
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265 | RADEON_WAIT_2D_IDLECLEAN | |
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266 | RADEON_WAIT_3D_IDLECLEAN); |
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267 | radeon_ring_write(rdev, PACKET0(R300_GB_AA_CONFIG, 0)); |
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268 | radeon_ring_write(rdev, 0); |
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269 | radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); |
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270 | radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE); |
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271 | radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); |
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272 | radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE); |
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273 | radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS0, 0)); |
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274 | radeon_ring_write(rdev, |
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275 | ((6 << R300_MS_X0_SHIFT) | |
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276 | (6 << R300_MS_Y0_SHIFT) | |
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277 | (6 << R300_MS_X1_SHIFT) | |
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278 | (6 << R300_MS_Y1_SHIFT) | |
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279 | (6 << R300_MS_X2_SHIFT) | |
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280 | (6 << R300_MS_Y2_SHIFT) | |
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281 | (6 << R300_MSBD0_Y_SHIFT) | |
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282 | (6 << R300_MSBD0_X_SHIFT))); |
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283 | radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS1, 0)); |
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284 | radeon_ring_write(rdev, |
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285 | ((6 << R300_MS_X3_SHIFT) | |
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286 | (6 << R300_MS_Y3_SHIFT) | |
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287 | (6 << R300_MS_X4_SHIFT) | |
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288 | (6 << R300_MS_Y4_SHIFT) | |
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289 | (6 << R300_MS_X5_SHIFT) | |
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290 | (6 << R300_MS_Y5_SHIFT) | |
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291 | (6 << R300_MSBD1_SHIFT))); |
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292 | radeon_ring_write(rdev, PACKET0(R300_GA_ENHANCE, 0)); |
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293 | radeon_ring_write(rdev, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL); |
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294 | radeon_ring_write(rdev, PACKET0(R300_GA_POLY_MODE, 0)); |
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295 | radeon_ring_write(rdev, |
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296 | R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE); |
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297 | radeon_ring_write(rdev, PACKET0(R300_GA_ROUND_MODE, 0)); |
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298 | radeon_ring_write(rdev, |
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299 | R300_GEOMETRY_ROUND_NEAREST | |
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300 | R300_COLOR_ROUND_NEAREST); |
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301 | radeon_ring_unlock_commit(rdev); |
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302 | } |
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303 | |||
304 | void r300_errata(struct radeon_device *rdev) |
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305 | { |
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306 | rdev->pll_errata = 0; |
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307 | |||
308 | if (rdev->family == CHIP_R300 && |
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309 | (RREG32(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) == RADEON_CFG_ATI_REV_A11) { |
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310 | rdev->pll_errata |= CHIP_ERRATA_R300_CG; |
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311 | } |
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312 | } |
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313 | |||
314 | int r300_mc_wait_for_idle(struct radeon_device *rdev) |
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315 | { |
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316 | unsigned i; |
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317 | uint32_t tmp; |
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318 | |||
319 | for (i = 0; i < rdev->usec_timeout; i++) { |
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320 | /* read MC_STATUS */ |
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1430 | serge | 321 | tmp = RREG32(RADEON_MC_STATUS); |
322 | if (tmp & R300_MC_IDLE) { |
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1120 | serge | 323 | return 0; |
324 | } |
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325 | DRM_UDELAY(1); |
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326 | } |
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327 | return -1; |
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328 | } |
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329 | |||
330 | void r300_gpu_init(struct radeon_device *rdev) |
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331 | { |
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332 | uint32_t gb_tile_config, tmp; |
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333 | |||
1963 | serge | 334 | if ((rdev->family == CHIP_R300 && rdev->pdev->device != 0x4144) || |
335 | (rdev->family == CHIP_R350 && rdev->pdev->device != 0x4148)) { |
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1120 | serge | 336 | /* r300,r350 */ |
337 | rdev->num_gb_pipes = 2; |
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338 | } else { |
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1963 | serge | 339 | /* rv350,rv370,rv380,r300 AD, r350 AH */ |
1120 | serge | 340 | rdev->num_gb_pipes = 1; |
341 | } |
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1179 | serge | 342 | rdev->num_z_pipes = 1; |
1120 | serge | 343 | gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16); |
344 | switch (rdev->num_gb_pipes) { |
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345 | case 2: |
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346 | gb_tile_config |= R300_PIPE_COUNT_R300; |
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347 | break; |
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348 | case 3: |
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349 | gb_tile_config |= R300_PIPE_COUNT_R420_3P; |
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350 | break; |
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351 | case 4: |
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352 | gb_tile_config |= R300_PIPE_COUNT_R420; |
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353 | break; |
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354 | default: |
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355 | case 1: |
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356 | gb_tile_config |= R300_PIPE_COUNT_RV350; |
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357 | break; |
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358 | } |
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359 | WREG32(R300_GB_TILE_CONFIG, gb_tile_config); |
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360 | |||
361 | if (r100_gui_wait_for_idle(rdev)) { |
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362 | printk(KERN_WARNING "Failed to wait GUI idle while " |
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363 | "programming pipes. Bad things might happen.\n"); |
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364 | } |
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365 | |||
1430 | serge | 366 | tmp = RREG32(R300_DST_PIPE_CONFIG); |
367 | WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG); |
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1120 | serge | 368 | |
369 | WREG32(R300_RB2D_DSTCACHE_MODE, |
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370 | R300_DC_AUTOFLUSH_ENABLE | |
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371 | R300_DC_DC_DISABLE_IGNORE_PE); |
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372 | |||
373 | if (r100_gui_wait_for_idle(rdev)) { |
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374 | printk(KERN_WARNING "Failed to wait GUI idle while " |
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375 | "programming pipes. Bad things might happen.\n"); |
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376 | } |
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377 | if (r300_mc_wait_for_idle(rdev)) { |
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378 | printk(KERN_WARNING "Failed to wait MC idle while " |
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379 | "programming pipes. Bad things might happen.\n"); |
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380 | } |
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1179 | serge | 381 | DRM_INFO("radeon: %d quad pipes, %d Z pipes initialized.\n", |
382 | rdev->num_gb_pipes, rdev->num_z_pipes); |
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1120 | serge | 383 | } |
384 | |||
1963 | serge | 385 | bool r300_gpu_is_lockup(struct radeon_device *rdev) |
1120 | serge | 386 | { |
1963 | serge | 387 | u32 rbbm_status; |
388 | int r; |
||
1120 | serge | 389 | |
1963 | serge | 390 | rbbm_status = RREG32(R_000E40_RBBM_STATUS); |
391 | if (!G_000E40_GUI_ACTIVE(rbbm_status)) { |
||
392 | r100_gpu_lockup_update(&rdev->config.r300.lockup, &rdev->cp); |
||
393 | return false; |
||
1120 | serge | 394 | } |
1963 | serge | 395 | /* force CP activities */ |
396 | r = radeon_ring_lock(rdev, 2); |
||
397 | if (!r) { |
||
398 | /* PACKET2 NOP */ |
||
399 | radeon_ring_write(rdev, 0x80000000); |
||
400 | radeon_ring_write(rdev, 0x80000000); |
||
401 | radeon_ring_unlock_commit(rdev); |
||
1120 | serge | 402 | } |
1963 | serge | 403 | rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR); |
404 | return r100_gpu_cp_is_lockup(rdev, &rdev->config.r300.lockup, &rdev->cp); |
||
1120 | serge | 405 | } |
406 | |||
1963 | serge | 407 | int r300_asic_reset(struct radeon_device *rdev) |
1120 | serge | 408 | { |
1963 | serge | 409 | struct r100_mc_save save; |
410 | u32 status, tmp; |
||
411 | int ret = 0; |
||
1120 | serge | 412 | |
1963 | serge | 413 | status = RREG32(R_000E40_RBBM_STATUS); |
414 | if (!G_000E40_GUI_ACTIVE(status)) { |
||
415 | return 0; |
||
1120 | serge | 416 | } |
1963 | serge | 417 | r100_mc_stop(rdev, &save); |
418 | status = RREG32(R_000E40_RBBM_STATUS); |
||
419 | dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); |
||
420 | /* stop CP */ |
||
421 | WREG32(RADEON_CP_CSQ_CNTL, 0); |
||
422 | tmp = RREG32(RADEON_CP_RB_CNTL); |
||
423 | WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA); |
||
424 | WREG32(RADEON_CP_RB_RPTR_WR, 0); |
||
425 | WREG32(RADEON_CP_RB_WPTR, 0); |
||
426 | WREG32(RADEON_CP_RB_CNTL, tmp); |
||
427 | /* save PCI state */ |
||
428 | // pci_save_state(rdev->pdev); |
||
429 | /* disable bus mastering */ |
||
430 | r100_bm_disable(rdev); |
||
431 | WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) | |
||
432 | S_0000F0_SOFT_RESET_GA(1)); |
||
433 | RREG32(R_0000F0_RBBM_SOFT_RESET); |
||
434 | mdelay(500); |
||
435 | WREG32(R_0000F0_RBBM_SOFT_RESET, 0); |
||
436 | mdelay(1); |
||
437 | status = RREG32(R_000E40_RBBM_STATUS); |
||
438 | dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); |
||
439 | /* resetting the CP seems to be problematic sometimes it end up |
||
440 | * hard locking the computer, but it's necessary for successful |
||
441 | * reset more test & playing is needed on R3XX/R4XX to find a |
||
442 | * reliable (if any solution) |
||
443 | */ |
||
444 | WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1)); |
||
445 | RREG32(R_0000F0_RBBM_SOFT_RESET); |
||
446 | mdelay(500); |
||
447 | WREG32(R_0000F0_RBBM_SOFT_RESET, 0); |
||
448 | mdelay(1); |
||
449 | status = RREG32(R_000E40_RBBM_STATUS); |
||
450 | dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); |
||
451 | /* restore PCI & busmastering */ |
||
452 | // pci_restore_state(rdev->pdev); |
||
453 | r100_enable_bm(rdev); |
||
1120 | serge | 454 | /* Check if GPU is idle */ |
1963 | serge | 455 | if (G_000E40_GA_BUSY(status) || G_000E40_VAP_BUSY(status)) { |
456 | dev_err(rdev->dev, "failed to reset GPU\n"); |
||
457 | rdev->gpu_lockup = true; |
||
458 | ret = -1; |
||
459 | } else |
||
460 | dev_info(rdev->dev, "GPU reset succeed\n"); |
||
461 | r100_mc_resume(rdev, &save); |
||
462 | return ret; |
||
1120 | serge | 463 | } |
464 | |||
465 | /* |
||
466 | * r300,r350,rv350,rv380 VRAM info |
||
467 | */ |
||
1430 | serge | 468 | void r300_mc_init(struct radeon_device *rdev) |
1120 | serge | 469 | { |
1430 | serge | 470 | u64 base; |
471 | u32 tmp; |
||
1120 | serge | 472 | |
473 | /* DDR for all card after R300 & IGP */ |
||
474 | rdev->mc.vram_is_ddr = true; |
||
475 | tmp = RREG32(RADEON_MEM_CNTL); |
||
1404 | serge | 476 | tmp &= R300_MEM_NUM_CHANNELS_MASK; |
477 | switch (tmp) { |
||
478 | case 0: rdev->mc.vram_width = 64; break; |
||
479 | case 1: rdev->mc.vram_width = 128; break; |
||
480 | case 2: rdev->mc.vram_width = 256; break; |
||
481 | default: rdev->mc.vram_width = 128; break; |
||
1120 | serge | 482 | } |
1179 | serge | 483 | r100_vram_init_sizes(rdev); |
1430 | serge | 484 | base = rdev->mc.aper_base; |
485 | if (rdev->flags & RADEON_IS_IGP) |
||
486 | base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16; |
||
487 | radeon_vram_location(rdev, &rdev->mc, base); |
||
1963 | serge | 488 | rdev->mc.gtt_base_align = 0; |
1430 | serge | 489 | if (!(rdev->flags & RADEON_IS_AGP)) |
490 | radeon_gtt_location(rdev, &rdev->mc); |
||
1963 | serge | 491 | radeon_update_bandwidth_info(rdev); |
1120 | serge | 492 | } |
493 | |||
494 | void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes) |
||
495 | { |
||
496 | uint32_t link_width_cntl, mask; |
||
497 | |||
498 | if (rdev->flags & RADEON_IS_IGP) |
||
499 | return; |
||
500 | |||
501 | if (!(rdev->flags & RADEON_IS_PCIE)) |
||
502 | return; |
||
503 | |||
504 | /* FIXME wait for idle */ |
||
505 | |||
506 | switch (lanes) { |
||
507 | case 0: |
||
508 | mask = RADEON_PCIE_LC_LINK_WIDTH_X0; |
||
509 | break; |
||
510 | case 1: |
||
511 | mask = RADEON_PCIE_LC_LINK_WIDTH_X1; |
||
512 | break; |
||
513 | case 2: |
||
514 | mask = RADEON_PCIE_LC_LINK_WIDTH_X2; |
||
515 | break; |
||
516 | case 4: |
||
517 | mask = RADEON_PCIE_LC_LINK_WIDTH_X4; |
||
518 | break; |
||
519 | case 8: |
||
520 | mask = RADEON_PCIE_LC_LINK_WIDTH_X8; |
||
521 | break; |
||
522 | case 12: |
||
523 | mask = RADEON_PCIE_LC_LINK_WIDTH_X12; |
||
524 | break; |
||
525 | case 16: |
||
526 | default: |
||
527 | mask = RADEON_PCIE_LC_LINK_WIDTH_X16; |
||
528 | break; |
||
529 | } |
||
530 | |||
531 | link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); |
||
532 | |||
533 | if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) == |
||
534 | (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT)) |
||
535 | return; |
||
536 | |||
537 | link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK | |
||
538 | RADEON_PCIE_LC_RECONFIG_NOW | |
||
539 | RADEON_PCIE_LC_RECONFIG_LATER | |
||
540 | RADEON_PCIE_LC_SHORT_RECONFIG_EN); |
||
541 | link_width_cntl |= mask; |
||
542 | WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); |
||
543 | WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl | |
||
544 | RADEON_PCIE_LC_RECONFIG_NOW)); |
||
545 | |||
546 | /* wait for lane set to complete */ |
||
547 | link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); |
||
548 | while (link_width_cntl == 0xffffffff) |
||
549 | link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); |
||
550 | |||
551 | } |
||
552 | |||
1430 | serge | 553 | int rv370_get_pcie_lanes(struct radeon_device *rdev) |
554 | { |
||
555 | u32 link_width_cntl; |
||
556 | |||
557 | if (rdev->flags & RADEON_IS_IGP) |
||
558 | return 0; |
||
559 | |||
560 | if (!(rdev->flags & RADEON_IS_PCIE)) |
||
561 | return 0; |
||
562 | |||
563 | /* FIXME wait for idle */ |
||
564 | |||
565 | link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); |
||
566 | |||
567 | switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) { |
||
568 | case RADEON_PCIE_LC_LINK_WIDTH_X0: |
||
569 | return 0; |
||
570 | case RADEON_PCIE_LC_LINK_WIDTH_X1: |
||
571 | return 1; |
||
572 | case RADEON_PCIE_LC_LINK_WIDTH_X2: |
||
573 | return 2; |
||
574 | case RADEON_PCIE_LC_LINK_WIDTH_X4: |
||
575 | return 4; |
||
576 | case RADEON_PCIE_LC_LINK_WIDTH_X8: |
||
577 | return 8; |
||
578 | case RADEON_PCIE_LC_LINK_WIDTH_X16: |
||
579 | default: |
||
580 | return 16; |
||
581 | } |
||
582 | } |
||
583 | |||
1120 | serge | 584 | #if defined(CONFIG_DEBUG_FS) |
585 | static int rv370_debugfs_pcie_gart_info(struct seq_file *m, void *data) |
||
586 | { |
||
587 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
||
588 | struct drm_device *dev = node->minor->dev; |
||
589 | struct radeon_device *rdev = dev->dev_private; |
||
590 | uint32_t tmp; |
||
591 | |||
592 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); |
||
593 | seq_printf(m, "PCIE_TX_GART_CNTL 0x%08x\n", tmp); |
||
594 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_BASE); |
||
595 | seq_printf(m, "PCIE_TX_GART_BASE 0x%08x\n", tmp); |
||
596 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_LO); |
||
597 | seq_printf(m, "PCIE_TX_GART_START_LO 0x%08x\n", tmp); |
||
598 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_HI); |
||
599 | seq_printf(m, "PCIE_TX_GART_START_HI 0x%08x\n", tmp); |
||
600 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_LO); |
||
601 | seq_printf(m, "PCIE_TX_GART_END_LO 0x%08x\n", tmp); |
||
602 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_HI); |
||
603 | seq_printf(m, "PCIE_TX_GART_END_HI 0x%08x\n", tmp); |
||
604 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_ERROR); |
||
605 | seq_printf(m, "PCIE_TX_GART_ERROR 0x%08x\n", tmp); |
||
606 | return 0; |
||
607 | } |
||
608 | |||
609 | static struct drm_info_list rv370_pcie_gart_info_list[] = { |
||
610 | {"rv370_pcie_gart_info", rv370_debugfs_pcie_gart_info, 0, NULL}, |
||
611 | }; |
||
612 | #endif |
||
613 | |||
1221 | serge | 614 | static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev) |
1120 | serge | 615 | { |
616 | #if defined(CONFIG_DEBUG_FS) |
||
617 | return radeon_debugfs_add_files(rdev, rv370_pcie_gart_info_list, 1); |
||
618 | #else |
||
619 | return 0; |
||
620 | #endif |
||
621 | } |
||
622 | |||
623 | |||
1128 | serge | 624 | #if 0 |
1221 | serge | 625 | |
1120 | serge | 626 | static int r300_packet0_check(struct radeon_cs_parser *p, |
627 | struct radeon_cs_packet *pkt, |
||
628 | unsigned idx, unsigned reg) |
||
629 | { |
||
630 | struct radeon_cs_reloc *reloc; |
||
1179 | serge | 631 | struct r100_cs_track *track; |
1120 | serge | 632 | volatile uint32_t *ib; |
1179 | serge | 633 | uint32_t tmp, tile_flags = 0; |
1120 | serge | 634 | unsigned i; |
635 | int r; |
||
1221 | serge | 636 | u32 idx_value; |
1120 | serge | 637 | |
638 | ib = p->ib->ptr; |
||
1179 | serge | 639 | track = (struct r100_cs_track *)p->track; |
1221 | serge | 640 | idx_value = radeon_get_ib_value(p, idx); |
641 | |||
1120 | serge | 642 | switch(reg) { |
1179 | serge | 643 | case AVIVO_D1MODE_VLINE_START_END: |
644 | case RADEON_CRTC_GUI_TRIG_VLINE: |
||
645 | r = r100_cs_packet_parse_vline(p); |
||
1120 | serge | 646 | if (r) { |
647 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
||
648 | idx, reg); |
||
649 | r100_cs_dump_packet(p, pkt); |
||
650 | return r; |
||
651 | } |
||
652 | break; |
||
1179 | serge | 653 | case RADEON_DST_PITCH_OFFSET: |
654 | case RADEON_SRC_PITCH_OFFSET: |
||
655 | r = r100_reloc_pitch_offset(p, pkt, idx, reg); |
||
656 | if (r) |
||
657 | return r; |
||
658 | break; |
||
1120 | serge | 659 | case R300_RB3D_COLOROFFSET0: |
660 | case R300_RB3D_COLOROFFSET1: |
||
661 | case R300_RB3D_COLOROFFSET2: |
||
662 | case R300_RB3D_COLOROFFSET3: |
||
663 | i = (reg - R300_RB3D_COLOROFFSET0) >> 2; |
||
664 | r = r100_cs_packet_next_reloc(p, &reloc); |
||
665 | if (r) { |
||
666 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
||
667 | idx, reg); |
||
668 | r100_cs_dump_packet(p, pkt); |
||
669 | return r; |
||
670 | } |
||
671 | track->cb[i].robj = reloc->robj; |
||
1221 | serge | 672 | track->cb[i].offset = idx_value; |
1963 | serge | 673 | track->cb_dirty = true; |
1221 | serge | 674 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
1120 | serge | 675 | break; |
676 | case R300_ZB_DEPTHOFFSET: |
||
677 | r = r100_cs_packet_next_reloc(p, &reloc); |
||
678 | if (r) { |
||
679 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
||
680 | idx, reg); |
||
681 | r100_cs_dump_packet(p, pkt); |
||
682 | return r; |
||
683 | } |
||
684 | track->zb.robj = reloc->robj; |
||
1221 | serge | 685 | track->zb.offset = idx_value; |
1963 | serge | 686 | track->zb_dirty = true; |
1221 | serge | 687 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
1120 | serge | 688 | break; |
689 | case R300_TX_OFFSET_0: |
||
690 | case R300_TX_OFFSET_0+4: |
||
691 | case R300_TX_OFFSET_0+8: |
||
692 | case R300_TX_OFFSET_0+12: |
||
693 | case R300_TX_OFFSET_0+16: |
||
694 | case R300_TX_OFFSET_0+20: |
||
695 | case R300_TX_OFFSET_0+24: |
||
696 | case R300_TX_OFFSET_0+28: |
||
697 | case R300_TX_OFFSET_0+32: |
||
698 | case R300_TX_OFFSET_0+36: |
||
699 | case R300_TX_OFFSET_0+40: |
||
700 | case R300_TX_OFFSET_0+44: |
||
701 | case R300_TX_OFFSET_0+48: |
||
702 | case R300_TX_OFFSET_0+52: |
||
703 | case R300_TX_OFFSET_0+56: |
||
704 | case R300_TX_OFFSET_0+60: |
||
705 | i = (reg - R300_TX_OFFSET_0) >> 2; |
||
706 | r = r100_cs_packet_next_reloc(p, &reloc); |
||
707 | if (r) { |
||
708 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
||
709 | idx, reg); |
||
710 | r100_cs_dump_packet(p, pkt); |
||
711 | return r; |
||
712 | } |
||
1403 | serge | 713 | |
714 | if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) |
||
715 | tile_flags |= R300_TXO_MACRO_TILE; |
||
716 | if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) |
||
717 | tile_flags |= R300_TXO_MICRO_TILE; |
||
1430 | serge | 718 | else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE) |
719 | tile_flags |= R300_TXO_MICRO_TILE_SQUARE; |
||
1403 | serge | 720 | |
721 | tmp = idx_value + ((u32)reloc->lobj.gpu_offset); |
||
722 | tmp |= tile_flags; |
||
723 | ib[idx] = tmp; |
||
1120 | serge | 724 | track->textures[i].robj = reloc->robj; |
1963 | serge | 725 | track->tex_dirty = true; |
1120 | serge | 726 | break; |
727 | /* Tracked registers */ |
||
728 | case 0x2084: |
||
729 | /* VAP_VF_CNTL */ |
||
1221 | serge | 730 | track->vap_vf_cntl = idx_value; |
1120 | serge | 731 | break; |
732 | case 0x20B4: |
||
733 | /* VAP_VTX_SIZE */ |
||
1221 | serge | 734 | track->vtx_size = idx_value & 0x7F; |
1120 | serge | 735 | break; |
736 | case 0x2134: |
||
737 | /* VAP_VF_MAX_VTX_INDX */ |
||
1221 | serge | 738 | track->max_indx = idx_value & 0x00FFFFFFUL; |
1120 | serge | 739 | break; |
1963 | serge | 740 | case 0x2088: |
741 | /* VAP_ALT_NUM_VERTICES - only valid on r500 */ |
||
742 | if (p->rdev->family < CHIP_RV515) |
||
743 | goto fail; |
||
744 | track->vap_alt_nverts = idx_value & 0xFFFFFF; |
||
745 | break; |
||
1120 | serge | 746 | case 0x43E4: |
747 | /* SC_SCISSOR1 */ |
||
1221 | serge | 748 | track->maxy = ((idx_value >> 13) & 0x1FFF) + 1; |
1120 | serge | 749 | if (p->rdev->family < CHIP_RV515) { |
750 | track->maxy -= 1440; |
||
751 | } |
||
1963 | serge | 752 | track->cb_dirty = true; |
753 | track->zb_dirty = true; |
||
1120 | serge | 754 | break; |
755 | case 0x4E00: |
||
756 | /* RB3D_CCTL */ |
||
1963 | serge | 757 | if ((idx_value & (1 << 10)) && /* CMASK_ENABLE */ |
758 | p->rdev->cmask_filp != p->filp) { |
||
759 | DRM_ERROR("Invalid RB3D_CCTL: Cannot enable CMASK.\n"); |
||
760 | return -EINVAL; |
||
761 | } |
||
1221 | serge | 762 | track->num_cb = ((idx_value >> 5) & 0x3) + 1; |
1963 | serge | 763 | track->cb_dirty = true; |
1120 | serge | 764 | break; |
765 | case 0x4E38: |
||
766 | case 0x4E3C: |
||
767 | case 0x4E40: |
||
768 | case 0x4E44: |
||
769 | /* RB3D_COLORPITCH0 */ |
||
770 | /* RB3D_COLORPITCH1 */ |
||
771 | /* RB3D_COLORPITCH2 */ |
||
772 | /* RB3D_COLORPITCH3 */ |
||
1179 | serge | 773 | r = r100_cs_packet_next_reloc(p, &reloc); |
774 | if (r) { |
||
775 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
||
776 | idx, reg); |
||
777 | r100_cs_dump_packet(p, pkt); |
||
778 | return r; |
||
779 | } |
||
780 | |||
781 | if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) |
||
782 | tile_flags |= R300_COLOR_TILE_ENABLE; |
||
783 | if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) |
||
784 | tile_flags |= R300_COLOR_MICROTILE_ENABLE; |
||
1430 | serge | 785 | else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE) |
786 | tile_flags |= R300_COLOR_MICROTILE_SQUARE_ENABLE; |
||
1179 | serge | 787 | |
1221 | serge | 788 | tmp = idx_value & ~(0x7 << 16); |
1179 | serge | 789 | tmp |= tile_flags; |
790 | ib[idx] = tmp; |
||
1120 | serge | 791 | i = (reg - 0x4E38) >> 2; |
1221 | serge | 792 | track->cb[i].pitch = idx_value & 0x3FFE; |
793 | switch (((idx_value >> 21) & 0xF)) { |
||
1120 | serge | 794 | case 9: |
795 | case 11: |
||
796 | case 12: |
||
797 | track->cb[i].cpp = 1; |
||
798 | break; |
||
799 | case 3: |
||
800 | case 4: |
||
801 | case 13: |
||
802 | case 15: |
||
803 | track->cb[i].cpp = 2; |
||
804 | break; |
||
1963 | serge | 805 | case 5: |
806 | if (p->rdev->family < CHIP_RV515) { |
||
807 | DRM_ERROR("Invalid color buffer format (%d)!\n", |
||
808 | ((idx_value >> 21) & 0xF)); |
||
809 | return -EINVAL; |
||
810 | } |
||
811 | /* Pass through. */ |
||
1120 | serge | 812 | case 6: |
813 | track->cb[i].cpp = 4; |
||
814 | break; |
||
815 | case 10: |
||
816 | track->cb[i].cpp = 8; |
||
817 | break; |
||
818 | case 7: |
||
819 | track->cb[i].cpp = 16; |
||
820 | break; |
||
821 | default: |
||
822 | DRM_ERROR("Invalid color buffer format (%d) !\n", |
||
1221 | serge | 823 | ((idx_value >> 21) & 0xF)); |
1120 | serge | 824 | return -EINVAL; |
825 | } |
||
1963 | serge | 826 | track->cb_dirty = true; |
1120 | serge | 827 | break; |
828 | case 0x4F00: |
||
829 | /* ZB_CNTL */ |
||
1221 | serge | 830 | if (idx_value & 2) { |
1120 | serge | 831 | track->z_enabled = true; |
832 | } else { |
||
833 | track->z_enabled = false; |
||
834 | } |
||
1963 | serge | 835 | track->zb_dirty = true; |
1120 | serge | 836 | break; |
837 | case 0x4F10: |
||
838 | /* ZB_FORMAT */ |
||
1221 | serge | 839 | switch ((idx_value & 0xF)) { |
1120 | serge | 840 | case 0: |
841 | case 1: |
||
842 | track->zb.cpp = 2; |
||
843 | break; |
||
844 | case 2: |
||
845 | track->zb.cpp = 4; |
||
846 | break; |
||
847 | default: |
||
848 | DRM_ERROR("Invalid z buffer format (%d) !\n", |
||
1221 | serge | 849 | (idx_value & 0xF)); |
1120 | serge | 850 | return -EINVAL; |
851 | } |
||
1963 | serge | 852 | track->zb_dirty = true; |
1120 | serge | 853 | break; |
854 | case 0x4F24: |
||
855 | /* ZB_DEPTHPITCH */ |
||
1179 | serge | 856 | r = r100_cs_packet_next_reloc(p, &reloc); |
857 | if (r) { |
||
858 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
||
859 | idx, reg); |
||
860 | r100_cs_dump_packet(p, pkt); |
||
861 | return r; |
||
862 | } |
||
863 | |||
864 | if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) |
||
865 | tile_flags |= R300_DEPTHMACROTILE_ENABLE; |
||
866 | if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) |
||
1430 | serge | 867 | tile_flags |= R300_DEPTHMICROTILE_TILED; |
868 | else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE) |
||
869 | tile_flags |= R300_DEPTHMICROTILE_TILED_SQUARE; |
||
1179 | serge | 870 | |
1221 | serge | 871 | tmp = idx_value & ~(0x7 << 16); |
1179 | serge | 872 | tmp |= tile_flags; |
873 | ib[idx] = tmp; |
||
874 | |||
1221 | serge | 875 | track->zb.pitch = idx_value & 0x3FFC; |
1963 | serge | 876 | track->zb_dirty = true; |
1120 | serge | 877 | break; |
878 | case 0x4104: |
||
1963 | serge | 879 | /* TX_ENABLE */ |
1120 | serge | 880 | for (i = 0; i < 16; i++) { |
881 | bool enabled; |
||
882 | |||
1221 | serge | 883 | enabled = !!(idx_value & (1 << i)); |
1120 | serge | 884 | track->textures[i].enabled = enabled; |
885 | } |
||
1963 | serge | 886 | track->tex_dirty = true; |
1120 | serge | 887 | break; |
888 | case 0x44C0: |
||
889 | case 0x44C4: |
||
890 | case 0x44C8: |
||
891 | case 0x44CC: |
||
892 | case 0x44D0: |
||
893 | case 0x44D4: |
||
894 | case 0x44D8: |
||
895 | case 0x44DC: |
||
896 | case 0x44E0: |
||
897 | case 0x44E4: |
||
898 | case 0x44E8: |
||
899 | case 0x44EC: |
||
900 | case 0x44F0: |
||
901 | case 0x44F4: |
||
902 | case 0x44F8: |
||
903 | case 0x44FC: |
||
904 | /* TX_FORMAT1_[0-15] */ |
||
905 | i = (reg - 0x44C0) >> 2; |
||
1221 | serge | 906 | tmp = (idx_value >> 25) & 0x3; |
1120 | serge | 907 | track->textures[i].tex_coord_type = tmp; |
1221 | serge | 908 | switch ((idx_value & 0x1F)) { |
1179 | serge | 909 | case R300_TX_FORMAT_X8: |
910 | case R300_TX_FORMAT_Y4X4: |
||
911 | case R300_TX_FORMAT_Z3Y3X2: |
||
1120 | serge | 912 | track->textures[i].cpp = 1; |
1963 | serge | 913 | track->textures[i].compress_format = R100_TRACK_COMP_NONE; |
1120 | serge | 914 | break; |
1179 | serge | 915 | case R300_TX_FORMAT_X16: |
1963 | serge | 916 | case R300_TX_FORMAT_FL_I16: |
1179 | serge | 917 | case R300_TX_FORMAT_Y8X8: |
918 | case R300_TX_FORMAT_Z5Y6X5: |
||
919 | case R300_TX_FORMAT_Z6Y5X5: |
||
920 | case R300_TX_FORMAT_W4Z4Y4X4: |
||
921 | case R300_TX_FORMAT_W1Z5Y5X5: |
||
922 | case R300_TX_FORMAT_D3DMFT_CxV8U8: |
||
923 | case R300_TX_FORMAT_B8G8_B8G8: |
||
924 | case R300_TX_FORMAT_G8R8_G8B8: |
||
1120 | serge | 925 | track->textures[i].cpp = 2; |
1963 | serge | 926 | track->textures[i].compress_format = R100_TRACK_COMP_NONE; |
1120 | serge | 927 | break; |
1179 | serge | 928 | case R300_TX_FORMAT_Y16X16: |
1963 | serge | 929 | case R300_TX_FORMAT_FL_I16A16: |
1179 | serge | 930 | case R300_TX_FORMAT_Z11Y11X10: |
931 | case R300_TX_FORMAT_Z10Y11X11: |
||
932 | case R300_TX_FORMAT_W8Z8Y8X8: |
||
933 | case R300_TX_FORMAT_W2Z10Y10X10: |
||
934 | case 0x17: |
||
935 | case R300_TX_FORMAT_FL_I32: |
||
936 | case 0x1e: |
||
1120 | serge | 937 | track->textures[i].cpp = 4; |
1963 | serge | 938 | track->textures[i].compress_format = R100_TRACK_COMP_NONE; |
1120 | serge | 939 | break; |
1179 | serge | 940 | case R300_TX_FORMAT_W16Z16Y16X16: |
941 | case R300_TX_FORMAT_FL_R16G16B16A16: |
||
942 | case R300_TX_FORMAT_FL_I32A32: |
||
1120 | serge | 943 | track->textures[i].cpp = 8; |
1963 | serge | 944 | track->textures[i].compress_format = R100_TRACK_COMP_NONE; |
1120 | serge | 945 | break; |
1179 | serge | 946 | case R300_TX_FORMAT_FL_R32G32B32A32: |
1120 | serge | 947 | track->textures[i].cpp = 16; |
1963 | serge | 948 | track->textures[i].compress_format = R100_TRACK_COMP_NONE; |
1120 | serge | 949 | break; |
1403 | serge | 950 | case R300_TX_FORMAT_DXT1: |
951 | track->textures[i].cpp = 1; |
||
952 | track->textures[i].compress_format = R100_TRACK_COMP_DXT1; |
||
953 | break; |
||
954 | case R300_TX_FORMAT_ATI2N: |
||
955 | if (p->rdev->family < CHIP_R420) { |
||
956 | DRM_ERROR("Invalid texture format %u\n", |
||
957 | (idx_value & 0x1F)); |
||
958 | return -EINVAL; |
||
959 | } |
||
960 | /* The same rules apply as for DXT3/5. */ |
||
961 | /* Pass through. */ |
||
962 | case R300_TX_FORMAT_DXT3: |
||
963 | case R300_TX_FORMAT_DXT5: |
||
964 | track->textures[i].cpp = 1; |
||
965 | track->textures[i].compress_format = R100_TRACK_COMP_DXT35; |
||
966 | break; |
||
1120 | serge | 967 | default: |
968 | DRM_ERROR("Invalid texture format %u\n", |
||
1221 | serge | 969 | (idx_value & 0x1F)); |
1120 | serge | 970 | return -EINVAL; |
971 | } |
||
1963 | serge | 972 | track->tex_dirty = true; |
1120 | serge | 973 | break; |
974 | case 0x4400: |
||
975 | case 0x4404: |
||
976 | case 0x4408: |
||
977 | case 0x440C: |
||
978 | case 0x4410: |
||
979 | case 0x4414: |
||
980 | case 0x4418: |
||
981 | case 0x441C: |
||
982 | case 0x4420: |
||
983 | case 0x4424: |
||
984 | case 0x4428: |
||
985 | case 0x442C: |
||
986 | case 0x4430: |
||
987 | case 0x4434: |
||
988 | case 0x4438: |
||
989 | case 0x443C: |
||
990 | /* TX_FILTER0_[0-15] */ |
||
991 | i = (reg - 0x4400) >> 2; |
||
1221 | serge | 992 | tmp = idx_value & 0x7; |
1120 | serge | 993 | if (tmp == 2 || tmp == 4 || tmp == 6) { |
994 | track->textures[i].roundup_w = false; |
||
995 | } |
||
1221 | serge | 996 | tmp = (idx_value >> 3) & 0x7; |
1120 | serge | 997 | if (tmp == 2 || tmp == 4 || tmp == 6) { |
998 | track->textures[i].roundup_h = false; |
||
999 | } |
||
1963 | serge | 1000 | track->tex_dirty = true; |
1120 | serge | 1001 | break; |
1002 | case 0x4500: |
||
1003 | case 0x4504: |
||
1004 | case 0x4508: |
||
1005 | case 0x450C: |
||
1006 | case 0x4510: |
||
1007 | case 0x4514: |
||
1008 | case 0x4518: |
||
1009 | case 0x451C: |
||
1010 | case 0x4520: |
||
1011 | case 0x4524: |
||
1012 | case 0x4528: |
||
1013 | case 0x452C: |
||
1014 | case 0x4530: |
||
1015 | case 0x4534: |
||
1016 | case 0x4538: |
||
1017 | case 0x453C: |
||
1018 | /* TX_FORMAT2_[0-15] */ |
||
1019 | i = (reg - 0x4500) >> 2; |
||
1221 | serge | 1020 | tmp = idx_value & 0x3FFF; |
1120 | serge | 1021 | track->textures[i].pitch = tmp + 1; |
1022 | if (p->rdev->family >= CHIP_RV515) { |
||
1221 | serge | 1023 | tmp = ((idx_value >> 15) & 1) << 11; |
1120 | serge | 1024 | track->textures[i].width_11 = tmp; |
1221 | serge | 1025 | tmp = ((idx_value >> 16) & 1) << 11; |
1120 | serge | 1026 | track->textures[i].height_11 = tmp; |
1403 | serge | 1027 | |
1028 | /* ATI1N */ |
||
1029 | if (idx_value & (1 << 14)) { |
||
1030 | /* The same rules apply as for DXT1. */ |
||
1031 | track->textures[i].compress_format = |
||
1032 | R100_TRACK_COMP_DXT1; |
||
1033 | } |
||
1034 | } else if (idx_value & (1 << 14)) { |
||
1035 | DRM_ERROR("Forbidden bit TXFORMAT_MSB\n"); |
||
1036 | return -EINVAL; |
||
1120 | serge | 1037 | } |
1963 | serge | 1038 | track->tex_dirty = true; |
1120 | serge | 1039 | break; |
1040 | case 0x4480: |
||
1041 | case 0x4484: |
||
1042 | case 0x4488: |
||
1043 | case 0x448C: |
||
1044 | case 0x4490: |
||
1045 | case 0x4494: |
||
1046 | case 0x4498: |
||
1047 | case 0x449C: |
||
1048 | case 0x44A0: |
||
1049 | case 0x44A4: |
||
1050 | case 0x44A8: |
||
1051 | case 0x44AC: |
||
1052 | case 0x44B0: |
||
1053 | case 0x44B4: |
||
1054 | case 0x44B8: |
||
1055 | case 0x44BC: |
||
1056 | /* TX_FORMAT0_[0-15] */ |
||
1057 | i = (reg - 0x4480) >> 2; |
||
1221 | serge | 1058 | tmp = idx_value & 0x7FF; |
1120 | serge | 1059 | track->textures[i].width = tmp + 1; |
1221 | serge | 1060 | tmp = (idx_value >> 11) & 0x7FF; |
1120 | serge | 1061 | track->textures[i].height = tmp + 1; |
1221 | serge | 1062 | tmp = (idx_value >> 26) & 0xF; |
1120 | serge | 1063 | track->textures[i].num_levels = tmp; |
1221 | serge | 1064 | tmp = idx_value & (1 << 31); |
1120 | serge | 1065 | track->textures[i].use_pitch = !!tmp; |
1221 | serge | 1066 | tmp = (idx_value >> 22) & 0xF; |
1120 | serge | 1067 | track->textures[i].txdepth = tmp; |
1963 | serge | 1068 | track->tex_dirty = true; |
1120 | serge | 1069 | break; |
1179 | serge | 1070 | case R300_ZB_ZPASS_ADDR: |
1071 | r = r100_cs_packet_next_reloc(p, &reloc); |
||
1072 | if (r) { |
||
1073 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
||
1074 | idx, reg); |
||
1075 | r100_cs_dump_packet(p, pkt); |
||
1076 | return r; |
||
1077 | } |
||
1221 | serge | 1078 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
1179 | serge | 1079 | break; |
1403 | serge | 1080 | case 0x4e0c: |
1081 | /* RB3D_COLOR_CHANNEL_MASK */ |
||
1082 | track->color_channel_mask = idx_value; |
||
1963 | serge | 1083 | track->cb_dirty = true; |
1403 | serge | 1084 | break; |
1963 | serge | 1085 | case 0x43a4: |
1086 | /* SC_HYPERZ_EN */ |
||
1087 | /* r300c emits this register - we need to disable hyperz for it |
||
1088 | * without complaining */ |
||
1089 | if (p->rdev->hyperz_filp != p->filp) { |
||
1090 | if (idx_value & 0x1) |
||
1091 | ib[idx] = idx_value & ~1; |
||
1092 | } |
||
1093 | break; |
||
1094 | case 0x4f1c: |
||
1403 | serge | 1095 | /* ZB_BW_CNTL */ |
1963 | serge | 1096 | track->zb_cb_clear = !!(idx_value & (1 << 5)); |
1097 | track->cb_dirty = true; |
||
1098 | track->zb_dirty = true; |
||
1099 | if (p->rdev->hyperz_filp != p->filp) { |
||
1100 | if (idx_value & (R300_HIZ_ENABLE | |
||
1101 | R300_RD_COMP_ENABLE | |
||
1102 | R300_WR_COMP_ENABLE | |
||
1103 | R300_FAST_FILL_ENABLE)) |
||
1104 | goto fail; |
||
1105 | } |
||
1403 | serge | 1106 | break; |
1107 | case 0x4e04: |
||
1108 | /* RB3D_BLENDCNTL */ |
||
1109 | track->blend_read_enable = !!(idx_value & (1 << 2)); |
||
1963 | serge | 1110 | track->cb_dirty = true; |
1403 | serge | 1111 | break; |
1963 | serge | 1112 | case R300_RB3D_AARESOLVE_OFFSET: |
1113 | r = r100_cs_packet_next_reloc(p, &reloc); |
||
1114 | if (r) { |
||
1115 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
||
1116 | idx, reg); |
||
1117 | r100_cs_dump_packet(p, pkt); |
||
1118 | return r; |
||
1119 | } |
||
1120 | track->aa.robj = reloc->robj; |
||
1121 | track->aa.offset = idx_value; |
||
1122 | track->aa_dirty = true; |
||
1123 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
||
1124 | break; |
||
1125 | case R300_RB3D_AARESOLVE_PITCH: |
||
1126 | track->aa.pitch = idx_value & 0x3FFE; |
||
1127 | track->aa_dirty = true; |
||
1128 | break; |
||
1129 | case R300_RB3D_AARESOLVE_CTL: |
||
1130 | track->aaresolve = idx_value & 0x1; |
||
1131 | track->aa_dirty = true; |
||
1132 | break; |
||
1133 | case 0x4f30: /* ZB_MASK_OFFSET */ |
||
1134 | case 0x4f34: /* ZB_ZMASK_PITCH */ |
||
1135 | case 0x4f44: /* ZB_HIZ_OFFSET */ |
||
1136 | case 0x4f54: /* ZB_HIZ_PITCH */ |
||
1137 | if (idx_value && (p->rdev->hyperz_filp != p->filp)) |
||
1138 | goto fail; |
||
1139 | break; |
||
1140 | case 0x4028: |
||
1141 | if (idx_value && (p->rdev->hyperz_filp != p->filp)) |
||
1142 | goto fail; |
||
1143 | /* GB_Z_PEQ_CONFIG */ |
||
1144 | if (p->rdev->family >= CHIP_RV350) |
||
1145 | break; |
||
1146 | goto fail; |
||
1147 | break; |
||
1179 | serge | 1148 | case 0x4be8: |
1149 | /* valid register only on RV530 */ |
||
1150 | if (p->rdev->family == CHIP_RV530) |
||
1151 | break; |
||
1152 | /* fallthrough do not move */ |
||
1120 | serge | 1153 | default: |
1963 | serge | 1154 | goto fail; |
1120 | serge | 1155 | } |
1156 | return 0; |
||
1963 | serge | 1157 | fail: |
1158 | printk(KERN_ERR "Forbidden register 0x%04X in cs at %d (val=%08x)\n", |
||
1159 | reg, idx, idx_value); |
||
1160 | return -EINVAL; |
||
1120 | serge | 1161 | } |
1162 | |||
1163 | static int r300_packet3_check(struct radeon_cs_parser *p, |
||
1164 | struct radeon_cs_packet *pkt) |
||
1165 | { |
||
1166 | struct radeon_cs_reloc *reloc; |
||
1179 | serge | 1167 | struct r100_cs_track *track; |
1120 | serge | 1168 | volatile uint32_t *ib; |
1169 | unsigned idx; |
||
1170 | int r; |
||
1171 | |||
1172 | ib = p->ib->ptr; |
||
1173 | idx = pkt->idx + 1; |
||
1179 | serge | 1174 | track = (struct r100_cs_track *)p->track; |
1120 | serge | 1175 | switch(pkt->opcode) { |
1176 | case PACKET3_3D_LOAD_VBPNTR: |
||
1221 | serge | 1177 | r = r100_packet3_load_vbpntr(p, pkt, idx); |
1178 | if (r) |
||
1120 | serge | 1179 | return r; |
1180 | break; |
||
1181 | case PACKET3_INDX_BUFFER: |
||
1182 | r = r100_cs_packet_next_reloc(p, &reloc); |
||
1183 | if (r) { |
||
1184 | DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode); |
||
1185 | r100_cs_dump_packet(p, pkt); |
||
1186 | return r; |
||
1187 | } |
||
1221 | serge | 1188 | ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset); |
1120 | serge | 1189 | r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj); |
1190 | if (r) { |
||
1191 | return r; |
||
1192 | } |
||
1193 | break; |
||
1194 | /* Draw packet */ |
||
1195 | case PACKET3_3D_DRAW_IMMD: |
||
1196 | /* Number of dwords is vtx_size * (num_vertices - 1) |
||
1197 | * PRIM_WALK must be equal to 3 vertex data in embedded |
||
1198 | * in cmd stream */ |
||
1221 | serge | 1199 | if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) { |
1120 | serge | 1200 | DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); |
1201 | return -EINVAL; |
||
1202 | } |
||
1221 | serge | 1203 | track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); |
1120 | serge | 1204 | track->immd_dwords = pkt->count - 1; |
1179 | serge | 1205 | r = r100_cs_track_check(p->rdev, track); |
1120 | serge | 1206 | if (r) { |
1207 | return r; |
||
1208 | } |
||
1209 | break; |
||
1210 | case PACKET3_3D_DRAW_IMMD_2: |
||
1211 | /* Number of dwords is vtx_size * (num_vertices - 1) |
||
1212 | * PRIM_WALK must be equal to 3 vertex data in embedded |
||
1213 | * in cmd stream */ |
||
1221 | serge | 1214 | if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) { |
1120 | serge | 1215 | DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); |
1216 | return -EINVAL; |
||
1217 | } |
||
1221 | serge | 1218 | track->vap_vf_cntl = radeon_get_ib_value(p, idx); |
1120 | serge | 1219 | track->immd_dwords = pkt->count; |
1179 | serge | 1220 | r = r100_cs_track_check(p->rdev, track); |
1120 | serge | 1221 | if (r) { |
1222 | return r; |
||
1223 | } |
||
1224 | break; |
||
1225 | case PACKET3_3D_DRAW_VBUF: |
||
1221 | serge | 1226 | track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); |
1179 | serge | 1227 | r = r100_cs_track_check(p->rdev, track); |
1120 | serge | 1228 | if (r) { |
1229 | return r; |
||
1230 | } |
||
1231 | break; |
||
1232 | case PACKET3_3D_DRAW_VBUF_2: |
||
1221 | serge | 1233 | track->vap_vf_cntl = radeon_get_ib_value(p, idx); |
1179 | serge | 1234 | r = r100_cs_track_check(p->rdev, track); |
1120 | serge | 1235 | if (r) { |
1236 | return r; |
||
1237 | } |
||
1238 | break; |
||
1239 | case PACKET3_3D_DRAW_INDX: |
||
1221 | serge | 1240 | track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); |
1179 | serge | 1241 | r = r100_cs_track_check(p->rdev, track); |
1120 | serge | 1242 | if (r) { |
1243 | return r; |
||
1244 | } |
||
1245 | break; |
||
1246 | case PACKET3_3D_DRAW_INDX_2: |
||
1221 | serge | 1247 | track->vap_vf_cntl = radeon_get_ib_value(p, idx); |
1179 | serge | 1248 | r = r100_cs_track_check(p->rdev, track); |
1120 | serge | 1249 | if (r) { |
1250 | return r; |
||
1251 | } |
||
1252 | break; |
||
1963 | serge | 1253 | case PACKET3_3D_CLEAR_HIZ: |
1254 | case PACKET3_3D_CLEAR_ZMASK: |
||
1255 | if (p->rdev->hyperz_filp != p->filp) |
||
1256 | return -EINVAL; |
||
1257 | break; |
||
1258 | case PACKET3_3D_CLEAR_CMASK: |
||
1259 | if (p->rdev->cmask_filp != p->filp) |
||
1260 | return -EINVAL; |
||
1261 | break; |
||
1120 | serge | 1262 | case PACKET3_NOP: |
1263 | break; |
||
1264 | default: |
||
1265 | DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode); |
||
1266 | return -EINVAL; |
||
1267 | } |
||
1268 | return 0; |
||
1269 | } |
||
1270 | |||
1271 | int r300_cs_parse(struct radeon_cs_parser *p) |
||
1272 | { |
||
1273 | struct radeon_cs_packet pkt; |
||
1179 | serge | 1274 | struct r100_cs_track *track; |
1120 | serge | 1275 | int r; |
1276 | |||
1179 | serge | 1277 | track = kzalloc(sizeof(*track), GFP_KERNEL); |
1963 | serge | 1278 | if (track == NULL) |
1279 | return -ENOMEM; |
||
1179 | serge | 1280 | r100_cs_track_clear(p->rdev, track); |
1281 | p->track = track; |
||
1120 | serge | 1282 | do { |
1283 | r = r100_cs_packet_parse(p, &pkt, p->idx); |
||
1284 | if (r) { |
||
1285 | return r; |
||
1286 | } |
||
1287 | p->idx += pkt.count + 2; |
||
1288 | switch (pkt.type) { |
||
1289 | case PACKET_TYPE0: |
||
1290 | r = r100_cs_parse_packet0(p, &pkt, |
||
1291 | p->rdev->config.r300.reg_safe_bm, |
||
1292 | p->rdev->config.r300.reg_safe_bm_size, |
||
1293 | &r300_packet0_check); |
||
1294 | break; |
||
1295 | case PACKET_TYPE2: |
||
1296 | break; |
||
1297 | case PACKET_TYPE3: |
||
1298 | r = r300_packet3_check(p, &pkt); |
||
1299 | break; |
||
1300 | default: |
||
1301 | DRM_ERROR("Unknown packet type %d !\n", pkt.type); |
||
1302 | return -EINVAL; |
||
1303 | } |
||
1304 | if (r) { |
||
1305 | return r; |
||
1306 | } |
||
1307 | } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw); |
||
1308 | return 0; |
||
1309 | } |
||
1128 | serge | 1310 | #endif |
1311 | |||
1179 | serge | 1312 | |
1313 | void r300_set_reg_safe(struct radeon_device *rdev) |
||
1120 | serge | 1314 | { |
1315 | rdev->config.r300.reg_safe_bm = r300_reg_safe_bm; |
||
1316 | rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r300_reg_safe_bm); |
||
1179 | serge | 1317 | } |
1318 | |||
1319 | void r300_mc_program(struct radeon_device *rdev) |
||
1320 | { |
||
1321 | struct r100_mc_save save; |
||
1322 | int r; |
||
1120 | serge | 1323 | |
1179 | serge | 1324 | r = r100_debugfs_mc_info_init(rdev); |
1325 | if (r) { |
||
1326 | dev_err(rdev->dev, "Failed to create r100_mc debugfs file.\n"); |
||
1327 | } |
||
1328 | |||
1329 | /* Stops all mc clients */ |
||
1330 | r100_mc_stop(rdev, &save); |
||
1331 | if (rdev->flags & RADEON_IS_AGP) { |
||
1332 | WREG32(R_00014C_MC_AGP_LOCATION, |
||
1333 | S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) | |
||
1334 | S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16)); |
||
1335 | WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); |
||
1336 | WREG32(R_00015C_AGP_BASE_2, |
||
1337 | upper_32_bits(rdev->mc.agp_base) & 0xff); |
||
1338 | } else { |
||
1339 | WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF); |
||
1340 | WREG32(R_000170_AGP_BASE, 0); |
||
1341 | WREG32(R_00015C_AGP_BASE_2, 0); |
||
1342 | } |
||
1343 | /* Wait for mc idle */ |
||
1344 | if (r300_mc_wait_for_idle(rdev)) |
||
1345 | DRM_INFO("Failed to wait MC idle before programming MC.\n"); |
||
1346 | /* Program MC, should be a 32bits limited address space */ |
||
1347 | WREG32(R_000148_MC_FB_LOCATION, |
||
1348 | S_000148_MC_FB_START(rdev->mc.vram_start >> 16) | |
||
1349 | S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16)); |
||
1350 | r100_mc_resume(rdev, &save); |
||
1351 | } |
||
1221 | serge | 1352 | |
1353 | void r300_clock_startup(struct radeon_device *rdev) |
||
1354 | { |
||
1355 | u32 tmp; |
||
1356 | |||
1357 | if (radeon_dynclks != -1 && radeon_dynclks) |
||
1358 | radeon_legacy_set_clock_gating(rdev, 1); |
||
1359 | /* We need to force on some of the block */ |
||
1360 | tmp = RREG32_PLL(R_00000D_SCLK_CNTL); |
||
1361 | tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1); |
||
1362 | if ((rdev->family == CHIP_RV350) || (rdev->family == CHIP_RV380)) |
||
1363 | tmp |= S_00000D_FORCE_VAP(1); |
||
1364 | WREG32_PLL(R_00000D_SCLK_CNTL, tmp); |
||
1365 | } |
||
1366 | |||
1367 | static int r300_startup(struct radeon_device *rdev) |
||
1368 | { |
||
1369 | int r; |
||
1370 | |||
1321 | serge | 1371 | /* set common regs */ |
1372 | r100_set_common_regs(rdev); |
||
1373 | /* program mc */ |
||
1221 | serge | 1374 | r300_mc_program(rdev); |
1375 | /* Resume clock */ |
||
1376 | r300_clock_startup(rdev); |
||
1377 | /* Initialize GPU configuration (# pipes, ...) */ |
||
1378 | r300_gpu_init(rdev); |
||
1379 | /* Initialize GART (initialize after TTM so we can allocate |
||
1380 | * memory through TTM but finalize after TTM) */ |
||
1381 | if (rdev->flags & RADEON_IS_PCIE) { |
||
1382 | r = rv370_pcie_gart_enable(rdev); |
||
1383 | if (r) |
||
1384 | return r; |
||
1385 | } |
||
1321 | serge | 1386 | |
1387 | if (rdev->family == CHIP_R300 || |
||
1388 | rdev->family == CHIP_R350 || |
||
1389 | rdev->family == CHIP_RV350) |
||
1390 | r100_enable_bm(rdev); |
||
1391 | |||
1221 | serge | 1392 | if (rdev->flags & RADEON_IS_PCI) { |
1393 | r = r100_pci_gart_enable(rdev); |
||
1394 | if (r) |
||
1395 | return r; |
||
1396 | } |
||
1963 | serge | 1397 | |
2005 | serge | 1398 | /* allocate wb buffer */ |
1399 | r = radeon_wb_init(rdev); |
||
1400 | if (r) |
||
1401 | return r; |
||
1963 | serge | 1402 | |
1221 | serge | 1403 | /* Enable IRQ */ |
2005 | serge | 1404 | r100_irq_set(rdev); |
1403 | serge | 1405 | rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); |
1221 | serge | 1406 | /* 1M ring buffer */ |
1412 | serge | 1407 | r = r100_cp_init(rdev, 1024 * 1024); |
1408 | if (r) { |
||
1963 | serge | 1409 | dev_err(rdev->dev, "failed initializing CP (%d).\n", r); |
1412 | serge | 1410 | return r; |
1411 | } |
||
2005 | serge | 1412 | r = r100_ib_init(rdev); |
1413 | if (r) { |
||
1414 | dev_err(rdev->dev, "failed initializing IB (%d).\n", r); |
||
1415 | return r; |
||
1416 | } |
||
1221 | serge | 1417 | return 0; |
1418 | } |
||
1419 | |||
1420 | |||
1421 | |||
1422 | |||
1423 | |||
1424 | int r300_init(struct radeon_device *rdev) |
||
1425 | { |
||
1426 | int r; |
||
1427 | |||
1428 | /* Disable VGA */ |
||
1429 | r100_vga_render_disable(rdev); |
||
1430 | /* Initialize scratch registers */ |
||
1431 | radeon_scratch_init(rdev); |
||
1432 | /* Initialize surface registers */ |
||
1433 | radeon_surface_init(rdev); |
||
1434 | /* TODO: disable VGA need to use VGA request */ |
||
1963 | serge | 1435 | /* restore some register to sane defaults */ |
1436 | r100_restore_sanity(rdev); |
||
1221 | serge | 1437 | /* BIOS*/ |
1438 | if (!radeon_get_bios(rdev)) { |
||
1439 | if (ASIC_IS_AVIVO(rdev)) |
||
1440 | return -EINVAL; |
||
1441 | } |
||
1442 | if (rdev->is_atom_bios) { |
||
1443 | dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n"); |
||
1444 | return -EINVAL; |
||
1445 | } else { |
||
1446 | r = radeon_combios_init(rdev); |
||
1447 | if (r) |
||
1448 | return r; |
||
1449 | } |
||
1450 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ |
||
1963 | serge | 1451 | if (radeon_asic_reset(rdev)) { |
1221 | serge | 1452 | dev_warn(rdev->dev, |
1453 | "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", |
||
1454 | RREG32(R_000E40_RBBM_STATUS), |
||
1455 | RREG32(R_0007C0_CP_STAT)); |
||
1456 | } |
||
1457 | /* check if cards are posted or not */ |
||
1321 | serge | 1458 | if (radeon_boot_test_post_card(rdev) == false) |
1459 | return -EINVAL; |
||
1221 | serge | 1460 | /* Set asic errata */ |
1461 | r300_errata(rdev); |
||
1462 | /* Initialize clocks */ |
||
1463 | radeon_get_clock_info(rdev->ddev); |
||
1430 | serge | 1464 | /* initialize AGP */ |
1465 | if (rdev->flags & RADEON_IS_AGP) { |
||
1466 | r = radeon_agp_init(rdev); |
||
1467 | if (r) { |
||
1468 | radeon_agp_disable(rdev); |
||
1469 | } |
||
1470 | } |
||
1471 | /* initialize memory controller */ |
||
1472 | r300_mc_init(rdev); |
||
1221 | serge | 1473 | /* Fence driver */ |
2005 | serge | 1474 | r = radeon_fence_driver_init(rdev); |
1475 | if (r) |
||
1476 | return r; |
||
1477 | r = radeon_irq_kms_init(rdev); |
||
1478 | if (r) |
||
1479 | return r; |
||
1221 | serge | 1480 | /* Memory manager */ |
1404 | serge | 1481 | r = radeon_bo_init(rdev); |
1221 | serge | 1482 | if (r) |
1483 | return r; |
||
1484 | if (rdev->flags & RADEON_IS_PCIE) { |
||
1485 | r = rv370_pcie_gart_init(rdev); |
||
1486 | if (r) |
||
1487 | return r; |
||
1488 | } |
||
1489 | if (rdev->flags & RADEON_IS_PCI) { |
||
1490 | r = r100_pci_gart_init(rdev); |
||
1491 | if (r) |
||
1492 | return r; |
||
1493 | } |
||
1494 | r300_set_reg_safe(rdev); |
||
1495 | rdev->accel_working = true; |
||
1496 | r = r300_startup(rdev); |
||
1497 | if (r) { |
||
1498 | /* Somethings want wront with the accel init stop accel */ |
||
1499 | dev_err(rdev->dev, "Disabling GPU acceleration\n"); |
||
1500 | if (rdev->flags & RADEON_IS_PCIE) |
||
1501 | rv370_pcie_gart_fini(rdev); |
||
1502 | if (rdev->flags & RADEON_IS_PCI) |
||
1503 | r100_pci_gart_fini(rdev); |
||
1504 | rdev->accel_working = false; |
||
1505 | } |
||
1506 | return 0; |
||
1507 | }>><>><>><>><>><>><>><>>><>>><>>><>><>>>><>><>>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>>><>><>> |