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1990 | serge | 1 | /* |
2 | * Copyright 2010 Advanced Micro Devices, Inc. |
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3 | * |
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4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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5 | * copy of this software and associated documentation files (the "Software"), |
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6 | * to deal in the Software without restriction, including without limitation |
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7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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8 | * and/or sell copies of the Software, and to permit persons to whom the |
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9 | * Software is furnished to do so, subject to the following conditions: |
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10 | * |
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11 | * The above copyright notice and this permission notice shall be included in |
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12 | * all copies or substantial portions of the Software. |
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13 | * |
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14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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20 | * OTHER DEALINGS IN THE SOFTWARE. |
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21 | * |
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22 | * Authors: Alex Deucher |
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23 | */ |
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24 | #include |
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25 | //#include |
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26 | #include |
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27 | #include "drmP.h" |
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28 | #include "radeon.h" |
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29 | #include "radeon_asic.h" |
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30 | #include "radeon_drm.h" |
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31 | #include "nid.h" |
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32 | #include "atom.h" |
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33 | #include "ni_reg.h" |
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2004 | serge | 34 | #include "cayman_blit_shaders.h" |
1990 | serge | 35 | |
36 | extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save); |
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37 | extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save); |
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38 | extern int evergreen_mc_wait_for_idle(struct radeon_device *rdev); |
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39 | extern void evergreen_mc_program(struct radeon_device *rdev); |
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40 | extern void evergreen_irq_suspend(struct radeon_device *rdev); |
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41 | extern int evergreen_mc_init(struct radeon_device *rdev); |
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42 | |||
43 | #define EVERGREEN_PFP_UCODE_SIZE 1120 |
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44 | #define EVERGREEN_PM4_UCODE_SIZE 1376 |
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45 | #define EVERGREEN_RLC_UCODE_SIZE 768 |
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46 | #define BTC_MC_UCODE_SIZE 6024 |
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47 | |||
48 | #define CAYMAN_PFP_UCODE_SIZE 2176 |
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49 | #define CAYMAN_PM4_UCODE_SIZE 2176 |
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50 | #define CAYMAN_RLC_UCODE_SIZE 1024 |
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51 | #define CAYMAN_MC_UCODE_SIZE 6037 |
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52 | |||
53 | /* Firmware Names */ |
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54 | MODULE_FIRMWARE("radeon/BARTS_pfp.bin"); |
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55 | MODULE_FIRMWARE("radeon/BARTS_me.bin"); |
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56 | MODULE_FIRMWARE("radeon/BARTS_mc.bin"); |
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57 | MODULE_FIRMWARE("radeon/BTC_rlc.bin"); |
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58 | MODULE_FIRMWARE("radeon/TURKS_pfp.bin"); |
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59 | MODULE_FIRMWARE("radeon/TURKS_me.bin"); |
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60 | MODULE_FIRMWARE("radeon/TURKS_mc.bin"); |
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61 | MODULE_FIRMWARE("radeon/CAICOS_pfp.bin"); |
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62 | MODULE_FIRMWARE("radeon/CAICOS_me.bin"); |
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63 | MODULE_FIRMWARE("radeon/CAICOS_mc.bin"); |
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64 | MODULE_FIRMWARE("radeon/CAYMAN_pfp.bin"); |
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65 | MODULE_FIRMWARE("radeon/CAYMAN_me.bin"); |
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66 | MODULE_FIRMWARE("radeon/CAYMAN_mc.bin"); |
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67 | MODULE_FIRMWARE("radeon/CAYMAN_rlc.bin"); |
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68 | |||
69 | #define BTC_IO_MC_REGS_SIZE 29 |
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70 | |||
71 | static const u32 barts_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = { |
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72 | {0x00000077, 0xff010100}, |
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73 | {0x00000078, 0x00000000}, |
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74 | {0x00000079, 0x00001434}, |
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75 | {0x0000007a, 0xcc08ec08}, |
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76 | {0x0000007b, 0x00040000}, |
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77 | {0x0000007c, 0x000080c0}, |
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78 | {0x0000007d, 0x09000000}, |
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79 | {0x0000007e, 0x00210404}, |
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80 | {0x00000081, 0x08a8e800}, |
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81 | {0x00000082, 0x00030444}, |
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82 | {0x00000083, 0x00000000}, |
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83 | {0x00000085, 0x00000001}, |
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84 | {0x00000086, 0x00000002}, |
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85 | {0x00000087, 0x48490000}, |
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86 | {0x00000088, 0x20244647}, |
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87 | {0x00000089, 0x00000005}, |
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88 | {0x0000008b, 0x66030000}, |
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89 | {0x0000008c, 0x00006603}, |
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90 | {0x0000008d, 0x00000100}, |
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91 | {0x0000008f, 0x00001c0a}, |
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92 | {0x00000090, 0xff000001}, |
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93 | {0x00000094, 0x00101101}, |
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94 | {0x00000095, 0x00000fff}, |
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95 | {0x00000096, 0x00116fff}, |
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96 | {0x00000097, 0x60010000}, |
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97 | {0x00000098, 0x10010000}, |
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98 | {0x00000099, 0x00006000}, |
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99 | {0x0000009a, 0x00001000}, |
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100 | {0x0000009f, 0x00946a00} |
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101 | }; |
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102 | |||
103 | static const u32 turks_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = { |
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104 | {0x00000077, 0xff010100}, |
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105 | {0x00000078, 0x00000000}, |
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106 | {0x00000079, 0x00001434}, |
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107 | {0x0000007a, 0xcc08ec08}, |
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108 | {0x0000007b, 0x00040000}, |
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109 | {0x0000007c, 0x000080c0}, |
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110 | {0x0000007d, 0x09000000}, |
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111 | {0x0000007e, 0x00210404}, |
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112 | {0x00000081, 0x08a8e800}, |
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113 | {0x00000082, 0x00030444}, |
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114 | {0x00000083, 0x00000000}, |
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115 | {0x00000085, 0x00000001}, |
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116 | {0x00000086, 0x00000002}, |
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117 | {0x00000087, 0x48490000}, |
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118 | {0x00000088, 0x20244647}, |
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119 | {0x00000089, 0x00000005}, |
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120 | {0x0000008b, 0x66030000}, |
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121 | {0x0000008c, 0x00006603}, |
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122 | {0x0000008d, 0x00000100}, |
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123 | {0x0000008f, 0x00001c0a}, |
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124 | {0x00000090, 0xff000001}, |
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125 | {0x00000094, 0x00101101}, |
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126 | {0x00000095, 0x00000fff}, |
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127 | {0x00000096, 0x00116fff}, |
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128 | {0x00000097, 0x60010000}, |
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129 | {0x00000098, 0x10010000}, |
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130 | {0x00000099, 0x00006000}, |
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131 | {0x0000009a, 0x00001000}, |
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132 | {0x0000009f, 0x00936a00} |
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133 | }; |
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134 | |||
135 | static const u32 caicos_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = { |
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136 | {0x00000077, 0xff010100}, |
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137 | {0x00000078, 0x00000000}, |
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138 | {0x00000079, 0x00001434}, |
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139 | {0x0000007a, 0xcc08ec08}, |
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140 | {0x0000007b, 0x00040000}, |
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141 | {0x0000007c, 0x000080c0}, |
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142 | {0x0000007d, 0x09000000}, |
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143 | {0x0000007e, 0x00210404}, |
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144 | {0x00000081, 0x08a8e800}, |
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145 | {0x00000082, 0x00030444}, |
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146 | {0x00000083, 0x00000000}, |
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147 | {0x00000085, 0x00000001}, |
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148 | {0x00000086, 0x00000002}, |
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149 | {0x00000087, 0x48490000}, |
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150 | {0x00000088, 0x20244647}, |
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151 | {0x00000089, 0x00000005}, |
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152 | {0x0000008b, 0x66030000}, |
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153 | {0x0000008c, 0x00006603}, |
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154 | {0x0000008d, 0x00000100}, |
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155 | {0x0000008f, 0x00001c0a}, |
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156 | {0x00000090, 0xff000001}, |
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157 | {0x00000094, 0x00101101}, |
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158 | {0x00000095, 0x00000fff}, |
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159 | {0x00000096, 0x00116fff}, |
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160 | {0x00000097, 0x60010000}, |
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161 | {0x00000098, 0x10010000}, |
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162 | {0x00000099, 0x00006000}, |
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163 | {0x0000009a, 0x00001000}, |
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164 | {0x0000009f, 0x00916a00} |
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165 | }; |
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166 | |||
167 | static const u32 cayman_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = { |
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168 | {0x00000077, 0xff010100}, |
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169 | {0x00000078, 0x00000000}, |
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170 | {0x00000079, 0x00001434}, |
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171 | {0x0000007a, 0xcc08ec08}, |
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172 | {0x0000007b, 0x00040000}, |
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173 | {0x0000007c, 0x000080c0}, |
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174 | {0x0000007d, 0x09000000}, |
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175 | {0x0000007e, 0x00210404}, |
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176 | {0x00000081, 0x08a8e800}, |
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177 | {0x00000082, 0x00030444}, |
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178 | {0x00000083, 0x00000000}, |
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179 | {0x00000085, 0x00000001}, |
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180 | {0x00000086, 0x00000002}, |
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181 | {0x00000087, 0x48490000}, |
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182 | {0x00000088, 0x20244647}, |
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183 | {0x00000089, 0x00000005}, |
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184 | {0x0000008b, 0x66030000}, |
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185 | {0x0000008c, 0x00006603}, |
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186 | {0x0000008d, 0x00000100}, |
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187 | {0x0000008f, 0x00001c0a}, |
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188 | {0x00000090, 0xff000001}, |
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189 | {0x00000094, 0x00101101}, |
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190 | {0x00000095, 0x00000fff}, |
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191 | {0x00000096, 0x00116fff}, |
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192 | {0x00000097, 0x60010000}, |
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193 | {0x00000098, 0x10010000}, |
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194 | {0x00000099, 0x00006000}, |
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195 | {0x0000009a, 0x00001000}, |
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196 | {0x0000009f, 0x00976b00} |
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197 | }; |
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198 | |||
199 | int ni_mc_load_microcode(struct radeon_device *rdev) |
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200 | { |
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201 | const __be32 *fw_data; |
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202 | u32 mem_type, running, blackout = 0; |
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203 | u32 *io_mc_regs; |
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204 | int i, ucode_size, regs_size; |
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205 | |||
206 | if (!rdev->mc_fw) |
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207 | return -EINVAL; |
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208 | |||
209 | switch (rdev->family) { |
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210 | case CHIP_BARTS: |
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211 | io_mc_regs = (u32 *)&barts_io_mc_regs; |
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212 | ucode_size = BTC_MC_UCODE_SIZE; |
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213 | regs_size = BTC_IO_MC_REGS_SIZE; |
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214 | break; |
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215 | case CHIP_TURKS: |
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216 | io_mc_regs = (u32 *)&turks_io_mc_regs; |
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217 | ucode_size = BTC_MC_UCODE_SIZE; |
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218 | regs_size = BTC_IO_MC_REGS_SIZE; |
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219 | break; |
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220 | case CHIP_CAICOS: |
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221 | default: |
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222 | io_mc_regs = (u32 *)&caicos_io_mc_regs; |
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223 | ucode_size = BTC_MC_UCODE_SIZE; |
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224 | regs_size = BTC_IO_MC_REGS_SIZE; |
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225 | break; |
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226 | case CHIP_CAYMAN: |
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227 | io_mc_regs = (u32 *)&cayman_io_mc_regs; |
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228 | ucode_size = CAYMAN_MC_UCODE_SIZE; |
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229 | regs_size = BTC_IO_MC_REGS_SIZE; |
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230 | break; |
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231 | } |
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232 | |||
233 | mem_type = (RREG32(MC_SEQ_MISC0) & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT; |
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234 | running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK; |
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235 | |||
236 | if ((mem_type == MC_SEQ_MISC0_GDDR5_VALUE) && (running == 0)) { |
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237 | if (running) { |
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238 | blackout = RREG32(MC_SHARED_BLACKOUT_CNTL); |
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239 | WREG32(MC_SHARED_BLACKOUT_CNTL, 1); |
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240 | } |
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241 | |||
242 | /* reset the engine and set to writable */ |
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243 | WREG32(MC_SEQ_SUP_CNTL, 0x00000008); |
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244 | WREG32(MC_SEQ_SUP_CNTL, 0x00000010); |
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245 | |||
246 | /* load mc io regs */ |
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247 | for (i = 0; i < regs_size; i++) { |
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248 | WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]); |
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249 | WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]); |
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250 | } |
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251 | /* load the MC ucode */ |
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252 | fw_data = (const __be32 *)rdev->mc_fw->data; |
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253 | for (i = 0; i < ucode_size; i++) |
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254 | WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++)); |
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255 | |||
256 | /* put the engine back into the active state */ |
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257 | WREG32(MC_SEQ_SUP_CNTL, 0x00000008); |
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258 | WREG32(MC_SEQ_SUP_CNTL, 0x00000004); |
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259 | WREG32(MC_SEQ_SUP_CNTL, 0x00000001); |
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260 | |||
261 | /* wait for training to complete */ |
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262 | while (!(RREG32(MC_IO_PAD_CNTL_D0) & MEM_FALL_OUT_CMD)) |
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263 | udelay(10); |
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264 | |||
265 | if (running) |
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266 | WREG32(MC_SHARED_BLACKOUT_CNTL, blackout); |
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267 | } |
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268 | |||
269 | return 0; |
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270 | } |
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271 | |||
272 | int ni_init_microcode(struct radeon_device *rdev) |
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273 | { |
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274 | struct platform_device *pdev; |
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275 | const char *chip_name; |
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276 | const char *rlc_chip_name; |
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277 | size_t pfp_req_size, me_req_size, rlc_req_size, mc_req_size; |
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278 | char fw_name[30]; |
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279 | int err; |
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280 | |||
281 | DRM_DEBUG("\n"); |
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282 | |||
283 | pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0); |
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284 | err = IS_ERR(pdev); |
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285 | if (err) { |
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286 | printk(KERN_ERR "radeon_cp: Failed to register firmware\n"); |
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287 | return -EINVAL; |
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288 | } |
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289 | |||
290 | switch (rdev->family) { |
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291 | case CHIP_BARTS: |
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292 | chip_name = "BARTS"; |
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293 | rlc_chip_name = "BTC"; |
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294 | pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4; |
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295 | me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4; |
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296 | rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4; |
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297 | mc_req_size = BTC_MC_UCODE_SIZE * 4; |
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298 | break; |
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299 | case CHIP_TURKS: |
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300 | chip_name = "TURKS"; |
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301 | rlc_chip_name = "BTC"; |
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302 | pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4; |
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303 | me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4; |
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304 | rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4; |
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305 | mc_req_size = BTC_MC_UCODE_SIZE * 4; |
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306 | break; |
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307 | case CHIP_CAICOS: |
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308 | chip_name = "CAICOS"; |
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309 | rlc_chip_name = "BTC"; |
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310 | pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4; |
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311 | me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4; |
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312 | rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4; |
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313 | mc_req_size = BTC_MC_UCODE_SIZE * 4; |
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314 | break; |
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315 | case CHIP_CAYMAN: |
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316 | chip_name = "CAYMAN"; |
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317 | rlc_chip_name = "CAYMAN"; |
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318 | pfp_req_size = CAYMAN_PFP_UCODE_SIZE * 4; |
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319 | me_req_size = CAYMAN_PM4_UCODE_SIZE * 4; |
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320 | rlc_req_size = CAYMAN_RLC_UCODE_SIZE * 4; |
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321 | mc_req_size = CAYMAN_MC_UCODE_SIZE * 4; |
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322 | break; |
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323 | default: BUG(); |
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324 | } |
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325 | |||
326 | DRM_INFO("Loading %s Microcode\n", chip_name); |
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327 | |||
328 | snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name); |
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329 | err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev); |
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330 | if (err) |
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331 | goto out; |
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332 | if (rdev->pfp_fw->size != pfp_req_size) { |
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333 | printk(KERN_ERR |
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334 | "ni_cp: Bogus length %zu in firmware \"%s\"\n", |
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335 | rdev->pfp_fw->size, fw_name); |
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336 | err = -EINVAL; |
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337 | goto out; |
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338 | } |
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339 | |||
340 | snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name); |
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341 | err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev); |
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342 | if (err) |
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343 | goto out; |
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344 | if (rdev->me_fw->size != me_req_size) { |
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345 | printk(KERN_ERR |
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346 | "ni_cp: Bogus length %zu in firmware \"%s\"\n", |
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347 | rdev->me_fw->size, fw_name); |
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348 | err = -EINVAL; |
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349 | } |
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350 | |||
351 | snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name); |
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352 | err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev); |
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353 | if (err) |
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354 | goto out; |
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355 | if (rdev->rlc_fw->size != rlc_req_size) { |
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356 | printk(KERN_ERR |
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357 | "ni_rlc: Bogus length %zu in firmware \"%s\"\n", |
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358 | rdev->rlc_fw->size, fw_name); |
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359 | err = -EINVAL; |
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360 | } |
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361 | |||
362 | snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name); |
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363 | err = request_firmware(&rdev->mc_fw, fw_name, &pdev->dev); |
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364 | if (err) |
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365 | goto out; |
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366 | if (rdev->mc_fw->size != mc_req_size) { |
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367 | printk(KERN_ERR |
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368 | "ni_mc: Bogus length %zu in firmware \"%s\"\n", |
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369 | rdev->mc_fw->size, fw_name); |
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370 | err = -EINVAL; |
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371 | } |
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372 | out: |
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373 | platform_device_unregister(pdev); |
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374 | |||
375 | if (err) { |
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376 | if (err != -EINVAL) |
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377 | printk(KERN_ERR |
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378 | "ni_cp: Failed to load firmware \"%s\"\n", |
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379 | fw_name); |
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380 | release_firmware(rdev->pfp_fw); |
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381 | rdev->pfp_fw = NULL; |
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382 | release_firmware(rdev->me_fw); |
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383 | rdev->me_fw = NULL; |
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384 | release_firmware(rdev->rlc_fw); |
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385 | rdev->rlc_fw = NULL; |
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386 | release_firmware(rdev->mc_fw); |
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387 | rdev->mc_fw = NULL; |
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388 | } |
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389 | return err; |
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390 | } |
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391 | |||
392 | /* |
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393 | * Core functions |
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394 | */ |
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395 | static u32 cayman_get_tile_pipe_to_backend_map(struct radeon_device *rdev, |
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396 | u32 num_tile_pipes, |
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397 | u32 num_backends_per_asic, |
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398 | u32 *backend_disable_mask_per_asic, |
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399 | u32 num_shader_engines) |
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400 | { |
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401 | u32 backend_map = 0; |
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402 | u32 enabled_backends_mask = 0; |
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403 | u32 enabled_backends_count = 0; |
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404 | u32 num_backends_per_se; |
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405 | u32 cur_pipe; |
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406 | u32 swizzle_pipe[CAYMAN_MAX_PIPES]; |
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407 | u32 cur_backend = 0; |
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408 | u32 i; |
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409 | bool force_no_swizzle; |
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410 | |||
411 | /* force legal values */ |
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412 | if (num_tile_pipes < 1) |
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413 | num_tile_pipes = 1; |
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414 | if (num_tile_pipes > rdev->config.cayman.max_tile_pipes) |
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415 | num_tile_pipes = rdev->config.cayman.max_tile_pipes; |
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416 | if (num_shader_engines < 1) |
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417 | num_shader_engines = 1; |
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418 | if (num_shader_engines > rdev->config.cayman.max_shader_engines) |
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419 | num_shader_engines = rdev->config.cayman.max_shader_engines; |
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420 | if (num_backends_per_asic < num_shader_engines) |
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421 | num_backends_per_asic = num_shader_engines; |
||
422 | if (num_backends_per_asic > (rdev->config.cayman.max_backends_per_se * num_shader_engines)) |
||
423 | num_backends_per_asic = rdev->config.cayman.max_backends_per_se * num_shader_engines; |
||
424 | |||
425 | /* make sure we have the same number of backends per se */ |
||
426 | num_backends_per_asic = ALIGN(num_backends_per_asic, num_shader_engines); |
||
427 | /* set up the number of backends per se */ |
||
428 | num_backends_per_se = num_backends_per_asic / num_shader_engines; |
||
429 | if (num_backends_per_se > rdev->config.cayman.max_backends_per_se) { |
||
430 | num_backends_per_se = rdev->config.cayman.max_backends_per_se; |
||
431 | num_backends_per_asic = num_backends_per_se * num_shader_engines; |
||
432 | } |
||
433 | |||
434 | /* create enable mask and count for enabled backends */ |
||
435 | for (i = 0; i < CAYMAN_MAX_BACKENDS; ++i) { |
||
436 | if (((*backend_disable_mask_per_asic >> i) & 1) == 0) { |
||
437 | enabled_backends_mask |= (1 << i); |
||
438 | ++enabled_backends_count; |
||
439 | } |
||
440 | if (enabled_backends_count == num_backends_per_asic) |
||
441 | break; |
||
442 | } |
||
443 | |||
444 | /* force the backends mask to match the current number of backends */ |
||
445 | if (enabled_backends_count != num_backends_per_asic) { |
||
446 | u32 this_backend_enabled; |
||
447 | u32 shader_engine; |
||
448 | u32 backend_per_se; |
||
449 | |||
450 | enabled_backends_mask = 0; |
||
451 | enabled_backends_count = 0; |
||
452 | *backend_disable_mask_per_asic = CAYMAN_MAX_BACKENDS_MASK; |
||
453 | for (i = 0; i < CAYMAN_MAX_BACKENDS; ++i) { |
||
454 | /* calc the current se */ |
||
455 | shader_engine = i / rdev->config.cayman.max_backends_per_se; |
||
456 | /* calc the backend per se */ |
||
457 | backend_per_se = i % rdev->config.cayman.max_backends_per_se; |
||
458 | /* default to not enabled */ |
||
459 | this_backend_enabled = 0; |
||
460 | if ((shader_engine < num_shader_engines) && |
||
461 | (backend_per_se < num_backends_per_se)) |
||
462 | this_backend_enabled = 1; |
||
463 | if (this_backend_enabled) { |
||
464 | enabled_backends_mask |= (1 << i); |
||
465 | *backend_disable_mask_per_asic &= ~(1 << i); |
||
466 | ++enabled_backends_count; |
||
467 | } |
||
468 | } |
||
469 | } |
||
470 | |||
471 | |||
472 | memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * CAYMAN_MAX_PIPES); |
||
473 | switch (rdev->family) { |
||
474 | case CHIP_CAYMAN: |
||
475 | force_no_swizzle = true; |
||
476 | break; |
||
477 | default: |
||
478 | force_no_swizzle = false; |
||
479 | break; |
||
480 | } |
||
481 | if (force_no_swizzle) { |
||
482 | bool last_backend_enabled = false; |
||
483 | |||
484 | force_no_swizzle = false; |
||
485 | for (i = 0; i < CAYMAN_MAX_BACKENDS; ++i) { |
||
486 | if (((enabled_backends_mask >> i) & 1) == 1) { |
||
487 | if (last_backend_enabled) |
||
488 | force_no_swizzle = true; |
||
489 | last_backend_enabled = true; |
||
490 | } else |
||
491 | last_backend_enabled = false; |
||
492 | } |
||
493 | } |
||
494 | |||
495 | switch (num_tile_pipes) { |
||
496 | case 1: |
||
497 | case 3: |
||
498 | case 5: |
||
499 | case 7: |
||
500 | DRM_ERROR("odd number of pipes!\n"); |
||
501 | break; |
||
502 | case 2: |
||
503 | swizzle_pipe[0] = 0; |
||
504 | swizzle_pipe[1] = 1; |
||
505 | break; |
||
506 | case 4: |
||
507 | if (force_no_swizzle) { |
||
508 | swizzle_pipe[0] = 0; |
||
509 | swizzle_pipe[1] = 1; |
||
510 | swizzle_pipe[2] = 2; |
||
511 | swizzle_pipe[3] = 3; |
||
512 | } else { |
||
513 | swizzle_pipe[0] = 0; |
||
514 | swizzle_pipe[1] = 2; |
||
515 | swizzle_pipe[2] = 1; |
||
516 | swizzle_pipe[3] = 3; |
||
517 | } |
||
518 | break; |
||
519 | case 6: |
||
520 | if (force_no_swizzle) { |
||
521 | swizzle_pipe[0] = 0; |
||
522 | swizzle_pipe[1] = 1; |
||
523 | swizzle_pipe[2] = 2; |
||
524 | swizzle_pipe[3] = 3; |
||
525 | swizzle_pipe[4] = 4; |
||
526 | swizzle_pipe[5] = 5; |
||
527 | } else { |
||
528 | swizzle_pipe[0] = 0; |
||
529 | swizzle_pipe[1] = 2; |
||
530 | swizzle_pipe[2] = 4; |
||
531 | swizzle_pipe[3] = 1; |
||
532 | swizzle_pipe[4] = 3; |
||
533 | swizzle_pipe[5] = 5; |
||
534 | } |
||
535 | break; |
||
536 | case 8: |
||
537 | if (force_no_swizzle) { |
||
538 | swizzle_pipe[0] = 0; |
||
539 | swizzle_pipe[1] = 1; |
||
540 | swizzle_pipe[2] = 2; |
||
541 | swizzle_pipe[3] = 3; |
||
542 | swizzle_pipe[4] = 4; |
||
543 | swizzle_pipe[5] = 5; |
||
544 | swizzle_pipe[6] = 6; |
||
545 | swizzle_pipe[7] = 7; |
||
546 | } else { |
||
547 | swizzle_pipe[0] = 0; |
||
548 | swizzle_pipe[1] = 2; |
||
549 | swizzle_pipe[2] = 4; |
||
550 | swizzle_pipe[3] = 6; |
||
551 | swizzle_pipe[4] = 1; |
||
552 | swizzle_pipe[5] = 3; |
||
553 | swizzle_pipe[6] = 5; |
||
554 | swizzle_pipe[7] = 7; |
||
555 | } |
||
556 | break; |
||
557 | } |
||
558 | |||
559 | for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) { |
||
560 | while (((1 << cur_backend) & enabled_backends_mask) == 0) |
||
561 | cur_backend = (cur_backend + 1) % CAYMAN_MAX_BACKENDS; |
||
562 | |||
563 | backend_map |= (((cur_backend & 0xf) << (swizzle_pipe[cur_pipe] * 4))); |
||
564 | |||
565 | cur_backend = (cur_backend + 1) % CAYMAN_MAX_BACKENDS; |
||
566 | } |
||
567 | |||
568 | return backend_map; |
||
569 | } |
||
570 | |||
571 | static void cayman_program_channel_remap(struct radeon_device *rdev) |
||
572 | { |
||
573 | u32 tcp_chan_steer_lo, tcp_chan_steer_hi, mc_shared_chremap, tmp; |
||
574 | |||
575 | tmp = RREG32(MC_SHARED_CHMAP); |
||
576 | switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { |
||
577 | case 0: |
||
578 | case 1: |
||
579 | case 2: |
||
580 | case 3: |
||
581 | default: |
||
582 | /* default mapping */ |
||
583 | mc_shared_chremap = 0x00fac688; |
||
584 | break; |
||
585 | } |
||
586 | |||
587 | switch (rdev->family) { |
||
588 | case CHIP_CAYMAN: |
||
589 | default: |
||
590 | //tcp_chan_steer_lo = 0x54763210 |
||
591 | tcp_chan_steer_lo = 0x76543210; |
||
592 | tcp_chan_steer_hi = 0x0000ba98; |
||
593 | break; |
||
594 | } |
||
595 | |||
596 | WREG32(TCP_CHAN_STEER_LO, tcp_chan_steer_lo); |
||
597 | WREG32(TCP_CHAN_STEER_HI, tcp_chan_steer_hi); |
||
598 | WREG32(MC_SHARED_CHREMAP, mc_shared_chremap); |
||
599 | } |
||
600 | |||
601 | static u32 cayman_get_disable_mask_per_asic(struct radeon_device *rdev, |
||
602 | u32 disable_mask_per_se, |
||
603 | u32 max_disable_mask_per_se, |
||
604 | u32 num_shader_engines) |
||
605 | { |
||
606 | u32 disable_field_width_per_se = r600_count_pipe_bits(disable_mask_per_se); |
||
607 | u32 disable_mask_per_asic = disable_mask_per_se & max_disable_mask_per_se; |
||
608 | |||
609 | if (num_shader_engines == 1) |
||
610 | return disable_mask_per_asic; |
||
611 | else if (num_shader_engines == 2) |
||
612 | return disable_mask_per_asic | (disable_mask_per_asic << disable_field_width_per_se); |
||
613 | else |
||
614 | return 0xffffffff; |
||
615 | } |
||
616 | |||
617 | static void cayman_gpu_init(struct radeon_device *rdev) |
||
618 | { |
||
619 | u32 cc_rb_backend_disable = 0; |
||
620 | u32 cc_gc_shader_pipe_config; |
||
621 | u32 gb_addr_config = 0; |
||
622 | u32 mc_shared_chmap, mc_arb_ramcfg; |
||
623 | u32 gb_backend_map; |
||
624 | u32 cgts_tcc_disable; |
||
625 | u32 sx_debug_1; |
||
626 | u32 smx_dc_ctl0; |
||
627 | u32 gc_user_shader_pipe_config; |
||
628 | u32 gc_user_rb_backend_disable; |
||
629 | u32 cgts_user_tcc_disable; |
||
630 | u32 cgts_sm_ctrl_reg; |
||
631 | u32 hdp_host_path_cntl; |
||
632 | u32 tmp; |
||
633 | int i, j; |
||
634 | |||
635 | switch (rdev->family) { |
||
636 | case CHIP_CAYMAN: |
||
637 | default: |
||
638 | rdev->config.cayman.max_shader_engines = 2; |
||
639 | rdev->config.cayman.max_pipes_per_simd = 4; |
||
640 | rdev->config.cayman.max_tile_pipes = 8; |
||
641 | rdev->config.cayman.max_simds_per_se = 12; |
||
642 | rdev->config.cayman.max_backends_per_se = 4; |
||
643 | rdev->config.cayman.max_texture_channel_caches = 8; |
||
644 | rdev->config.cayman.max_gprs = 256; |
||
645 | rdev->config.cayman.max_threads = 256; |
||
646 | rdev->config.cayman.max_gs_threads = 32; |
||
647 | rdev->config.cayman.max_stack_entries = 512; |
||
648 | rdev->config.cayman.sx_num_of_sets = 8; |
||
649 | rdev->config.cayman.sx_max_export_size = 256; |
||
650 | rdev->config.cayman.sx_max_export_pos_size = 64; |
||
651 | rdev->config.cayman.sx_max_export_smx_size = 192; |
||
652 | rdev->config.cayman.max_hw_contexts = 8; |
||
653 | rdev->config.cayman.sq_num_cf_insts = 2; |
||
654 | |||
655 | rdev->config.cayman.sc_prim_fifo_size = 0x100; |
||
656 | rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30; |
||
657 | rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130; |
||
658 | break; |
||
659 | } |
||
660 | |||
661 | /* Initialize HDP */ |
||
662 | for (i = 0, j = 0; i < 32; i++, j += 0x18) { |
||
663 | WREG32((0x2c14 + j), 0x00000000); |
||
664 | WREG32((0x2c18 + j), 0x00000000); |
||
665 | WREG32((0x2c1c + j), 0x00000000); |
||
666 | WREG32((0x2c20 + j), 0x00000000); |
||
667 | WREG32((0x2c24 + j), 0x00000000); |
||
668 | } |
||
669 | |||
670 | WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); |
||
671 | |||
672 | mc_shared_chmap = RREG32(MC_SHARED_CHMAP); |
||
673 | mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG); |
||
674 | |||
675 | cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE); |
||
676 | cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG); |
||
677 | cgts_tcc_disable = 0xff000000; |
||
678 | gc_user_rb_backend_disable = RREG32(GC_USER_RB_BACKEND_DISABLE); |
||
679 | gc_user_shader_pipe_config = RREG32(GC_USER_SHADER_PIPE_CONFIG); |
||
680 | cgts_user_tcc_disable = RREG32(CGTS_USER_TCC_DISABLE); |
||
681 | |||
682 | rdev->config.cayman.num_shader_engines = rdev->config.cayman.max_shader_engines; |
||
683 | tmp = ((~gc_user_shader_pipe_config) & INACTIVE_QD_PIPES_MASK) >> INACTIVE_QD_PIPES_SHIFT; |
||
684 | rdev->config.cayman.num_shader_pipes_per_simd = r600_count_pipe_bits(tmp); |
||
685 | rdev->config.cayman.num_tile_pipes = rdev->config.cayman.max_tile_pipes; |
||
686 | tmp = ((~gc_user_shader_pipe_config) & INACTIVE_SIMDS_MASK) >> INACTIVE_SIMDS_SHIFT; |
||
687 | rdev->config.cayman.num_simds_per_se = r600_count_pipe_bits(tmp); |
||
688 | tmp = ((~gc_user_rb_backend_disable) & BACKEND_DISABLE_MASK) >> BACKEND_DISABLE_SHIFT; |
||
689 | rdev->config.cayman.num_backends_per_se = r600_count_pipe_bits(tmp); |
||
690 | tmp = (gc_user_rb_backend_disable & BACKEND_DISABLE_MASK) >> BACKEND_DISABLE_SHIFT; |
||
691 | rdev->config.cayman.backend_disable_mask_per_asic = |
||
692 | cayman_get_disable_mask_per_asic(rdev, tmp, CAYMAN_MAX_BACKENDS_PER_SE_MASK, |
||
693 | rdev->config.cayman.num_shader_engines); |
||
694 | rdev->config.cayman.backend_map = |
||
695 | cayman_get_tile_pipe_to_backend_map(rdev, rdev->config.cayman.num_tile_pipes, |
||
696 | rdev->config.cayman.num_backends_per_se * |
||
697 | rdev->config.cayman.num_shader_engines, |
||
698 | &rdev->config.cayman.backend_disable_mask_per_asic, |
||
699 | rdev->config.cayman.num_shader_engines); |
||
700 | tmp = ((~cgts_user_tcc_disable) & TCC_DISABLE_MASK) >> TCC_DISABLE_SHIFT; |
||
701 | rdev->config.cayman.num_texture_channel_caches = r600_count_pipe_bits(tmp); |
||
702 | tmp = (mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT; |
||
703 | rdev->config.cayman.mem_max_burst_length_bytes = (tmp + 1) * 256; |
||
704 | if (rdev->config.cayman.mem_max_burst_length_bytes > 512) |
||
705 | rdev->config.cayman.mem_max_burst_length_bytes = 512; |
||
706 | tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT; |
||
707 | rdev->config.cayman.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024; |
||
708 | if (rdev->config.cayman.mem_row_size_in_kb > 4) |
||
709 | rdev->config.cayman.mem_row_size_in_kb = 4; |
||
710 | /* XXX use MC settings? */ |
||
711 | rdev->config.cayman.shader_engine_tile_size = 32; |
||
712 | rdev->config.cayman.num_gpus = 1; |
||
713 | rdev->config.cayman.multi_gpu_tile_size = 64; |
||
714 | |||
715 | //gb_addr_config = 0x02011003 |
||
716 | #if 0 |
||
717 | gb_addr_config = RREG32(GB_ADDR_CONFIG); |
||
718 | #else |
||
719 | gb_addr_config = 0; |
||
720 | switch (rdev->config.cayman.num_tile_pipes) { |
||
721 | case 1: |
||
722 | default: |
||
723 | gb_addr_config |= NUM_PIPES(0); |
||
724 | break; |
||
725 | case 2: |
||
726 | gb_addr_config |= NUM_PIPES(1); |
||
727 | break; |
||
728 | case 4: |
||
729 | gb_addr_config |= NUM_PIPES(2); |
||
730 | break; |
||
731 | case 8: |
||
732 | gb_addr_config |= NUM_PIPES(3); |
||
733 | break; |
||
734 | } |
||
735 | |||
736 | tmp = (rdev->config.cayman.mem_max_burst_length_bytes / 256) - 1; |
||
737 | gb_addr_config |= PIPE_INTERLEAVE_SIZE(tmp); |
||
738 | gb_addr_config |= NUM_SHADER_ENGINES(rdev->config.cayman.num_shader_engines - 1); |
||
739 | tmp = (rdev->config.cayman.shader_engine_tile_size / 16) - 1; |
||
740 | gb_addr_config |= SHADER_ENGINE_TILE_SIZE(tmp); |
||
741 | switch (rdev->config.cayman.num_gpus) { |
||
742 | case 1: |
||
743 | default: |
||
744 | gb_addr_config |= NUM_GPUS(0); |
||
745 | break; |
||
746 | case 2: |
||
747 | gb_addr_config |= NUM_GPUS(1); |
||
748 | break; |
||
749 | case 4: |
||
750 | gb_addr_config |= NUM_GPUS(2); |
||
751 | break; |
||
752 | } |
||
753 | switch (rdev->config.cayman.multi_gpu_tile_size) { |
||
754 | case 16: |
||
755 | gb_addr_config |= MULTI_GPU_TILE_SIZE(0); |
||
756 | break; |
||
757 | case 32: |
||
758 | default: |
||
759 | gb_addr_config |= MULTI_GPU_TILE_SIZE(1); |
||
760 | break; |
||
761 | case 64: |
||
762 | gb_addr_config |= MULTI_GPU_TILE_SIZE(2); |
||
763 | break; |
||
764 | case 128: |
||
765 | gb_addr_config |= MULTI_GPU_TILE_SIZE(3); |
||
766 | break; |
||
767 | } |
||
768 | switch (rdev->config.cayman.mem_row_size_in_kb) { |
||
769 | case 1: |
||
770 | default: |
||
771 | gb_addr_config |= ROW_SIZE(0); |
||
772 | break; |
||
773 | case 2: |
||
774 | gb_addr_config |= ROW_SIZE(1); |
||
775 | break; |
||
776 | case 4: |
||
777 | gb_addr_config |= ROW_SIZE(2); |
||
778 | break; |
||
779 | } |
||
780 | #endif |
||
781 | |||
782 | tmp = (gb_addr_config & NUM_PIPES_MASK) >> NUM_PIPES_SHIFT; |
||
783 | rdev->config.cayman.num_tile_pipes = (1 << tmp); |
||
784 | tmp = (gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT; |
||
785 | rdev->config.cayman.mem_max_burst_length_bytes = (tmp + 1) * 256; |
||
786 | tmp = (gb_addr_config & NUM_SHADER_ENGINES_MASK) >> NUM_SHADER_ENGINES_SHIFT; |
||
787 | rdev->config.cayman.num_shader_engines = tmp + 1; |
||
788 | tmp = (gb_addr_config & NUM_GPUS_MASK) >> NUM_GPUS_SHIFT; |
||
789 | rdev->config.cayman.num_gpus = tmp + 1; |
||
790 | tmp = (gb_addr_config & MULTI_GPU_TILE_SIZE_MASK) >> MULTI_GPU_TILE_SIZE_SHIFT; |
||
791 | rdev->config.cayman.multi_gpu_tile_size = 1 << tmp; |
||
792 | tmp = (gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT; |
||
793 | rdev->config.cayman.mem_row_size_in_kb = 1 << tmp; |
||
794 | |||
795 | //gb_backend_map = 0x76541032; |
||
796 | #if 0 |
||
797 | gb_backend_map = RREG32(GB_BACKEND_MAP); |
||
798 | #else |
||
799 | gb_backend_map = |
||
800 | cayman_get_tile_pipe_to_backend_map(rdev, rdev->config.cayman.num_tile_pipes, |
||
801 | rdev->config.cayman.num_backends_per_se * |
||
802 | rdev->config.cayman.num_shader_engines, |
||
803 | &rdev->config.cayman.backend_disable_mask_per_asic, |
||
804 | rdev->config.cayman.num_shader_engines); |
||
805 | #endif |
||
806 | /* setup tiling info dword. gb_addr_config is not adequate since it does |
||
807 | * not have bank info, so create a custom tiling dword. |
||
808 | * bits 3:0 num_pipes |
||
809 | * bits 7:4 num_banks |
||
810 | * bits 11:8 group_size |
||
811 | * bits 15:12 row_size |
||
812 | */ |
||
813 | rdev->config.cayman.tile_config = 0; |
||
814 | switch (rdev->config.cayman.num_tile_pipes) { |
||
815 | case 1: |
||
816 | default: |
||
817 | rdev->config.cayman.tile_config |= (0 << 0); |
||
818 | break; |
||
819 | case 2: |
||
820 | rdev->config.cayman.tile_config |= (1 << 0); |
||
821 | break; |
||
822 | case 4: |
||
823 | rdev->config.cayman.tile_config |= (2 << 0); |
||
824 | break; |
||
825 | case 8: |
||
826 | rdev->config.cayman.tile_config |= (3 << 0); |
||
827 | break; |
||
828 | } |
||
829 | rdev->config.cayman.tile_config |= |
||
830 | ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) << 4; |
||
831 | rdev->config.cayman.tile_config |= |
||
832 | ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8; |
||
833 | rdev->config.cayman.tile_config |= |
||
834 | ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12; |
||
835 | |||
836 | WREG32(GB_BACKEND_MAP, gb_backend_map); |
||
837 | WREG32(GB_ADDR_CONFIG, gb_addr_config); |
||
838 | WREG32(DMIF_ADDR_CONFIG, gb_addr_config); |
||
839 | WREG32(HDP_ADDR_CONFIG, gb_addr_config); |
||
840 | |||
841 | cayman_program_channel_remap(rdev); |
||
842 | |||
843 | /* primary versions */ |
||
844 | WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable); |
||
845 | WREG32(CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable); |
||
846 | WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); |
||
847 | |||
848 | WREG32(CGTS_TCC_DISABLE, cgts_tcc_disable); |
||
849 | WREG32(CGTS_SYS_TCC_DISABLE, cgts_tcc_disable); |
||
850 | |||
851 | /* user versions */ |
||
852 | WREG32(GC_USER_RB_BACKEND_DISABLE, cc_rb_backend_disable); |
||
853 | WREG32(GC_USER_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable); |
||
854 | WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); |
||
855 | |||
856 | WREG32(CGTS_USER_SYS_TCC_DISABLE, cgts_tcc_disable); |
||
857 | WREG32(CGTS_USER_TCC_DISABLE, cgts_tcc_disable); |
||
858 | |||
859 | /* reprogram the shader complex */ |
||
860 | cgts_sm_ctrl_reg = RREG32(CGTS_SM_CTRL_REG); |
||
861 | for (i = 0; i < 16; i++) |
||
862 | WREG32(CGTS_SM_CTRL_REG, OVERRIDE); |
||
863 | WREG32(CGTS_SM_CTRL_REG, cgts_sm_ctrl_reg); |
||
864 | |||
865 | /* set HW defaults for 3D engine */ |
||
866 | WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60)); |
||
867 | |||
868 | sx_debug_1 = RREG32(SX_DEBUG_1); |
||
869 | sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS; |
||
870 | WREG32(SX_DEBUG_1, sx_debug_1); |
||
871 | |||
872 | smx_dc_ctl0 = RREG32(SMX_DC_CTL0); |
||
873 | smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff); |
||
874 | smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.cayman.sx_num_of_sets); |
||
875 | WREG32(SMX_DC_CTL0, smx_dc_ctl0); |
||
876 | |||
877 | WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4) | CRC_SIMD_ID_WADDR_DISABLE); |
||
878 | |||
879 | /* need to be explicitly zero-ed */ |
||
880 | WREG32(VGT_OFFCHIP_LDS_BASE, 0); |
||
881 | WREG32(SQ_LSTMP_RING_BASE, 0); |
||
882 | WREG32(SQ_HSTMP_RING_BASE, 0); |
||
883 | WREG32(SQ_ESTMP_RING_BASE, 0); |
||
884 | WREG32(SQ_GSTMP_RING_BASE, 0); |
||
885 | WREG32(SQ_VSTMP_RING_BASE, 0); |
||
886 | WREG32(SQ_PSTMP_RING_BASE, 0); |
||
887 | |||
888 | WREG32(TA_CNTL_AUX, DISABLE_CUBE_ANISO); |
||
889 | |||
890 | WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.cayman.sx_max_export_size / 4) - 1) | |
||
891 | POSITION_BUFFER_SIZE((rdev->config.cayman.sx_max_export_pos_size / 4) - 1) | |
||
892 | SMX_BUFFER_SIZE((rdev->config.cayman.sx_max_export_smx_size / 4) - 1))); |
||
893 | |||
894 | WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.cayman.sc_prim_fifo_size) | |
||
895 | SC_HIZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_hiz_tile_fifo_size) | |
||
896 | SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_earlyz_tile_fifo_size))); |
||
897 | |||
898 | |||
899 | WREG32(VGT_NUM_INSTANCES, 1); |
||
900 | |||
901 | WREG32(CP_PERFMON_CNTL, 0); |
||
902 | |||
903 | WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.cayman.sq_num_cf_insts) | |
||
904 | FETCH_FIFO_HIWATER(0x4) | |
||
905 | DONE_FIFO_HIWATER(0xe0) | |
||
906 | ALU_UPDATE_FIFO_HIWATER(0x8))); |
||
907 | |||
908 | WREG32(SQ_GPR_RESOURCE_MGMT_1, NUM_CLAUSE_TEMP_GPRS(4)); |
||
909 | WREG32(SQ_CONFIG, (VC_ENABLE | |
||
910 | EXPORT_SRC_C | |
||
911 | GFX_PRIO(0) | |
||
912 | CS1_PRIO(0) | |
||
913 | CS2_PRIO(1))); |
||
914 | WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, DYN_GPR_ENABLE); |
||
915 | |||
916 | WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) | |
||
917 | FORCE_EOV_MAX_REZ_CNT(255))); |
||
918 | |||
919 | WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) | |
||
920 | AUTO_INVLD_EN(ES_AND_GS_AUTO)); |
||
921 | |||
922 | WREG32(VGT_GS_VERTEX_REUSE, 16); |
||
923 | WREG32(PA_SC_LINE_STIPPLE_STATE, 0); |
||
924 | |||
925 | WREG32(CB_PERF_CTR0_SEL_0, 0); |
||
926 | WREG32(CB_PERF_CTR0_SEL_1, 0); |
||
927 | WREG32(CB_PERF_CTR1_SEL_0, 0); |
||
928 | WREG32(CB_PERF_CTR1_SEL_1, 0); |
||
929 | WREG32(CB_PERF_CTR2_SEL_0, 0); |
||
930 | WREG32(CB_PERF_CTR2_SEL_1, 0); |
||
931 | WREG32(CB_PERF_CTR3_SEL_0, 0); |
||
932 | WREG32(CB_PERF_CTR3_SEL_1, 0); |
||
933 | |||
934 | tmp = RREG32(HDP_MISC_CNTL); |
||
935 | tmp |= HDP_FLUSH_INVALIDATE_CACHE; |
||
936 | WREG32(HDP_MISC_CNTL, tmp); |
||
937 | |||
938 | hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL); |
||
939 | WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl); |
||
940 | |||
941 | WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3)); |
||
942 | |||
943 | udelay(50); |
||
944 | } |
||
945 | |||
946 | /* |
||
947 | * GART |
||
948 | */ |
||
949 | void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev) |
||
950 | { |
||
951 | /* flush hdp cache */ |
||
952 | WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); |
||
953 | |||
954 | /* bits 0-7 are the VM contexts0-7 */ |
||
955 | WREG32(VM_INVALIDATE_REQUEST, 1); |
||
956 | } |
||
957 | |||
958 | int cayman_pcie_gart_enable(struct radeon_device *rdev) |
||
959 | { |
||
960 | int r; |
||
961 | |||
962 | if (rdev->gart.table.vram.robj == NULL) { |
||
963 | dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); |
||
964 | return -EINVAL; |
||
965 | } |
||
966 | r = radeon_gart_table_vram_pin(rdev); |
||
967 | if (r) |
||
968 | return r; |
||
969 | radeon_gart_restore(rdev); |
||
970 | /* Setup TLB control */ |
||
971 | WREG32(MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB | |
||
972 | ENABLE_L1_FRAGMENT_PROCESSING | |
||
973 | SYSTEM_ACCESS_MODE_NOT_IN_SYS | |
||
974 | SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU); |
||
975 | /* Setup L2 cache */ |
||
976 | WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | |
||
977 | ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | |
||
978 | ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE | |
||
979 | EFFECTIVE_L2_QUEUE_SIZE(7) | |
||
980 | CONTEXT1_IDENTITY_ACCESS_MODE(1)); |
||
981 | WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE); |
||
982 | WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY | |
||
983 | L2_CACHE_BIGK_FRAGMENT_SIZE(6)); |
||
984 | /* setup context0 */ |
||
985 | WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); |
||
986 | WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); |
||
987 | WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); |
||
988 | WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, |
||
989 | (u32)(rdev->dummy_page.addr >> 12)); |
||
990 | WREG32(VM_CONTEXT0_CNTL2, 0); |
||
991 | WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | |
||
992 | RANGE_PROTECTION_FAULT_ENABLE_DEFAULT); |
||
993 | /* disable context1-7 */ |
||
994 | WREG32(VM_CONTEXT1_CNTL2, 0); |
||
995 | WREG32(VM_CONTEXT1_CNTL, 0); |
||
996 | |||
997 | cayman_pcie_gart_tlb_flush(rdev); |
||
998 | rdev->gart.ready = true; |
||
999 | return 0; |
||
1000 | } |
||
1001 | |||
1002 | void cayman_pcie_gart_disable(struct radeon_device *rdev) |
||
1003 | { |
||
1004 | int r; |
||
1005 | |||
1006 | /* Disable all tables */ |
||
1007 | WREG32(VM_CONTEXT0_CNTL, 0); |
||
1008 | WREG32(VM_CONTEXT1_CNTL, 0); |
||
1009 | /* Setup TLB control */ |
||
1010 | WREG32(MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING | |
||
1011 | SYSTEM_ACCESS_MODE_NOT_IN_SYS | |
||
1012 | SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU); |
||
1013 | /* Setup L2 cache */ |
||
1014 | WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | |
||
1015 | ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE | |
||
1016 | EFFECTIVE_L2_QUEUE_SIZE(7) | |
||
1017 | CONTEXT1_IDENTITY_ACCESS_MODE(1)); |
||
1018 | WREG32(VM_L2_CNTL2, 0); |
||
1019 | WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY | |
||
1020 | L2_CACHE_BIGK_FRAGMENT_SIZE(6)); |
||
1021 | if (rdev->gart.table.vram.robj) { |
||
1022 | r = radeon_bo_reserve(rdev->gart.table.vram.robj, false); |
||
1023 | if (likely(r == 0)) { |
||
1024 | radeon_bo_kunmap(rdev->gart.table.vram.robj); |
||
1025 | radeon_bo_unpin(rdev->gart.table.vram.robj); |
||
1026 | radeon_bo_unreserve(rdev->gart.table.vram.robj); |
||
1027 | } |
||
1028 | } |
||
1029 | } |
||
1030 | |||
1031 | |||
1032 | /* |
||
1033 | * CP. |
||
1034 | */ |
||
1035 | static void cayman_cp_enable(struct radeon_device *rdev, bool enable) |
||
1036 | { |
||
1037 | if (enable) |
||
1038 | WREG32(CP_ME_CNTL, 0); |
||
1039 | else { |
||
1040 | WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT)); |
||
1041 | WREG32(SCRATCH_UMSK, 0); |
||
1042 | } |
||
1043 | } |
||
1044 | |||
1045 | static int cayman_cp_load_microcode(struct radeon_device *rdev) |
||
1046 | { |
||
1047 | const __be32 *fw_data; |
||
1048 | int i; |
||
1049 | |||
1050 | if (!rdev->me_fw || !rdev->pfp_fw) |
||
1051 | return -EINVAL; |
||
1052 | |||
1053 | cayman_cp_enable(rdev, false); |
||
1054 | |||
1055 | fw_data = (const __be32 *)rdev->pfp_fw->data; |
||
1056 | WREG32(CP_PFP_UCODE_ADDR, 0); |
||
1057 | for (i = 0; i < CAYMAN_PFP_UCODE_SIZE; i++) |
||
1058 | WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++)); |
||
1059 | WREG32(CP_PFP_UCODE_ADDR, 0); |
||
1060 | |||
1061 | fw_data = (const __be32 *)rdev->me_fw->data; |
||
1062 | WREG32(CP_ME_RAM_WADDR, 0); |
||
1063 | for (i = 0; i < CAYMAN_PM4_UCODE_SIZE; i++) |
||
1064 | WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++)); |
||
1065 | |||
1066 | WREG32(CP_PFP_UCODE_ADDR, 0); |
||
1067 | WREG32(CP_ME_RAM_WADDR, 0); |
||
1068 | WREG32(CP_ME_RAM_RADDR, 0); |
||
1069 | return 0; |
||
1070 | } |
||
1071 | |||
1072 | static int cayman_cp_start(struct radeon_device *rdev) |
||
1073 | { |
||
1074 | int r, i; |
||
1075 | |||
1076 | r = radeon_ring_lock(rdev, 7); |
||
1077 | if (r) { |
||
1078 | DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); |
||
1079 | return r; |
||
1080 | } |
||
1081 | radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5)); |
||
1082 | radeon_ring_write(rdev, 0x1); |
||
1083 | radeon_ring_write(rdev, 0x0); |
||
1084 | radeon_ring_write(rdev, rdev->config.cayman.max_hw_contexts - 1); |
||
1085 | radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); |
||
1086 | radeon_ring_write(rdev, 0); |
||
1087 | radeon_ring_write(rdev, 0); |
||
1088 | radeon_ring_unlock_commit(rdev); |
||
1089 | |||
1090 | cayman_cp_enable(rdev, true); |
||
1091 | |||
1092 | r = radeon_ring_lock(rdev, cayman_default_size + 19); |
||
1093 | if (r) { |
||
1094 | DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); |
||
1095 | return r; |
||
1096 | } |
||
1097 | |||
1098 | /* setup clear context state */ |
||
1099 | radeon_ring_write(rdev, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); |
||
1100 | radeon_ring_write(rdev, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); |
||
1101 | |||
1102 | for (i = 0; i < cayman_default_size; i++) |
||
1103 | radeon_ring_write(rdev, cayman_default_state[i]); |
||
1104 | |||
1105 | radeon_ring_write(rdev, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); |
||
1106 | radeon_ring_write(rdev, PACKET3_PREAMBLE_END_CLEAR_STATE); |
||
1107 | |||
1108 | /* set clear context state */ |
||
1109 | radeon_ring_write(rdev, PACKET3(PACKET3_CLEAR_STATE, 0)); |
||
1110 | radeon_ring_write(rdev, 0); |
||
1111 | |||
1112 | /* SQ_VTX_BASE_VTX_LOC */ |
||
1113 | radeon_ring_write(rdev, 0xc0026f00); |
||
1114 | radeon_ring_write(rdev, 0x00000000); |
||
1115 | radeon_ring_write(rdev, 0x00000000); |
||
1116 | radeon_ring_write(rdev, 0x00000000); |
||
1117 | |||
1118 | /* Clear consts */ |
||
1119 | radeon_ring_write(rdev, 0xc0036f00); |
||
1120 | radeon_ring_write(rdev, 0x00000bc4); |
||
1121 | radeon_ring_write(rdev, 0xffffffff); |
||
1122 | radeon_ring_write(rdev, 0xffffffff); |
||
1123 | radeon_ring_write(rdev, 0xffffffff); |
||
1124 | |||
1125 | radeon_ring_write(rdev, 0xc0026900); |
||
1126 | radeon_ring_write(rdev, 0x00000316); |
||
1127 | radeon_ring_write(rdev, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */ |
||
1128 | radeon_ring_write(rdev, 0x00000010); /* */ |
||
1129 | |||
1130 | radeon_ring_unlock_commit(rdev); |
||
1131 | |||
1132 | /* XXX init other rings */ |
||
1133 | |||
1134 | return 0; |
||
1135 | } |
||
1136 | |||
1137 | |||
2004 | serge | 1138 | |
1990 | serge | 1139 | int cayman_cp_resume(struct radeon_device *rdev) |
1140 | { |
||
1141 | u32 tmp; |
||
1142 | u32 rb_bufsz; |
||
1143 | int r; |
||
1144 | |||
1145 | /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */ |
||
1146 | WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP | |
||
1147 | SOFT_RESET_PA | |
||
1148 | SOFT_RESET_SH | |
||
1149 | SOFT_RESET_VGT | |
||
1150 | SOFT_RESET_SX)); |
||
1151 | RREG32(GRBM_SOFT_RESET); |
||
1152 | mdelay(15); |
||
1153 | WREG32(GRBM_SOFT_RESET, 0); |
||
1154 | RREG32(GRBM_SOFT_RESET); |
||
1155 | |||
1156 | WREG32(CP_SEM_WAIT_TIMER, 0x4); |
||
1157 | |||
1158 | /* Set the write pointer delay */ |
||
1159 | WREG32(CP_RB_WPTR_DELAY, 0); |
||
1160 | |||
1161 | WREG32(CP_DEBUG, (1 << 27)); |
||
1162 | |||
1163 | /* ring 0 - compute and gfx */ |
||
1164 | /* Set ring buffer size */ |
||
1165 | rb_bufsz = drm_order(rdev->cp.ring_size / 8); |
||
1166 | tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; |
||
1167 | #ifdef __BIG_ENDIAN |
||
1168 | tmp |= BUF_SWAP_32BIT; |
||
1169 | #endif |
||
1170 | WREG32(CP_RB0_CNTL, tmp); |
||
1171 | |||
1172 | /* Initialize the ring buffer's read and write pointers */ |
||
1173 | WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA); |
||
1174 | WREG32(CP_RB0_WPTR, 0); |
||
1175 | |||
1176 | /* set the wb address wether it's enabled or not */ |
||
1177 | WREG32(CP_RB0_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC); |
||
1178 | WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); |
||
1179 | WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); |
||
1180 | |||
1181 | if (rdev->wb.enabled) |
||
1182 | WREG32(SCRATCH_UMSK, 0xff); |
||
1183 | else { |
||
1184 | tmp |= RB_NO_UPDATE; |
||
1185 | WREG32(SCRATCH_UMSK, 0); |
||
1186 | } |
||
1187 | |||
1188 | mdelay(1); |
||
1189 | WREG32(CP_RB0_CNTL, tmp); |
||
1190 | |||
1191 | WREG32(CP_RB0_BASE, rdev->cp.gpu_addr >> 8); |
||
1192 | |||
1193 | rdev->cp.rptr = RREG32(CP_RB0_RPTR); |
||
1194 | rdev->cp.wptr = RREG32(CP_RB0_WPTR); |
||
1195 | |||
1196 | /* ring1 - compute only */ |
||
1197 | /* Set ring buffer size */ |
||
1198 | rb_bufsz = drm_order(rdev->cp1.ring_size / 8); |
||
1199 | tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; |
||
1200 | #ifdef __BIG_ENDIAN |
||
1201 | tmp |= BUF_SWAP_32BIT; |
||
1202 | #endif |
||
1203 | WREG32(CP_RB1_CNTL, tmp); |
||
1204 | |||
1205 | /* Initialize the ring buffer's read and write pointers */ |
||
1206 | WREG32(CP_RB1_CNTL, tmp | RB_RPTR_WR_ENA); |
||
1207 | WREG32(CP_RB1_WPTR, 0); |
||
1208 | |||
1209 | /* set the wb address wether it's enabled or not */ |
||
1210 | WREG32(CP_RB1_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFFFFFFFC); |
||
1211 | WREG32(CP_RB1_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFF); |
||
1212 | |||
1213 | mdelay(1); |
||
1214 | WREG32(CP_RB1_CNTL, tmp); |
||
1215 | |||
1216 | WREG32(CP_RB1_BASE, rdev->cp1.gpu_addr >> 8); |
||
1217 | |||
1218 | rdev->cp1.rptr = RREG32(CP_RB1_RPTR); |
||
1219 | rdev->cp1.wptr = RREG32(CP_RB1_WPTR); |
||
1220 | |||
1221 | /* ring2 - compute only */ |
||
1222 | /* Set ring buffer size */ |
||
1223 | rb_bufsz = drm_order(rdev->cp2.ring_size / 8); |
||
1224 | tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; |
||
1225 | #ifdef __BIG_ENDIAN |
||
1226 | tmp |= BUF_SWAP_32BIT; |
||
1227 | #endif |
||
1228 | WREG32(CP_RB2_CNTL, tmp); |
||
1229 | |||
1230 | /* Initialize the ring buffer's read and write pointers */ |
||
1231 | WREG32(CP_RB2_CNTL, tmp | RB_RPTR_WR_ENA); |
||
1232 | WREG32(CP_RB2_WPTR, 0); |
||
1233 | |||
1234 | /* set the wb address wether it's enabled or not */ |
||
1235 | WREG32(CP_RB2_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFFFFFFFC); |
||
1236 | WREG32(CP_RB2_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFF); |
||
1237 | |||
1238 | mdelay(1); |
||
1239 | WREG32(CP_RB2_CNTL, tmp); |
||
1240 | |||
1241 | WREG32(CP_RB2_BASE, rdev->cp2.gpu_addr >> 8); |
||
1242 | |||
1243 | rdev->cp2.rptr = RREG32(CP_RB2_RPTR); |
||
1244 | rdev->cp2.wptr = RREG32(CP_RB2_WPTR); |
||
1245 | |||
1246 | /* start the rings */ |
||
1247 | cayman_cp_start(rdev); |
||
1248 | rdev->cp.ready = true; |
||
1249 | rdev->cp1.ready = true; |
||
1250 | rdev->cp2.ready = true; |
||
1251 | /* this only test cp0 */ |
||
1252 | r = radeon_ring_test(rdev); |
||
1253 | if (r) { |
||
1254 | rdev->cp.ready = false; |
||
1255 | rdev->cp1.ready = false; |
||
1256 | rdev->cp2.ready = false; |
||
1257 | return r; |
||
1258 | } |
||
1259 | |||
1260 | return 0; |
||
1261 | } |
||
1262 | |||
1263 | bool cayman_gpu_is_lockup(struct radeon_device *rdev) |
||
1264 | { |
||
1265 | u32 srbm_status; |
||
1266 | u32 grbm_status; |
||
1267 | u32 grbm_status_se0, grbm_status_se1; |
||
1268 | struct r100_gpu_lockup *lockup = &rdev->config.cayman.lockup; |
||
1269 | int r; |
||
1270 | |||
1271 | srbm_status = RREG32(SRBM_STATUS); |
||
1272 | grbm_status = RREG32(GRBM_STATUS); |
||
1273 | grbm_status_se0 = RREG32(GRBM_STATUS_SE0); |
||
1274 | grbm_status_se1 = RREG32(GRBM_STATUS_SE1); |
||
1275 | if (!(grbm_status & GUI_ACTIVE)) { |
||
1276 | r100_gpu_lockup_update(lockup, &rdev->cp); |
||
1277 | return false; |
||
1278 | } |
||
1279 | /* force CP activities */ |
||
1280 | r = radeon_ring_lock(rdev, 2); |
||
1281 | if (!r) { |
||
1282 | /* PACKET2 NOP */ |
||
1283 | radeon_ring_write(rdev, 0x80000000); |
||
1284 | radeon_ring_write(rdev, 0x80000000); |
||
1285 | radeon_ring_unlock_commit(rdev); |
||
1286 | } |
||
1287 | /* XXX deal with CP0,1,2 */ |
||
1288 | rdev->cp.rptr = RREG32(CP_RB0_RPTR); |
||
1289 | return r100_gpu_cp_is_lockup(rdev, lockup, &rdev->cp); |
||
1290 | } |
||
1291 | |||
1292 | static int cayman_gpu_soft_reset(struct radeon_device *rdev) |
||
1293 | { |
||
1294 | struct evergreen_mc_save save; |
||
1295 | u32 grbm_reset = 0; |
||
1296 | |||
1297 | if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE)) |
||
1298 | return 0; |
||
1299 | |||
1300 | dev_info(rdev->dev, "GPU softreset \n"); |
||
1301 | dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n", |
||
1302 | RREG32(GRBM_STATUS)); |
||
1303 | dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n", |
||
1304 | RREG32(GRBM_STATUS_SE0)); |
||
1305 | dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n", |
||
1306 | RREG32(GRBM_STATUS_SE1)); |
||
1307 | dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n", |
||
1308 | RREG32(SRBM_STATUS)); |
||
1309 | evergreen_mc_stop(rdev, &save); |
||
1310 | if (evergreen_mc_wait_for_idle(rdev)) { |
||
1311 | dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); |
||
1312 | } |
||
1313 | /* Disable CP parsing/prefetching */ |
||
1314 | WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT); |
||
1315 | |||
1316 | /* reset all the gfx blocks */ |
||
1317 | grbm_reset = (SOFT_RESET_CP | |
||
1318 | SOFT_RESET_CB | |
||
1319 | SOFT_RESET_DB | |
||
1320 | SOFT_RESET_GDS | |
||
1321 | SOFT_RESET_PA | |
||
1322 | SOFT_RESET_SC | |
||
1323 | SOFT_RESET_SPI | |
||
1324 | SOFT_RESET_SH | |
||
1325 | SOFT_RESET_SX | |
||
1326 | SOFT_RESET_TC | |
||
1327 | SOFT_RESET_TA | |
||
1328 | SOFT_RESET_VGT | |
||
1329 | SOFT_RESET_IA); |
||
1330 | |||
1331 | dev_info(rdev->dev, " GRBM_SOFT_RESET=0x%08X\n", grbm_reset); |
||
1332 | WREG32(GRBM_SOFT_RESET, grbm_reset); |
||
1333 | (void)RREG32(GRBM_SOFT_RESET); |
||
1334 | udelay(50); |
||
1335 | WREG32(GRBM_SOFT_RESET, 0); |
||
1336 | (void)RREG32(GRBM_SOFT_RESET); |
||
1337 | /* Wait a little for things to settle down */ |
||
1338 | udelay(50); |
||
1339 | dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n", |
||
1340 | RREG32(GRBM_STATUS)); |
||
1341 | dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n", |
||
1342 | RREG32(GRBM_STATUS_SE0)); |
||
1343 | dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n", |
||
1344 | RREG32(GRBM_STATUS_SE1)); |
||
1345 | dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n", |
||
1346 | RREG32(SRBM_STATUS)); |
||
1347 | evergreen_mc_resume(rdev, &save); |
||
1348 | return 0; |
||
1349 | } |
||
1350 | |||
1351 | int cayman_asic_reset(struct radeon_device *rdev) |
||
1352 | { |
||
1353 | return cayman_gpu_soft_reset(rdev); |
||
1354 | } |
||
1355 | |||
1356 | static int cayman_startup(struct radeon_device *rdev) |
||
1357 | { |
||
1358 | int r; |
||
1359 | |||
1360 | if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) { |
||
1361 | r = ni_init_microcode(rdev); |
||
1362 | if (r) { |
||
1363 | DRM_ERROR("Failed to load firmware!\n"); |
||
1364 | return r; |
||
1365 | } |
||
1366 | } |
||
1367 | r = ni_mc_load_microcode(rdev); |
||
1368 | if (r) { |
||
1369 | DRM_ERROR("Failed to load MC firmware!\n"); |
||
1370 | return r; |
||
1371 | } |
||
1372 | |||
1373 | evergreen_mc_program(rdev); |
||
1374 | r = cayman_pcie_gart_enable(rdev); |
||
1375 | if (r) |
||
1376 | return r; |
||
1377 | cayman_gpu_init(rdev); |
||
1378 | |||
2005 | serge | 1379 | r = evergreen_blit_init(rdev); |
1380 | if (r) { |
||
1381 | // evergreen_blit_fini(rdev); |
||
1382 | rdev->asic->copy = NULL; |
||
1383 | dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r); |
||
1384 | } |
||
1990 | serge | 1385 | |
1386 | /* allocate wb buffer */ |
||
2005 | serge | 1387 | r = radeon_wb_init(rdev); |
1388 | if (r) |
||
1389 | return r; |
||
1990 | serge | 1390 | |
1391 | /* Enable IRQ */ |
||
2005 | serge | 1392 | r = r600_irq_init(rdev); |
1393 | if (r) { |
||
1394 | DRM_ERROR("radeon: IH init failed (%d).\n", r); |
||
1395 | // radeon_irq_kms_fini(rdev); |
||
1396 | return r; |
||
1397 | } |
||
1398 | evergreen_irq_set(rdev); |
||
1990 | serge | 1399 | |
1400 | r = radeon_ring_init(rdev, rdev->cp.ring_size); |
||
1401 | if (r) |
||
1402 | return r; |
||
1403 | r = cayman_cp_load_microcode(rdev); |
||
1404 | if (r) |
||
1405 | return r; |
||
1406 | r = cayman_cp_resume(rdev); |
||
1407 | if (r) |
||
1408 | return r; |
||
1409 | |||
1410 | return 0; |
||
1411 | } |
||
1412 | |||
1413 | |||
1414 | |||
1415 | |||
1416 | |||
1417 | /* Plan is to move initialization in that function and use |
||
1418 | * helper function so that radeon_device_init pretty much |
||
1419 | * do nothing more than calling asic specific function. This |
||
1420 | * should also allow to remove a bunch of callback function |
||
1421 | * like vram_info. |
||
1422 | */ |
||
1423 | int cayman_init(struct radeon_device *rdev) |
||
1424 | { |
||
1425 | int r; |
||
1426 | |||
1427 | /* This don't do much */ |
||
1428 | r = radeon_gem_init(rdev); |
||
1429 | if (r) |
||
1430 | return r; |
||
1431 | /* Read BIOS */ |
||
1432 | if (!radeon_get_bios(rdev)) { |
||
1433 | if (ASIC_IS_AVIVO(rdev)) |
||
1434 | return -EINVAL; |
||
1435 | } |
||
1436 | /* Must be an ATOMBIOS */ |
||
1437 | if (!rdev->is_atom_bios) { |
||
1438 | dev_err(rdev->dev, "Expecting atombios for cayman GPU\n"); |
||
1439 | return -EINVAL; |
||
1440 | } |
||
1441 | r = radeon_atombios_init(rdev); |
||
1442 | if (r) |
||
1443 | return r; |
||
1444 | |||
1445 | /* Post card if necessary */ |
||
1446 | if (!radeon_card_posted(rdev)) { |
||
1447 | if (!rdev->bios) { |
||
1448 | dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); |
||
1449 | return -EINVAL; |
||
1450 | } |
||
1451 | DRM_INFO("GPU not posted. posting now...\n"); |
||
1452 | atom_asic_init(rdev->mode_info.atom_context); |
||
1453 | } |
||
1454 | /* Initialize scratch registers */ |
||
1455 | r600_scratch_init(rdev); |
||
1456 | /* Initialize surface registers */ |
||
1457 | radeon_surface_init(rdev); |
||
1458 | /* Initialize clocks */ |
||
1459 | radeon_get_clock_info(rdev->ddev); |
||
1460 | /* Fence driver */ |
||
2005 | serge | 1461 | r = radeon_fence_driver_init(rdev); |
1462 | if (r) |
||
1463 | return r; |
||
1990 | serge | 1464 | /* initialize memory controller */ |
1465 | r = evergreen_mc_init(rdev); |
||
1466 | if (r) |
||
1467 | return r; |
||
1468 | /* Memory manager */ |
||
1469 | r = radeon_bo_init(rdev); |
||
1470 | if (r) |
||
1471 | return r; |
||
1472 | |||
2005 | serge | 1473 | r = radeon_irq_kms_init(rdev); |
1474 | if (r) |
||
1475 | return r; |
||
1990 | serge | 1476 | |
1477 | rdev->cp.ring_obj = NULL; |
||
1478 | r600_ring_init(rdev, 1024 * 1024); |
||
1479 | |||
2005 | serge | 1480 | rdev->ih.ring_obj = NULL; |
1481 | r600_ih_ring_init(rdev, 64 * 1024); |
||
1990 | serge | 1482 | |
1483 | r = r600_pcie_gart_init(rdev); |
||
1484 | if (r) |
||
1485 | return r; |
||
1486 | |||
1487 | rdev->accel_working = true; |
||
1488 | r = cayman_startup(rdev); |
||
1489 | if (r) { |
||
1490 | dev_err(rdev->dev, "disabling GPU acceleration\n"); |
||
1491 | rdev->accel_working = false; |
||
1492 | } |
||
1493 | if (rdev->accel_working) { |
||
2005 | serge | 1494 | r = radeon_ib_pool_init(rdev); |
1495 | if (r) { |
||
1496 | DRM_ERROR("radeon: failed initializing IB pool (%d).\n", r); |
||
1497 | rdev->accel_working = false; |
||
1498 | } |
||
1499 | r = r600_ib_test(rdev); |
||
1500 | if (r) { |
||
1501 | DRM_ERROR("radeon: failed testing IB (%d).\n", r); |
||
1502 | rdev->accel_working = false; |
||
1503 | } |
||
1990 | serge | 1504 | } |
1505 | |||
1506 | /* Don't start up if the MC ucode is missing. |
||
1507 | * The default clocks and voltages before the MC ucode |
||
1508 | * is loaded are not suffient for advanced operations. |
||
1509 | */ |
||
1510 | if (!rdev->mc_fw) { |
||
1511 | DRM_ERROR("radeon: MC ucode required for NI+.\n"); |
||
1512 | return -EINVAL; |
||
1513 | } |
||
1514 | |||
1515 | return 0; |
||
1516 | }><>><>><>><>>>>>><>><>><>><>><>><>><>><>><>><>><>>><>><>><>>>><>><>>>>><>>>>>>><>><>> |
||
1517 |