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5078 | serge | 1 | /* |
2 | * Copyright 2010 Advanced Micro Devices, Inc. |
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3 | * |
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4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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5 | * copy of this software and associated documentation files (the "Software"), |
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6 | * to deal in the Software without restriction, including without limitation |
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7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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8 | * and/or sell copies of the Software, and to permit persons to whom the |
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9 | * Software is furnished to do so, subject to the following conditions: |
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10 | * |
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11 | * The above copyright notice and this permission notice shall be included in |
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12 | * all copies or substantial portions of the Software. |
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13 | * |
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14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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20 | * OTHER DEALINGS IN THE SOFTWARE. |
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21 | * |
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22 | * Authors: Alex Deucher |
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23 | */ |
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24 | #include |
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25 | #include "radeon.h" |
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26 | #include "radeon_asic.h" |
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27 | #include "evergreend.h" |
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28 | |||
29 | u32 evergreen_gpu_check_soft_reset(struct radeon_device *rdev); |
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30 | |||
31 | /** |
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32 | * evergreen_dma_fence_ring_emit - emit a fence on the DMA ring |
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33 | * |
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34 | * @rdev: radeon_device pointer |
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35 | * @fence: radeon fence object |
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36 | * |
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37 | * Add a DMA fence packet to the ring to write |
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38 | * the fence seq number and DMA trap packet to generate |
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39 | * an interrupt if needed (evergreen-SI). |
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40 | */ |
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41 | void evergreen_dma_fence_ring_emit(struct radeon_device *rdev, |
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42 | struct radeon_fence *fence) |
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43 | { |
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44 | struct radeon_ring *ring = &rdev->ring[fence->ring]; |
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45 | u64 addr = rdev->fence_drv[fence->ring].gpu_addr; |
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46 | /* write the fence */ |
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47 | radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0)); |
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48 | radeon_ring_write(ring, addr & 0xfffffffc); |
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49 | radeon_ring_write(ring, (upper_32_bits(addr) & 0xff)); |
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50 | radeon_ring_write(ring, fence->seq); |
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51 | /* generate an interrupt */ |
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52 | radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_TRAP, 0, 0)); |
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53 | /* flush HDP */ |
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54 | radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0)); |
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55 | radeon_ring_write(ring, (0xf << 16) | (HDP_MEM_COHERENCY_FLUSH_CNTL >> 2)); |
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56 | radeon_ring_write(ring, 1); |
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57 | } |
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58 | |||
59 | /** |
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60 | * evergreen_dma_ring_ib_execute - schedule an IB on the DMA engine |
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61 | * |
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62 | * @rdev: radeon_device pointer |
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63 | * @ib: IB object to schedule |
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64 | * |
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65 | * Schedule an IB in the DMA ring (evergreen). |
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66 | */ |
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67 | void evergreen_dma_ring_ib_execute(struct radeon_device *rdev, |
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68 | struct radeon_ib *ib) |
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69 | { |
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70 | struct radeon_ring *ring = &rdev->ring[ib->ring]; |
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71 | |||
72 | if (rdev->wb.enabled) { |
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73 | u32 next_rptr = ring->wptr + 4; |
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74 | while ((next_rptr & 7) != 5) |
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75 | next_rptr++; |
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76 | next_rptr += 3; |
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77 | radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 1)); |
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78 | radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); |
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79 | radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff); |
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80 | radeon_ring_write(ring, next_rptr); |
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81 | } |
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82 | |||
83 | /* The indirect buffer packet must end on an 8 DW boundary in the DMA ring. |
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84 | * Pad as necessary with NOPs. |
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85 | */ |
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86 | while ((ring->wptr & 7) != 5) |
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87 | radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0)); |
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88 | radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_INDIRECT_BUFFER, 0, 0)); |
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89 | radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0)); |
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90 | radeon_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF)); |
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91 | |||
92 | } |
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93 | |||
94 | /** |
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95 | * evergreen_copy_dma - copy pages using the DMA engine |
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96 | * |
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97 | * @rdev: radeon_device pointer |
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98 | * @src_offset: src GPU address |
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99 | * @dst_offset: dst GPU address |
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100 | * @num_gpu_pages: number of GPU pages to xfer |
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101 | * @fence: radeon fence object |
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102 | * |
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103 | * Copy GPU paging using the DMA engine (evergreen-cayman). |
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104 | * Used by the radeon ttm implementation to move pages if |
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105 | * registered as the asic copy callback. |
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106 | */ |
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5271 | serge | 107 | struct radeon_fence *evergreen_copy_dma(struct radeon_device *rdev, |
108 | uint64_t src_offset, |
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109 | uint64_t dst_offset, |
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5078 | serge | 110 | unsigned num_gpu_pages, |
5271 | serge | 111 | struct reservation_object *resv) |
5078 | serge | 112 | { |
5271 | serge | 113 | struct radeon_fence *fence; |
114 | struct radeon_sync sync; |
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5078 | serge | 115 | int ring_index = rdev->asic->copy.dma_ring_index; |
116 | struct radeon_ring *ring = &rdev->ring[ring_index]; |
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117 | u32 size_in_dw, cur_size_in_dw; |
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118 | int i, num_loops; |
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119 | int r = 0; |
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120 | |||
5271 | serge | 121 | radeon_sync_create(&sync); |
5078 | serge | 122 | |
123 | size_in_dw = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT) / 4; |
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124 | num_loops = DIV_ROUND_UP(size_in_dw, 0xfffff); |
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125 | r = radeon_ring_lock(rdev, ring, num_loops * 5 + 11); |
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126 | if (r) { |
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127 | DRM_ERROR("radeon: moving bo (%d).\n", r); |
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5271 | serge | 128 | radeon_sync_free(rdev, &sync, NULL); |
129 | return ERR_PTR(r); |
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5078 | serge | 130 | } |
131 | |||
5271 | serge | 132 | radeon_sync_resv(rdev, &sync, resv, false); |
133 | radeon_sync_rings(rdev, &sync, ring->idx); |
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5078 | serge | 134 | |
135 | for (i = 0; i < num_loops; i++) { |
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136 | cur_size_in_dw = size_in_dw; |
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137 | if (cur_size_in_dw > 0xFFFFF) |
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138 | cur_size_in_dw = 0xFFFFF; |
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139 | size_in_dw -= cur_size_in_dw; |
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140 | radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 0, cur_size_in_dw)); |
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141 | radeon_ring_write(ring, dst_offset & 0xfffffffc); |
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142 | radeon_ring_write(ring, src_offset & 0xfffffffc); |
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143 | radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff); |
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144 | radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff); |
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145 | src_offset += cur_size_in_dw * 4; |
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146 | dst_offset += cur_size_in_dw * 4; |
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147 | } |
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148 | |||
5271 | serge | 149 | r = radeon_fence_emit(rdev, &fence, ring->idx); |
5078 | serge | 150 | if (r) { |
151 | radeon_ring_unlock_undo(rdev, ring); |
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5271 | serge | 152 | radeon_sync_free(rdev, &sync, NULL); |
153 | return ERR_PTR(r); |
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5078 | serge | 154 | } |
155 | |||
156 | radeon_ring_unlock_commit(rdev, ring, false); |
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5271 | serge | 157 | radeon_sync_free(rdev, &sync, fence); |
5078 | serge | 158 | |
5271 | serge | 159 | return fence; |
5078 | serge | 160 | } |
161 | |||
162 | /** |
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163 | * evergreen_dma_is_lockup - Check if the DMA engine is locked up |
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164 | * |
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165 | * @rdev: radeon_device pointer |
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166 | * @ring: radeon_ring structure holding ring information |
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167 | * |
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168 | * Check if the async DMA engine is locked up. |
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169 | * Returns true if the engine appears to be locked up, false if not. |
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170 | */ |
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171 | bool evergreen_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) |
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172 | { |
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173 | u32 reset_mask = evergreen_gpu_check_soft_reset(rdev); |
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174 | |||
175 | if (!(reset_mask & RADEON_RESET_DMA)) { |
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176 | radeon_ring_lockup_update(rdev, ring); |
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177 | return false; |
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178 | } |
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179 | return radeon_ring_test_lockup(rdev, ring); |
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180 | }>><>><>><> |
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181 |