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Rev | Author | Line No. | Line |
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2325 | Serge | 1 | |
2 | #include |
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3 | #include |
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4 | #include |
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5 | #include |
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6 | #include |
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7 | |||
8 | |||
9 | |||
10 | |||
11 | |||
12 | |||
13 | #define IORESOURCE_PCI_FIXED (1<<4) /* Do not move resource */ |
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14 | |||
15 | |||
16 | |||
17 | |||
18 | * Translate the low bits of the PCI base |
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19 | * to the resource type |
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20 | */ |
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21 | static inline unsigned int pci_calc_resource_flags(unsigned int flags) |
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22 | { |
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23 | if (flags & PCI_BASE_ADDRESS_SPACE_IO) |
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24 | return IORESOURCE_IO; |
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25 | |||
26 | |||
27 | return IORESOURCE_MEM | IORESOURCE_PREFETCH; |
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28 | |||
29 | |||
30 | } |
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31 | |||
32 | |||
33 | |||
34 | { |
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35 | u32_t size = mask & maxbase; /* Find the significant bits */ |
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36 | |||
37 | |||
38 | return 0; |
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39 | |||
40 | |||
41 | from that the extent. */ |
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42 | size = (size & ~(size-1)) - 1; |
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43 | |||
44 | |||
45 | already been programmed with all 1s. */ |
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46 | if (base == maxbase && ((base | size) & mask) != mask) |
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47 | return 0; |
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48 | |||
49 | |||
50 | } |
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51 | |||
52 | |||
53 | { |
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54 | u64_t size = mask & maxbase; /* Find the significant bits */ |
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55 | |||
56 | |||
57 | return 0; |
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58 | |||
59 | |||
60 | from that the extent. */ |
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61 | size = (size & ~(size-1)) - 1; |
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62 | |||
63 | |||
64 | already been programmed with all 1s. */ |
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65 | if (base == maxbase && ((base | size) & mask) != mask) |
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66 | return 0; |
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67 | |||
68 | |||
69 | } |
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70 | |||
71 | |||
72 | { |
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73 | if ((mask & (PCI_BASE_ADDRESS_SPACE|PCI_BASE_ADDRESS_MEM_TYPE_MASK)) == |
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74 | (PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64)) |
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75 | return 1; |
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76 | return 0; |
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77 | } |
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78 | |||
79 | |||
80 | { |
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81 | u32_t pos, reg, next; |
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82 | u32_t l, sz; |
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83 | struct resource *res; |
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84 | |||
85 | |||
86 | { |
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87 | u64_t l64; |
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88 | u64_t sz64; |
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89 | u32_t raw_sz; |
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90 | |||
91 | |||
92 | |||
93 | |||
94 | |||
95 | |||
96 | l = PciRead32(dev->busnr, dev->devfn, reg); |
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97 | PciWrite32(dev->busnr, dev->devfn, reg, ~0); |
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98 | sz = PciRead32(dev->busnr, dev->devfn, reg); |
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99 | PciWrite32(dev->busnr, dev->devfn, reg, l); |
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100 | |||
101 | |||
102 | continue; |
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103 | |||
104 | |||
105 | l = 0; |
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106 | |||
107 | |||
108 | if ((l & PCI_BASE_ADDRESS_SPACE) == |
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109 | PCI_BASE_ADDRESS_SPACE_MEMORY) |
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110 | { |
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111 | sz = pci_size(l, sz, (u32_t)PCI_BASE_ADDRESS_MEM_MASK); |
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112 | /* |
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113 | * For 64bit prefetchable memory sz could be 0, if the |
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114 | * real size is bigger than 4G, so we need to check |
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115 | * szhi for that. |
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116 | */ |
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117 | if (!is_64bit_memory(l) && !sz) |
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118 | continue; |
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119 | res->start = l & PCI_BASE_ADDRESS_MEM_MASK; |
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120 | res->flags |= l & ~PCI_BASE_ADDRESS_MEM_MASK; |
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121 | } |
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122 | else { |
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123 | sz = pci_size(l, sz, PCI_BASE_ADDRESS_IO_MASK & 0xffff); |
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124 | if (!sz) |
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125 | continue; |
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126 | res->start = l & PCI_BASE_ADDRESS_IO_MASK; |
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127 | res->flags |= l & ~PCI_BASE_ADDRESS_IO_MASK; |
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128 | } |
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129 | res->end = res->start + (unsigned long) sz; |
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130 | res->flags |= pci_calc_resource_flags(l); |
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131 | if (is_64bit_memory(l)) |
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132 | { |
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133 | u32_t szhi, lhi; |
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134 | |||
135 | |||
136 | PciWrite32(dev->busnr, dev->devfn, reg+4, ~0); |
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137 | szhi = PciRead32(dev->busnr, dev->devfn, reg+4); |
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138 | PciWrite32(dev->busnr, dev->devfn, reg+4, lhi); |
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139 | sz64 = ((u64_t)szhi << 32) | raw_sz; |
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140 | l64 = ((u64_t)lhi << 32) | l; |
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141 | sz64 = pci_size64(l64, sz64, PCI_BASE_ADDRESS_MEM_MASK); |
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142 | next++; |
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143 | |||
144 | |||
145 | if (!sz64) { |
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146 | res->start = 0; |
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147 | res->end = 0; |
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148 | res->flags = 0; |
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149 | continue; |
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150 | } |
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151 | res->start = l64 & PCI_BASE_ADDRESS_MEM_MASK; |
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152 | res->end = res->start + sz64; |
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153 | #else |
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154 | if (sz64 > 0x100000000ULL) { |
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155 | printk(KERN_ERR "PCI: Unable to handle 64-bit " |
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156 | "BAR for device %s\n", pci_name(dev)); |
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157 | res->start = 0; |
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158 | res->flags = 0; |
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159 | } |
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160 | else if (lhi) |
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161 | { |
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162 | /* 64-bit wide address, treat as disabled */ |
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163 | PciWrite32(dev->busnr, dev->devfn, reg, |
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164 | l & ~(u32_t)PCI_BASE_ADDRESS_MEM_MASK); |
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165 | PciWrite32(dev->busnr, dev->devfn, reg+4, 0); |
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166 | res->start = 0; |
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167 | res->end = sz; |
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168 | } |
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169 | #endif |
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170 | } |
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171 | } |
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172 | |||
173 | |||
174 | { |
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175 | dev->rom_base_reg = rom; |
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176 | res = &dev->resource[PCI_ROM_RESOURCE]; |
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177 | |||
178 | |||
179 | PciWrite32(dev->busnr, dev->devfn, rom, ~PCI_ROM_ADDRESS_ENABLE); |
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180 | sz = PciRead32(dev->busnr, dev->devfn, rom); |
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181 | PciWrite32(dev->busnr, dev->devfn, rom, l); |
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182 | |||
183 | |||
184 | l = 0; |
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185 | |||
186 | |||
187 | { |
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188 | sz = pci_size(l, sz, (u32_t)PCI_ROM_ADDRESS_MASK); |
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189 | |||
190 | |||
191 | { |
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192 | res->flags = (l & IORESOURCE_ROM_ENABLE) | |
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193 | IORESOURCE_MEM | IORESOURCE_PREFETCH | |
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194 | IORESOURCE_READONLY | IORESOURCE_CACHEABLE; |
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195 | res->start = l & PCI_ROM_ADDRESS_MASK; |
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196 | res->end = res->start + (unsigned long) sz; |
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197 | } |
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198 | } |
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199 | } |
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200 | } |
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201 | |||
202 | |||
203 | { |
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204 | u8_t irq; |
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205 | |||
206 | |||
207 | dev->pin = irq; |
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208 | if (irq) |
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209 | irq = PciRead8(dev->busnr, dev->devfn, PCI_INTERRUPT_LINE); |
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210 | dev->irq = irq; |
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211 | }; |
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212 | |||
213 | |||
214 | |||
215 | { |
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216 | u32_t class; |
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217 | |||
218 | |||
219 | dev->revision = class & 0xff; |
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220 | class >>= 8; /* upper 3 bytes */ |
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221 | dev->class = class; |
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222 | |||
223 | |||
224 | // dev->current_state = PCI_UNKNOWN; |
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225 | |||
226 | |||
227 | // pci_fixup_device(pci_fixup_early, dev); |
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228 | class = dev->class >> 8; |
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229 | |||
230 | |||
231 | { |
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232 | case PCI_HEADER_TYPE_NORMAL: /* standard header */ |
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233 | if (class == PCI_CLASS_BRIDGE_PCI) |
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234 | goto bad; |
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235 | pci_read_irq(dev); |
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236 | pci_read_bases(dev, 6, PCI_ROM_ADDRESS); |
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237 | dev->subsystem_vendor = PciRead16(dev->busnr, dev->devfn,PCI_SUBSYSTEM_VENDOR_ID); |
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238 | dev->subsystem_device = PciRead16(dev->busnr, dev->devfn, PCI_SUBSYSTEM_ID); |
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239 | |||
240 | |||
241 | * Do the ugly legacy mode stuff here rather than broken chip |
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242 | * quirk code. Legacy mode ATA controllers have fixed |
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243 | * addresses. These are not always echoed in BAR0-3, and |
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244 | * BAR0-3 in a few cases contain junk! |
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245 | */ |
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246 | if (class == PCI_CLASS_STORAGE_IDE) |
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247 | { |
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248 | u8_t progif; |
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249 | |||
250 | |||
251 | if ((progif & 1) == 0) |
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252 | { |
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253 | dev->resource[0].start = 0x1F0; |
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254 | dev->resource[0].end = 0x1F7; |
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255 | dev->resource[0].flags = LEGACY_IO_RESOURCE; |
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256 | dev->resource[1].start = 0x3F6; |
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257 | dev->resource[1].end = 0x3F6; |
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258 | dev->resource[1].flags = LEGACY_IO_RESOURCE; |
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259 | } |
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260 | if ((progif & 4) == 0) |
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261 | { |
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262 | dev->resource[2].start = 0x170; |
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263 | dev->resource[2].end = 0x177; |
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264 | dev->resource[2].flags = LEGACY_IO_RESOURCE; |
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265 | dev->resource[3].start = 0x376; |
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266 | dev->resource[3].end = 0x376; |
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267 | dev->resource[3].flags = LEGACY_IO_RESOURCE; |
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268 | }; |
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269 | } |
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270 | break; |
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271 | |||
272 | |||
273 | if (class != PCI_CLASS_BRIDGE_PCI) |
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274 | goto bad; |
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275 | /* The PCI-to-PCI bridge spec requires that subtractive |
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276 | decoding (i.e. transparent) bridge must have programming |
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277 | interface code of 0x01. */ |
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278 | pci_read_irq(dev); |
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279 | dev->transparent = ((dev->class & 0xff) == 1); |
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280 | pci_read_bases(dev, 2, PCI_ROM_ADDRESS1); |
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281 | break; |
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282 | |||
283 | |||
284 | if (class != PCI_CLASS_BRIDGE_CARDBUS) |
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285 | goto bad; |
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286 | pci_read_irq(dev); |
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287 | pci_read_bases(dev, 1, 0); |
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288 | dev->subsystem_vendor = PciRead16(dev->busnr, |
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289 | dev->devfn, |
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290 | PCI_CB_SUBSYSTEM_VENDOR_ID); |
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291 | |||
292 | |||
293 | dev->devfn, |
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294 | PCI_CB_SUBSYSTEM_ID); |
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295 | break; |
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296 | |||
297 | |||
298 | printk(KERN_ERR "PCI: device %s has unknown header type %02x, ignoring.\n", |
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299 | pci_name(dev), dev->hdr_type); |
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300 | return -1; |
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301 | |||
302 | |||
303 | printk(KERN_ERR "PCI: %s: class %x doesn't match header type %02x. Ignoring class.\n", |
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304 | pci_name(dev), class, dev->hdr_type); |
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305 | dev->class = PCI_CLASS_NOT_DEFINED; |
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306 | } |
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307 | |||
308 | |||
309 | |||
310 | |||
311 | }; |
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312 | |||
313 | |||
314 | { |
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315 | pci_dev_t *dev; |
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316 | |||
317 | |||
318 | u8_t hdr; |
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319 | |||
320 | |||
321 | |||
322 | |||
323 | |||
324 | |||
325 | if (id == 0xffffffff || id == 0x00000000 || |
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326 | id == 0x0000ffff || id == 0xffff0000) |
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327 | return NULL; |
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328 | |||
329 | |||
330 | { |
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331 | |||
332 | |||
333 | timeout *= 2; |
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334 | |||
335 | |||
336 | |||
337 | |||
338 | if (timeout > 60 * 100) |
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339 | { |
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340 | printk(KERN_WARNING "Device %04x:%02x:%02x.%d not " |
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341 | "responding\n", busnr,PCI_SLOT(devfn),PCI_FUNC(devfn)); |
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342 | return NULL; |
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343 | } |
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344 | }; |
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345 | |||
346 | |||
347 | return NULL; |
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348 | |||
349 | |||
350 | |||
351 | |||
352 | |||
353 | |||
354 | |||
355 | |||
356 | return NULL; |
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357 | |||
358 | |||
359 | dev->pci_dev.devfn = devfn; |
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360 | dev->pci_dev.hdr_type = hdr & 0x7f; |
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361 | dev->pci_dev.multifunction = !!(hdr & 0x80); |
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362 | dev->pci_dev.vendor = id & 0xffff; |
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363 | dev->pci_dev.device = (id >> 16) & 0xffff; |
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364 | |||
365 | |||
366 | |||
367 | |||
368 | |||
369 | |||
370 | |||
371 | |||
372 | |||
373 | |||
374 | |||
375 | { |
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376 | int func, nr = 0; |
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377 | |||
378 | |||
379 | { |
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380 | pci_dev_t *dev; |
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381 | |||
382 | |||
383 | if( dev ) |
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384 | { |
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385 | list_add(&dev->link, &devices); |
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386 | |||
387 | |||
388 | |||
389 | |||
390 | * If this is a single function device, |
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391 | * don't scan past the first function. |
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392 | */ |
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393 | if (!dev->pci_dev.multifunction) |
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394 | { |
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395 | if (func > 0) { |
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396 | dev->pci_dev.multifunction = 1; |
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397 | } |
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398 | else { |
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399 | break; |
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400 | } |
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401 | } |
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402 | } |
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403 | else { |
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404 | if (func == 0) |
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405 | break; |
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406 | } |
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407 | }; |
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408 | |||
409 | |||
410 | }; |
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411 | |||
412 | |||
413 | |||
414 | |||
415 | u8 pos, int cap, int *ttl) |
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416 | { |
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417 | u8 id; |
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418 | |||
419 | |||
420 | pos = PciRead8(bus, devfn, pos); |
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421 | if (pos < 0x40) |
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422 | break; |
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423 | pos &= ~3; |
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424 | id = PciRead8(bus, devfn, pos + PCI_CAP_LIST_ID); |
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425 | if (id == 0xff) |
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426 | break; |
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427 | if (id == cap) |
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428 | return pos; |
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429 | pos += PCI_CAP_LIST_NEXT; |
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430 | } |
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431 | return 0; |
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432 | } |
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433 | |||
434 | |||
435 | u8 pos, int cap) |
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436 | { |
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437 | int ttl = PCI_FIND_CAP_TTL; |
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438 | |||
439 | |||
440 | } |
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441 | |||
442 | |||
443 | unsigned int devfn, u8 hdr_type) |
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444 | { |
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445 | u16 status; |
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446 | |||
447 | |||
448 | if (!(status & PCI_STATUS_CAP_LIST)) |
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449 | return 0; |
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450 | |||
451 | |||
452 | case PCI_HEADER_TYPE_NORMAL: |
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453 | case PCI_HEADER_TYPE_BRIDGE: |
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454 | return PCI_CAPABILITY_LIST; |
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455 | case PCI_HEADER_TYPE_CARDBUS: |
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456 | return PCI_CB_CAPABILITY_LIST; |
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457 | default: |
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458 | return 0; |
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459 | } |
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460 | |||
461 | |||
462 | } |
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463 | |||
464 | |||
465 | |||
466 | { |
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467 | int pos; |
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468 | |||
469 | |||
470 | if (pos) |
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471 | pos = __pci_find_next_cap(dev->busnr, dev->devfn, pos, cap); |
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472 | |||
473 | |||
474 | } |
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475 | |||
476 | |||
477 | |||
478 | |||
479 | |||
480 | { |
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481 | pci_dev_t *dev; |
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482 | u32_t last_bus; |
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483 | u32_t bus = 0 , devfn = 0; |
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484 | |||
485 | |||
486 | |||
487 | |||
488 | |||
489 | |||
490 | return -1; |
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491 | |||
492 | |||
493 | { |
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494 | for (devfn = 0; devfn < 0x100; devfn += 8) |
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495 | pci_scan_slot(bus, devfn); |
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496 | |||
497 | |||
498 | |||
499 | for(dev = (pci_dev_t*)devices.next; |
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500 | &dev->link != &devices; |
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501 | dev = (pci_dev_t*)dev->link.next) |
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502 | { |
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503 | dbgprintf("PCI device %x:%x bus:%x devfn:%x\n", |
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504 | dev->pci_dev.vendor, |
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505 | dev->pci_dev.device, |
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506 | dev->pci_dev.busnr, |
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2326 | Serge | 507 | dev->pci_dev.devfn); |
2325 | Serge | 508 | |
509 | |||
510 | return 0; |
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511 | } |
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512 | |||
513 | |||
514 | { |
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515 | pci_dev_t *dev; |
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516 | const struct pci_device_id *ent; |
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517 | |||
518 | |||
519 | &dev->link != &devices; |
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520 | dev = (pci_dev_t*)dev->link.next) |
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521 | { |
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522 | if( dev->pci_dev.vendor != idlist->vendor ) |
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523 | continue; |
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524 | |||
525 | |||
526 | { |
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527 | if(unlikely(ent->device == dev->pci_dev.device)) |
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528 | { |
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529 | pdev->pci_dev = dev->pci_dev; |
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530 | return ent; |
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531 | } |
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532 | }; |
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533 | } |
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534 | |||
535 | |||
536 | }; |
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537 | |||
538 | |||
539 | pci_get_device(unsigned int vendor, unsigned int device, struct pci_dev *from) |
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540 | { |
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541 | pci_dev_t *dev; |
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542 | |||
543 | |||
544 | |||
545 | |||
546 | { |
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547 | for(; &dev->link != &devices; |
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548 | dev = (pci_dev_t*)dev->link.next) |
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549 | { |
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550 | if( &dev->pci_dev == from) |
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551 | { |
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552 | dev = (pci_dev_t*)dev->link.next; |
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553 | break; |
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554 | }; |
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555 | } |
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556 | }; |
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557 | |||
558 | |||
559 | dev = (pci_dev_t*)dev->link.next) |
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560 | { |
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561 | if( dev->pci_dev.vendor != vendor ) |
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562 | continue; |
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563 | |||
564 | |||
565 | { |
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566 | return &dev->pci_dev; |
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567 | } |
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568 | } |
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569 | return NULL; |
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570 | }; |
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571 | |||
2326 | Serge | 572 | |
573 | |||
574 | { |
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575 | pci_dev_t *dev; |
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576 | |||
577 | |||
578 | &dev->link != &devices; |
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579 | dev = (pci_dev_t*)dev->link.next) |
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580 | { |
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581 | if ( dev->pci_dev.busnr == bus && dev->pci_dev.devfn == devfn) |
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582 | return &dev->pci_dev; |
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583 | } |
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584 | return NULL; |
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585 | } |
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586 | |||
587 | |||
588 | { |
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589 | pci_dev_t *dev; |
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590 | |||
591 | |||
592 | |||
593 | |||
594 | { |
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595 | for(; &dev->link != &devices; |
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596 | dev = (pci_dev_t*)dev->link.next) |
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597 | { |
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598 | if( &dev->pci_dev == from) |
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599 | { |
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600 | dev = (pci_dev_t*)dev->link.next; |
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601 | break; |
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602 | }; |
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603 | } |
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604 | }; |
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605 | |||
606 | |||
607 | dev = (pci_dev_t*)dev->link.next) |
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608 | { |
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609 | if( dev->pci_dev.class == class) |
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610 | { |
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611 | return &dev->pci_dev; |
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612 | } |
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613 | } |
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614 | |||
615 | |||
616 | } |
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617 | |||
618 | |||
619 | |||
620 | #define PIO_MASK 0x0ffffUL |
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621 | #define PIO_RESERVED 0x40000UL |
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622 | |||
623 | |||
624 | unsigned long port = (unsigned long __force)addr; \ |
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625 | if (port >= PIO_RESERVED) { \ |
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626 | is_mmio; \ |
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627 | } else if (port > PIO_OFFSET) { \ |
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628 | port &= PIO_MASK; \ |
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629 | is_pio; \ |
||
630 | }; \ |
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631 | } while (0) |
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632 | |||
633 | |||
634 | void __iomem *ioport_map(unsigned long port, unsigned int nr) |
||
635 | { |
||
636 | if (port > PIO_MASK) |
||
637 | return NULL; |
||
638 | return (void __iomem *) (unsigned long) (port + PIO_OFFSET); |
||
639 | } |
||
640 | |||
641 | |||
642 | { |
||
643 | resource_size_t start = pci_resource_start(dev, bar); |
||
644 | resource_size_t len = pci_resource_len(dev, bar); |
||
645 | unsigned long flags = pci_resource_flags(dev, bar); |
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646 | |||
647 | |||
648 | return NULL; |
||
649 | if (maxlen && len > maxlen) |
||
650 | len = maxlen; |
||
651 | if (flags & IORESOURCE_IO) |
||
652 | return ioport_map(start, len); |
||
653 | if (flags & IORESOURCE_MEM) { |
||
654 | return ioremap(start, len); |
||
655 | } |
||
656 | /* What? */ |
||
657 | return NULL; |
||
658 | } |
||
659 | |||
660 | |||
661 | { |
||
662 | IO_COND(addr, /* nothing */, iounmap(addr)); |
||
663 | }>=>>>><>><>><>>4)><4)> |
||
664 |