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4104 | Serge | 1 | /* |
2 | * Copyright © 2013 Intel Corporation |
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3 | * |
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4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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5 | * copy of this software and associated documentation files (the "Software"), |
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6 | * to deal in the Software without restriction, including without limitation |
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7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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8 | * and/or sell copies of the Software, and to permit persons to whom the |
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9 | * Software is furnished to do so, subject to the following conditions: |
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10 | * |
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11 | * The above copyright notice and this permission notice (including the next |
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12 | * paragraph) shall be included in all copies or substantial portions of the |
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13 | * Software. |
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14 | * |
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15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
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21 | * IN THE SOFTWARE. |
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22 | */ |
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23 | |||
24 | #include "i915_drv.h" |
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25 | #include "intel_drv.h" |
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26 | |||
27 | #define FORCEWAKE_ACK_TIMEOUT_MS 2 |
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28 | |||
29 | #define __raw_i915_read8(dev_priv__, reg__) readb((dev_priv__)->regs + (reg__)) |
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30 | #define __raw_i915_write8(dev_priv__, reg__, val__) writeb(val__, (dev_priv__)->regs + (reg__)) |
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31 | |||
32 | #define __raw_i915_read16(dev_priv__, reg__) readw((dev_priv__)->regs + (reg__)) |
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33 | #define __raw_i915_write16(dev_priv__, reg__, val__) writew(val__, (dev_priv__)->regs + (reg__)) |
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34 | |||
35 | #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__)) |
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36 | #define __raw_i915_write32(dev_priv__, reg__, val__) writel(val__, (dev_priv__)->regs + (reg__)) |
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37 | |||
38 | #define __raw_i915_read64(dev_priv__, reg__) readq((dev_priv__)->regs + (reg__)) |
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39 | #define __raw_i915_write64(dev_priv__, reg__, val__) writeq(val__, (dev_priv__)->regs + (reg__)) |
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40 | |||
41 | #define __raw_posting_read(dev_priv__, reg__) (void)__raw_i915_read32(dev_priv__, reg__) |
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42 | |||
43 | |||
44 | static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv) |
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45 | { |
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46 | u32 gt_thread_status_mask; |
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47 | |||
48 | if (IS_HASWELL(dev_priv->dev)) |
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49 | gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK_HSW; |
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50 | else |
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51 | gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK; |
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52 | |||
53 | /* w/a for a sporadic read returning 0 by waiting for the GT |
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54 | * thread to wake up. |
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55 | */ |
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56 | if (wait_for_atomic_us((__raw_i915_read32(dev_priv, GEN6_GT_THREAD_STATUS_REG) & gt_thread_status_mask) == 0, 500)) |
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57 | DRM_ERROR("GT thread status wait timed out\n"); |
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58 | } |
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59 | |||
60 | static void __gen6_gt_force_wake_reset(struct drm_i915_private *dev_priv) |
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61 | { |
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62 | __raw_i915_write32(dev_priv, FORCEWAKE, 0); |
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63 | /* something from same cacheline, but !FORCEWAKE */ |
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64 | __raw_posting_read(dev_priv, ECOBUS); |
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65 | } |
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66 | |||
67 | static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv) |
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68 | { |
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69 | if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK) & 1) == 0, |
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70 | FORCEWAKE_ACK_TIMEOUT_MS)) |
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71 | DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n"); |
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72 | |||
73 | __raw_i915_write32(dev_priv, FORCEWAKE, 1); |
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74 | /* something from same cacheline, but !FORCEWAKE */ |
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75 | __raw_posting_read(dev_priv, ECOBUS); |
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76 | |||
77 | if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK) & 1), |
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78 | FORCEWAKE_ACK_TIMEOUT_MS)) |
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79 | DRM_ERROR("Timed out waiting for forcewake to ack request.\n"); |
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80 | |||
81 | /* WaRsForcewakeWaitTC0:snb */ |
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82 | __gen6_gt_wait_for_thread_c0(dev_priv); |
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83 | } |
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84 | |||
85 | static void __gen6_gt_force_wake_mt_reset(struct drm_i915_private *dev_priv) |
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86 | { |
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87 | __raw_i915_write32(dev_priv, FORCEWAKE_MT, _MASKED_BIT_DISABLE(0xffff)); |
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88 | /* something from same cacheline, but !FORCEWAKE_MT */ |
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89 | __raw_posting_read(dev_priv, ECOBUS); |
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90 | } |
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91 | |||
92 | static void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv) |
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93 | { |
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94 | u32 forcewake_ack; |
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95 | |||
96 | if (IS_HASWELL(dev_priv->dev)) |
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97 | forcewake_ack = FORCEWAKE_ACK_HSW; |
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98 | else |
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99 | forcewake_ack = FORCEWAKE_MT_ACK; |
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100 | |||
101 | if (wait_for_atomic((__raw_i915_read32(dev_priv, forcewake_ack) & FORCEWAKE_KERNEL) == 0, |
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102 | FORCEWAKE_ACK_TIMEOUT_MS)) |
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103 | DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n"); |
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104 | |||
105 | __raw_i915_write32(dev_priv, FORCEWAKE_MT, |
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106 | _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL)); |
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107 | /* something from same cacheline, but !FORCEWAKE_MT */ |
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108 | __raw_posting_read(dev_priv, ECOBUS); |
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109 | |||
110 | if (wait_for_atomic((__raw_i915_read32(dev_priv, forcewake_ack) & FORCEWAKE_KERNEL), |
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111 | FORCEWAKE_ACK_TIMEOUT_MS)) |
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112 | DRM_ERROR("Timed out waiting for forcewake to ack request.\n"); |
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113 | |||
114 | /* WaRsForcewakeWaitTC0:ivb,hsw */ |
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115 | __gen6_gt_wait_for_thread_c0(dev_priv); |
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116 | } |
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117 | |||
118 | static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv) |
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119 | { |
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120 | u32 gtfifodbg; |
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121 | |||
122 | gtfifodbg = __raw_i915_read32(dev_priv, GTFIFODBG); |
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123 | if (WARN(gtfifodbg & GT_FIFO_CPU_ERROR_MASK, |
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124 | "MMIO read or write has been dropped %x\n", gtfifodbg)) |
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125 | __raw_i915_write32(dev_priv, GTFIFODBG, GT_FIFO_CPU_ERROR_MASK); |
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126 | } |
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127 | |||
128 | static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv) |
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129 | { |
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130 | __raw_i915_write32(dev_priv, FORCEWAKE, 0); |
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131 | /* something from same cacheline, but !FORCEWAKE */ |
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132 | __raw_posting_read(dev_priv, ECOBUS); |
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133 | gen6_gt_check_fifodbg(dev_priv); |
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134 | } |
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135 | |||
136 | static void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv) |
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137 | { |
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138 | __raw_i915_write32(dev_priv, FORCEWAKE_MT, |
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139 | _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL)); |
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140 | /* something from same cacheline, but !FORCEWAKE_MT */ |
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141 | __raw_posting_read(dev_priv, ECOBUS); |
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142 | gen6_gt_check_fifodbg(dev_priv); |
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143 | } |
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144 | |||
145 | static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv) |
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146 | { |
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147 | int ret = 0; |
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148 | |||
149 | if (dev_priv->uncore.fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) { |
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150 | int loop = 500; |
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151 | u32 fifo = __raw_i915_read32(dev_priv, GT_FIFO_FREE_ENTRIES); |
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152 | while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) { |
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153 | udelay(10); |
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154 | fifo = __raw_i915_read32(dev_priv, GT_FIFO_FREE_ENTRIES); |
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155 | } |
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156 | if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES)) |
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157 | ++ret; |
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158 | dev_priv->uncore.fifo_count = fifo; |
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159 | } |
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160 | dev_priv->uncore.fifo_count--; |
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161 | |||
162 | return ret; |
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163 | } |
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164 | |||
165 | static void vlv_force_wake_reset(struct drm_i915_private *dev_priv) |
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166 | { |
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167 | __raw_i915_write32(dev_priv, FORCEWAKE_VLV, |
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168 | _MASKED_BIT_DISABLE(0xffff)); |
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169 | /* something from same cacheline, but !FORCEWAKE_VLV */ |
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170 | __raw_posting_read(dev_priv, FORCEWAKE_ACK_VLV); |
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171 | } |
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172 | |||
173 | static void vlv_force_wake_get(struct drm_i915_private *dev_priv) |
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174 | { |
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175 | if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK_VLV) & FORCEWAKE_KERNEL) == 0, |
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176 | FORCEWAKE_ACK_TIMEOUT_MS)) |
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177 | DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n"); |
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178 | |||
179 | __raw_i915_write32(dev_priv, FORCEWAKE_VLV, |
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180 | _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL)); |
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181 | __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV, |
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182 | _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL)); |
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183 | |||
184 | if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK_VLV) & FORCEWAKE_KERNEL), |
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185 | FORCEWAKE_ACK_TIMEOUT_MS)) |
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186 | DRM_ERROR("Timed out waiting for GT to ack forcewake request.\n"); |
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187 | |||
188 | if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK_MEDIA_VLV) & |
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189 | FORCEWAKE_KERNEL), |
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190 | FORCEWAKE_ACK_TIMEOUT_MS)) |
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191 | DRM_ERROR("Timed out waiting for media to ack forcewake request.\n"); |
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192 | |||
193 | /* WaRsForcewakeWaitTC0:vlv */ |
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194 | __gen6_gt_wait_for_thread_c0(dev_priv); |
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195 | } |
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196 | |||
197 | static void vlv_force_wake_put(struct drm_i915_private *dev_priv) |
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198 | { |
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199 | __raw_i915_write32(dev_priv, FORCEWAKE_VLV, |
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200 | _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL)); |
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201 | __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV, |
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202 | _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL)); |
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203 | /* The below doubles as a POSTING_READ */ |
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204 | gen6_gt_check_fifodbg(dev_priv); |
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205 | } |
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206 | |||
207 | void intel_uncore_early_sanitize(struct drm_device *dev) |
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208 | { |
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209 | struct drm_i915_private *dev_priv = dev->dev_private; |
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210 | |||
211 | if (HAS_FPGA_DBG_UNCLAIMED(dev)) |
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212 | __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM); |
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213 | } |
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214 | |||
215 | void intel_uncore_init(struct drm_device *dev) |
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216 | { |
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217 | struct drm_i915_private *dev_priv = dev->dev_private; |
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218 | |||
219 | if (IS_VALLEYVIEW(dev)) { |
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220 | dev_priv->uncore.funcs.force_wake_get = vlv_force_wake_get; |
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221 | dev_priv->uncore.funcs.force_wake_put = vlv_force_wake_put; |
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222 | } else if (IS_HASWELL(dev)) { |
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223 | dev_priv->uncore.funcs.force_wake_get = __gen6_gt_force_wake_mt_get; |
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224 | dev_priv->uncore.funcs.force_wake_put = __gen6_gt_force_wake_mt_put; |
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225 | } else if (IS_IVYBRIDGE(dev)) { |
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226 | u32 ecobus; |
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227 | |||
228 | /* IVB configs may use multi-threaded forcewake */ |
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229 | |||
230 | /* A small trick here - if the bios hasn't configured |
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231 | * MT forcewake, and if the device is in RC6, then |
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232 | * force_wake_mt_get will not wake the device and the |
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233 | * ECOBUS read will return zero. Which will be |
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234 | * (correctly) interpreted by the test below as MT |
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235 | * forcewake being disabled. |
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236 | */ |
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237 | mutex_lock(&dev->struct_mutex); |
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238 | __gen6_gt_force_wake_mt_get(dev_priv); |
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239 | ecobus = __raw_i915_read32(dev_priv, ECOBUS); |
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240 | __gen6_gt_force_wake_mt_put(dev_priv); |
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241 | mutex_unlock(&dev->struct_mutex); |
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242 | |||
243 | if (ecobus & FORCEWAKE_MT_ENABLE) { |
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244 | dev_priv->uncore.funcs.force_wake_get = |
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245 | __gen6_gt_force_wake_mt_get; |
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246 | dev_priv->uncore.funcs.force_wake_put = |
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247 | __gen6_gt_force_wake_mt_put; |
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248 | } else { |
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249 | DRM_INFO("No MT forcewake available on Ivybridge, this can result in issues\n"); |
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250 | DRM_INFO("when using vblank-synced partial screen updates.\n"); |
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251 | dev_priv->uncore.funcs.force_wake_get = |
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252 | __gen6_gt_force_wake_get; |
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253 | dev_priv->uncore.funcs.force_wake_put = |
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254 | __gen6_gt_force_wake_put; |
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255 | } |
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256 | } else if (IS_GEN6(dev)) { |
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257 | dev_priv->uncore.funcs.force_wake_get = |
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258 | __gen6_gt_force_wake_get; |
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259 | dev_priv->uncore.funcs.force_wake_put = |
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260 | __gen6_gt_force_wake_put; |
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261 | } |
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262 | } |
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263 | |||
264 | static void intel_uncore_forcewake_reset(struct drm_device *dev) |
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265 | { |
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266 | struct drm_i915_private *dev_priv = dev->dev_private; |
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267 | |||
268 | if (IS_VALLEYVIEW(dev)) { |
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269 | vlv_force_wake_reset(dev_priv); |
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270 | } else if (INTEL_INFO(dev)->gen >= 6) { |
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271 | __gen6_gt_force_wake_reset(dev_priv); |
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272 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) |
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273 | __gen6_gt_force_wake_mt_reset(dev_priv); |
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274 | } |
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275 | } |
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276 | |||
277 | void intel_uncore_sanitize(struct drm_device *dev) |
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278 | { |
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279 | intel_uncore_forcewake_reset(dev); |
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280 | |||
281 | /* BIOS often leaves RC6 enabled, but disable it for hw init */ |
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282 | intel_disable_gt_powersave(dev); |
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283 | } |
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284 | |||
285 | /* |
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286 | * Generally this is called implicitly by the register read function. However, |
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287 | * if some sequence requires the GT to not power down then this function should |
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288 | * be called at the beginning of the sequence followed by a call to |
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289 | * gen6_gt_force_wake_put() at the end of the sequence. |
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290 | */ |
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291 | void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv) |
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292 | { |
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293 | unsigned long irqflags; |
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294 | |||
295 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
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296 | if (dev_priv->uncore.forcewake_count++ == 0) |
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297 | dev_priv->uncore.funcs.force_wake_get(dev_priv); |
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298 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
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299 | } |
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300 | |||
301 | /* |
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302 | * see gen6_gt_force_wake_get() |
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303 | */ |
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304 | void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv) |
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305 | { |
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306 | unsigned long irqflags; |
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307 | |||
308 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
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309 | if (--dev_priv->uncore.forcewake_count == 0) |
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310 | dev_priv->uncore.funcs.force_wake_put(dev_priv); |
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311 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
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312 | } |
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313 | |||
314 | /* We give fast paths for the really cool registers */ |
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315 | #define NEEDS_FORCE_WAKE(dev_priv, reg) \ |
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316 | ((HAS_FORCE_WAKE((dev_priv)->dev)) && \ |
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317 | ((reg) < 0x40000) && \ |
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318 | ((reg) != FORCEWAKE)) |
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319 | |||
320 | static void |
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321 | ilk_dummy_write(struct drm_i915_private *dev_priv) |
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322 | { |
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323 | /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up |
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324 | * the chip from rc6 before touching it for real. MI_MODE is masked, |
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325 | * hence harmless to write 0 into. */ |
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326 | __raw_i915_write32(dev_priv, MI_MODE, 0); |
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327 | } |
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328 | |||
329 | static void |
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330 | hsw_unclaimed_reg_clear(struct drm_i915_private *dev_priv, u32 reg) |
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331 | { |
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332 | if (HAS_FPGA_DBG_UNCLAIMED(dev_priv->dev) && |
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333 | (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) { |
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334 | DRM_ERROR("Unknown unclaimed register before writing to %x\n", |
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335 | reg); |
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336 | __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM); |
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337 | } |
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338 | } |
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339 | |||
340 | static void |
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341 | hsw_unclaimed_reg_check(struct drm_i915_private *dev_priv, u32 reg) |
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342 | { |
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343 | if (HAS_FPGA_DBG_UNCLAIMED(dev_priv->dev) && |
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344 | (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) { |
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345 | DRM_ERROR("Unclaimed write to %x\n", reg); |
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346 | __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM); |
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347 | } |
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348 | } |
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349 | |||
350 | #define __i915_read(x) \ |
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351 | u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg, bool trace) { \ |
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352 | unsigned long irqflags; \ |
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353 | u##x val = 0; \ |
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354 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); \ |
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355 | if (dev_priv->info->gen == 5) \ |
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356 | ilk_dummy_write(dev_priv); \ |
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357 | if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ |
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358 | if (dev_priv->uncore.forcewake_count == 0) \ |
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359 | dev_priv->uncore.funcs.force_wake_get(dev_priv); \ |
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360 | val = __raw_i915_read##x(dev_priv, reg); \ |
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361 | if (dev_priv->uncore.forcewake_count == 0) \ |
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362 | dev_priv->uncore.funcs.force_wake_put(dev_priv); \ |
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363 | } else { \ |
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364 | val = __raw_i915_read##x(dev_priv, reg); \ |
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365 | } \ |
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366 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \ |
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367 | return val; \ |
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368 | } |
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369 | |||
370 | __i915_read(8) |
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371 | __i915_read(16) |
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372 | __i915_read(32) |
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373 | __i915_read(64) |
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374 | #undef __i915_read |
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375 | |||
376 | #define __i915_write(x) \ |
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377 | void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val, bool trace) { \ |
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378 | unsigned long irqflags; \ |
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379 | u32 __fifo_ret = 0; \ |
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380 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); \ |
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381 | if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ |
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382 | __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \ |
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383 | } \ |
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384 | if (dev_priv->info->gen == 5) \ |
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385 | ilk_dummy_write(dev_priv); \ |
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386 | hsw_unclaimed_reg_clear(dev_priv, reg); \ |
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387 | __raw_i915_write##x(dev_priv, reg, val); \ |
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388 | if (unlikely(__fifo_ret)) { \ |
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389 | gen6_gt_check_fifodbg(dev_priv); \ |
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390 | } \ |
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391 | hsw_unclaimed_reg_check(dev_priv, reg); \ |
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392 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \ |
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393 | } |
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394 | __i915_write(8) |
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395 | __i915_write(16) |
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396 | __i915_write(32) |
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397 | __i915_write(64) |
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398 | #undef __i915_write |
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399 | |||
400 | static const struct register_whitelist { |
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401 | uint64_t offset; |
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402 | uint32_t size; |
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403 | uint32_t gen_bitmask; /* support gens, 0x10 for 4, 0x30 for 4 and 5, etc. */ |
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404 | } whitelist[] = { |
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405 | { RING_TIMESTAMP(RENDER_RING_BASE), 8, 0xF0 }, |
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406 | }; |
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407 | |||
408 | int i915_reg_read_ioctl(struct drm_device *dev, |
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409 | void *data, struct drm_file *file) |
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410 | { |
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411 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
412 | struct drm_i915_reg_read *reg = data; |
||
413 | struct register_whitelist const *entry = whitelist; |
||
414 | int i; |
||
415 | |||
416 | for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) { |
||
417 | if (entry->offset == reg->offset && |
||
418 | (1 << INTEL_INFO(dev)->gen & entry->gen_bitmask)) |
||
419 | break; |
||
420 | } |
||
421 | |||
422 | if (i == ARRAY_SIZE(whitelist)) |
||
423 | return -EINVAL; |
||
424 | |||
425 | switch (entry->size) { |
||
426 | case 8: |
||
427 | reg->val = I915_READ64(reg->offset); |
||
428 | break; |
||
429 | case 4: |
||
430 | reg->val = I915_READ(reg->offset); |
||
431 | break; |
||
432 | case 2: |
||
433 | reg->val = I915_READ16(reg->offset); |
||
434 | break; |
||
435 | case 1: |
||
436 | reg->val = I915_READ8(reg->offset); |
||
437 | break; |
||
438 | default: |
||
439 | WARN_ON(1); |
||
440 | return -EINVAL; |
||
441 | } |
||
442 | |||
443 | return 0; |
||
444 | } |
||
445 | |||
446 | static int i8xx_do_reset(struct drm_device *dev) |
||
447 | { |
||
448 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
449 | |||
450 | if (IS_I85X(dev)) |
||
451 | return -ENODEV; |
||
452 | |||
453 | I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830); |
||
454 | POSTING_READ(D_STATE); |
||
455 | |||
456 | if (IS_I830(dev) || IS_845G(dev)) { |
||
457 | I915_WRITE(DEBUG_RESET_I830, |
||
458 | DEBUG_RESET_DISPLAY | |
||
459 | DEBUG_RESET_RENDER | |
||
460 | DEBUG_RESET_FULL); |
||
461 | POSTING_READ(DEBUG_RESET_I830); |
||
462 | msleep(1); |
||
463 | |||
464 | I915_WRITE(DEBUG_RESET_I830, 0); |
||
465 | POSTING_READ(DEBUG_RESET_I830); |
||
466 | } |
||
467 | |||
468 | msleep(1); |
||
469 | |||
470 | I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830); |
||
471 | POSTING_READ(D_STATE); |
||
472 | |||
473 | return 0; |
||
474 | } |
||
475 | |||
476 | static int i965_reset_complete(struct drm_device *dev) |
||
477 | { |
||
478 | u8 gdrst; |
||
479 | pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst); |
||
480 | return (gdrst & GRDOM_RESET_ENABLE) == 0; |
||
481 | } |
||
482 | |||
483 | static int i965_do_reset(struct drm_device *dev) |
||
484 | { |
||
485 | int ret; |
||
486 | |||
487 | /* |
||
488 | * Set the domains we want to reset (GRDOM/bits 2 and 3) as |
||
489 | * well as the reset bit (GR/bit 0). Setting the GR bit |
||
490 | * triggers the reset; when done, the hardware will clear it. |
||
491 | */ |
||
492 | pci_write_config_byte(dev->pdev, I965_GDRST, |
||
493 | GRDOM_RENDER | GRDOM_RESET_ENABLE); |
||
494 | ret = wait_for(i965_reset_complete(dev), 500); |
||
495 | if (ret) |
||
496 | return ret; |
||
497 | |||
498 | /* We can't reset render&media without also resetting display ... */ |
||
499 | pci_write_config_byte(dev->pdev, I965_GDRST, |
||
500 | GRDOM_MEDIA | GRDOM_RESET_ENABLE); |
||
501 | |||
502 | ret = wait_for(i965_reset_complete(dev), 500); |
||
503 | if (ret) |
||
504 | return ret; |
||
505 | |||
506 | pci_write_config_byte(dev->pdev, I965_GDRST, 0); |
||
507 | |||
508 | return 0; |
||
509 | } |
||
510 | |||
511 | static int ironlake_do_reset(struct drm_device *dev) |
||
512 | { |
||
513 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
514 | u32 gdrst; |
||
515 | int ret; |
||
516 | |||
517 | gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR); |
||
518 | gdrst &= ~GRDOM_MASK; |
||
519 | I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, |
||
520 | gdrst | GRDOM_RENDER | GRDOM_RESET_ENABLE); |
||
521 | ret = wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500); |
||
522 | if (ret) |
||
523 | return ret; |
||
524 | |||
525 | /* We can't reset render&media without also resetting display ... */ |
||
526 | gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR); |
||
527 | gdrst &= ~GRDOM_MASK; |
||
528 | I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, |
||
529 | gdrst | GRDOM_MEDIA | GRDOM_RESET_ENABLE); |
||
530 | return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500); |
||
531 | } |
||
532 | |||
533 | static int gen6_do_reset(struct drm_device *dev) |
||
534 | { |
||
535 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
536 | int ret; |
||
537 | unsigned long irqflags; |
||
538 | |||
539 | /* Hold uncore.lock across reset to prevent any register access |
||
540 | * with forcewake not set correctly |
||
541 | */ |
||
542 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
||
543 | |||
544 | /* Reset the chip */ |
||
545 | |||
546 | /* GEN6_GDRST is not in the gt power well, no need to check |
||
547 | * for fifo space for the write or forcewake the chip for |
||
548 | * the read |
||
549 | */ |
||
550 | __raw_i915_write32(dev_priv, GEN6_GDRST, GEN6_GRDOM_FULL); |
||
551 | |||
552 | /* Spin waiting for the device to ack the reset request */ |
||
553 | ret = wait_for((__raw_i915_read32(dev_priv, GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500); |
||
554 | |||
555 | intel_uncore_forcewake_reset(dev); |
||
556 | |||
557 | /* If reset with a user forcewake, try to restore, otherwise turn it off */ |
||
558 | if (dev_priv->uncore.forcewake_count) |
||
559 | dev_priv->uncore.funcs.force_wake_get(dev_priv); |
||
560 | else |
||
561 | dev_priv->uncore.funcs.force_wake_put(dev_priv); |
||
562 | |||
563 | /* Restore fifo count */ |
||
564 | dev_priv->uncore.fifo_count = __raw_i915_read32(dev_priv, GT_FIFO_FREE_ENTRIES); |
||
565 | |||
566 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
||
567 | return ret; |
||
568 | } |
||
569 | |||
570 | int intel_gpu_reset(struct drm_device *dev) |
||
571 | { |
||
572 | switch (INTEL_INFO(dev)->gen) { |
||
573 | case 7: |
||
574 | case 6: return gen6_do_reset(dev); |
||
575 | case 5: return ironlake_do_reset(dev); |
||
576 | case 4: return i965_do_reset(dev); |
||
577 | case 2: return i8xx_do_reset(dev); |
||
578 | default: return -ENODEV; |
||
579 | } |
||
580 | } |
||
581 | |||
582 | void intel_uncore_clear_errors(struct drm_device *dev) |
||
583 | { |
||
584 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
585 | |||
586 | /* XXX needs spinlock around caller's grouping */ |
||
587 | if (HAS_FPGA_DBG_UNCLAIMED(dev)) |
||
588 | __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM); |
||
589 | } |
||
590 | |||
591 | void intel_uncore_check_errors(struct drm_device *dev) |
||
592 | { |
||
593 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
594 | |||
595 | if (HAS_FPGA_DBG_UNCLAIMED(dev) && |
||
596 | (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) { |
||
597 | DRM_ERROR("Unclaimed register before interrupt\n"); |
||
598 | __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM); |
||
599 | } |
||
600 | }><>>>=>>=>> |