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2332 | Serge | 1 | /* |
2 | * Copyright © 2008-2010 Intel Corporation |
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3 | * |
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4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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5 | * copy of this software and associated documentation files (the "Software"), |
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6 | * to deal in the Software without restriction, including without limitation |
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7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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8 | * and/or sell copies of the Software, and to permit persons to whom the |
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9 | * Software is furnished to do so, subject to the following conditions: |
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10 | * |
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11 | * The above copyright notice and this permission notice (including the next |
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12 | * paragraph) shall be included in all copies or substantial portions of the |
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13 | * Software. |
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14 | * |
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15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
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21 | * IN THE SOFTWARE. |
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22 | * |
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23 | * Authors: |
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24 | * Eric Anholt |
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25 | * Zou Nan hai |
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26 | * Xiang Hai hao |
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27 | * |
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28 | */ |
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29 | #define iowrite32(v, addr) writel((v), (addr)) |
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30 | #define ioread32(addr) readl(addr) |
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31 | |||
32 | #include "drmP.h" |
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33 | #include "drm.h" |
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34 | #include "i915_drv.h" |
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35 | #include "i915_drm.h" |
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36 | //#include "i915_trace.h" |
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37 | #include "intel_drv.h" |
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38 | |||
39 | static inline int ring_space(struct intel_ring_buffer *ring) |
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40 | { |
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41 | int space = (ring->head & HEAD_ADDR) - (ring->tail + 8); |
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42 | if (space < 0) |
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43 | space += ring->size; |
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44 | return space; |
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45 | } |
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46 | |||
47 | static u32 i915_gem_get_seqno(struct drm_device *dev) |
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48 | { |
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49 | drm_i915_private_t *dev_priv = dev->dev_private; |
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50 | u32 seqno; |
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51 | |||
52 | seqno = dev_priv->next_seqno; |
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53 | |||
54 | /* reserve 0 for non-seqno */ |
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55 | if (++dev_priv->next_seqno == 0) |
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56 | dev_priv->next_seqno = 1; |
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57 | |||
58 | return seqno; |
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59 | } |
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60 | |||
61 | static int |
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62 | render_ring_flush(struct intel_ring_buffer *ring, |
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63 | u32 invalidate_domains, |
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64 | u32 flush_domains) |
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65 | { |
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66 | struct drm_device *dev = ring->dev; |
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67 | u32 cmd; |
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68 | int ret; |
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69 | |||
70 | /* |
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71 | * read/write caches: |
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72 | * |
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73 | * I915_GEM_DOMAIN_RENDER is always invalidated, but is |
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74 | * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is |
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75 | * also flushed at 2d versus 3d pipeline switches. |
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76 | * |
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77 | * read-only caches: |
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78 | * |
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79 | * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if |
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80 | * MI_READ_FLUSH is set, and is always flushed on 965. |
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81 | * |
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82 | * I915_GEM_DOMAIN_COMMAND may not exist? |
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83 | * |
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84 | * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is |
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85 | * invalidated when MI_EXE_FLUSH is set. |
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86 | * |
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87 | * I915_GEM_DOMAIN_VERTEX, which exists on 965, is |
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88 | * invalidated with every MI_FLUSH. |
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89 | * |
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90 | * TLBs: |
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91 | * |
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92 | * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND |
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93 | * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and |
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94 | * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER |
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95 | * are flushed at any MI_FLUSH. |
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96 | */ |
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97 | |||
98 | cmd = MI_FLUSH | MI_NO_WRITE_FLUSH; |
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99 | if ((invalidate_domains|flush_domains) & |
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100 | I915_GEM_DOMAIN_RENDER) |
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101 | cmd &= ~MI_NO_WRITE_FLUSH; |
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102 | if (INTEL_INFO(dev)->gen < 4) { |
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103 | /* |
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104 | * On the 965, the sampler cache always gets flushed |
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105 | * and this bit is reserved. |
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106 | */ |
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107 | if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER) |
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108 | cmd |= MI_READ_FLUSH; |
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109 | } |
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110 | if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION) |
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111 | cmd |= MI_EXE_FLUSH; |
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112 | |||
113 | if (invalidate_domains & I915_GEM_DOMAIN_COMMAND && |
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114 | (IS_G4X(dev) || IS_GEN5(dev))) |
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115 | cmd |= MI_INVALIDATE_ISP; |
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116 | |||
117 | ret = intel_ring_begin(ring, 2); |
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118 | if (ret) |
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119 | return ret; |
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120 | |||
121 | intel_ring_emit(ring, cmd); |
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122 | intel_ring_emit(ring, MI_NOOP); |
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123 | intel_ring_advance(ring); |
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124 | |||
125 | return 0; |
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126 | } |
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127 | |||
128 | static void ring_write_tail(struct intel_ring_buffer *ring, |
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129 | u32 value) |
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130 | { |
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131 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
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132 | I915_WRITE_TAIL(ring, value); |
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133 | } |
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134 | |||
135 | u32 intel_ring_get_active_head(struct intel_ring_buffer *ring) |
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136 | { |
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137 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
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138 | u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ? |
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139 | RING_ACTHD(ring->mmio_base) : ACTHD; |
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140 | |||
141 | return I915_READ(acthd_reg); |
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142 | } |
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143 | |||
144 | |||
145 | static int init_ring_common(struct intel_ring_buffer *ring) |
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146 | { |
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147 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
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148 | struct drm_i915_gem_object *obj = ring->obj; |
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149 | u32 head; |
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150 | |||
151 | ENTER(); |
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152 | |||
153 | /* Stop the ring if it's running. */ |
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154 | I915_WRITE_CTL(ring, 0); |
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155 | I915_WRITE_HEAD(ring, 0); |
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156 | ring->write_tail(ring, 0); |
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157 | |||
158 | /* Initialize the ring. */ |
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159 | I915_WRITE_START(ring, obj->gtt_offset); |
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160 | head = I915_READ_HEAD(ring) & HEAD_ADDR; |
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161 | |||
162 | /* G45 ring initialization fails to reset head to zero */ |
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163 | if (head != 0) { |
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164 | DRM_DEBUG_KMS("%s head not reset to zero " |
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165 | "ctl %08x head %08x tail %08x start %08x\n", |
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166 | ring->name, |
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167 | I915_READ_CTL(ring), |
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168 | I915_READ_HEAD(ring), |
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169 | I915_READ_TAIL(ring), |
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170 | I915_READ_START(ring)); |
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171 | |||
172 | I915_WRITE_HEAD(ring, 0); |
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173 | |||
174 | if (I915_READ_HEAD(ring) & HEAD_ADDR) { |
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175 | DRM_ERROR("failed to set %s head to zero " |
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176 | "ctl %08x head %08x tail %08x start %08x\n", |
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177 | ring->name, |
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178 | I915_READ_CTL(ring), |
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179 | I915_READ_HEAD(ring), |
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180 | I915_READ_TAIL(ring), |
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181 | I915_READ_START(ring)); |
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182 | } |
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183 | } |
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184 | |||
185 | I915_WRITE_CTL(ring, |
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186 | ((ring->size - PAGE_SIZE) & RING_NR_PAGES) |
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187 | | RING_REPORT_64K | RING_VALID); |
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188 | |||
189 | /* If the head is still not zero, the ring is dead */ |
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190 | if ((I915_READ_CTL(ring) & RING_VALID) == 0 || |
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191 | I915_READ_START(ring) != obj->gtt_offset || |
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192 | (I915_READ_HEAD(ring) & HEAD_ADDR) != 0) { |
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193 | DRM_ERROR("%s initialization failed " |
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194 | "ctl %08x head %08x tail %08x start %08x\n", |
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195 | ring->name, |
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196 | I915_READ_CTL(ring), |
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197 | I915_READ_HEAD(ring), |
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198 | I915_READ_TAIL(ring), |
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199 | I915_READ_START(ring)); |
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200 | return -EIO; |
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201 | } |
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202 | |||
203 | ring->head = I915_READ_HEAD(ring); |
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204 | ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR; |
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205 | ring->space = ring_space(ring); |
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206 | |||
207 | LEAVE(); |
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208 | |||
209 | return 0; |
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210 | } |
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211 | |||
212 | #if 0 |
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213 | |||
214 | /* |
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215 | * 965+ support PIPE_CONTROL commands, which provide finer grained control |
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216 | * over cache flushing. |
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217 | */ |
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218 | struct pipe_control { |
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219 | struct drm_i915_gem_object *obj; |
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220 | volatile u32 *cpu_page; |
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221 | u32 gtt_offset; |
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222 | }; |
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223 | |||
224 | static int |
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225 | init_pipe_control(struct intel_ring_buffer *ring) |
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226 | { |
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227 | struct pipe_control *pc; |
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228 | struct drm_i915_gem_object *obj; |
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229 | int ret; |
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230 | |||
231 | if (ring->private) |
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232 | return 0; |
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233 | |||
234 | pc = kmalloc(sizeof(*pc), GFP_KERNEL); |
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235 | if (!pc) |
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236 | return -ENOMEM; |
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237 | |||
238 | obj = i915_gem_alloc_object(ring->dev, 4096); |
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239 | if (obj == NULL) { |
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240 | DRM_ERROR("Failed to allocate seqno page\n"); |
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241 | ret = -ENOMEM; |
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242 | goto err; |
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243 | } |
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244 | |||
245 | i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); |
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246 | |||
247 | ret = i915_gem_object_pin(obj, 4096, true); |
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248 | if (ret) |
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249 | goto err_unref; |
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250 | |||
251 | pc->gtt_offset = obj->gtt_offset; |
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252 | pc->cpu_page = kmap(obj->pages[0]); |
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253 | if (pc->cpu_page == NULL) |
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254 | goto err_unpin; |
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255 | |||
256 | pc->obj = obj; |
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257 | ring->private = pc; |
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258 | return 0; |
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259 | |||
260 | err_unpin: |
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261 | i915_gem_object_unpin(obj); |
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262 | err_unref: |
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263 | drm_gem_object_unreference(&obj->base); |
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264 | err: |
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265 | kfree(pc); |
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266 | return ret; |
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267 | } |
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268 | |||
269 | static void |
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270 | cleanup_pipe_control(struct intel_ring_buffer *ring) |
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271 | { |
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272 | struct pipe_control *pc = ring->private; |
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273 | struct drm_i915_gem_object *obj; |
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274 | |||
275 | if (!ring->private) |
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276 | return; |
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277 | |||
278 | obj = pc->obj; |
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279 | kunmap(obj->pages[0]); |
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280 | i915_gem_object_unpin(obj); |
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281 | drm_gem_object_unreference(&obj->base); |
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282 | |||
283 | kfree(pc); |
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284 | ring->private = NULL; |
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285 | } |
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286 | |||
287 | #endif |
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288 | |||
289 | static int init_render_ring(struct intel_ring_buffer *ring) |
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290 | { |
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291 | struct drm_device *dev = ring->dev; |
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292 | struct drm_i915_private *dev_priv = dev->dev_private; |
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293 | |||
294 | ENTER(); |
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295 | |||
296 | int ret = init_ring_common(ring); |
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297 | |||
298 | |||
299 | if (INTEL_INFO(dev)->gen > 3) { |
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300 | int mode = VS_TIMER_DISPATCH << 16 | VS_TIMER_DISPATCH; |
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301 | if (IS_GEN6(dev) || IS_GEN7(dev)) |
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302 | mode |= MI_FLUSH_ENABLE << 16 | MI_FLUSH_ENABLE; |
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303 | I915_WRITE(MI_MODE, mode); |
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304 | if (IS_GEN7(dev)) |
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305 | I915_WRITE(GFX_MODE_GEN7, |
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306 | GFX_MODE_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) | |
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307 | GFX_MODE_ENABLE(GFX_REPLAY_MODE)); |
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308 | } |
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309 | |||
310 | if (INTEL_INFO(dev)->gen >= 6) { |
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311 | } else if (IS_GEN5(dev)) { |
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312 | // ret = init_pipe_control(ring); |
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313 | if (ret) |
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314 | return ret; |
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315 | } |
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316 | |||
317 | LEAVE(); |
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318 | |||
319 | return ret; |
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320 | } |
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321 | |||
322 | #if 0 |
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323 | |||
324 | static void render_ring_cleanup(struct intel_ring_buffer *ring) |
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325 | { |
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326 | if (!ring->private) |
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327 | return; |
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328 | |||
329 | cleanup_pipe_control(ring); |
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330 | } |
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331 | |||
332 | static void |
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333 | update_semaphore(struct intel_ring_buffer *ring, int i, u32 seqno) |
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334 | { |
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335 | struct drm_device *dev = ring->dev; |
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336 | struct drm_i915_private *dev_priv = dev->dev_private; |
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337 | int id; |
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338 | |||
339 | /* |
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340 | * cs -> 1 = vcs, 0 = bcs |
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341 | * vcs -> 1 = bcs, 0 = cs, |
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342 | * bcs -> 1 = cs, 0 = vcs. |
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343 | */ |
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344 | id = ring - dev_priv->ring; |
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345 | id += 2 - i; |
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346 | id %= 3; |
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347 | |||
348 | intel_ring_emit(ring, |
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349 | MI_SEMAPHORE_MBOX | |
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350 | MI_SEMAPHORE_REGISTER | |
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351 | MI_SEMAPHORE_UPDATE); |
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352 | intel_ring_emit(ring, seqno); |
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353 | intel_ring_emit(ring, |
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354 | RING_SYNC_0(dev_priv->ring[id].mmio_base) + 4*i); |
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355 | } |
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356 | |||
357 | static int |
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358 | gen6_add_request(struct intel_ring_buffer *ring, |
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359 | u32 *result) |
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360 | { |
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361 | u32 seqno; |
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362 | int ret; |
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363 | |||
364 | ret = intel_ring_begin(ring, 10); |
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365 | if (ret) |
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366 | return ret; |
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367 | |||
368 | seqno = i915_gem_get_seqno(ring->dev); |
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369 | update_semaphore(ring, 0, seqno); |
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370 | update_semaphore(ring, 1, seqno); |
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371 | |||
372 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
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373 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
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374 | intel_ring_emit(ring, seqno); |
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375 | intel_ring_emit(ring, MI_USER_INTERRUPT); |
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376 | intel_ring_advance(ring); |
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377 | |||
378 | *result = seqno; |
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379 | return 0; |
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380 | } |
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381 | |||
382 | int |
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383 | intel_ring_sync(struct intel_ring_buffer *ring, |
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384 | struct intel_ring_buffer *to, |
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385 | u32 seqno) |
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386 | { |
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387 | int ret; |
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388 | |||
389 | ret = intel_ring_begin(ring, 4); |
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390 | if (ret) |
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391 | return ret; |
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392 | |||
393 | intel_ring_emit(ring, |
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394 | MI_SEMAPHORE_MBOX | |
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395 | MI_SEMAPHORE_REGISTER | |
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396 | intel_ring_sync_index(ring, to) << 17 | |
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397 | MI_SEMAPHORE_COMPARE); |
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398 | intel_ring_emit(ring, seqno); |
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399 | intel_ring_emit(ring, 0); |
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400 | intel_ring_emit(ring, MI_NOOP); |
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401 | intel_ring_advance(ring); |
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402 | |||
403 | return 0; |
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404 | } |
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405 | |||
406 | #define PIPE_CONTROL_FLUSH(ring__, addr__) \ |
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407 | do { \ |
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408 | intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE | \ |
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409 | PIPE_CONTROL_DEPTH_STALL | 2); \ |
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410 | intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \ |
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411 | intel_ring_emit(ring__, 0); \ |
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412 | intel_ring_emit(ring__, 0); \ |
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413 | } while (0) |
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414 | |||
415 | static int |
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416 | pc_render_add_request(struct intel_ring_buffer *ring, |
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417 | u32 *result) |
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418 | { |
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419 | struct drm_device *dev = ring->dev; |
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420 | u32 seqno = i915_gem_get_seqno(dev); |
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421 | struct pipe_control *pc = ring->private; |
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422 | u32 scratch_addr = pc->gtt_offset + 128; |
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423 | int ret; |
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424 | |||
425 | /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently |
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426 | * incoherent with writes to memory, i.e. completely fubar, |
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427 | * so we need to use PIPE_NOTIFY instead. |
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428 | * |
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429 | * However, we also need to workaround the qword write |
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430 | * incoherence by flushing the 6 PIPE_NOTIFY buffers out to |
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431 | * memory before requesting an interrupt. |
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432 | */ |
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433 | ret = intel_ring_begin(ring, 32); |
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434 | if (ret) |
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435 | return ret; |
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436 | |||
437 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE | |
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438 | PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH); |
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439 | intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT); |
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440 | intel_ring_emit(ring, seqno); |
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441 | intel_ring_emit(ring, 0); |
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442 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
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443 | scratch_addr += 128; /* write to separate cachelines */ |
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444 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
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445 | scratch_addr += 128; |
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446 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
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447 | scratch_addr += 128; |
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448 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
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449 | scratch_addr += 128; |
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450 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
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451 | scratch_addr += 128; |
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452 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
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453 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE | |
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454 | PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH | |
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455 | PIPE_CONTROL_NOTIFY); |
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456 | intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT); |
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457 | intel_ring_emit(ring, seqno); |
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458 | intel_ring_emit(ring, 0); |
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459 | intel_ring_advance(ring); |
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460 | |||
461 | *result = seqno; |
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462 | return 0; |
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463 | } |
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464 | |||
465 | static int |
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466 | render_ring_add_request(struct intel_ring_buffer *ring, |
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467 | u32 *result) |
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468 | { |
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469 | struct drm_device *dev = ring->dev; |
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470 | u32 seqno = i915_gem_get_seqno(dev); |
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471 | int ret; |
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472 | |||
473 | ret = intel_ring_begin(ring, 4); |
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474 | if (ret) |
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475 | return ret; |
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476 | |||
477 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
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478 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
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479 | intel_ring_emit(ring, seqno); |
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480 | intel_ring_emit(ring, MI_USER_INTERRUPT); |
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481 | intel_ring_advance(ring); |
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482 | |||
483 | *result = seqno; |
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484 | return 0; |
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485 | } |
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486 | |||
487 | static u32 |
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488 | ring_get_seqno(struct intel_ring_buffer *ring) |
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489 | { |
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490 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); |
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491 | } |
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492 | |||
493 | static u32 |
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494 | pc_render_get_seqno(struct intel_ring_buffer *ring) |
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495 | { |
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496 | struct pipe_control *pc = ring->private; |
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497 | return pc->cpu_page[0]; |
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498 | } |
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499 | |||
500 | static void |
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501 | ironlake_enable_irq(drm_i915_private_t *dev_priv, u32 mask) |
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502 | { |
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503 | dev_priv->gt_irq_mask &= ~mask; |
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504 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); |
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505 | POSTING_READ(GTIMR); |
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506 | } |
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507 | |||
508 | static void |
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509 | ironlake_disable_irq(drm_i915_private_t *dev_priv, u32 mask) |
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510 | { |
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511 | dev_priv->gt_irq_mask |= mask; |
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512 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); |
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513 | POSTING_READ(GTIMR); |
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514 | } |
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515 | |||
516 | static void |
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517 | i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask) |
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518 | { |
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519 | dev_priv->irq_mask &= ~mask; |
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520 | I915_WRITE(IMR, dev_priv->irq_mask); |
||
521 | POSTING_READ(IMR); |
||
522 | } |
||
523 | |||
524 | static void |
||
525 | i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask) |
||
526 | { |
||
527 | dev_priv->irq_mask |= mask; |
||
528 | I915_WRITE(IMR, dev_priv->irq_mask); |
||
529 | POSTING_READ(IMR); |
||
530 | } |
||
531 | |||
532 | static bool |
||
533 | render_ring_get_irq(struct intel_ring_buffer *ring) |
||
534 | { |
||
535 | struct drm_device *dev = ring->dev; |
||
536 | drm_i915_private_t *dev_priv = dev->dev_private; |
||
537 | |||
538 | if (!dev->irq_enabled) |
||
539 | return false; |
||
540 | |||
541 | spin_lock(&ring->irq_lock); |
||
542 | if (ring->irq_refcount++ == 0) { |
||
543 | if (HAS_PCH_SPLIT(dev)) |
||
544 | ironlake_enable_irq(dev_priv, |
||
545 | GT_PIPE_NOTIFY | GT_USER_INTERRUPT); |
||
546 | else |
||
547 | i915_enable_irq(dev_priv, I915_USER_INTERRUPT); |
||
548 | } |
||
549 | spin_unlock(&ring->irq_lock); |
||
550 | |||
551 | return true; |
||
552 | } |
||
553 | |||
554 | static void |
||
555 | render_ring_put_irq(struct intel_ring_buffer *ring) |
||
556 | { |
||
557 | struct drm_device *dev = ring->dev; |
||
558 | drm_i915_private_t *dev_priv = dev->dev_private; |
||
559 | |||
560 | spin_lock(&ring->irq_lock); |
||
561 | if (--ring->irq_refcount == 0) { |
||
562 | if (HAS_PCH_SPLIT(dev)) |
||
563 | ironlake_disable_irq(dev_priv, |
||
564 | GT_USER_INTERRUPT | |
||
565 | GT_PIPE_NOTIFY); |
||
566 | else |
||
567 | i915_disable_irq(dev_priv, I915_USER_INTERRUPT); |
||
568 | } |
||
569 | spin_unlock(&ring->irq_lock); |
||
570 | } |
||
571 | |||
572 | void intel_ring_setup_status_page(struct intel_ring_buffer *ring) |
||
573 | { |
||
574 | struct drm_device *dev = ring->dev; |
||
575 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
||
576 | u32 mmio = 0; |
||
577 | |||
578 | /* The ring status page addresses are no longer next to the rest of |
||
579 | * the ring registers as of gen7. |
||
580 | */ |
||
581 | if (IS_GEN7(dev)) { |
||
582 | switch (ring->id) { |
||
583 | case RING_RENDER: |
||
584 | mmio = RENDER_HWS_PGA_GEN7; |
||
585 | break; |
||
586 | case RING_BLT: |
||
587 | mmio = BLT_HWS_PGA_GEN7; |
||
588 | break; |
||
589 | case RING_BSD: |
||
590 | mmio = BSD_HWS_PGA_GEN7; |
||
591 | break; |
||
592 | } |
||
593 | } else if (IS_GEN6(ring->dev)) { |
||
594 | mmio = RING_HWS_PGA_GEN6(ring->mmio_base); |
||
595 | } else { |
||
596 | mmio = RING_HWS_PGA(ring->mmio_base); |
||
597 | } |
||
598 | |||
599 | I915_WRITE(mmio, (u32)ring->status_page.gfx_addr); |
||
600 | POSTING_READ(mmio); |
||
601 | } |
||
602 | #endif |
||
603 | |||
604 | static int |
||
605 | bsd_ring_flush(struct intel_ring_buffer *ring, |
||
606 | u32 invalidate_domains, |
||
607 | u32 flush_domains) |
||
608 | { |
||
609 | int ret; |
||
610 | |||
611 | ret = intel_ring_begin(ring, 2); |
||
612 | if (ret) |
||
613 | return ret; |
||
614 | |||
615 | intel_ring_emit(ring, MI_FLUSH); |
||
616 | intel_ring_emit(ring, MI_NOOP); |
||
617 | intel_ring_advance(ring); |
||
618 | return 0; |
||
619 | } |
||
620 | |||
621 | #if 0 |
||
622 | |||
623 | static int |
||
624 | ring_add_request(struct intel_ring_buffer *ring, |
||
625 | u32 *result) |
||
626 | { |
||
627 | u32 seqno; |
||
628 | int ret; |
||
629 | |||
630 | ret = intel_ring_begin(ring, 4); |
||
631 | if (ret) |
||
632 | return ret; |
||
633 | |||
634 | seqno = i915_gem_get_seqno(ring->dev); |
||
635 | |||
636 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
||
637 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
||
638 | intel_ring_emit(ring, seqno); |
||
639 | intel_ring_emit(ring, MI_USER_INTERRUPT); |
||
640 | intel_ring_advance(ring); |
||
641 | |||
642 | *result = seqno; |
||
643 | return 0; |
||
644 | } |
||
645 | |||
646 | static bool |
||
647 | gen6_ring_get_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag) |
||
648 | { |
||
649 | struct drm_device *dev = ring->dev; |
||
650 | drm_i915_private_t *dev_priv = dev->dev_private; |
||
651 | |||
652 | if (!dev->irq_enabled) |
||
653 | return false; |
||
654 | |||
655 | spin_lock(&ring->irq_lock); |
||
656 | if (ring->irq_refcount++ == 0) { |
||
657 | ring->irq_mask &= ~rflag; |
||
658 | I915_WRITE_IMR(ring, ring->irq_mask); |
||
659 | ironlake_enable_irq(dev_priv, gflag); |
||
660 | } |
||
661 | spin_unlock(&ring->irq_lock); |
||
662 | |||
663 | return true; |
||
664 | } |
||
665 | |||
666 | static void |
||
667 | gen6_ring_put_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag) |
||
668 | { |
||
669 | struct drm_device *dev = ring->dev; |
||
670 | drm_i915_private_t *dev_priv = dev->dev_private; |
||
671 | |||
672 | spin_lock(&ring->irq_lock); |
||
673 | if (--ring->irq_refcount == 0) { |
||
674 | ring->irq_mask |= rflag; |
||
675 | I915_WRITE_IMR(ring, ring->irq_mask); |
||
676 | ironlake_disable_irq(dev_priv, gflag); |
||
677 | } |
||
678 | spin_unlock(&ring->irq_lock); |
||
679 | } |
||
680 | |||
681 | static bool |
||
682 | bsd_ring_get_irq(struct intel_ring_buffer *ring) |
||
683 | { |
||
684 | struct drm_device *dev = ring->dev; |
||
685 | drm_i915_private_t *dev_priv = dev->dev_private; |
||
686 | |||
687 | if (!dev->irq_enabled) |
||
688 | return false; |
||
689 | |||
690 | spin_lock(&ring->irq_lock); |
||
691 | if (ring->irq_refcount++ == 0) { |
||
692 | if (IS_G4X(dev)) |
||
693 | i915_enable_irq(dev_priv, I915_BSD_USER_INTERRUPT); |
||
694 | else |
||
695 | ironlake_enable_irq(dev_priv, GT_BSD_USER_INTERRUPT); |
||
696 | } |
||
697 | spin_unlock(&ring->irq_lock); |
||
698 | |||
699 | return true; |
||
700 | } |
||
701 | static void |
||
702 | bsd_ring_put_irq(struct intel_ring_buffer *ring) |
||
703 | { |
||
704 | struct drm_device *dev = ring->dev; |
||
705 | drm_i915_private_t *dev_priv = dev->dev_private; |
||
706 | |||
707 | spin_lock(&ring->irq_lock); |
||
708 | if (--ring->irq_refcount == 0) { |
||
709 | if (IS_G4X(dev)) |
||
710 | i915_disable_irq(dev_priv, I915_BSD_USER_INTERRUPT); |
||
711 | else |
||
712 | ironlake_disable_irq(dev_priv, GT_BSD_USER_INTERRUPT); |
||
713 | } |
||
714 | spin_unlock(&ring->irq_lock); |
||
715 | } |
||
716 | |||
717 | static int |
||
718 | ring_dispatch_execbuffer(struct intel_ring_buffer *ring, u32 offset, u32 length) |
||
719 | { |
||
720 | int ret; |
||
721 | |||
722 | ret = intel_ring_begin(ring, 2); |
||
723 | if (ret) |
||
724 | return ret; |
||
725 | |||
726 | intel_ring_emit(ring, |
||
727 | MI_BATCH_BUFFER_START | (2 << 6) | |
||
728 | MI_BATCH_NON_SECURE_I965); |
||
729 | intel_ring_emit(ring, offset); |
||
730 | intel_ring_advance(ring); |
||
731 | |||
732 | return 0; |
||
733 | } |
||
734 | |||
735 | static int |
||
736 | render_ring_dispatch_execbuffer(struct intel_ring_buffer *ring, |
||
737 | u32 offset, u32 len) |
||
738 | { |
||
739 | struct drm_device *dev = ring->dev; |
||
740 | int ret; |
||
741 | |||
742 | if (IS_I830(dev) || IS_845G(dev)) { |
||
743 | ret = intel_ring_begin(ring, 4); |
||
744 | if (ret) |
||
745 | return ret; |
||
746 | |||
747 | intel_ring_emit(ring, MI_BATCH_BUFFER); |
||
748 | intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE); |
||
749 | intel_ring_emit(ring, offset + len - 8); |
||
750 | intel_ring_emit(ring, 0); |
||
751 | } else { |
||
752 | ret = intel_ring_begin(ring, 2); |
||
753 | if (ret) |
||
754 | return ret; |
||
755 | |||
756 | if (INTEL_INFO(dev)->gen >= 4) { |
||
757 | intel_ring_emit(ring, |
||
758 | MI_BATCH_BUFFER_START | (2 << 6) | |
||
759 | MI_BATCH_NON_SECURE_I965); |
||
760 | intel_ring_emit(ring, offset); |
||
761 | } else { |
||
762 | intel_ring_emit(ring, |
||
763 | MI_BATCH_BUFFER_START | (2 << 6)); |
||
764 | intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE); |
||
765 | } |
||
766 | } |
||
767 | intel_ring_advance(ring); |
||
768 | |||
769 | return 0; |
||
770 | } |
||
771 | |||
772 | static void cleanup_status_page(struct intel_ring_buffer *ring) |
||
773 | { |
||
774 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
||
775 | struct drm_i915_gem_object *obj; |
||
776 | |||
777 | obj = ring->status_page.obj; |
||
778 | if (obj == NULL) |
||
779 | return; |
||
780 | |||
781 | kunmap(obj->pages[0]); |
||
782 | i915_gem_object_unpin(obj); |
||
783 | drm_gem_object_unreference(&obj->base); |
||
784 | ring->status_page.obj = NULL; |
||
785 | |||
786 | memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map)); |
||
787 | } |
||
788 | |||
789 | static int init_status_page(struct intel_ring_buffer *ring) |
||
790 | { |
||
791 | struct drm_device *dev = ring->dev; |
||
792 | drm_i915_private_t *dev_priv = dev->dev_private; |
||
793 | struct drm_i915_gem_object *obj; |
||
794 | int ret; |
||
795 | |||
796 | obj = i915_gem_alloc_object(dev, 4096); |
||
797 | if (obj == NULL) { |
||
798 | DRM_ERROR("Failed to allocate status page\n"); |
||
799 | ret = -ENOMEM; |
||
800 | goto err; |
||
801 | } |
||
802 | |||
803 | i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); |
||
804 | |||
805 | ret = i915_gem_object_pin(obj, 4096, true); |
||
806 | if (ret != 0) { |
||
807 | goto err_unref; |
||
808 | } |
||
809 | |||
810 | ring->status_page.gfx_addr = obj->gtt_offset; |
||
811 | ring->status_page.page_addr = kmap(obj->pages[0]); |
||
812 | if (ring->status_page.page_addr == NULL) { |
||
813 | memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map)); |
||
814 | goto err_unpin; |
||
815 | } |
||
816 | ring->status_page.obj = obj; |
||
817 | memset(ring->status_page.page_addr, 0, PAGE_SIZE); |
||
818 | |||
819 | intel_ring_setup_status_page(ring); |
||
820 | DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n", |
||
821 | ring->name, ring->status_page.gfx_addr); |
||
822 | |||
823 | return 0; |
||
824 | |||
825 | err_unpin: |
||
826 | i915_gem_object_unpin(obj); |
||
827 | err_unref: |
||
828 | drm_gem_object_unreference(&obj->base); |
||
829 | err: |
||
830 | return ret; |
||
831 | } |
||
832 | #endif |
||
833 | |||
834 | int intel_init_ring_buffer(struct drm_device *dev, |
||
835 | struct intel_ring_buffer *ring) |
||
836 | { |
||
837 | struct drm_i915_gem_object *obj=NULL; |
||
838 | int ret; |
||
839 | ENTER(); |
||
840 | ring->dev = dev; |
||
841 | INIT_LIST_HEAD(&ring->active_list); |
||
842 | INIT_LIST_HEAD(&ring->request_list); |
||
843 | INIT_LIST_HEAD(&ring->gpu_write_list); |
||
844 | |||
845 | // init_waitqueue_head(&ring->irq_queue); |
||
846 | // spin_lock_init(&ring->irq_lock); |
||
847 | ring->irq_mask = ~0; |
||
848 | |||
849 | if (I915_NEED_GFX_HWS(dev)) { |
||
850 | // ret = init_status_page(ring); |
||
851 | // if (ret) |
||
852 | // return ret; |
||
853 | } |
||
854 | |||
855 | obj = i915_gem_alloc_object(dev, ring->size); |
||
856 | if (obj == NULL) { |
||
857 | DRM_ERROR("Failed to allocate ringbuffer\n"); |
||
858 | ret = -ENOMEM; |
||
859 | goto err_hws; |
||
860 | } |
||
861 | |||
862 | ring->obj = obj; |
||
863 | |||
864 | ret = i915_gem_object_pin(obj, PAGE_SIZE, true); |
||
865 | if (ret) |
||
866 | goto err_unref; |
||
867 | |||
868 | ring->map.size = ring->size; |
||
869 | ring->map.offset = get_bus_addr() + obj->gtt_offset; |
||
870 | ring->map.type = 0; |
||
871 | ring->map.flags = 0; |
||
872 | ring->map.mtrr = 0; |
||
873 | |||
874 | // drm_core_ioremap_wc(&ring->map, dev); |
||
875 | |||
876 | ring->map.handle = ioremap(ring->map.offset, ring->map.size); |
||
877 | |||
878 | if (ring->map.handle == NULL) { |
||
879 | DRM_ERROR("Failed to map ringbuffer.\n"); |
||
880 | ret = -EINVAL; |
||
881 | goto err_unpin; |
||
882 | } |
||
883 | |||
884 | ring->virtual_start = ring->map.handle; |
||
885 | ret = ring->init(ring); |
||
886 | if (ret) |
||
887 | goto err_unmap; |
||
888 | |||
889 | /* Workaround an erratum on the i830 which causes a hang if |
||
890 | * the TAIL pointer points to within the last 2 cachelines |
||
891 | * of the buffer. |
||
892 | */ |
||
893 | ring->effective_size = ring->size; |
||
894 | if (IS_I830(ring->dev)) |
||
895 | ring->effective_size -= 128; |
||
896 | LEAVE(); |
||
897 | return 0; |
||
898 | |||
899 | err_unmap: |
||
900 | // drm_core_ioremapfree(&ring->map, dev); |
||
901 | FreeKernelSpace(ring->virtual_start); |
||
902 | err_unpin: |
||
903 | // i915_gem_object_unpin(obj); |
||
904 | err_unref: |
||
905 | // drm_gem_object_unreference(&obj->base); |
||
906 | ring->obj = NULL; |
||
907 | err_hws: |
||
908 | // cleanup_status_page(ring); |
||
909 | return ret; |
||
910 | } |
||
911 | |||
912 | |||
913 | void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring) |
||
914 | { |
||
915 | struct drm_i915_private *dev_priv; |
||
916 | int ret; |
||
917 | |||
918 | if (ring->obj == NULL) |
||
919 | return; |
||
920 | |||
921 | /* Disable the ring buffer. The ring must be idle at this point */ |
||
922 | dev_priv = ring->dev->dev_private; |
||
923 | ret = intel_wait_ring_idle(ring); |
||
924 | if (ret) |
||
925 | DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n", |
||
926 | ring->name, ret); |
||
927 | |||
928 | I915_WRITE_CTL(ring, 0); |
||
929 | |||
930 | // drm_core_ioremapfree(&ring->map, ring->dev); |
||
931 | |||
932 | // i915_gem_object_unpin(ring->obj); |
||
933 | // drm_gem_object_unreference(&ring->obj->base); |
||
934 | ring->obj = NULL; |
||
935 | |||
936 | if (ring->cleanup) |
||
937 | ring->cleanup(ring); |
||
938 | |||
939 | // cleanup_status_page(ring); |
||
940 | } |
||
941 | |||
942 | |||
943 | static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring) |
||
944 | { |
||
945 | unsigned int *virt; |
||
946 | int rem = ring->size - ring->tail; |
||
947 | |||
948 | if (ring->space < rem) { |
||
949 | int ret = intel_wait_ring_buffer(ring, rem); |
||
950 | if (ret) |
||
951 | return ret; |
||
952 | } |
||
953 | |||
954 | virt = (unsigned int *)(ring->virtual_start + ring->tail); |
||
955 | rem /= 8; |
||
956 | while (rem--) { |
||
957 | *virt++ = MI_NOOP; |
||
958 | *virt++ = MI_NOOP; |
||
959 | } |
||
960 | |||
961 | ring->tail = 0; |
||
962 | ring->space = ring_space(ring); |
||
963 | |||
964 | return 0; |
||
965 | } |
||
966 | |||
967 | int intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n) |
||
968 | { |
||
969 | struct drm_device *dev = ring->dev; |
||
970 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
971 | unsigned long end; |
||
972 | u32 head; |
||
973 | |||
974 | /* If the reported head position has wrapped or hasn't advanced, |
||
975 | * fallback to the slow and accurate path. |
||
976 | */ |
||
977 | head = intel_read_status_page(ring, 4); |
||
978 | if (head > ring->head) { |
||
979 | ring->head = head; |
||
980 | ring->space = ring_space(ring); |
||
981 | if (ring->space >= n) |
||
982 | return 0; |
||
983 | } |
||
984 | |||
985 | // trace_i915_ring_wait_begin(ring); |
||
986 | end = jiffies + 3 * HZ; |
||
987 | do { |
||
988 | ring->head = I915_READ_HEAD(ring); |
||
989 | ring->space = ring_space(ring); |
||
990 | if (ring->space >= n) { |
||
991 | // trace_i915_ring_wait_end(ring); |
||
992 | return 0; |
||
993 | } |
||
994 | |||
995 | if (dev->primary->master) { |
||
996 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
||
997 | if (master_priv->sarea_priv) |
||
998 | master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; |
||
999 | } |
||
1000 | |||
1001 | msleep(1); |
||
1002 | if (atomic_read(&dev_priv->mm.wedged)) |
||
1003 | return -EAGAIN; |
||
1004 | } while (!time_after(jiffies, end)); |
||
1005 | // trace_i915_ring_wait_end(ring); |
||
1006 | return -EBUSY; |
||
1007 | } |
||
1008 | |||
1009 | int intel_ring_begin(struct intel_ring_buffer *ring, |
||
1010 | int num_dwords) |
||
1011 | { |
||
1012 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
||
1013 | int n = 4*num_dwords; |
||
1014 | int ret; |
||
1015 | |||
1016 | if (unlikely(atomic_read(&dev_priv->mm.wedged))) |
||
1017 | return -EIO; |
||
1018 | |||
1019 | if (unlikely(ring->tail + n > ring->effective_size)) { |
||
1020 | ret = intel_wrap_ring_buffer(ring); |
||
1021 | if (unlikely(ret)) |
||
1022 | return ret; |
||
1023 | } |
||
1024 | |||
1025 | if (unlikely(ring->space < n)) { |
||
1026 | ret = intel_wait_ring_buffer(ring, n); |
||
1027 | if (unlikely(ret)) |
||
1028 | return ret; |
||
1029 | } |
||
1030 | |||
1031 | ring->space -= n; |
||
1032 | return 0; |
||
1033 | } |
||
1034 | |||
1035 | void intel_ring_advance(struct intel_ring_buffer *ring) |
||
1036 | { |
||
1037 | ring->tail &= ring->size - 1; |
||
1038 | ring->write_tail(ring, ring->tail); |
||
1039 | } |
||
1040 | |||
1041 | |||
1042 | static const struct intel_ring_buffer render_ring = { |
||
1043 | .name = "render ring", |
||
1044 | .id = RING_RENDER, |
||
1045 | .mmio_base = RENDER_RING_BASE, |
||
1046 | .size = 32 * PAGE_SIZE, |
||
1047 | .init = init_render_ring, |
||
1048 | .write_tail = ring_write_tail, |
||
1049 | .flush = render_ring_flush, |
||
1050 | // .add_request = render_ring_add_request, |
||
1051 | // .get_seqno = ring_get_seqno, |
||
1052 | // .irq_get = render_ring_get_irq, |
||
1053 | // .irq_put = render_ring_put_irq, |
||
1054 | // .dispatch_execbuffer = render_ring_dispatch_execbuffer, |
||
1055 | // .cleanup = render_ring_cleanup, |
||
1056 | }; |
||
1057 | |||
1058 | /* ring buffer for bit-stream decoder */ |
||
1059 | |||
1060 | static const struct intel_ring_buffer bsd_ring = { |
||
1061 | .name = "bsd ring", |
||
1062 | .id = RING_BSD, |
||
1063 | .mmio_base = BSD_RING_BASE, |
||
1064 | .size = 32 * PAGE_SIZE, |
||
1065 | .init = init_ring_common, |
||
1066 | .write_tail = ring_write_tail, |
||
1067 | .flush = bsd_ring_flush, |
||
1068 | // .add_request = ring_add_request, |
||
1069 | // .get_seqno = ring_get_seqno, |
||
1070 | // .irq_get = bsd_ring_get_irq, |
||
1071 | // .irq_put = bsd_ring_put_irq, |
||
1072 | // .dispatch_execbuffer = ring_dispatch_execbuffer, |
||
1073 | }; |
||
1074 | |||
1075 | |||
1076 | static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring, |
||
1077 | u32 value) |
||
1078 | { |
||
1079 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
||
1080 | |||
1081 | /* Every tail move must follow the sequence below */ |
||
1082 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
||
1083 | GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK | |
||
1084 | GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE); |
||
1085 | I915_WRITE(GEN6_BSD_RNCID, 0x0); |
||
1086 | |||
1087 | if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) & |
||
1088 | GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR) == 0, |
||
1089 | 50)) |
||
1090 | DRM_ERROR("timed out waiting for IDLE Indicator\n"); |
||
1091 | |||
1092 | I915_WRITE_TAIL(ring, value); |
||
1093 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
||
1094 | GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK | |
||
1095 | GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE); |
||
1096 | } |
||
1097 | |||
1098 | |||
1099 | static int gen6_ring_flush(struct intel_ring_buffer *ring, |
||
1100 | u32 invalidate, u32 flush) |
||
1101 | { |
||
1102 | uint32_t cmd; |
||
1103 | int ret; |
||
1104 | |||
1105 | ret = intel_ring_begin(ring, 4); |
||
1106 | if (ret) |
||
1107 | return ret; |
||
1108 | |||
1109 | cmd = MI_FLUSH_DW; |
||
1110 | if (invalidate & I915_GEM_GPU_DOMAINS) |
||
1111 | cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD; |
||
1112 | intel_ring_emit(ring, cmd); |
||
1113 | intel_ring_emit(ring, 0); |
||
1114 | intel_ring_emit(ring, 0); |
||
1115 | intel_ring_emit(ring, MI_NOOP); |
||
1116 | intel_ring_advance(ring); |
||
1117 | return 0; |
||
1118 | } |
||
1119 | |||
1120 | #if 0 |
||
1121 | static int |
||
1122 | gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring, |
||
1123 | u32 offset, u32 len) |
||
1124 | { |
||
1125 | int ret; |
||
1126 | |||
1127 | ret = intel_ring_begin(ring, 2); |
||
1128 | if (ret) |
||
1129 | return ret; |
||
1130 | |||
1131 | intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_NON_SECURE_I965); |
||
1132 | /* bit0-7 is the length on GEN6+ */ |
||
1133 | intel_ring_emit(ring, offset); |
||
1134 | intel_ring_advance(ring); |
||
1135 | |||
1136 | return 0; |
||
1137 | } |
||
1138 | |||
1139 | static bool |
||
1140 | gen6_render_ring_get_irq(struct intel_ring_buffer *ring) |
||
1141 | { |
||
1142 | return gen6_ring_get_irq(ring, |
||
1143 | GT_USER_INTERRUPT, |
||
1144 | GEN6_RENDER_USER_INTERRUPT); |
||
1145 | } |
||
1146 | |||
1147 | static void |
||
1148 | gen6_render_ring_put_irq(struct intel_ring_buffer *ring) |
||
1149 | { |
||
1150 | return gen6_ring_put_irq(ring, |
||
1151 | GT_USER_INTERRUPT, |
||
1152 | GEN6_RENDER_USER_INTERRUPT); |
||
1153 | } |
||
1154 | |||
1155 | static bool |
||
1156 | gen6_bsd_ring_get_irq(struct intel_ring_buffer *ring) |
||
1157 | { |
||
1158 | return gen6_ring_get_irq(ring, |
||
1159 | GT_GEN6_BSD_USER_INTERRUPT, |
||
1160 | GEN6_BSD_USER_INTERRUPT); |
||
1161 | } |
||
1162 | |||
1163 | static void |
||
1164 | gen6_bsd_ring_put_irq(struct intel_ring_buffer *ring) |
||
1165 | { |
||
1166 | return gen6_ring_put_irq(ring, |
||
1167 | GT_GEN6_BSD_USER_INTERRUPT, |
||
1168 | GEN6_BSD_USER_INTERRUPT); |
||
1169 | } |
||
1170 | |||
1171 | #endif |
||
1172 | |||
1173 | /* ring buffer for Video Codec for Gen6+ */ |
||
1174 | static const struct intel_ring_buffer gen6_bsd_ring = { |
||
1175 | .name = "gen6 bsd ring", |
||
1176 | .id = RING_BSD, |
||
1177 | .mmio_base = GEN6_BSD_RING_BASE, |
||
1178 | .size = 32 * PAGE_SIZE, |
||
1179 | .init = init_ring_common, |
||
1180 | .write_tail = gen6_bsd_ring_write_tail, |
||
1181 | .flush = gen6_ring_flush, |
||
1182 | // .add_request = gen6_add_request, |
||
1183 | // .get_seqno = ring_get_seqno, |
||
1184 | // .irq_get = gen6_bsd_ring_get_irq, |
||
1185 | // .irq_put = gen6_bsd_ring_put_irq, |
||
1186 | // .dispatch_execbuffer = gen6_ring_dispatch_execbuffer, |
||
1187 | }; |
||
1188 | |||
1189 | #if 0 |
||
1190 | /* Blitter support (SandyBridge+) */ |
||
1191 | |||
1192 | static bool |
||
1193 | blt_ring_get_irq(struct intel_ring_buffer *ring) |
||
1194 | { |
||
1195 | return gen6_ring_get_irq(ring, |
||
1196 | GT_BLT_USER_INTERRUPT, |
||
1197 | GEN6_BLITTER_USER_INTERRUPT); |
||
1198 | } |
||
1199 | |||
1200 | static void |
||
1201 | blt_ring_put_irq(struct intel_ring_buffer *ring) |
||
1202 | { |
||
1203 | gen6_ring_put_irq(ring, |
||
1204 | GT_BLT_USER_INTERRUPT, |
||
1205 | GEN6_BLITTER_USER_INTERRUPT); |
||
1206 | } |
||
1207 | #endif |
||
1208 | |||
1209 | |||
1210 | /* Workaround for some stepping of SNB, |
||
1211 | * each time when BLT engine ring tail moved, |
||
1212 | * the first command in the ring to be parsed |
||
1213 | * should be MI_BATCH_BUFFER_START |
||
1214 | */ |
||
1215 | #define NEED_BLT_WORKAROUND(dev) \ |
||
1216 | (IS_GEN6(dev) && (dev->pdev->revision < 8)) |
||
1217 | |||
1218 | static inline struct drm_i915_gem_object * |
||
1219 | to_blt_workaround(struct intel_ring_buffer *ring) |
||
1220 | { |
||
1221 | return ring->private; |
||
1222 | } |
||
1223 | |||
1224 | |||
1225 | static int blt_ring_init(struct intel_ring_buffer *ring) |
||
1226 | { |
||
1227 | if (NEED_BLT_WORKAROUND(ring->dev)) { |
||
1228 | struct drm_i915_gem_object *obj; |
||
1229 | u32 *ptr; |
||
1230 | int ret; |
||
1231 | |||
1232 | obj = i915_gem_alloc_object(ring->dev, 4096); |
||
1233 | if (obj == NULL) |
||
1234 | return -ENOMEM; |
||
1235 | |||
1236 | ret = i915_gem_object_pin(obj, 4096, true); |
||
1237 | if (ret) { |
||
1238 | // drm_gem_object_unreference(&obj->base); |
||
1239 | return ret; |
||
1240 | } |
||
1241 | |||
1242 | ptr = ioremap(obj->pages[0], 4096); |
||
1243 | *ptr++ = MI_BATCH_BUFFER_END; |
||
1244 | *ptr++ = MI_NOOP; |
||
1245 | iounmap(obj->pages[0]); |
||
1246 | |||
1247 | ret = i915_gem_object_set_to_gtt_domain(obj, false); |
||
1248 | if (ret) { |
||
1249 | // i915_gem_object_unpin(obj); |
||
1250 | // drm_gem_object_unreference(&obj->base); |
||
1251 | return ret; |
||
1252 | } |
||
1253 | |||
1254 | ring->private = obj; |
||
1255 | } |
||
1256 | |||
1257 | return init_ring_common(ring); |
||
1258 | } |
||
1259 | |||
1260 | static int blt_ring_begin(struct intel_ring_buffer *ring, |
||
1261 | int num_dwords) |
||
1262 | { |
||
1263 | if (ring->private) { |
||
1264 | int ret = intel_ring_begin(ring, num_dwords+2); |
||
1265 | if (ret) |
||
1266 | return ret; |
||
1267 | |||
1268 | intel_ring_emit(ring, MI_BATCH_BUFFER_START); |
||
1269 | intel_ring_emit(ring, to_blt_workaround(ring)->gtt_offset); |
||
1270 | |||
1271 | return 0; |
||
1272 | } else |
||
1273 | return intel_ring_begin(ring, 4); |
||
1274 | } |
||
1275 | |||
1276 | static int blt_ring_flush(struct intel_ring_buffer *ring, |
||
1277 | u32 invalidate, u32 flush) |
||
1278 | { |
||
1279 | uint32_t cmd; |
||
1280 | int ret; |
||
1281 | |||
1282 | ret = blt_ring_begin(ring, 4); |
||
1283 | if (ret) |
||
1284 | return ret; |
||
1285 | |||
1286 | cmd = MI_FLUSH_DW; |
||
1287 | if (invalidate & I915_GEM_DOMAIN_RENDER) |
||
1288 | cmd |= MI_INVALIDATE_TLB; |
||
1289 | intel_ring_emit(ring, cmd); |
||
1290 | intel_ring_emit(ring, 0); |
||
1291 | intel_ring_emit(ring, 0); |
||
1292 | intel_ring_emit(ring, MI_NOOP); |
||
1293 | intel_ring_advance(ring); |
||
1294 | return 0; |
||
1295 | } |
||
1296 | |||
1297 | static void blt_ring_cleanup(struct intel_ring_buffer *ring) |
||
1298 | { |
||
1299 | if (!ring->private) |
||
1300 | return; |
||
1301 | |||
1302 | i915_gem_object_unpin(ring->private); |
||
1303 | drm_gem_object_unreference(ring->private); |
||
1304 | ring->private = NULL; |
||
1305 | } |
||
1306 | |||
1307 | |||
1308 | static const struct intel_ring_buffer gen6_blt_ring = { |
||
1309 | .name = "blt ring", |
||
1310 | .id = RING_BLT, |
||
1311 | .mmio_base = BLT_RING_BASE, |
||
1312 | .size = 32 * PAGE_SIZE, |
||
1313 | .init = blt_ring_init, |
||
1314 | .write_tail = ring_write_tail, |
||
1315 | .flush = blt_ring_flush, |
||
1316 | // .add_request = gen6_add_request, |
||
1317 | // .get_seqno = ring_get_seqno, |
||
1318 | // .irq_get = blt_ring_get_irq, |
||
1319 | // .irq_put = blt_ring_put_irq, |
||
1320 | // .dispatch_execbuffer = gen6_ring_dispatch_execbuffer, |
||
1321 | // .cleanup = blt_ring_cleanup, |
||
1322 | }; |
||
1323 | |||
1324 | |||
1325 | |||
1326 | int intel_init_render_ring_buffer(struct drm_device *dev) |
||
1327 | { |
||
1328 | drm_i915_private_t *dev_priv = dev->dev_private; |
||
1329 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
||
1330 | ENTER(); |
||
1331 | *ring = render_ring; |
||
1332 | if (INTEL_INFO(dev)->gen >= 6) { |
||
1333 | // ring->add_request = gen6_add_request; |
||
1334 | // ring->irq_get = gen6_render_ring_get_irq; |
||
1335 | // ring->irq_put = gen6_render_ring_put_irq; |
||
1336 | } else if (IS_GEN5(dev)) { |
||
1337 | // ring->add_request = pc_render_add_request; |
||
1338 | // ring->get_seqno = pc_render_get_seqno; |
||
1339 | } |
||
1340 | |||
1341 | if (!I915_NEED_GFX_HWS(dev)) { |
||
1342 | ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr; |
||
1343 | memset(ring->status_page.page_addr, 0, PAGE_SIZE); |
||
1344 | } |
||
1345 | LEAVE(); |
||
1346 | return intel_init_ring_buffer(dev, ring); |
||
1347 | } |
||
1348 | |||
1349 | |||
1350 | int intel_init_bsd_ring_buffer(struct drm_device *dev) |
||
1351 | { |
||
1352 | drm_i915_private_t *dev_priv = dev->dev_private; |
||
1353 | struct intel_ring_buffer *ring = &dev_priv->ring[VCS]; |
||
1354 | |||
1355 | if (IS_GEN6(dev) || IS_GEN7(dev)) |
||
1356 | *ring = gen6_bsd_ring; |
||
1357 | else |
||
1358 | *ring = bsd_ring; |
||
1359 | |||
1360 | return intel_init_ring_buffer(dev, ring); |
||
1361 | } |
||
1362 | |||
1363 | int intel_init_blt_ring_buffer(struct drm_device *dev) |
||
1364 | { |
||
1365 | drm_i915_private_t *dev_priv = dev->dev_private; |
||
1366 | struct intel_ring_buffer *ring = &dev_priv->ring[BCS]; |
||
1367 | |||
1368 | *ring = gen6_blt_ring; |
||
1369 | |||
1370 | return intel_init_ring_buffer(dev, ring); |
||
1371 | }>>>><>><>><>><>><>><>><>><>><>>> |
||
1372 |