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6084 | serge | 1 | /* |
2 | * Copyright © 2014 Intel Corporation |
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3 | * |
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4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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5 | * copy of this software and associated documentation files (the "Software"), |
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6 | * to deal in the Software without restriction, including without limitation |
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7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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8 | * and/or sell copies of the Software, and to permit persons to whom the |
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9 | * Software is furnished to do so, subject to the following conditions: |
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10 | * |
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11 | * The above copyright notice and this permission notice (including the next |
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12 | * paragraph) shall be included in all copies or substantial portions of the |
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13 | * Software. |
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14 | * |
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15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
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21 | * IN THE SOFTWARE. |
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22 | */ |
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23 | #ifndef _INTEL_GUC_FWIF_H |
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24 | #define _INTEL_GUC_FWIF_H |
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25 | |||
26 | /* |
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27 | * This file is partially autogenerated, although currently with some manual |
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28 | * fixups afterwards. In future, it should be entirely autogenerated, in order |
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29 | * to ensure that the definitions herein remain in sync with those used by the |
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30 | * GuC's own firmware. |
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31 | * |
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32 | * EDITING THIS FILE IS THEREFORE NOT RECOMMENDED - YOUR CHANGES MAY BE LOST. |
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33 | */ |
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34 | |||
35 | #define GFXCORE_FAMILY_GEN9 12 |
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36 | #define GFXCORE_FAMILY_UNKNOWN 0x7fffffff |
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37 | |||
38 | #define GUC_CTX_PRIORITY_KMD_HIGH 0 |
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39 | #define GUC_CTX_PRIORITY_HIGH 1 |
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40 | #define GUC_CTX_PRIORITY_KMD_NORMAL 2 |
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41 | #define GUC_CTX_PRIORITY_NORMAL 3 |
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42 | |||
43 | #define GUC_MAX_GPU_CONTEXTS 1024 |
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44 | #define GUC_INVALID_CTX_ID GUC_MAX_GPU_CONTEXTS |
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45 | |||
46 | /* Work queue item header definitions */ |
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47 | #define WQ_STATUS_ACTIVE 1 |
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48 | #define WQ_STATUS_SUSPENDED 2 |
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49 | #define WQ_STATUS_CMD_ERROR 3 |
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50 | #define WQ_STATUS_ENGINE_ID_NOT_USED 4 |
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51 | #define WQ_STATUS_SUSPENDED_FROM_RESET 5 |
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52 | #define WQ_TYPE_SHIFT 0 |
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53 | #define WQ_TYPE_BATCH_BUF (0x1 << WQ_TYPE_SHIFT) |
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54 | #define WQ_TYPE_PSEUDO (0x2 << WQ_TYPE_SHIFT) |
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55 | #define WQ_TYPE_INORDER (0x3 << WQ_TYPE_SHIFT) |
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56 | #define WQ_TARGET_SHIFT 10 |
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57 | #define WQ_LEN_SHIFT 16 |
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58 | #define WQ_NO_WCFLUSH_WAIT (1 << 27) |
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59 | #define WQ_PRESENT_WORKLOAD (1 << 28) |
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60 | #define WQ_WORKLOAD_SHIFT 29 |
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61 | #define WQ_WORKLOAD_GENERAL (0 << WQ_WORKLOAD_SHIFT) |
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62 | #define WQ_WORKLOAD_GPGPU (1 << WQ_WORKLOAD_SHIFT) |
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63 | #define WQ_WORKLOAD_TOUCH (2 << WQ_WORKLOAD_SHIFT) |
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64 | |||
65 | #define WQ_RING_TAIL_SHIFT 20 |
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66 | #define WQ_RING_TAIL_MASK (0x7FF << WQ_RING_TAIL_SHIFT) |
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67 | |||
68 | #define GUC_DOORBELL_ENABLED 1 |
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69 | #define GUC_DOORBELL_DISABLED 0 |
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70 | |||
71 | #define GUC_CTX_DESC_ATTR_ACTIVE (1 << 0) |
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72 | #define GUC_CTX_DESC_ATTR_PENDING_DB (1 << 1) |
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73 | #define GUC_CTX_DESC_ATTR_KERNEL (1 << 2) |
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74 | #define GUC_CTX_DESC_ATTR_PREEMPT (1 << 3) |
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75 | #define GUC_CTX_DESC_ATTR_RESET (1 << 4) |
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76 | #define GUC_CTX_DESC_ATTR_WQLOCKED (1 << 5) |
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77 | #define GUC_CTX_DESC_ATTR_PCH (1 << 6) |
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78 | #define GUC_CTX_DESC_ATTR_TERMINATED (1 << 7) |
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79 | |||
80 | /* The guc control data is 10 DWORDs */ |
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81 | #define GUC_CTL_CTXINFO 0 |
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82 | #define GUC_CTL_CTXNUM_IN16_SHIFT 0 |
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83 | #define GUC_CTL_BASE_ADDR_SHIFT 12 |
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84 | #define GUC_CTL_ARAT_HIGH 1 |
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85 | #define GUC_CTL_ARAT_LOW 2 |
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86 | #define GUC_CTL_DEVICE_INFO 3 |
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87 | #define GUC_CTL_GTTYPE_SHIFT 0 |
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88 | #define GUC_CTL_COREFAMILY_SHIFT 7 |
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89 | #define GUC_CTL_LOG_PARAMS 4 |
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90 | #define GUC_LOG_VALID (1 << 0) |
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91 | #define GUC_LOG_NOTIFY_ON_HALF_FULL (1 << 1) |
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92 | #define GUC_LOG_ALLOC_IN_MEGABYTE (1 << 3) |
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93 | #define GUC_LOG_CRASH_PAGES 1 |
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94 | #define GUC_LOG_CRASH_SHIFT 4 |
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95 | #define GUC_LOG_DPC_PAGES 3 |
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96 | #define GUC_LOG_DPC_SHIFT 6 |
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97 | #define GUC_LOG_ISR_PAGES 3 |
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98 | #define GUC_LOG_ISR_SHIFT 9 |
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99 | #define GUC_LOG_BUF_ADDR_SHIFT 12 |
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100 | #define GUC_CTL_PAGE_FAULT_CONTROL 5 |
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101 | #define GUC_CTL_WA 6 |
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102 | #define GUC_CTL_WA_UK_BY_DRIVER (1 << 3) |
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103 | #define GUC_CTL_FEATURE 7 |
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104 | #define GUC_CTL_VCS2_ENABLED (1 << 0) |
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105 | #define GUC_CTL_KERNEL_SUBMISSIONS (1 << 1) |
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106 | #define GUC_CTL_FEATURE2 (1 << 2) |
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107 | #define GUC_CTL_POWER_GATING (1 << 3) |
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108 | #define GUC_CTL_DISABLE_SCHEDULER (1 << 4) |
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109 | #define GUC_CTL_PREEMPTION_LOG (1 << 5) |
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110 | #define GUC_CTL_ENABLE_SLPC (1 << 7) |
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111 | #define GUC_CTL_RESET_ON_PREMPT_FAILURE (1 << 8) |
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112 | #define GUC_CTL_DEBUG 8 |
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113 | #define GUC_LOG_VERBOSITY_SHIFT 0 |
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114 | #define GUC_LOG_VERBOSITY_LOW (0 << GUC_LOG_VERBOSITY_SHIFT) |
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115 | #define GUC_LOG_VERBOSITY_MED (1 << GUC_LOG_VERBOSITY_SHIFT) |
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116 | #define GUC_LOG_VERBOSITY_HIGH (2 << GUC_LOG_VERBOSITY_SHIFT) |
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117 | #define GUC_LOG_VERBOSITY_ULTRA (3 << GUC_LOG_VERBOSITY_SHIFT) |
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118 | /* Verbosity range-check limits, without the shift */ |
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119 | #define GUC_LOG_VERBOSITY_MIN 0 |
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120 | #define GUC_LOG_VERBOSITY_MAX 3 |
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121 | #define GUC_CTL_RSRVD 9 |
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122 | |||
123 | #define GUC_CTL_MAX_DWORDS (GUC_CTL_RSRVD + 1) |
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124 | |||
125 | struct guc_doorbell_info { |
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126 | u32 db_status; |
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127 | u32 cookie; |
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128 | u32 reserved[14]; |
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129 | } __packed; |
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130 | |||
131 | union guc_doorbell_qw { |
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132 | struct { |
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133 | u32 db_status; |
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134 | u32 cookie; |
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135 | }; |
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136 | u64 value_qw; |
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137 | } __packed; |
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138 | |||
139 | #define GUC_MAX_DOORBELLS 256 |
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140 | #define GUC_INVALID_DOORBELL_ID (GUC_MAX_DOORBELLS) |
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141 | |||
142 | #define GUC_DB_SIZE (PAGE_SIZE) |
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143 | #define GUC_WQ_SIZE (PAGE_SIZE * 2) |
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144 | |||
145 | /* Work item for submitting workloads into work queue of GuC. */ |
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146 | struct guc_wq_item { |
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147 | u32 header; |
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148 | u32 context_desc; |
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149 | u32 ring_tail; |
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150 | u32 fence_id; |
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151 | } __packed; |
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152 | |||
153 | struct guc_process_desc { |
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154 | u32 context_id; |
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155 | u64 db_base_addr; |
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156 | u32 head; |
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157 | u32 tail; |
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158 | u32 error_offset; |
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159 | u64 wq_base_addr; |
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160 | u32 wq_size_bytes; |
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161 | u32 wq_status; |
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162 | u32 engine_presence; |
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163 | u32 priority; |
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164 | u32 reserved[30]; |
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165 | } __packed; |
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166 | |||
167 | /* engine id and context id is packed into guc_execlist_context.context_id*/ |
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168 | #define GUC_ELC_CTXID_OFFSET 0 |
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169 | #define GUC_ELC_ENGINE_OFFSET 29 |
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170 | |||
171 | /* The execlist context including software and HW information */ |
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172 | struct guc_execlist_context { |
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173 | u32 context_desc; |
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174 | u32 context_id; |
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175 | u32 ring_status; |
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176 | u32 ring_lcra; |
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177 | u32 ring_begin; |
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178 | u32 ring_end; |
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179 | u32 ring_next_free_location; |
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180 | u32 ring_current_tail_pointer_value; |
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181 | u8 engine_state_submit_value; |
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182 | u8 engine_state_wait_value; |
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183 | u16 pagefault_count; |
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184 | u16 engine_submit_queue_count; |
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185 | } __packed; |
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186 | |||
187 | /*Context descriptor for communicating between uKernel and Driver*/ |
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188 | struct guc_context_desc { |
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189 | u32 sched_common_area; |
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190 | u32 context_id; |
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191 | u32 pas_id; |
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192 | u8 engines_used; |
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193 | u64 db_trigger_cpu; |
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194 | u32 db_trigger_uk; |
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195 | u64 db_trigger_phy; |
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196 | u16 db_id; |
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197 | |||
198 | struct guc_execlist_context lrc[I915_NUM_RINGS]; |
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199 | |||
200 | u8 attribute; |
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201 | |||
202 | u32 priority; |
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203 | |||
204 | u32 wq_sampled_tail_offset; |
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205 | u32 wq_total_submit_enqueues; |
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206 | |||
207 | u32 process_desc; |
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208 | u32 wq_addr; |
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209 | u32 wq_size; |
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210 | |||
211 | u32 engine_presence; |
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212 | |||
213 | u8 engine_suspended; |
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214 | |||
215 | u8 reserved0[3]; |
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216 | u64 reserved1[1]; |
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217 | |||
218 | u64 desc_private; |
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219 | } __packed; |
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220 | |||
221 | #define GUC_FORCEWAKE_RENDER (1 << 0) |
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222 | #define GUC_FORCEWAKE_MEDIA (1 << 1) |
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223 | |||
224 | #define GUC_POWER_UNSPECIFIED 0 |
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225 | #define GUC_POWER_D0 1 |
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226 | #define GUC_POWER_D1 2 |
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227 | #define GUC_POWER_D2 3 |
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228 | #define GUC_POWER_D3 4 |
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229 | |||
230 | /* This Action will be programmed in C180 - SOFT_SCRATCH_O_REG */ |
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231 | enum host2guc_action { |
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232 | HOST2GUC_ACTION_DEFAULT = 0x0, |
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233 | HOST2GUC_ACTION_SAMPLE_FORCEWAKE = 0x6, |
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234 | HOST2GUC_ACTION_ALLOCATE_DOORBELL = 0x10, |
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235 | HOST2GUC_ACTION_DEALLOCATE_DOORBELL = 0x20, |
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236 | HOST2GUC_ACTION_ENTER_S_STATE = 0x501, |
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237 | HOST2GUC_ACTION_EXIT_S_STATE = 0x502, |
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238 | HOST2GUC_ACTION_SLPC_REQUEST = 0x3003, |
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239 | HOST2GUC_ACTION_LIMIT |
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240 | }; |
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241 | |||
242 | /* |
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243 | * The GuC sends its response to a command by overwriting the |
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244 | * command in SS0. The response is distinguishable from a command |
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245 | * by the fact that all the MASK bits are set. The remaining bits |
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246 | * give more detail. |
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247 | */ |
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248 | #define GUC2HOST_RESPONSE_MASK ((u32)0xF0000000) |
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249 | #define GUC2HOST_IS_RESPONSE(x) ((u32)(x) >= GUC2HOST_RESPONSE_MASK) |
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250 | #define GUC2HOST_STATUS(x) (GUC2HOST_RESPONSE_MASK | (x)) |
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251 | |||
252 | /* GUC will return status back to SOFT_SCRATCH_O_REG */ |
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253 | enum guc2host_status { |
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254 | GUC2HOST_STATUS_SUCCESS = GUC2HOST_STATUS(0x0), |
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255 | GUC2HOST_STATUS_ALLOCATE_DOORBELL_FAIL = GUC2HOST_STATUS(0x10), |
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256 | GUC2HOST_STATUS_DEALLOCATE_DOORBELL_FAIL = GUC2HOST_STATUS(0x20), |
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257 | GUC2HOST_STATUS_GENERIC_FAIL = GUC2HOST_STATUS(0x0000F000) |
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258 | }; |
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259 | |||
260 | #endif><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><> |