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Rev | Author | Line No. | Line |
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2330 | Serge | 1 | /* |
2 | * Copyright 2006 Dave Airlie |
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3 | * Copyright © 2006-2007 Intel Corporation |
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4 | * |
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5 | * Permission is hereby granted, free of charge, to any person obtaining a |
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6 | * copy of this software and associated documentation files (the "Software"), |
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7 | * to deal in the Software without restriction, including without limitation |
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8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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9 | * and/or sell copies of the Software, and to permit persons to whom the |
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10 | * Software is furnished to do so, subject to the following conditions: |
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11 | * |
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12 | * The above copyright notice and this permission notice (including the next |
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13 | * paragraph) shall be included in all copies or substantial portions of the |
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14 | * Software. |
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15 | * |
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16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
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22 | * DEALINGS IN THE SOFTWARE. |
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23 | * |
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24 | * Authors: |
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25 | * Eric Anholt |
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26 | */ |
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27 | #include |
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28 | #include |
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3031 | serge | 29 | #include |
30 | #include |
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2330 | Serge | 31 | #include "intel_drv.h" |
3031 | serge | 32 | #include |
2330 | Serge | 33 | #include "i915_drv.h" |
34 | #include "dvo.h" |
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35 | |||
36 | #define SIL164_ADDR 0x38 |
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37 | #define CH7xxx_ADDR 0x76 |
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38 | #define TFP410_ADDR 0x38 |
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3031 | serge | 39 | #define NS2501_ADDR 0x38 |
2330 | Serge | 40 | |
41 | static const struct intel_dvo_device intel_dvo_devices[] = { |
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42 | { |
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43 | .type = INTEL_DVO_CHIP_TMDS, |
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44 | .name = "sil164", |
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45 | .dvo_reg = DVOC, |
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46 | .slave_addr = SIL164_ADDR, |
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47 | .dev_ops = &sil164_ops, |
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48 | }, |
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49 | { |
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50 | .type = INTEL_DVO_CHIP_TMDS, |
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51 | .name = "ch7xxx", |
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52 | .dvo_reg = DVOC, |
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53 | .slave_addr = CH7xxx_ADDR, |
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54 | .dev_ops = &ch7xxx_ops, |
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55 | }, |
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56 | { |
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4104 | Serge | 57 | .type = INTEL_DVO_CHIP_TMDS, |
58 | .name = "ch7xxx", |
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59 | .dvo_reg = DVOC, |
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60 | .slave_addr = 0x75, /* For some ch7010 */ |
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61 | .dev_ops = &ch7xxx_ops, |
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62 | }, |
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63 | { |
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2330 | Serge | 64 | .type = INTEL_DVO_CHIP_LVDS, |
65 | .name = "ivch", |
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66 | .dvo_reg = DVOA, |
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67 | .slave_addr = 0x02, /* Might also be 0x44, 0x84, 0xc4 */ |
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68 | .dev_ops = &ivch_ops, |
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69 | }, |
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70 | { |
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71 | .type = INTEL_DVO_CHIP_TMDS, |
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72 | .name = "tfp410", |
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73 | .dvo_reg = DVOC, |
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74 | .slave_addr = TFP410_ADDR, |
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75 | .dev_ops = &tfp410_ops, |
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76 | }, |
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77 | { |
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78 | .type = INTEL_DVO_CHIP_LVDS, |
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79 | .name = "ch7017", |
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80 | .dvo_reg = DVOC, |
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81 | .slave_addr = 0x75, |
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82 | .gpio = GMBUS_PORT_DPB, |
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83 | .dev_ops = &ch7017_ops, |
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3031 | serge | 84 | }, |
85 | { |
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86 | .type = INTEL_DVO_CHIP_TMDS, |
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87 | .name = "ns2501", |
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88 | .dvo_reg = DVOC, |
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89 | .slave_addr = NS2501_ADDR, |
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90 | .dev_ops = &ns2501_ops, |
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2330 | Serge | 91 | } |
92 | }; |
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93 | |||
94 | struct intel_dvo { |
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95 | struct intel_encoder base; |
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96 | |||
97 | struct intel_dvo_device dev; |
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98 | |||
99 | struct drm_display_mode *panel_fixed_mode; |
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100 | bool panel_wants_dither; |
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101 | }; |
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102 | |||
4104 | Serge | 103 | static struct intel_dvo *enc_to_dvo(struct intel_encoder *encoder) |
2330 | Serge | 104 | { |
4104 | Serge | 105 | return container_of(encoder, struct intel_dvo, base); |
2330 | Serge | 106 | } |
107 | |||
108 | static struct intel_dvo *intel_attached_dvo(struct drm_connector *connector) |
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109 | { |
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4104 | Serge | 110 | return enc_to_dvo(intel_attached_encoder(connector)); |
2330 | Serge | 111 | } |
112 | |||
3031 | serge | 113 | static bool intel_dvo_connector_get_hw_state(struct intel_connector *connector) |
2330 | Serge | 114 | { |
3031 | serge | 115 | struct intel_dvo *intel_dvo = intel_attached_dvo(&connector->base); |
116 | |||
117 | return intel_dvo->dev.dev_ops->get_hw_state(&intel_dvo->dev); |
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118 | } |
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119 | |||
120 | static bool intel_dvo_get_hw_state(struct intel_encoder *encoder, |
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121 | enum pipe *pipe) |
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122 | { |
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123 | struct drm_device *dev = encoder->base.dev; |
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124 | struct drm_i915_private *dev_priv = dev->dev_private; |
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4104 | Serge | 125 | struct intel_dvo *intel_dvo = enc_to_dvo(encoder); |
3031 | serge | 126 | u32 tmp; |
127 | |||
128 | tmp = I915_READ(intel_dvo->dev.dvo_reg); |
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129 | |||
130 | if (!(tmp & DVO_ENABLE)) |
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131 | return false; |
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132 | |||
133 | *pipe = PORT_TO_PIPE(tmp); |
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134 | |||
135 | return true; |
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136 | } |
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137 | |||
4104 | Serge | 138 | static void intel_dvo_get_config(struct intel_encoder *encoder, |
139 | struct intel_crtc_config *pipe_config) |
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140 | { |
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141 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
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142 | struct intel_dvo *intel_dvo = enc_to_dvo(encoder); |
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143 | u32 tmp, flags = 0; |
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144 | |||
145 | tmp = I915_READ(intel_dvo->dev.dvo_reg); |
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146 | if (tmp & DVO_HSYNC_ACTIVE_HIGH) |
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147 | flags |= DRM_MODE_FLAG_PHSYNC; |
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148 | else |
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149 | flags |= DRM_MODE_FLAG_NHSYNC; |
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150 | if (tmp & DVO_VSYNC_ACTIVE_HIGH) |
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151 | flags |= DRM_MODE_FLAG_PVSYNC; |
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152 | else |
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153 | flags |= DRM_MODE_FLAG_NVSYNC; |
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154 | |||
155 | pipe_config->adjusted_mode.flags |= flags; |
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156 | } |
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157 | |||
3031 | serge | 158 | static void intel_disable_dvo(struct intel_encoder *encoder) |
159 | { |
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160 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
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4104 | Serge | 161 | struct intel_dvo *intel_dvo = enc_to_dvo(encoder); |
2330 | Serge | 162 | u32 dvo_reg = intel_dvo->dev.dvo_reg; |
163 | u32 temp = I915_READ(dvo_reg); |
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164 | |||
3031 | serge | 165 | intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, false); |
166 | I915_WRITE(dvo_reg, temp & ~DVO_ENABLE); |
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167 | I915_READ(dvo_reg); |
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168 | } |
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169 | |||
170 | static void intel_enable_dvo(struct intel_encoder *encoder) |
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171 | { |
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172 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
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4104 | Serge | 173 | struct intel_dvo *intel_dvo = enc_to_dvo(encoder); |
4398 | Serge | 174 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
3031 | serge | 175 | u32 dvo_reg = intel_dvo->dev.dvo_reg; |
176 | u32 temp = I915_READ(dvo_reg); |
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177 | |||
2330 | Serge | 178 | I915_WRITE(dvo_reg, temp | DVO_ENABLE); |
179 | I915_READ(dvo_reg); |
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4398 | Serge | 180 | intel_dvo->dev.dev_ops->mode_set(&intel_dvo->dev, |
181 | &crtc->config.requested_mode, |
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182 | &crtc->config.adjusted_mode); |
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183 | |||
3031 | serge | 184 | intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, true); |
185 | } |
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186 | |||
4104 | Serge | 187 | /* Special dpms function to support cloning between dvo/sdvo/crt. */ |
3031 | serge | 188 | static void intel_dvo_dpms(struct drm_connector *connector, int mode) |
189 | { |
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190 | struct intel_dvo *intel_dvo = intel_attached_dvo(connector); |
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191 | struct drm_crtc *crtc; |
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4398 | Serge | 192 | struct intel_crtc_config *config; |
3031 | serge | 193 | |
194 | /* dvo supports only 2 dpms states. */ |
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195 | if (mode != DRM_MODE_DPMS_ON) |
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196 | mode = DRM_MODE_DPMS_OFF; |
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197 | |||
198 | if (mode == connector->dpms) |
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199 | return; |
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200 | |||
201 | connector->dpms = mode; |
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202 | |||
203 | /* Only need to change hw state when actually enabled */ |
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204 | crtc = intel_dvo->base.base.crtc; |
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205 | if (!crtc) { |
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206 | intel_dvo->base.connectors_active = false; |
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207 | return; |
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208 | } |
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209 | |||
4104 | Serge | 210 | /* We call connector dpms manually below in case pipe dpms doesn't |
211 | * change due to cloning. */ |
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3031 | serge | 212 | if (mode == DRM_MODE_DPMS_ON) { |
4398 | Serge | 213 | config = &to_intel_crtc(crtc)->config; |
214 | |||
3031 | serge | 215 | intel_dvo->base.connectors_active = true; |
216 | |||
217 | intel_crtc_update_dpms(crtc); |
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218 | |||
4398 | Serge | 219 | intel_dvo->dev.dev_ops->mode_set(&intel_dvo->dev, |
220 | &config->requested_mode, |
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221 | &config->adjusted_mode); |
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222 | |||
3031 | serge | 223 | intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, true); |
2330 | Serge | 224 | } else { |
3031 | serge | 225 | intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, false); |
226 | |||
227 | intel_dvo->base.connectors_active = false; |
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228 | |||
229 | intel_crtc_update_dpms(crtc); |
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2330 | Serge | 230 | } |
3031 | serge | 231 | |
232 | intel_modeset_check_state(connector->dev); |
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2330 | Serge | 233 | } |
234 | |||
235 | static int intel_dvo_mode_valid(struct drm_connector *connector, |
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236 | struct drm_display_mode *mode) |
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237 | { |
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238 | struct intel_dvo *intel_dvo = intel_attached_dvo(connector); |
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239 | |||
240 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) |
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241 | return MODE_NO_DBLESCAN; |
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242 | |||
243 | /* XXX: Validate clock range */ |
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244 | |||
245 | if (intel_dvo->panel_fixed_mode) { |
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246 | if (mode->hdisplay > intel_dvo->panel_fixed_mode->hdisplay) |
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247 | return MODE_PANEL; |
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248 | if (mode->vdisplay > intel_dvo->panel_fixed_mode->vdisplay) |
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249 | return MODE_PANEL; |
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250 | } |
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251 | |||
252 | return intel_dvo->dev.dev_ops->mode_valid(&intel_dvo->dev, mode); |
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253 | } |
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254 | |||
4104 | Serge | 255 | static bool intel_dvo_compute_config(struct intel_encoder *encoder, |
256 | struct intel_crtc_config *pipe_config) |
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2330 | Serge | 257 | { |
4104 | Serge | 258 | struct intel_dvo *intel_dvo = enc_to_dvo(encoder); |
259 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
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2330 | Serge | 260 | |
261 | /* If we have timings from the BIOS for the panel, put them in |
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262 | * to the adjusted mode. The CRTC will be set up for this mode, |
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263 | * with the panel scaling set up to source from the H/VDisplay |
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264 | * of the original mode. |
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265 | */ |
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266 | if (intel_dvo->panel_fixed_mode != NULL) { |
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267 | #define C(x) adjusted_mode->x = intel_dvo->panel_fixed_mode->x |
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268 | C(hdisplay); |
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269 | C(hsync_start); |
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270 | C(hsync_end); |
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271 | C(htotal); |
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272 | C(vdisplay); |
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273 | C(vsync_start); |
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274 | C(vsync_end); |
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275 | C(vtotal); |
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276 | C(clock); |
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277 | #undef C |
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4104 | Serge | 278 | |
279 | drm_mode_set_crtcinfo(adjusted_mode, 0); |
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2330 | Serge | 280 | } |
281 | |||
282 | if (intel_dvo->dev.dev_ops->mode_fixup) |
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4104 | Serge | 283 | return intel_dvo->dev.dev_ops->mode_fixup(&intel_dvo->dev, |
284 | &pipe_config->requested_mode, |
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285 | adjusted_mode); |
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2330 | Serge | 286 | |
287 | return true; |
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288 | } |
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289 | |||
4104 | Serge | 290 | static void intel_dvo_mode_set(struct intel_encoder *encoder) |
2330 | Serge | 291 | { |
4104 | Serge | 292 | struct drm_device *dev = encoder->base.dev; |
2330 | Serge | 293 | struct drm_i915_private *dev_priv = dev->dev_private; |
4104 | Serge | 294 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
295 | struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode; |
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296 | struct intel_dvo *intel_dvo = enc_to_dvo(encoder); |
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297 | int pipe = crtc->pipe; |
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2330 | Serge | 298 | u32 dvo_val; |
299 | u32 dvo_reg = intel_dvo->dev.dvo_reg, dvo_srcdim_reg; |
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300 | |||
301 | switch (dvo_reg) { |
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302 | case DVOA: |
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303 | default: |
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304 | dvo_srcdim_reg = DVOA_SRCDIM; |
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305 | break; |
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306 | case DVOB: |
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307 | dvo_srcdim_reg = DVOB_SRCDIM; |
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308 | break; |
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309 | case DVOC: |
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310 | dvo_srcdim_reg = DVOC_SRCDIM; |
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311 | break; |
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312 | } |
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313 | |||
314 | /* Save the data order, since I don't know what it should be set to. */ |
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315 | dvo_val = I915_READ(dvo_reg) & |
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316 | (DVO_PRESERVE_MASK | DVO_DATA_ORDER_GBRG); |
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317 | dvo_val |= DVO_DATA_ORDER_FP | DVO_BORDER_ENABLE | |
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318 | DVO_BLANK_ACTIVE_HIGH; |
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319 | |||
320 | if (pipe == 1) |
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321 | dvo_val |= DVO_PIPE_B_SELECT; |
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322 | dvo_val |= DVO_PIPE_STALL; |
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323 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
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324 | dvo_val |= DVO_HSYNC_ACTIVE_HIGH; |
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325 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
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326 | dvo_val |= DVO_VSYNC_ACTIVE_HIGH; |
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327 | |||
328 | /*I915_WRITE(DVOB_SRCDIM, |
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329 | (adjusted_mode->hdisplay << DVO_SRCDIM_HORIZONTAL_SHIFT) | |
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330 | (adjusted_mode->VDisplay << DVO_SRCDIM_VERTICAL_SHIFT));*/ |
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331 | I915_WRITE(dvo_srcdim_reg, |
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332 | (adjusted_mode->hdisplay << DVO_SRCDIM_HORIZONTAL_SHIFT) | |
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333 | (adjusted_mode->vdisplay << DVO_SRCDIM_VERTICAL_SHIFT)); |
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334 | /*I915_WRITE(DVOB, dvo_val);*/ |
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335 | I915_WRITE(dvo_reg, dvo_val); |
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336 | } |
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337 | |||
338 | /** |
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339 | * Detect the output connection on our DVO device. |
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340 | * |
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341 | * Unimplemented. |
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342 | */ |
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343 | static enum drm_connector_status |
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344 | intel_dvo_detect(struct drm_connector *connector, bool force) |
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345 | { |
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346 | struct intel_dvo *intel_dvo = intel_attached_dvo(connector); |
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4104 | Serge | 347 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
348 | connector->base.id, drm_get_connector_name(connector)); |
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2330 | Serge | 349 | return intel_dvo->dev.dev_ops->detect(&intel_dvo->dev); |
350 | } |
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351 | |||
352 | static int intel_dvo_get_modes(struct drm_connector *connector) |
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353 | { |
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354 | struct intel_dvo *intel_dvo = intel_attached_dvo(connector); |
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355 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
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356 | |||
357 | /* We should probably have an i2c driver get_modes function for those |
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358 | * devices which will have a fixed set of modes determined by the chip |
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359 | * (TV-out, for example), but for now with just TMDS and LVDS, |
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360 | * that's not the case. |
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361 | */ |
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362 | intel_ddc_get_modes(connector, |
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3031 | serge | 363 | intel_gmbus_get_adapter(dev_priv, GMBUS_PORT_DPC)); |
2330 | Serge | 364 | if (!list_empty(&connector->probed_modes)) |
365 | return 1; |
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366 | |||
367 | if (intel_dvo->panel_fixed_mode != NULL) { |
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368 | struct drm_display_mode *mode; |
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369 | mode = drm_mode_duplicate(connector->dev, intel_dvo->panel_fixed_mode); |
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370 | if (mode) { |
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371 | drm_mode_probed_add(connector, mode); |
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372 | return 1; |
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373 | } |
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374 | } |
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375 | |||
376 | return 0; |
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377 | } |
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378 | |||
379 | static void intel_dvo_destroy(struct drm_connector *connector) |
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380 | { |
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381 | drm_sysfs_connector_remove(connector); |
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382 | drm_connector_cleanup(connector); |
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383 | kfree(connector); |
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384 | } |
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385 | |||
386 | static const struct drm_connector_funcs intel_dvo_connector_funcs = { |
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3031 | serge | 387 | .dpms = intel_dvo_dpms, |
2330 | Serge | 388 | .detect = intel_dvo_detect, |
389 | .destroy = intel_dvo_destroy, |
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390 | .fill_modes = drm_helper_probe_single_connector_modes, |
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391 | }; |
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392 | |||
393 | static const struct drm_connector_helper_funcs intel_dvo_connector_helper_funcs = { |
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394 | .mode_valid = intel_dvo_mode_valid, |
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395 | .get_modes = intel_dvo_get_modes, |
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396 | .best_encoder = intel_best_encoder, |
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397 | }; |
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398 | |||
399 | static void intel_dvo_enc_destroy(struct drm_encoder *encoder) |
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400 | { |
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4104 | Serge | 401 | struct intel_dvo *intel_dvo = enc_to_dvo(to_intel_encoder(encoder)); |
2330 | Serge | 402 | |
403 | if (intel_dvo->dev.dev_ops->destroy) |
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404 | intel_dvo->dev.dev_ops->destroy(&intel_dvo->dev); |
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405 | |||
406 | kfree(intel_dvo->panel_fixed_mode); |
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407 | |||
408 | intel_encoder_destroy(encoder); |
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409 | } |
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410 | |||
411 | static const struct drm_encoder_funcs intel_dvo_enc_funcs = { |
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412 | .destroy = intel_dvo_enc_destroy, |
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413 | }; |
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414 | |||
415 | /** |
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416 | * Attempts to get a fixed panel timing for LVDS (currently only the i830). |
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417 | * |
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418 | * Other chips with DVO LVDS will need to extend this to deal with the LVDS |
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419 | * chip being on DVOB/C and having multiple pipes. |
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420 | */ |
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421 | static struct drm_display_mode * |
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422 | intel_dvo_get_current_mode(struct drm_connector *connector) |
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423 | { |
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424 | struct drm_device *dev = connector->dev; |
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425 | struct drm_i915_private *dev_priv = dev->dev_private; |
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426 | struct intel_dvo *intel_dvo = intel_attached_dvo(connector); |
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427 | uint32_t dvo_val = I915_READ(intel_dvo->dev.dvo_reg); |
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428 | struct drm_display_mode *mode = NULL; |
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429 | |||
430 | /* If the DVO port is active, that'll be the LVDS, so we can pull out |
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431 | * its timings to get how the BIOS set up the panel. |
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432 | */ |
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433 | if (dvo_val & DVO_ENABLE) { |
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434 | struct drm_crtc *crtc; |
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435 | int pipe = (dvo_val & DVO_PIPE_B_SELECT) ? 1 : 0; |
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436 | |||
437 | crtc = intel_get_crtc_for_pipe(dev, pipe); |
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438 | if (crtc) { |
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439 | mode = intel_crtc_mode_get(dev, crtc); |
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440 | if (mode) { |
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441 | mode->type |= DRM_MODE_TYPE_PREFERRED; |
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442 | if (dvo_val & DVO_HSYNC_ACTIVE_HIGH) |
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443 | mode->flags |= DRM_MODE_FLAG_PHSYNC; |
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444 | if (dvo_val & DVO_VSYNC_ACTIVE_HIGH) |
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445 | mode->flags |= DRM_MODE_FLAG_PVSYNC; |
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446 | } |
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447 | } |
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448 | } |
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449 | |||
450 | return mode; |
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451 | } |
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452 | |||
453 | void intel_dvo_init(struct drm_device *dev) |
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454 | { |
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455 | struct drm_i915_private *dev_priv = dev->dev_private; |
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456 | struct intel_encoder *intel_encoder; |
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457 | struct intel_dvo *intel_dvo; |
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458 | struct intel_connector *intel_connector; |
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459 | int i; |
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460 | int encoder_type = DRM_MODE_ENCODER_NONE; |
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461 | |||
462 | intel_dvo = kzalloc(sizeof(struct intel_dvo), GFP_KERNEL); |
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463 | if (!intel_dvo) |
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464 | return; |
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465 | |||
466 | intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); |
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467 | if (!intel_connector) { |
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468 | kfree(intel_dvo); |
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469 | return; |
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470 | } |
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471 | |||
472 | intel_encoder = &intel_dvo->base; |
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473 | drm_encoder_init(dev, &intel_encoder->base, |
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474 | &intel_dvo_enc_funcs, encoder_type); |
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475 | |||
3031 | serge | 476 | intel_encoder->disable = intel_disable_dvo; |
477 | intel_encoder->enable = intel_enable_dvo; |
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478 | intel_encoder->get_hw_state = intel_dvo_get_hw_state; |
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4104 | Serge | 479 | intel_encoder->get_config = intel_dvo_get_config; |
480 | intel_encoder->compute_config = intel_dvo_compute_config; |
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481 | intel_encoder->mode_set = intel_dvo_mode_set; |
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3031 | serge | 482 | intel_connector->get_hw_state = intel_dvo_connector_get_hw_state; |
483 | |||
2330 | Serge | 484 | /* Now, try to find a controller */ |
485 | for (i = 0; i < ARRAY_SIZE(intel_dvo_devices); i++) { |
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486 | struct drm_connector *connector = &intel_connector->base; |
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487 | const struct intel_dvo_device *dvo = &intel_dvo_devices[i]; |
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488 | struct i2c_adapter *i2c; |
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489 | int gpio; |
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3746 | Serge | 490 | bool dvoinit; |
2330 | Serge | 491 | |
492 | /* Allow the I2C driver info to specify the GPIO to be used in |
||
493 | * special cases, but otherwise default to what's defined |
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494 | * in the spec. |
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495 | */ |
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3031 | serge | 496 | if (intel_gmbus_is_port_valid(dvo->gpio)) |
2330 | Serge | 497 | gpio = dvo->gpio; |
498 | else if (dvo->type == INTEL_DVO_CHIP_LVDS) |
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499 | gpio = GMBUS_PORT_SSC; |
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500 | else |
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501 | gpio = GMBUS_PORT_DPB; |
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502 | |||
503 | /* Set up the I2C bus necessary for the chip we're probing. |
||
504 | * It appears that everything is on GPIOE except for panels |
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505 | * on i830 laptops, which are on GPIOB (DVOA). |
||
506 | */ |
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3031 | serge | 507 | i2c = intel_gmbus_get_adapter(dev_priv, gpio); |
2330 | Serge | 508 | |
509 | intel_dvo->dev = *dvo; |
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3746 | Serge | 510 | |
511 | /* GMBUS NAK handling seems to be unstable, hence let the |
||
512 | * transmitter detection run in bit banging mode for now. |
||
513 | */ |
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514 | intel_gmbus_force_bit(i2c, true); |
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515 | |||
516 | dvoinit = dvo->dev_ops->init(&intel_dvo->dev, i2c); |
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517 | |||
518 | intel_gmbus_force_bit(i2c, false); |
||
519 | |||
520 | if (!dvoinit) |
||
2330 | Serge | 521 | continue; |
522 | |||
523 | intel_encoder->type = INTEL_OUTPUT_DVO; |
||
524 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1); |
||
525 | switch (dvo->type) { |
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526 | case INTEL_DVO_CHIP_TMDS: |
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3031 | serge | 527 | intel_encoder->cloneable = true; |
2330 | Serge | 528 | drm_connector_init(dev, connector, |
529 | &intel_dvo_connector_funcs, |
||
530 | DRM_MODE_CONNECTOR_DVII); |
||
531 | encoder_type = DRM_MODE_ENCODER_TMDS; |
||
532 | break; |
||
533 | case INTEL_DVO_CHIP_LVDS: |
||
3031 | serge | 534 | intel_encoder->cloneable = false; |
2330 | Serge | 535 | drm_connector_init(dev, connector, |
536 | &intel_dvo_connector_funcs, |
||
537 | DRM_MODE_CONNECTOR_LVDS); |
||
538 | encoder_type = DRM_MODE_ENCODER_LVDS; |
||
539 | break; |
||
540 | } |
||
541 | |||
542 | drm_connector_helper_add(connector, |
||
543 | &intel_dvo_connector_helper_funcs); |
||
544 | connector->display_info.subpixel_order = SubPixelHorizontalRGB; |
||
545 | connector->interlace_allowed = false; |
||
546 | connector->doublescan_allowed = false; |
||
547 | |||
548 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
||
549 | if (dvo->type == INTEL_DVO_CHIP_LVDS) { |
||
550 | /* For our LVDS chipsets, we should hopefully be able |
||
551 | * to dig the fixed panel mode out of the BIOS data. |
||
552 | * However, it's in a different format from the BIOS |
||
553 | * data on chipsets with integrated LVDS (stored in AIM |
||
554 | * headers, likely), so for now, just get the current |
||
555 | * mode being output through DVO. |
||
556 | */ |
||
557 | intel_dvo->panel_fixed_mode = |
||
558 | intel_dvo_get_current_mode(connector); |
||
559 | intel_dvo->panel_wants_dither = true; |
||
560 | } |
||
561 | |||
562 | drm_sysfs_connector_add(connector); |
||
563 | return; |
||
564 | } |
||
565 | |||
566 | drm_encoder_cleanup(&intel_encoder->base); |
||
567 | kfree(intel_dvo); |
||
568 | kfree(intel_connector); |
||
569 | }><>><>>><>><>><>><> |