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Rev | Author | Line No. | Line |
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4560 | Serge | 1 | /* |
2 | * Copyright © 2013 Intel Corporation |
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3 | * |
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4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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5 | * copy of this software and associated documentation files (the "Software"), |
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6 | * to deal in the Software without restriction, including without limitation |
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7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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8 | * and/or sell copies of the Software, and to permit persons to whom the |
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9 | * Software is furnished to do so, subject to the following conditions: |
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10 | * |
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11 | * The above copyright notice and this permission notice (including the next |
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12 | * paragraph) shall be included in all copies or substantial portions of the |
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13 | * Software. |
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14 | * |
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15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
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21 | * DEALINGS IN THE SOFTWARE. |
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22 | * |
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23 | * Authors: |
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24 | * Shobhit Kumar |
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25 | * Yogesh Mohan Marimuthu |
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26 | */ |
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27 | |||
28 | #include |
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29 | #include "intel_drv.h" |
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30 | #include "i915_drv.h" |
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31 | #include "intel_dsi.h" |
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32 | |||
33 | #define DSI_HSS_PACKET_SIZE 4 |
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34 | #define DSI_HSE_PACKET_SIZE 4 |
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35 | #define DSI_HSA_PACKET_EXTRA_SIZE 6 |
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36 | #define DSI_HBP_PACKET_EXTRA_SIZE 6 |
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37 | #define DSI_HACTIVE_PACKET_EXTRA_SIZE 6 |
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38 | #define DSI_HFP_PACKET_EXTRA_SIZE 6 |
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39 | #define DSI_EOTP_PACKET_SIZE 4 |
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40 | |||
6084 | serge | 41 | static int dsi_pixel_format_bpp(int pixel_format) |
42 | { |
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43 | int bpp; |
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44 | |||
45 | switch (pixel_format) { |
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46 | default: |
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47 | case VID_MODE_FORMAT_RGB888: |
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48 | case VID_MODE_FORMAT_RGB666_LOOSE: |
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49 | bpp = 24; |
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50 | break; |
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51 | case VID_MODE_FORMAT_RGB666: |
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52 | bpp = 18; |
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53 | break; |
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54 | case VID_MODE_FORMAT_RGB565: |
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55 | bpp = 16; |
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56 | break; |
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57 | } |
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58 | |||
59 | return bpp; |
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60 | } |
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61 | |||
4560 | Serge | 62 | struct dsi_mnp { |
63 | u32 dsi_pll_ctrl; |
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64 | u32 dsi_pll_div; |
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65 | }; |
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66 | |||
67 | static const u32 lfsr_converts[] = { |
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68 | 426, 469, 234, 373, 442, 221, 110, 311, 411, /* 62 - 70 */ |
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69 | 461, 486, 243, 377, 188, 350, 175, 343, 427, 213, /* 71 - 80 */ |
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6084 | serge | 70 | 106, 53, 282, 397, 454, 227, 113, 56, 284, 142, /* 81 - 90 */ |
71 | 71, 35, 273, 136, 324, 418, 465, 488, 500, 506 /* 91 - 100 */ |
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4560 | Serge | 72 | }; |
73 | |||
74 | #ifdef DSI_CLK_FROM_RR |
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75 | |||
76 | static u32 dsi_rr_formula(const struct drm_display_mode *mode, |
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77 | int pixel_format, int video_mode_format, |
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78 | int lane_count, bool eotp) |
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79 | { |
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80 | u32 bpp; |
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81 | u32 hactive, vactive, hfp, hsync, hbp, vfp, vsync, vbp; |
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82 | u32 hsync_bytes, hbp_bytes, hactive_bytes, hfp_bytes; |
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83 | u32 bytes_per_line, bytes_per_frame; |
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84 | u32 num_frames; |
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85 | u32 bytes_per_x_frames, bytes_per_x_frames_x_lanes; |
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86 | u32 dsi_bit_clock_hz; |
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87 | u32 dsi_clk; |
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88 | |||
6084 | serge | 89 | bpp = dsi_pixel_format_bpp(pixel_format); |
4560 | Serge | 90 | |
91 | hactive = mode->hdisplay; |
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92 | vactive = mode->vdisplay; |
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93 | hfp = mode->hsync_start - mode->hdisplay; |
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94 | hsync = mode->hsync_end - mode->hsync_start; |
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95 | hbp = mode->htotal - mode->hsync_end; |
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96 | |||
97 | vfp = mode->vsync_start - mode->vdisplay; |
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98 | vsync = mode->vsync_end - mode->vsync_start; |
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99 | vbp = mode->vtotal - mode->vsync_end; |
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100 | |||
101 | hsync_bytes = DIV_ROUND_UP(hsync * bpp, 8); |
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102 | hbp_bytes = DIV_ROUND_UP(hbp * bpp, 8); |
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103 | hactive_bytes = DIV_ROUND_UP(hactive * bpp, 8); |
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104 | hfp_bytes = DIV_ROUND_UP(hfp * bpp, 8); |
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105 | |||
106 | bytes_per_line = DSI_HSS_PACKET_SIZE + hsync_bytes + |
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107 | DSI_HSA_PACKET_EXTRA_SIZE + DSI_HSE_PACKET_SIZE + |
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108 | hbp_bytes + DSI_HBP_PACKET_EXTRA_SIZE + |
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109 | hactive_bytes + DSI_HACTIVE_PACKET_EXTRA_SIZE + |
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110 | hfp_bytes + DSI_HFP_PACKET_EXTRA_SIZE; |
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111 | |||
112 | /* |
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113 | * XXX: Need to accurately calculate LP to HS transition timeout and add |
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114 | * it to bytes_per_line/bytes_per_frame. |
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115 | */ |
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116 | |||
117 | if (eotp && video_mode_format == VIDEO_MODE_BURST) |
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118 | bytes_per_line += DSI_EOTP_PACKET_SIZE; |
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119 | |||
120 | bytes_per_frame = vsync * bytes_per_line + vbp * bytes_per_line + |
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121 | vactive * bytes_per_line + vfp * bytes_per_line; |
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122 | |||
123 | if (eotp && |
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124 | (video_mode_format == VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE || |
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125 | video_mode_format == VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS)) |
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126 | bytes_per_frame += DSI_EOTP_PACKET_SIZE; |
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127 | |||
128 | num_frames = drm_mode_vrefresh(mode); |
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129 | bytes_per_x_frames = num_frames * bytes_per_frame; |
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130 | |||
131 | bytes_per_x_frames_x_lanes = bytes_per_x_frames / lane_count; |
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132 | |||
133 | /* the dsi clock is divided by 2 in the hardware to get dsi ddr clock */ |
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134 | dsi_bit_clock_hz = bytes_per_x_frames_x_lanes * 8; |
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135 | dsi_clk = dsi_bit_clock_hz / 1000; |
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136 | |||
137 | if (eotp && video_mode_format == VIDEO_MODE_BURST) |
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138 | dsi_clk *= 2; |
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139 | |||
140 | return dsi_clk; |
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141 | } |
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142 | |||
143 | #else |
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144 | |||
145 | /* Get DSI clock from pixel clock */ |
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5354 | serge | 146 | static u32 dsi_clk_from_pclk(u32 pclk, int pixel_format, int lane_count) |
4560 | Serge | 147 | { |
148 | u32 dsi_clk_khz; |
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6084 | serge | 149 | u32 bpp = dsi_pixel_format_bpp(pixel_format); |
4560 | Serge | 150 | |
151 | /* DSI data rate = pixel clock * bits per pixel / lane count |
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152 | pixel clock is converted from KHz to Hz */ |
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5354 | serge | 153 | dsi_clk_khz = DIV_ROUND_CLOSEST(pclk * bpp, lane_count); |
4560 | Serge | 154 | |
155 | return dsi_clk_khz; |
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156 | } |
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157 | |||
158 | #endif |
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159 | |||
6084 | serge | 160 | static int dsi_calc_mnp(struct drm_i915_private *dev_priv, |
161 | struct dsi_mnp *dsi_mnp, int target_dsi_clk) |
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4560 | Serge | 162 | { |
6084 | serge | 163 | unsigned int calc_m = 0, calc_p = 0; |
164 | unsigned int m_min, m_max, p_min = 2, p_max = 6; |
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165 | unsigned int m, n, p; |
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166 | int ref_clk; |
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167 | int delta = target_dsi_clk; |
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4560 | Serge | 168 | u32 m_seed; |
169 | |||
6084 | serge | 170 | /* target_dsi_clk is expected in kHz */ |
171 | if (target_dsi_clk < 300000 || target_dsi_clk > 1150000) { |
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4560 | Serge | 172 | DRM_ERROR("DSI CLK Out of Range\n"); |
173 | return -ECHRNG; |
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174 | } |
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175 | |||
6084 | serge | 176 | if (IS_CHERRYVIEW(dev_priv)) { |
177 | ref_clk = 100000; |
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178 | n = 4; |
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179 | m_min = 70; |
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180 | m_max = 96; |
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181 | } else { |
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182 | ref_clk = 25000; |
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183 | n = 1; |
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184 | m_min = 62; |
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185 | m_max = 92; |
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186 | } |
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4560 | Serge | 187 | |
6084 | serge | 188 | for (m = m_min; m <= m_max && delta; m++) { |
189 | for (p = p_min; p <= p_max && delta; p++) { |
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190 | /* |
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191 | * Find the optimal m and p divisors with minimal delta |
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192 | * +/- the required clock |
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193 | */ |
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194 | int calc_dsi_clk = (m * ref_clk) / (p * n); |
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195 | int d = abs(target_dsi_clk - calc_dsi_clk); |
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196 | if (d < delta) { |
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197 | delta = d; |
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4560 | Serge | 198 | calc_m = m; |
199 | calc_p = p; |
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200 | } |
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201 | } |
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202 | } |
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203 | |||
6084 | serge | 204 | /* register has log2(N1), this works fine for powers of two */ |
205 | n = ffs(n) - 1; |
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4560 | Serge | 206 | m_seed = lfsr_converts[calc_m - 62]; |
207 | dsi_mnp->dsi_pll_ctrl = 1 << (DSI_PLL_P1_POST_DIV_SHIFT + calc_p - 2); |
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6084 | serge | 208 | dsi_mnp->dsi_pll_div = n << DSI_PLL_N1_DIV_SHIFT | |
4560 | Serge | 209 | m_seed << DSI_PLL_M1_DIV_SHIFT; |
210 | |||
211 | return 0; |
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212 | } |
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213 | |||
214 | /* |
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215 | * XXX: The muxing and gating is hard coded for now. Need to add support for |
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216 | * sharing PLLs with two DSI outputs. |
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217 | */ |
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218 | static void vlv_configure_dsi_pll(struct intel_encoder *encoder) |
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219 | { |
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220 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
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221 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
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222 | int ret; |
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223 | struct dsi_mnp dsi_mnp; |
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224 | u32 dsi_clk; |
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225 | |||
5354 | serge | 226 | dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format, |
6084 | serge | 227 | intel_dsi->lane_count); |
4560 | Serge | 228 | |
6084 | serge | 229 | ret = dsi_calc_mnp(dev_priv, &dsi_mnp, dsi_clk); |
4560 | Serge | 230 | if (ret) { |
231 | DRM_DEBUG_KMS("dsi_calc_mnp failed\n"); |
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232 | return; |
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233 | } |
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234 | |||
6084 | serge | 235 | if (intel_dsi->ports & (1 << PORT_A)) |
236 | dsi_mnp.dsi_pll_ctrl |= DSI_PLL_CLK_GATE_DSI0_DSIPLL; |
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4560 | Serge | 237 | |
6084 | serge | 238 | if (intel_dsi->ports & (1 << PORT_C)) |
239 | dsi_mnp.dsi_pll_ctrl |= DSI_PLL_CLK_GATE_DSI1_DSIPLL; |
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240 | |||
4560 | Serge | 241 | DRM_DEBUG_KMS("dsi pll div %08x, ctrl %08x\n", |
242 | dsi_mnp.dsi_pll_div, dsi_mnp.dsi_pll_ctrl); |
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243 | |||
244 | vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, 0); |
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245 | vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_DIVIDER, dsi_mnp.dsi_pll_div); |
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246 | vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, dsi_mnp.dsi_pll_ctrl); |
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247 | } |
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248 | |||
6084 | serge | 249 | static void vlv_enable_dsi_pll(struct intel_encoder *encoder) |
4560 | Serge | 250 | { |
251 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
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252 | u32 tmp; |
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253 | |||
254 | DRM_DEBUG_KMS("\n"); |
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255 | |||
6084 | serge | 256 | mutex_lock(&dev_priv->sb_lock); |
4560 | Serge | 257 | |
258 | vlv_configure_dsi_pll(encoder); |
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259 | |||
260 | /* wait at least 0.5 us after ungating before enabling VCO */ |
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261 | usleep_range(1, 10); |
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262 | |||
263 | tmp = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); |
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264 | tmp |= DSI_PLL_VCO_EN; |
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265 | vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, tmp); |
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266 | |||
6084 | serge | 267 | if (wait_for(vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL) & |
268 | DSI_PLL_LOCK, 20)) { |
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4560 | Serge | 269 | |
6084 | serge | 270 | mutex_unlock(&dev_priv->sb_lock); |
4560 | Serge | 271 | DRM_ERROR("DSI PLL lock failed\n"); |
272 | return; |
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273 | } |
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6084 | serge | 274 | mutex_unlock(&dev_priv->sb_lock); |
4560 | Serge | 275 | |
276 | DRM_DEBUG_KMS("DSI PLL locked\n"); |
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277 | } |
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278 | |||
6084 | serge | 279 | static void vlv_disable_dsi_pll(struct intel_encoder *encoder) |
4560 | Serge | 280 | { |
281 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
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282 | u32 tmp; |
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283 | |||
284 | DRM_DEBUG_KMS("\n"); |
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285 | |||
6084 | serge | 286 | mutex_lock(&dev_priv->sb_lock); |
4560 | Serge | 287 | |
288 | tmp = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); |
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289 | tmp &= ~DSI_PLL_VCO_EN; |
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290 | tmp |= DSI_PLL_LDO_GATE; |
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291 | vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, tmp); |
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292 | |||
6084 | serge | 293 | mutex_unlock(&dev_priv->sb_lock); |
4560 | Serge | 294 | } |
5060 | serge | 295 | |
6084 | serge | 296 | static void bxt_disable_dsi_pll(struct intel_encoder *encoder) |
297 | { |
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298 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
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299 | u32 val; |
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300 | |||
301 | DRM_DEBUG_KMS("\n"); |
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302 | |||
303 | val = I915_READ(BXT_DSI_PLL_ENABLE); |
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304 | val &= ~BXT_DSI_PLL_DO_ENABLE; |
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305 | I915_WRITE(BXT_DSI_PLL_ENABLE, val); |
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306 | |||
307 | /* |
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308 | * PLL lock should deassert within 200us. |
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309 | * Wait up to 1ms before timing out. |
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310 | */ |
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311 | if (wait_for((I915_READ(BXT_DSI_PLL_ENABLE) |
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312 | & BXT_DSI_PLL_LOCKED) == 0, 1)) |
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313 | DRM_ERROR("Timeout waiting for PLL lock deassertion\n"); |
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314 | } |
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315 | |||
5060 | serge | 316 | static void assert_bpp_mismatch(int pixel_format, int pipe_bpp) |
317 | { |
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6084 | serge | 318 | int bpp = dsi_pixel_format_bpp(pixel_format); |
5060 | serge | 319 | |
320 | WARN(bpp != pipe_bpp, |
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6084 | serge | 321 | "bpp match assertion failure (expected %d, current %d)\n", |
322 | bpp, pipe_bpp); |
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5060 | serge | 323 | } |
324 | |||
325 | u32 vlv_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp) |
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326 | { |
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327 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
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328 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
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329 | u32 dsi_clock, pclk; |
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330 | u32 pll_ctl, pll_div; |
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6084 | serge | 331 | u32 m = 0, p = 0, n; |
5060 | serge | 332 | int refclk = 25000; |
333 | int i; |
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334 | |||
335 | DRM_DEBUG_KMS("\n"); |
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336 | |||
6084 | serge | 337 | mutex_lock(&dev_priv->sb_lock); |
5060 | serge | 338 | pll_ctl = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); |
339 | pll_div = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_DIVIDER); |
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6084 | serge | 340 | mutex_unlock(&dev_priv->sb_lock); |
5060 | serge | 341 | |
342 | /* mask out other bits and extract the P1 divisor */ |
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343 | pll_ctl &= DSI_PLL_P1_POST_DIV_MASK; |
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344 | pll_ctl = pll_ctl >> (DSI_PLL_P1_POST_DIV_SHIFT - 2); |
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345 | |||
6084 | serge | 346 | /* N1 divisor */ |
347 | n = (pll_div & DSI_PLL_N1_DIV_MASK) >> DSI_PLL_N1_DIV_SHIFT; |
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348 | n = 1 << n; /* register has log2(N1) */ |
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349 | |||
5060 | serge | 350 | /* mask out the other bits and extract the M1 divisor */ |
351 | pll_div &= DSI_PLL_M1_DIV_MASK; |
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352 | pll_div = pll_div >> DSI_PLL_M1_DIV_SHIFT; |
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353 | |||
354 | while (pll_ctl) { |
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355 | pll_ctl = pll_ctl >> 1; |
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356 | p++; |
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357 | } |
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358 | p--; |
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359 | |||
360 | if (!p) { |
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361 | DRM_ERROR("wrong P1 divisor\n"); |
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362 | return 0; |
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363 | } |
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364 | |||
365 | for (i = 0; i < ARRAY_SIZE(lfsr_converts); i++) { |
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366 | if (lfsr_converts[i] == pll_div) |
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367 | break; |
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368 | } |
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369 | |||
370 | if (i == ARRAY_SIZE(lfsr_converts)) { |
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371 | DRM_ERROR("wrong m_seed programmed\n"); |
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372 | return 0; |
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373 | } |
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374 | |||
375 | m = i + 62; |
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376 | |||
6084 | serge | 377 | dsi_clock = (m * refclk) / (p * n); |
5060 | serge | 378 | |
379 | /* pixel_format and pipe_bpp should agree */ |
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380 | assert_bpp_mismatch(intel_dsi->pixel_format, pipe_bpp); |
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381 | |||
382 | pclk = DIV_ROUND_CLOSEST(dsi_clock * intel_dsi->lane_count, pipe_bpp); |
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383 | |||
384 | return pclk; |
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385 | } |
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6084 | serge | 386 | |
387 | u32 bxt_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp) |
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388 | { |
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389 | u32 pclk; |
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390 | u32 dsi_clk; |
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391 | u32 dsi_ratio; |
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392 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
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393 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
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394 | |||
395 | /* Divide by zero */ |
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396 | if (!pipe_bpp) { |
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397 | DRM_ERROR("Invalid BPP(0)\n"); |
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398 | return 0; |
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399 | } |
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400 | |||
401 | dsi_ratio = I915_READ(BXT_DSI_PLL_CTL) & |
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402 | BXT_DSI_PLL_RATIO_MASK; |
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403 | |||
404 | /* Invalid DSI ratio ? */ |
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405 | if (dsi_ratio < BXT_DSI_PLL_RATIO_MIN || |
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406 | dsi_ratio > BXT_DSI_PLL_RATIO_MAX) { |
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407 | DRM_ERROR("Invalid DSI pll ratio(%u) programmed\n", dsi_ratio); |
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408 | return 0; |
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409 | } |
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410 | |||
411 | dsi_clk = (dsi_ratio * BXT_REF_CLOCK_KHZ) / 2; |
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412 | |||
413 | /* pixel_format and pipe_bpp should agree */ |
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414 | assert_bpp_mismatch(intel_dsi->pixel_format, pipe_bpp); |
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415 | |||
416 | pclk = DIV_ROUND_CLOSEST(dsi_clk * intel_dsi->lane_count, pipe_bpp); |
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417 | |||
418 | DRM_DEBUG_DRIVER("Calculated pclk=%u\n", pclk); |
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419 | return pclk; |
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420 | } |
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421 | |||
422 | static void vlv_dsi_reset_clocks(struct intel_encoder *encoder, enum port port) |
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423 | { |
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424 | u32 temp; |
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425 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
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426 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
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427 | |||
428 | temp = I915_READ(MIPI_CTRL(port)); |
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429 | temp &= ~ESCAPE_CLOCK_DIVIDER_MASK; |
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430 | I915_WRITE(MIPI_CTRL(port), temp | |
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431 | intel_dsi->escape_clk_div << |
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432 | ESCAPE_CLOCK_DIVIDER_SHIFT); |
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433 | } |
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434 | |||
435 | /* Program BXT Mipi clocks and dividers */ |
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436 | static void bxt_dsi_program_clocks(struct drm_device *dev, enum port port) |
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437 | { |
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438 | u32 tmp; |
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439 | u32 divider; |
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440 | u32 dsi_rate; |
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441 | u32 pll_ratio; |
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442 | struct drm_i915_private *dev_priv = dev->dev_private; |
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443 | |||
444 | /* Clear old configurations */ |
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445 | tmp = I915_READ(BXT_MIPI_CLOCK_CTL); |
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446 | tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port)); |
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447 | tmp &= ~(BXT_MIPI_RX_ESCLK_FIXDIV_MASK(port)); |
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448 | tmp &= ~(BXT_MIPI_ESCLK_VAR_DIV_MASK(port)); |
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449 | tmp &= ~(BXT_MIPI_DPHY_DIVIDER_MASK(port)); |
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450 | |||
451 | /* Get the current DSI rate(actual) */ |
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452 | pll_ratio = I915_READ(BXT_DSI_PLL_CTL) & |
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453 | BXT_DSI_PLL_RATIO_MASK; |
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454 | dsi_rate = (BXT_REF_CLOCK_KHZ * pll_ratio) / 2; |
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455 | |||
456 | /* Max possible output of clock is 39.5 MHz, program value -1 */ |
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457 | divider = (dsi_rate / BXT_MAX_VAR_OUTPUT_KHZ) - 1; |
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458 | tmp |= BXT_MIPI_ESCLK_VAR_DIV(port, divider); |
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459 | |||
460 | /* |
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461 | * Tx escape clock must be as close to 20MHz possible, but should |
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462 | * not exceed it. Hence select divide by 2 |
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463 | */ |
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464 | tmp |= BXT_MIPI_TX_ESCLK_8XDIV_BY2(port); |
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465 | |||
466 | tmp |= BXT_MIPI_RX_ESCLK_8X_BY3(port); |
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467 | |||
468 | I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp); |
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469 | } |
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470 | |||
471 | static bool bxt_configure_dsi_pll(struct intel_encoder *encoder) |
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472 | { |
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473 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
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474 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
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475 | u8 dsi_ratio; |
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476 | u32 dsi_clk; |
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477 | u32 val; |
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478 | |||
479 | dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format, |
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480 | intel_dsi->lane_count); |
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481 | |||
482 | /* |
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483 | * From clock diagram, to get PLL ratio divider, divide double of DSI |
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484 | * link rate (i.e., 2*8x=16x frequency value) by ref clock. Make sure to |
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485 | * round 'up' the result |
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486 | */ |
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487 | dsi_ratio = DIV_ROUND_UP(dsi_clk * 2, BXT_REF_CLOCK_KHZ); |
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488 | if (dsi_ratio < BXT_DSI_PLL_RATIO_MIN || |
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489 | dsi_ratio > BXT_DSI_PLL_RATIO_MAX) { |
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490 | DRM_ERROR("Cant get a suitable ratio from DSI PLL ratios\n"); |
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491 | return false; |
||
492 | } |
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493 | |||
494 | /* |
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495 | * Program DSI ratio and Select MIPIC and MIPIA PLL output as 8x |
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496 | * Spec says both have to be programmed, even if one is not getting |
||
497 | * used. Configure MIPI_CLOCK_CTL dividers in modeset |
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498 | */ |
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499 | val = I915_READ(BXT_DSI_PLL_CTL); |
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500 | val &= ~BXT_DSI_PLL_PVD_RATIO_MASK; |
||
501 | val &= ~BXT_DSI_FREQ_SEL_MASK; |
||
502 | val &= ~BXT_DSI_PLL_RATIO_MASK; |
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503 | val |= (dsi_ratio | BXT_DSIA_16X_BY2 | BXT_DSIC_16X_BY2); |
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504 | |||
505 | /* As per recommendation from hardware team, |
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506 | * Prog PVD ratio =1 if dsi ratio <= 50 |
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507 | */ |
||
508 | if (dsi_ratio <= 50) { |
||
509 | val &= ~BXT_DSI_PLL_PVD_RATIO_MASK; |
||
510 | val |= BXT_DSI_PLL_PVD_RATIO_1; |
||
511 | } |
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512 | |||
513 | I915_WRITE(BXT_DSI_PLL_CTL, val); |
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514 | POSTING_READ(BXT_DSI_PLL_CTL); |
||
515 | |||
516 | return true; |
||
517 | } |
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518 | |||
519 | static void bxt_enable_dsi_pll(struct intel_encoder *encoder) |
||
520 | { |
||
521 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
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522 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
||
523 | enum port port; |
||
524 | u32 val; |
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525 | |||
526 | DRM_DEBUG_KMS("\n"); |
||
527 | |||
528 | val = I915_READ(BXT_DSI_PLL_ENABLE); |
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529 | |||
530 | if (val & BXT_DSI_PLL_DO_ENABLE) { |
||
531 | WARN(1, "DSI PLL already enabled. Disabling it.\n"); |
||
532 | val &= ~BXT_DSI_PLL_DO_ENABLE; |
||
533 | I915_WRITE(BXT_DSI_PLL_ENABLE, val); |
||
534 | } |
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535 | |||
536 | /* Configure PLL vales */ |
||
537 | if (!bxt_configure_dsi_pll(encoder)) { |
||
538 | DRM_ERROR("Configure DSI PLL failed, abort PLL enable\n"); |
||
539 | return; |
||
540 | } |
||
541 | |||
542 | /* Program TX, RX, Dphy clocks */ |
||
543 | for_each_dsi_port(port, intel_dsi->ports) |
||
544 | bxt_dsi_program_clocks(encoder->base.dev, port); |
||
545 | |||
546 | /* Enable DSI PLL */ |
||
547 | val = I915_READ(BXT_DSI_PLL_ENABLE); |
||
548 | val |= BXT_DSI_PLL_DO_ENABLE; |
||
549 | I915_WRITE(BXT_DSI_PLL_ENABLE, val); |
||
550 | |||
551 | /* Timeout and fail if PLL not locked */ |
||
552 | if (wait_for(I915_READ(BXT_DSI_PLL_ENABLE) & BXT_DSI_PLL_LOCKED, 1)) { |
||
553 | DRM_ERROR("Timed out waiting for DSI PLL to lock\n"); |
||
554 | return; |
||
555 | } |
||
556 | |||
557 | DRM_DEBUG_KMS("DSI PLL locked\n"); |
||
558 | } |
||
559 | |||
560 | void intel_enable_dsi_pll(struct intel_encoder *encoder) |
||
561 | { |
||
562 | struct drm_device *dev = encoder->base.dev; |
||
563 | |||
564 | if (IS_VALLEYVIEW(dev)) |
||
565 | vlv_enable_dsi_pll(encoder); |
||
566 | else if (IS_BROXTON(dev)) |
||
567 | bxt_enable_dsi_pll(encoder); |
||
568 | } |
||
569 | |||
570 | void intel_disable_dsi_pll(struct intel_encoder *encoder) |
||
571 | { |
||
572 | struct drm_device *dev = encoder->base.dev; |
||
573 | |||
574 | if (IS_VALLEYVIEW(dev)) |
||
575 | vlv_disable_dsi_pll(encoder); |
||
576 | else if (IS_BROXTON(dev)) |
||
577 | bxt_disable_dsi_pll(encoder); |
||
578 | } |
||
579 | |||
580 | static void bxt_dsi_reset_clocks(struct intel_encoder *encoder, enum port port) |
||
581 | { |
||
582 | u32 tmp; |
||
583 | struct drm_device *dev = encoder->base.dev; |
||
584 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
585 | |||
586 | /* Clear old configurations */ |
||
587 | tmp = I915_READ(BXT_MIPI_CLOCK_CTL); |
||
588 | tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port)); |
||
589 | tmp &= ~(BXT_MIPI_RX_ESCLK_FIXDIV_MASK(port)); |
||
590 | tmp &= ~(BXT_MIPI_ESCLK_VAR_DIV_MASK(port)); |
||
591 | tmp &= ~(BXT_MIPI_DPHY_DIVIDER_MASK(port)); |
||
592 | I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp); |
||
593 | I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP); |
||
594 | } |
||
595 | |||
596 | void intel_dsi_reset_clocks(struct intel_encoder *encoder, enum port port) |
||
597 | { |
||
598 | struct drm_device *dev = encoder->base.dev; |
||
599 | |||
600 | if (IS_BROXTON(dev)) |
||
601 | bxt_dsi_reset_clocks(encoder, port); |
||
602 | else if (IS_VALLEYVIEW(dev)) |
||
603 | vlv_dsi_reset_clocks(encoder, port); |
||
604 | }=>=>> |