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Rev | Author | Line No. | Line |
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2326 | Serge | 1 | /* |
2 | * Copyright (c) 2006 Dave Airlie |
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3 | * Copyright (c) 2007-2008 Intel Corporation |
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4 | * Jesse Barnes |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the "Software"), |
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8 | * to deal in the Software without restriction, including without limitation |
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9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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10 | * and/or sell copies of the Software, and to permit persons to whom the |
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11 | * Software is furnished to do so, subject to the following conditions: |
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12 | * |
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13 | * The above copyright notice and this permission notice (including the next |
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14 | * paragraph) shall be included in all copies or substantial portions of the |
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15 | * Software. |
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16 | * |
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17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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22 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
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23 | * IN THE SOFTWARE. |
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24 | */ |
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25 | #ifndef __INTEL_DRV_H__ |
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26 | #define __INTEL_DRV_H__ |
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27 | |||
28 | #include |
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4104 | Serge | 29 | #include |
3031 | serge | 30 | #include |
2326 | Serge | 31 | #include "i915_drv.h" |
3031 | serge | 32 | #include |
33 | #include |
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34 | #include |
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5060 | serge | 35 | #include |
2326 | Serge | 36 | |
3482 | Serge | 37 | #define KBUILD_MODNAME "i915.dll" |
38 | |||
3746 | Serge | 39 | |
3031 | serge | 40 | #define cpu_relax() asm volatile("rep; nop") |
41 | |||
3746 | Serge | 42 | /** |
43 | * _wait_for - magic (register) wait macro |
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44 | * |
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45 | * Does the right thing for modeset paths when run under kdgb or similar atomic |
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46 | * contexts. Note that it's important that we check the condition again after |
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47 | * having timed out, since the timeout could be due to preemption or similar and |
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48 | * we've never had a chance to check the condition before the timeout. |
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49 | */ |
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2326 | Serge | 50 | #define _wait_for(COND, MS, W) ({ \ |
5060 | serge | 51 | unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \ |
2326 | Serge | 52 | int ret__ = 0; \ |
2342 | Serge | 53 | while (!(COND)) { \ |
5060 | serge | 54 | if (time_after(jiffies, timeout__)) { \ |
3746 | Serge | 55 | if (!(COND)) \ |
2326 | Serge | 56 | ret__ = -ETIMEDOUT; \ |
57 | break; \ |
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58 | } \ |
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3031 | serge | 59 | if (W ) { \ |
60 | msleep(W); \ |
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61 | } else { \ |
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62 | cpu_relax(); \ |
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63 | } \ |
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2326 | Serge | 64 | } \ |
65 | ret__; \ |
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66 | }) |
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67 | |||
68 | #define wait_for(COND, MS) _wait_for(COND, MS, 1) |
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69 | #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0) |
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4104 | Serge | 70 | #define wait_for_atomic_us(COND, US) _wait_for((COND), \ |
71 | DIV_ROUND_UP((US), 1000), 0) |
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2326 | Serge | 72 | |
4560 | Serge | 73 | #define KHz(x) (1000 * (x)) |
74 | #define MHz(x) KHz(1000 * (x)) |
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2326 | Serge | 75 | |
76 | /* |
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77 | * Display related stuff |
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78 | */ |
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79 | |||
80 | /* store information about an Ixxx DVO */ |
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81 | /* The i830->i865 use multiple DVOs with multiple i2cs */ |
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82 | /* the i915, i945 have a single sDVO i2c bus - which is different */ |
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83 | #define MAX_OUTPUTS 6 |
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84 | /* maximum connectors per crtcs in the mode set */ |
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85 | |||
5060 | serge | 86 | /* Maximum cursor sizes */ |
87 | #define GEN2_CURSOR_WIDTH 64 |
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88 | #define GEN2_CURSOR_HEIGHT 64 |
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89 | #define MAX_CURSOR_WIDTH 256 |
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90 | #define MAX_CURSOR_HEIGHT 256 |
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91 | |||
2326 | Serge | 92 | #define INTEL_I2C_BUS_DVO 1 |
93 | #define INTEL_I2C_BUS_SDVO 2 |
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94 | |||
95 | /* these are outputs from the chip - integrated only |
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96 | external chips are via DVO or SDVO output */ |
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97 | #define INTEL_OUTPUT_UNUSED 0 |
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98 | #define INTEL_OUTPUT_ANALOG 1 |
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99 | #define INTEL_OUTPUT_DVO 2 |
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100 | #define INTEL_OUTPUT_SDVO 3 |
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101 | #define INTEL_OUTPUT_LVDS 4 |
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102 | #define INTEL_OUTPUT_TVOUT 5 |
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103 | #define INTEL_OUTPUT_HDMI 6 |
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104 | #define INTEL_OUTPUT_DISPLAYPORT 7 |
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105 | #define INTEL_OUTPUT_EDP 8 |
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4560 | Serge | 106 | #define INTEL_OUTPUT_DSI 9 |
107 | #define INTEL_OUTPUT_UNKNOWN 10 |
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5060 | serge | 108 | #define INTEL_OUTPUT_DP_MST 11 |
2326 | Serge | 109 | |
110 | #define INTEL_DVO_CHIP_NONE 0 |
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111 | #define INTEL_DVO_CHIP_LVDS 1 |
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112 | #define INTEL_DVO_CHIP_TMDS 2 |
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113 | #define INTEL_DVO_CHIP_TVOUT 4 |
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114 | |||
5060 | serge | 115 | #define INTEL_DSI_VIDEO_MODE 0 |
116 | #define INTEL_DSI_COMMAND_MODE 1 |
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4560 | Serge | 117 | |
2326 | Serge | 118 | struct intel_framebuffer { |
119 | struct drm_framebuffer base; |
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120 | struct drm_i915_gem_object *obj; |
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121 | }; |
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122 | |||
123 | struct intel_fbdev { |
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124 | struct drm_fb_helper helper; |
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5060 | serge | 125 | struct intel_framebuffer *fb; |
2326 | Serge | 126 | struct list_head fbdev_list; |
127 | struct drm_display_mode *our_mode; |
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5060 | serge | 128 | int preferred_bpp; |
2326 | Serge | 129 | }; |
130 | |||
131 | struct intel_encoder { |
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132 | struct drm_encoder base; |
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3031 | serge | 133 | /* |
134 | * The new crtc this encoder will be driven from. Only differs from |
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135 | * base->crtc while a modeset is in progress. |
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136 | */ |
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137 | struct intel_crtc *new_crtc; |
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138 | |||
2326 | Serge | 139 | int type; |
5060 | serge | 140 | unsigned int cloneable; |
3031 | serge | 141 | bool connectors_active; |
2326 | Serge | 142 | void (*hot_plug)(struct intel_encoder *); |
3746 | Serge | 143 | bool (*compute_config)(struct intel_encoder *, |
144 | struct intel_crtc_config *); |
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3480 | Serge | 145 | void (*pre_pll_enable)(struct intel_encoder *); |
3031 | serge | 146 | void (*pre_enable)(struct intel_encoder *); |
147 | void (*enable)(struct intel_encoder *); |
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3746 | Serge | 148 | void (*mode_set)(struct intel_encoder *intel_encoder); |
3031 | serge | 149 | void (*disable)(struct intel_encoder *); |
150 | void (*post_disable)(struct intel_encoder *); |
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151 | /* Read out the current hw state of this connector, returning true if |
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152 | * the encoder is active. If the encoder is enabled it also set the pipe |
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153 | * it is connected to in the pipe parameter. */ |
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154 | bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe); |
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4104 | Serge | 155 | /* Reconstructs the equivalent mode flags for the current hardware |
156 | * state. This must be called _after_ display->get_pipe_config has |
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157 | * pre-filled the pipe config. Note that intel_encoder->base.crtc must |
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158 | * be set correctly before calling this function. */ |
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159 | void (*get_config)(struct intel_encoder *, |
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160 | struct intel_crtc_config *pipe_config); |
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5060 | serge | 161 | /* |
162 | * Called during system suspend after all pending requests for the |
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163 | * encoder are flushed (for example for DP AUX transactions) and |
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164 | * device interrupts are disabled. |
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165 | */ |
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166 | void (*suspend)(struct intel_encoder *); |
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2326 | Serge | 167 | int crtc_mask; |
3746 | Serge | 168 | enum hpd_pin hpd_pin; |
2326 | Serge | 169 | }; |
170 | |||
3243 | Serge | 171 | struct intel_panel { |
172 | struct drm_display_mode *fixed_mode; |
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4560 | Serge | 173 | struct drm_display_mode *downclock_mode; |
3243 | Serge | 174 | int fitting_mode; |
4560 | Serge | 175 | |
176 | /* backlight */ |
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177 | struct { |
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178 | bool present; |
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179 | u32 level; |
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5060 | serge | 180 | u32 min; |
4560 | Serge | 181 | u32 max; |
182 | bool enabled; |
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183 | bool combination_mode; /* gen 2/4 only */ |
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184 | bool active_low_pwm; |
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185 | struct backlight_device *device; |
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186 | } backlight; |
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3243 | Serge | 187 | }; |
188 | |||
2326 | Serge | 189 | struct intel_connector { |
190 | struct drm_connector base; |
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3031 | serge | 191 | /* |
192 | * The fixed encoder this connector is connected to. |
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193 | */ |
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2326 | Serge | 194 | struct intel_encoder *encoder; |
3031 | serge | 195 | |
196 | /* |
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197 | * The new encoder this connector will be driven. Only differs from |
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198 | * encoder while a modeset is in progress. |
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199 | */ |
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200 | struct intel_encoder *new_encoder; |
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201 | |||
202 | /* Reads out the current hw, returning true if the connector is enabled |
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203 | * and active (i.e. dpms ON state). */ |
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204 | bool (*get_hw_state)(struct intel_connector *); |
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3243 | Serge | 205 | |
5060 | serge | 206 | /* |
207 | * Removes all interfaces through which the connector is accessible |
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208 | * - like sysfs, debugfs entries -, so that no new operations can be |
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209 | * started on the connector. Also makes sure all currently pending |
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210 | * operations finish before returing. |
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211 | */ |
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212 | void (*unregister)(struct intel_connector *); |
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213 | |||
3243 | Serge | 214 | /* Panel info for eDP and LVDS */ |
215 | struct intel_panel panel; |
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216 | |||
217 | /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */ |
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218 | struct edid *edid; |
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3746 | Serge | 219 | |
220 | /* since POLL and HPD connectors may use the same HPD line keep the native |
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221 | state of connector->polled in case hotplug storm detection changes it */ |
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222 | u8 polled; |
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5060 | serge | 223 | |
224 | void *port; /* store this opaque as its illegal to dereference it */ |
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225 | |||
226 | struct intel_dp *mst_port; |
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2326 | Serge | 227 | }; |
228 | |||
4104 | Serge | 229 | typedef struct dpll { |
230 | /* given values */ |
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231 | int n; |
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232 | int m1, m2; |
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233 | int p1, p2; |
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234 | /* derived values */ |
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235 | int dot; |
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236 | int vco; |
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237 | int m; |
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238 | int p; |
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239 | } intel_clock_t; |
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240 | |||
5060 | serge | 241 | struct intel_plane_config { |
242 | bool tiled; |
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243 | int size; |
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244 | u32 base; |
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245 | }; |
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246 | |||
3746 | Serge | 247 | struct intel_crtc_config { |
4104 | Serge | 248 | /** |
249 | * quirks - bitfield with hw state readout quirks |
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250 | * |
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251 | * For various reasons the hw state readout code might not be able to |
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252 | * completely faithfully read out the current state. These cases are |
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253 | * tracked with quirk flags so that fastboot and state checker can act |
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254 | * accordingly. |
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255 | */ |
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256 | #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */ |
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5060 | serge | 257 | #define PIPE_CONFIG_QUIRK_INHERITED_MODE (1<<1) /* mode inherited from firmware */ |
4104 | Serge | 258 | unsigned long quirks; |
259 | |||
4560 | Serge | 260 | /* User requested mode, only valid as a starting point to |
261 | * compute adjusted_mode, except in the case of (S)DVO where |
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262 | * it's also for the output timings of the (S)DVO chip. |
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263 | * adjusted_mode will then correspond to the S(DVO) chip's |
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264 | * preferred input timings. */ |
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3746 | Serge | 265 | struct drm_display_mode requested_mode; |
4560 | Serge | 266 | /* Actual pipe timings ie. what we program into the pipe timing |
267 | * registers. adjusted_mode.crtc_clock is the pipe pixel clock. */ |
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3746 | Serge | 268 | struct drm_display_mode adjusted_mode; |
4560 | Serge | 269 | |
270 | /* Pipe source size (ie. panel fitter input size) |
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271 | * All planes will be positioned inside this space, |
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272 | * and get clipped at the edges. */ |
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273 | int pipe_src_w, pipe_src_h; |
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274 | |||
3746 | Serge | 275 | /* Whether to set up the PCH/FDI. Note that we never allow sharing |
276 | * between pch encoders and cpu encoders. */ |
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277 | bool has_pch_encoder; |
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278 | |||
279 | /* CPU Transcoder for the pipe. Currently this can only differ from the |
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280 | * pipe on Haswell (where we have a special eDP transcoder). */ |
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281 | enum transcoder cpu_transcoder; |
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282 | |||
283 | /* |
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284 | * Use reduced/limited/broadcast rbg range, compressing from the full |
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285 | * range fed into the crtcs. |
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286 | */ |
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287 | bool limited_color_range; |
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288 | |||
289 | /* DP has a bunch of special case unfortunately, so mark the pipe |
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290 | * accordingly. */ |
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291 | bool has_dp_encoder; |
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4104 | Serge | 292 | |
5060 | serge | 293 | /* Whether we should send NULL infoframes. Required for audio. */ |
294 | bool has_hdmi_sink; |
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295 | |||
296 | /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or |
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297 | * has_dp_encoder is set. */ |
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298 | bool has_audio; |
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299 | |||
4104 | Serge | 300 | /* |
301 | * Enable dithering, used when the selected pipe bpp doesn't match the |
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302 | * plane bpp. |
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303 | */ |
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3746 | Serge | 304 | bool dither; |
305 | |||
306 | /* Controls for the clock computation, to override various stages. */ |
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307 | bool clock_set; |
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308 | |||
4104 | Serge | 309 | /* SDVO TV has a bunch of special case. To make multifunction encoders |
310 | * work correctly, we need to track this at runtime.*/ |
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311 | bool sdvo_tv_clock; |
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312 | |||
313 | /* |
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314 | * crtc bandwidth limit, don't increase pipe bpp or clock if not really |
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315 | * required. This is set in the 2nd loop of calling encoder's |
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316 | * ->compute_config if the first pick doesn't work out. |
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317 | */ |
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318 | bool bw_constrained; |
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319 | |||
3746 | Serge | 320 | /* Settings for the intel dpll used on pretty much everything but |
321 | * haswell. */ |
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4104 | Serge | 322 | struct dpll dpll; |
3746 | Serge | 323 | |
4104 | Serge | 324 | /* Selected dpll when shared or DPLL_ID_PRIVATE. */ |
325 | enum intel_dpll_id shared_dpll; |
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326 | |||
5060 | serge | 327 | /* PORT_CLK_SEL for DDI ports. */ |
328 | uint32_t ddi_pll_sel; |
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329 | |||
4104 | Serge | 330 | /* Actual register state of the dpll, for shared dpll cross-checking. */ |
331 | struct intel_dpll_hw_state dpll_hw_state; |
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332 | |||
3746 | Serge | 333 | int pipe_bpp; |
334 | struct intel_link_m_n dp_m_n; |
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4104 | Serge | 335 | |
5060 | serge | 336 | /* m2_n2 for eDP downclock */ |
337 | struct intel_link_m_n dp_m2_n2; |
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338 | |||
4104 | Serge | 339 | /* |
340 | * Frequence the dpll for the port should run at. Differs from the |
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4560 | Serge | 341 | * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also |
342 | * already multiplied by pixel_multiplier. |
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3746 | Serge | 343 | */ |
4104 | Serge | 344 | int port_clock; |
345 | |||
3746 | Serge | 346 | /* Used by SDVO (and if we ever fix it, HDMI). */ |
347 | unsigned pixel_multiplier; |
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4104 | Serge | 348 | |
349 | /* Panel fitter controls for gen2-gen4 + VLV */ |
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350 | struct { |
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351 | u32 control; |
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352 | u32 pgm_ratios; |
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353 | u32 lvds_border_bits; |
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354 | } gmch_pfit; |
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355 | |||
356 | /* Panel fitter placement and size for Ironlake+ */ |
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357 | struct { |
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358 | u32 pos; |
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359 | u32 size; |
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360 | bool enabled; |
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5060 | serge | 361 | bool force_thru; |
4104 | Serge | 362 | } pch_pfit; |
363 | |||
364 | /* FDI configuration, only valid if has_pch_encoder is set. */ |
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365 | int fdi_lanes; |
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366 | struct intel_link_m_n fdi_m_n; |
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367 | |||
368 | bool ips_enabled; |
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4560 | Serge | 369 | |
370 | bool double_wide; |
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5060 | serge | 371 | |
372 | bool dp_encoder_is_mst; |
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373 | int pbn; |
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3746 | Serge | 374 | }; |
375 | |||
4560 | Serge | 376 | struct intel_pipe_wm { |
377 | struct intel_wm_level wm[5]; |
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378 | uint32_t linetime; |
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379 | bool fbc_wm_enabled; |
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5060 | serge | 380 | bool pipe_enabled; |
381 | bool sprites_enabled; |
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382 | bool sprites_scaled; |
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4560 | Serge | 383 | }; |
384 | |||
5060 | serge | 385 | struct intel_mmio_flip { |
386 | u32 seqno; |
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387 | u32 ring_id; |
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388 | }; |
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389 | |||
2326 | Serge | 390 | struct intel_crtc { |
391 | struct drm_crtc base; |
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392 | enum pipe pipe; |
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393 | enum plane plane; |
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394 | u8 lut_r[256], lut_g[256], lut_b[256]; |
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3031 | serge | 395 | /* |
396 | * Whether the crtc and the connected output pipeline is active. Implies |
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397 | * that crtc->enabled is set, i.e. the current mode configuration has |
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398 | * some outputs connected to this crtc. |
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399 | */ |
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400 | bool active; |
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4560 | Serge | 401 | unsigned long enabled_power_domains; |
402 | bool primary_enabled; /* is the primary plane (partially) visible? */ |
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2326 | Serge | 403 | bool lowfreq_avail; |
404 | struct intel_overlay *overlay; |
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405 | struct intel_unpin_work *unpin_work; |
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406 | |||
3243 | Serge | 407 | atomic_t unpin_work_count; |
408 | |||
3031 | serge | 409 | /* Display surface base address adjustement for pageflips. Note that on |
410 | * gen4+ this only adjusts up to a tile, offsets within a tile are |
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411 | * handled in the hw itself (with the TILEOFF register). */ |
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412 | unsigned long dspaddr_offset; |
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413 | |||
2326 | Serge | 414 | struct drm_i915_gem_object *cursor_bo; |
415 | uint32_t cursor_addr; |
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416 | int16_t cursor_width, cursor_height; |
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5060 | serge | 417 | uint32_t cursor_cntl; |
418 | uint32_t cursor_base; |
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2342 | Serge | 419 | |
5060 | serge | 420 | struct intel_plane_config plane_config; |
3746 | Serge | 421 | struct intel_crtc_config config; |
5060 | serge | 422 | struct intel_crtc_config *new_config; |
423 | bool new_enabled; |
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3746 | Serge | 424 | |
3480 | Serge | 425 | /* reset counter value when the last flip was submitted */ |
426 | unsigned int reset_counter; |
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4104 | Serge | 427 | |
428 | /* Access to these should be protected by dev_priv->irq_lock. */ |
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429 | bool cpu_fifo_underrun_disabled; |
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430 | bool pch_fifo_underrun_disabled; |
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4560 | Serge | 431 | |
432 | /* per-pipe watermark state */ |
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433 | struct { |
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434 | /* watermarks currently being used */ |
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435 | struct intel_pipe_wm active; |
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436 | } wm; |
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5060 | serge | 437 | |
438 | wait_queue_head_t vbl_wait; |
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439 | |||
440 | int scanline_offset; |
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2326 | Serge | 441 | }; |
442 | |||
4104 | Serge | 443 | struct intel_plane_wm_parameters { |
444 | uint32_t horiz_pixels; |
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5060 | serge | 445 | uint32_t vert_pixels; |
4104 | Serge | 446 | uint8_t bytes_per_pixel; |
447 | bool enabled; |
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448 | bool scaled; |
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449 | }; |
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450 | |||
2342 | Serge | 451 | struct intel_plane { |
452 | struct drm_plane base; |
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3746 | Serge | 453 | int plane; |
2342 | Serge | 454 | enum pipe pipe; |
455 | struct drm_i915_gem_object *obj; |
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3243 | Serge | 456 | bool can_scale; |
2342 | Serge | 457 | int max_downscale; |
3746 | Serge | 458 | int crtc_x, crtc_y; |
459 | unsigned int crtc_w, crtc_h; |
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460 | uint32_t src_x, src_y; |
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461 | uint32_t src_w, src_h; |
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4104 | Serge | 462 | |
463 | /* Since we need to change the watermarks before/after |
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464 | * enabling/disabling the planes, we need to store the parameters here |
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465 | * as the other pieces of the struct may not reflect the values we want |
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466 | * for the watermark calculations. Currently only Haswell uses this. |
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467 | */ |
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468 | struct intel_plane_wm_parameters wm; |
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469 | |||
2342 | Serge | 470 | void (*update_plane)(struct drm_plane *plane, |
4104 | Serge | 471 | struct drm_crtc *crtc, |
2342 | Serge | 472 | struct drm_framebuffer *fb, |
473 | struct drm_i915_gem_object *obj, |
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474 | int crtc_x, int crtc_y, |
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475 | unsigned int crtc_w, unsigned int crtc_h, |
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476 | uint32_t x, uint32_t y, |
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477 | uint32_t src_w, uint32_t src_h); |
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4104 | Serge | 478 | void (*disable_plane)(struct drm_plane *plane, |
479 | struct drm_crtc *crtc); |
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2342 | Serge | 480 | int (*update_colorkey)(struct drm_plane *plane, |
481 | struct drm_intel_sprite_colorkey *key); |
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482 | void (*get_colorkey)(struct drm_plane *plane, |
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483 | struct drm_intel_sprite_colorkey *key); |
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484 | }; |
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485 | |||
3031 | serge | 486 | struct intel_watermark_params { |
487 | unsigned long fifo_size; |
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488 | unsigned long max_wm; |
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489 | unsigned long default_wm; |
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490 | unsigned long guard_size; |
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491 | unsigned long cacheline_size; |
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492 | }; |
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493 | |||
494 | struct cxsr_latency { |
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495 | int is_desktop; |
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496 | int is_ddr3; |
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497 | unsigned long fsb_freq; |
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498 | unsigned long mem_freq; |
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499 | unsigned long display_sr; |
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500 | unsigned long display_hpll_disable; |
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501 | unsigned long cursor_sr; |
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502 | unsigned long cursor_hpll_disable; |
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503 | }; |
||
504 | |||
2326 | Serge | 505 | #define to_intel_crtc(x) container_of(x, struct intel_crtc, base) |
506 | #define to_intel_connector(x) container_of(x, struct intel_connector, base) |
||
507 | #define to_intel_encoder(x) container_of(x, struct intel_encoder, base) |
||
508 | #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base) |
||
2342 | Serge | 509 | #define to_intel_plane(x) container_of(x, struct intel_plane, base) |
5060 | serge | 510 | #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL) |
2326 | Serge | 511 | |
3031 | serge | 512 | struct intel_hdmi { |
3746 | Serge | 513 | u32 hdmi_reg; |
3031 | serge | 514 | int ddc_bus; |
515 | uint32_t color_range; |
||
3480 | Serge | 516 | bool color_range_auto; |
3031 | serge | 517 | bool has_hdmi_sink; |
518 | bool has_audio; |
||
519 | enum hdmi_force_audio force_audio; |
||
3480 | Serge | 520 | bool rgb_quant_range_selectable; |
5060 | serge | 521 | enum hdmi_picture_aspect aspect_ratio; |
3031 | serge | 522 | void (*write_infoframe)(struct drm_encoder *encoder, |
4104 | Serge | 523 | enum hdmi_infoframe_type type, |
4560 | Serge | 524 | const void *frame, ssize_t len); |
3031 | serge | 525 | void (*set_infoframes)(struct drm_encoder *encoder, |
5060 | serge | 526 | bool enable, |
3031 | serge | 527 | struct drm_display_mode *adjusted_mode); |
528 | }; |
||
529 | |||
5060 | serge | 530 | struct intel_dp_mst_encoder; |
3031 | serge | 531 | #define DP_MAX_DOWNSTREAM_PORTS 0x10 |
532 | |||
5060 | serge | 533 | /** |
534 | * HIGH_RR is the highest eDP panel refresh rate read from EDID |
||
535 | * LOW_RR is the lowest eDP panel refresh rate found from EDID |
||
536 | * parsing for same resolution. |
||
537 | */ |
||
538 | enum edp_drrs_refresh_rate_type { |
||
539 | DRRS_HIGH_RR, |
||
540 | DRRS_LOW_RR, |
||
541 | DRRS_MAX_RR, /* RR count */ |
||
542 | }; |
||
543 | |||
3031 | serge | 544 | struct intel_dp { |
545 | uint32_t output_reg; |
||
3746 | Serge | 546 | uint32_t aux_ch_ctl_reg; |
3031 | serge | 547 | uint32_t DP; |
548 | bool has_audio; |
||
549 | enum hdmi_force_audio force_audio; |
||
550 | uint32_t color_range; |
||
3480 | Serge | 551 | bool color_range_auto; |
3031 | serge | 552 | uint8_t link_bw; |
553 | uint8_t lane_count; |
||
554 | uint8_t dpcd[DP_RECEIVER_CAP_SIZE]; |
||
4104 | Serge | 555 | uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE]; |
3031 | serge | 556 | uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS]; |
5060 | serge | 557 | struct drm_dp_aux aux; |
3031 | serge | 558 | uint8_t train_set[4]; |
559 | int panel_power_up_delay; |
||
560 | int panel_power_down_delay; |
||
561 | int panel_power_cycle_delay; |
||
562 | int backlight_on_delay; |
||
563 | int backlight_off_delay; |
||
564 | struct delayed_work panel_vdd_work; |
||
565 | bool want_panel_vdd; |
||
5060 | serge | 566 | unsigned long last_power_cycle; |
567 | unsigned long last_power_on; |
||
568 | unsigned long last_backlight_off; |
||
569 | |||
570 | bool use_tps3; |
||
571 | bool can_mst; /* this port supports mst */ |
||
572 | bool is_mst; |
||
573 | int active_mst_links; |
||
574 | /* connector directly attached - won't be use for modeset in mst world */ |
||
3243 | Serge | 575 | struct intel_connector *attached_connector; |
5060 | serge | 576 | |
577 | /* mst connector list */ |
||
578 | struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES]; |
||
579 | struct drm_dp_mst_topology_mgr mst_mgr; |
||
580 | |||
581 | uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index); |
||
582 | /* |
||
583 | * This function returns the value we have to program the AUX_CTL |
||
584 | * register with to kick off an AUX transaction. |
||
585 | */ |
||
586 | uint32_t (*get_aux_send_ctl)(struct intel_dp *dp, |
||
587 | bool has_aux_irq, |
||
588 | int send_bytes, |
||
589 | uint32_t aux_clock_divider); |
||
590 | struct { |
||
591 | enum drrs_support_type type; |
||
592 | enum edp_drrs_refresh_rate_type refresh_rate_type; |
||
593 | struct mutex mutex; |
||
594 | } drrs_state; |
||
595 | |||
3031 | serge | 596 | }; |
597 | |||
3243 | Serge | 598 | struct intel_digital_port { |
599 | struct intel_encoder base; |
||
600 | enum port port; |
||
4104 | Serge | 601 | u32 saved_port_bits; |
3243 | Serge | 602 | struct intel_dp dp; |
603 | struct intel_hdmi hdmi; |
||
5060 | serge | 604 | bool (*hpd_pulse)(struct intel_digital_port *, bool); |
3243 | Serge | 605 | }; |
606 | |||
5060 | serge | 607 | struct intel_dp_mst_encoder { |
608 | struct intel_encoder base; |
||
609 | enum pipe pipe; |
||
610 | struct intel_digital_port *primary; |
||
611 | void *port; /* store this opaque as its illegal to dereference it */ |
||
612 | }; |
||
613 | |||
4104 | Serge | 614 | static inline int |
615 | vlv_dport_to_channel(struct intel_digital_port *dport) |
||
616 | { |
||
617 | switch (dport->port) { |
||
618 | case PORT_B: |
||
5060 | serge | 619 | case PORT_D: |
4560 | Serge | 620 | return DPIO_CH0; |
4104 | Serge | 621 | case PORT_C: |
4560 | Serge | 622 | return DPIO_CH1; |
4104 | Serge | 623 | default: |
624 | BUG(); |
||
625 | } |
||
626 | } |
||
627 | |||
5060 | serge | 628 | static inline int |
629 | vlv_pipe_to_channel(enum pipe pipe) |
||
630 | { |
||
631 | switch (pipe) { |
||
632 | case PIPE_A: |
||
633 | case PIPE_C: |
||
634 | return DPIO_CH0; |
||
635 | case PIPE_B: |
||
636 | return DPIO_CH1; |
||
637 | default: |
||
638 | BUG(); |
||
639 | } |
||
640 | } |
||
641 | |||
2326 | Serge | 642 | static inline struct drm_crtc * |
643 | intel_get_crtc_for_pipe(struct drm_device *dev, int pipe) |
||
644 | { |
||
645 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
646 | return dev_priv->pipe_to_crtc_mapping[pipe]; |
||
647 | } |
||
648 | |||
649 | static inline struct drm_crtc * |
||
650 | intel_get_crtc_for_plane(struct drm_device *dev, int plane) |
||
651 | { |
||
652 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
653 | return dev_priv->plane_to_crtc_mapping[plane]; |
||
654 | } |
||
655 | |||
656 | struct intel_unpin_work { |
||
2360 | Serge | 657 | struct work_struct work; |
3243 | Serge | 658 | struct drm_crtc *crtc; |
2326 | Serge | 659 | struct drm_i915_gem_object *old_fb_obj; |
660 | struct drm_i915_gem_object *pending_flip_obj; |
||
661 | struct drm_pending_vblank_event *event; |
||
3243 | Serge | 662 | atomic_t pending; |
663 | #define INTEL_FLIP_INACTIVE 0 |
||
664 | #define INTEL_FLIP_PENDING 1 |
||
665 | #define INTEL_FLIP_COMPLETE 2 |
||
5060 | serge | 666 | u32 flip_count; |
667 | u32 gtt_offset; |
||
2326 | Serge | 668 | bool enable_stall_check; |
669 | }; |
||
670 | |||
3031 | serge | 671 | struct intel_set_config { |
672 | struct drm_encoder **save_connector_encoders; |
||
673 | struct drm_crtc **save_encoder_crtcs; |
||
5060 | serge | 674 | bool *save_crtc_enabled; |
3031 | serge | 675 | |
676 | bool fb_changed; |
||
677 | bool mode_changed; |
||
678 | }; |
||
679 | |||
4560 | Serge | 680 | struct intel_load_detect_pipe { |
681 | struct drm_framebuffer *release_fb; |
||
682 | bool load_detect_temp; |
||
683 | int dpms_mode; |
||
684 | }; |
||
2326 | Serge | 685 | |
4560 | Serge | 686 | static inline struct intel_encoder * |
687 | intel_attached_encoder(struct drm_connector *connector) |
||
2326 | Serge | 688 | { |
689 | return to_intel_connector(connector)->encoder; |
||
690 | } |
||
691 | |||
3243 | Serge | 692 | static inline struct intel_digital_port * |
693 | enc_to_dig_port(struct drm_encoder *encoder) |
||
694 | { |
||
695 | return container_of(encoder, struct intel_digital_port, base.base); |
||
696 | } |
||
697 | |||
5060 | serge | 698 | static inline struct intel_dp_mst_encoder * |
699 | enc_to_mst(struct drm_encoder *encoder) |
||
700 | { |
||
701 | return container_of(encoder, struct intel_dp_mst_encoder, base.base); |
||
702 | } |
||
703 | |||
4104 | Serge | 704 | static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder) |
705 | { |
||
706 | return &enc_to_dig_port(encoder)->dp; |
||
707 | } |
||
708 | |||
3243 | Serge | 709 | static inline struct intel_digital_port * |
710 | dp_to_dig_port(struct intel_dp *intel_dp) |
||
711 | { |
||
712 | return container_of(intel_dp, struct intel_digital_port, dp); |
||
713 | } |
||
714 | |||
715 | static inline struct intel_digital_port * |
||
716 | hdmi_to_dig_port(struct intel_hdmi *intel_hdmi) |
||
717 | { |
||
718 | return container_of(intel_hdmi, struct intel_digital_port, hdmi); |
||
719 | } |
||
720 | |||
4560 | Serge | 721 | |
722 | /* i915_irq.c */ |
||
723 | bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev, |
||
724 | enum pipe pipe, bool enable); |
||
725 | bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev, |
||
726 | enum transcoder pch_transcoder, |
||
727 | bool enable); |
||
5060 | serge | 728 | void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask); |
729 | void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask); |
||
730 | void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask); |
||
731 | void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask); |
||
732 | void gen8_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask); |
||
733 | void gen8_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask); |
||
734 | void intel_runtime_pm_disable_interrupts(struct drm_device *dev); |
||
735 | void intel_runtime_pm_restore_interrupts(struct drm_device *dev); |
||
736 | static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv) |
||
737 | { |
||
738 | /* |
||
739 | * We only use drm_irq_uninstall() at unload and VT switch, so |
||
740 | * this is the only thing we need to check. |
||
741 | */ |
||
742 | return !dev_priv->pm._irqs_disabled; |
||
743 | } |
||
4560 | Serge | 744 | |
5060 | serge | 745 | int intel_get_crtc_scanline(struct intel_crtc *crtc); |
746 | void i9xx_check_fifo_underruns(struct drm_device *dev); |
||
747 | void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv); |
||
4560 | Serge | 748 | |
749 | /* intel_crt.c */ |
||
750 | void intel_crt_init(struct drm_device *dev); |
||
751 | |||
752 | |||
753 | /* intel_ddi.c */ |
||
754 | void intel_prepare_ddi(struct drm_device *dev); |
||
755 | void hsw_fdi_link_train(struct drm_crtc *crtc); |
||
756 | void intel_ddi_init(struct drm_device *dev, enum port port); |
||
757 | enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder); |
||
758 | bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe); |
||
759 | int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv); |
||
760 | void intel_ddi_pll_init(struct drm_device *dev); |
||
761 | void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc); |
||
762 | void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv, |
||
763 | enum transcoder cpu_transcoder); |
||
764 | void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc); |
||
765 | void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc); |
||
766 | bool intel_ddi_pll_select(struct intel_crtc *crtc); |
||
767 | void intel_ddi_set_pipe_settings(struct drm_crtc *crtc); |
||
768 | void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder); |
||
769 | bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector); |
||
770 | void intel_ddi_fdi_disable(struct drm_crtc *crtc); |
||
771 | void intel_ddi_get_config(struct intel_encoder *encoder, |
||
772 | struct intel_crtc_config *pipe_config); |
||
773 | |||
5060 | serge | 774 | void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder); |
775 | void intel_ddi_clock_get(struct intel_encoder *encoder, |
||
776 | struct intel_crtc_config *pipe_config); |
||
777 | void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state); |
||
4560 | Serge | 778 | |
779 | /* intel_display.c */ |
||
780 | const char *intel_output_name(int output); |
||
781 | bool intel_has_pending_fb_unpin(struct drm_device *dev); |
||
782 | int intel_pch_rawclk(struct drm_device *dev); |
||
783 | void intel_mark_busy(struct drm_device *dev); |
||
5060 | serge | 784 | void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj, |
785 | struct intel_engine_cs *ring); |
||
786 | void intel_frontbuffer_flip_prepare(struct drm_device *dev, |
||
787 | unsigned frontbuffer_bits); |
||
788 | void intel_frontbuffer_flip_complete(struct drm_device *dev, |
||
789 | unsigned frontbuffer_bits); |
||
790 | void intel_frontbuffer_flush(struct drm_device *dev, |
||
791 | unsigned frontbuffer_bits); |
||
792 | /** |
||
793 | * intel_frontbuffer_flip - prepare frontbuffer flip |
||
794 | * @dev: DRM device |
||
795 | * @frontbuffer_bits: frontbuffer plane tracking bits |
||
796 | * |
||
797 | * This function gets called after scheduling a flip on @obj. This is for |
||
798 | * synchronous plane updates which will happen on the next vblank and which will |
||
799 | * not get delayed by pending gpu rendering. |
||
800 | * |
||
801 | * Can be called without any locks held. |
||
802 | */ |
||
803 | static inline |
||
804 | void intel_frontbuffer_flip(struct drm_device *dev, |
||
805 | unsigned frontbuffer_bits) |
||
806 | { |
||
807 | intel_frontbuffer_flush(dev, frontbuffer_bits); |
||
808 | } |
||
809 | |||
810 | void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire); |
||
4560 | Serge | 811 | void intel_mark_idle(struct drm_device *dev); |
812 | void intel_crtc_restore_mode(struct drm_crtc *crtc); |
||
5060 | serge | 813 | void intel_crtc_control(struct drm_crtc *crtc, bool enable); |
4560 | Serge | 814 | void intel_crtc_update_dpms(struct drm_crtc *crtc); |
815 | void intel_encoder_destroy(struct drm_encoder *encoder); |
||
816 | void intel_connector_dpms(struct drm_connector *, int mode); |
||
817 | bool intel_connector_get_hw_state(struct intel_connector *connector); |
||
818 | void intel_modeset_check_state(struct drm_device *dev); |
||
3480 | Serge | 819 | bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, |
820 | struct intel_digital_port *port); |
||
4560 | Serge | 821 | void intel_connector_attach_encoder(struct intel_connector *connector, |
2326 | Serge | 822 | struct intel_encoder *encoder); |
4560 | Serge | 823 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector); |
824 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, |
||
2326 | Serge | 825 | struct drm_crtc *crtc); |
4560 | Serge | 826 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector); |
2326 | Serge | 827 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
828 | struct drm_file *file_priv); |
||
4560 | Serge | 829 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
3243 | Serge | 830 | enum pipe pipe); |
4560 | Serge | 831 | void intel_wait_for_vblank(struct drm_device *dev, int pipe); |
832 | void intel_wait_for_pipe_off(struct drm_device *dev, int pipe); |
||
833 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp); |
||
834 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
||
835 | struct intel_digital_port *dport); |
||
836 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
||
2326 | Serge | 837 | struct drm_display_mode *mode, |
5060 | serge | 838 | struct intel_load_detect_pipe *old, |
839 | struct drm_modeset_acquire_ctx *ctx); |
||
4560 | Serge | 840 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
5060 | serge | 841 | struct intel_load_detect_pipe *old); |
4560 | Serge | 842 | int intel_pin_and_fence_fb_obj(struct drm_device *dev, |
2326 | Serge | 843 | struct drm_i915_gem_object *obj, |
5060 | serge | 844 | struct intel_engine_cs *pipelined); |
4560 | Serge | 845 | void intel_unpin_fb_obj(struct drm_i915_gem_object *obj); |
5060 | serge | 846 | struct drm_framebuffer * |
847 | __intel_framebuffer_create(struct drm_device *dev, |
||
2342 | Serge | 848 | struct drm_mode_fb_cmd2 *mode_cmd, |
2326 | Serge | 849 | struct drm_i915_gem_object *obj); |
4560 | Serge | 850 | void intel_prepare_page_flip(struct drm_device *dev, int plane); |
851 | void intel_finish_page_flip(struct drm_device *dev, int pipe); |
||
852 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane); |
||
5060 | serge | 853 | |
854 | /* shared dpll functions */ |
||
4560 | Serge | 855 | struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc); |
4104 | Serge | 856 | void assert_shared_dpll(struct drm_i915_private *dev_priv, |
857 | struct intel_shared_dpll *pll, |
||
858 | bool state); |
||
859 | #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true) |
||
860 | #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false) |
||
5060 | serge | 861 | struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc); |
862 | void intel_put_shared_dpll(struct intel_crtc *crtc); |
||
863 | |||
864 | /* modesetting asserts */ |
||
4104 | Serge | 865 | void assert_pll(struct drm_i915_private *dev_priv, |
866 | enum pipe pipe, bool state); |
||
867 | #define assert_pll_enabled(d, p) assert_pll(d, p, true) |
||
868 | #define assert_pll_disabled(d, p) assert_pll(d, p, false) |
||
869 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
||
870 | enum pipe pipe, bool state); |
||
871 | #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true) |
||
872 | #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false) |
||
4560 | Serge | 873 | void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state); |
2342 | Serge | 874 | #define assert_pipe_enabled(d, p) assert_pipe(d, p, true) |
875 | #define assert_pipe_disabled(d, p) assert_pipe(d, p, false) |
||
4560 | Serge | 876 | void intel_write_eld(struct drm_encoder *encoder, |
2342 | Serge | 877 | struct drm_display_mode *mode); |
4560 | Serge | 878 | unsigned long intel_gen4_compute_page_offset(int *x, int *y, |
3480 | Serge | 879 | unsigned int tiling_mode, |
3243 | Serge | 880 | unsigned int bpp, |
881 | unsigned int pitch); |
||
4560 | Serge | 882 | void intel_display_handle_reset(struct drm_device *dev); |
5060 | serge | 883 | void hsw_enable_pc8(struct drm_i915_private *dev_priv); |
884 | void hsw_disable_pc8(struct drm_i915_private *dev_priv); |
||
4560 | Serge | 885 | void intel_dp_get_m_n(struct intel_crtc *crtc, |
886 | struct intel_crtc_config *pipe_config); |
||
887 | int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n); |
||
888 | void |
||
889 | ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config, |
||
890 | int dotclock); |
||
891 | bool intel_crtc_active(struct drm_crtc *crtc); |
||
892 | void hsw_enable_ips(struct intel_crtc *crtc); |
||
893 | void hsw_disable_ips(struct intel_crtc *crtc); |
||
5060 | serge | 894 | void intel_display_set_init_power(struct drm_i915_private *dev, bool enable); |
895 | enum intel_display_power_domain |
||
896 | intel_display_port_power_domain(struct intel_encoder *intel_encoder); |
||
897 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
||
898 | struct intel_crtc_config *pipe_config); |
||
899 | int intel_format_to_fourcc(int format); |
||
900 | void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc); |
||
3243 | Serge | 901 | |
5060 | serge | 902 | |
4560 | Serge | 903 | /* intel_dp.c */ |
904 | void intel_dp_init(struct drm_device *dev, int output_reg, enum port port); |
||
905 | bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port, |
||
906 | struct intel_connector *intel_connector); |
||
907 | void intel_dp_start_link_train(struct intel_dp *intel_dp); |
||
908 | void intel_dp_complete_link_train(struct intel_dp *intel_dp); |
||
909 | void intel_dp_stop_link_train(struct intel_dp *intel_dp); |
||
910 | void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode); |
||
911 | void intel_dp_encoder_destroy(struct drm_encoder *encoder); |
||
912 | void intel_dp_check_link_status(struct intel_dp *intel_dp); |
||
5060 | serge | 913 | int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc); |
4560 | Serge | 914 | bool intel_dp_compute_config(struct intel_encoder *encoder, |
915 | struct intel_crtc_config *pipe_config); |
||
916 | bool intel_dp_is_edp(struct drm_device *dev, enum port port); |
||
5060 | serge | 917 | bool intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, |
918 | bool long_hpd); |
||
919 | void intel_edp_backlight_on(struct intel_dp *intel_dp); |
||
920 | void intel_edp_backlight_off(struct intel_dp *intel_dp); |
||
921 | void intel_edp_panel_vdd_on(struct intel_dp *intel_dp); |
||
922 | void intel_edp_panel_vdd_sanitize(struct intel_encoder *intel_encoder); |
||
923 | void intel_edp_panel_on(struct intel_dp *intel_dp); |
||
924 | void intel_edp_panel_off(struct intel_dp *intel_dp); |
||
4560 | Serge | 925 | void intel_edp_psr_enable(struct intel_dp *intel_dp); |
926 | void intel_edp_psr_disable(struct intel_dp *intel_dp); |
||
5060 | serge | 927 | void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate); |
928 | void intel_edp_psr_invalidate(struct drm_device *dev, |
||
929 | unsigned frontbuffer_bits); |
||
930 | void intel_edp_psr_flush(struct drm_device *dev, |
||
931 | unsigned frontbuffer_bits); |
||
932 | void intel_edp_psr_init(struct drm_device *dev); |
||
4560 | Serge | 933 | |
5060 | serge | 934 | int intel_dp_handle_hpd_irq(struct intel_digital_port *digport, bool long_hpd); |
935 | void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector); |
||
936 | void intel_dp_mst_suspend(struct drm_device *dev); |
||
937 | void intel_dp_mst_resume(struct drm_device *dev); |
||
938 | int intel_dp_max_link_bw(struct intel_dp *intel_dp); |
||
939 | void intel_dp_hot_plug(struct intel_encoder *intel_encoder); |
||
940 | /* intel_dp_mst.c */ |
||
941 | int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id); |
||
942 | void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port); |
||
4560 | Serge | 943 | /* intel_dsi.c */ |
5060 | serge | 944 | void intel_dsi_init(struct drm_device *dev); |
4560 | Serge | 945 | |
946 | |||
947 | /* intel_dvo.c */ |
||
948 | void intel_dvo_init(struct drm_device *dev); |
||
949 | |||
950 | |||
951 | /* legacy fbdev emulation in intel_fbdev.c */ |
||
952 | #ifdef CONFIG_DRM_I915_FBDEV |
||
953 | extern int intel_fbdev_init(struct drm_device *dev); |
||
954 | extern void intel_fbdev_initial_config(struct drm_device *dev); |
||
955 | extern void intel_fbdev_fini(struct drm_device *dev); |
||
956 | extern void intel_fbdev_set_suspend(struct drm_device *dev, int state); |
||
957 | extern void intel_fbdev_output_poll_changed(struct drm_device *dev); |
||
958 | extern void intel_fbdev_restore_mode(struct drm_device *dev); |
||
959 | #else |
||
960 | static inline int intel_fbdev_init(struct drm_device *dev) |
||
961 | { |
||
962 | return 0; |
||
963 | } |
||
964 | |||
965 | static inline void intel_fbdev_initial_config(struct drm_device *dev) |
||
966 | { |
||
967 | } |
||
968 | |||
969 | static inline void intel_fbdev_fini(struct drm_device *dev) |
||
970 | { |
||
971 | } |
||
972 | |||
973 | static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state) |
||
974 | { |
||
975 | } |
||
976 | |||
977 | static inline void intel_fbdev_restore_mode(struct drm_device *dev) |
||
978 | { |
||
979 | } |
||
980 | #endif |
||
981 | |||
982 | /* intel_hdmi.c */ |
||
983 | void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port); |
||
984 | void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, |
||
985 | struct intel_connector *intel_connector); |
||
986 | struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder); |
||
987 | bool intel_hdmi_compute_config(struct intel_encoder *encoder, |
||
988 | struct intel_crtc_config *pipe_config); |
||
989 | |||
990 | |||
991 | /* intel_lvds.c */ |
||
992 | void intel_lvds_init(struct drm_device *dev); |
||
993 | bool intel_is_dual_link_lvds(struct drm_device *dev); |
||
994 | |||
995 | |||
996 | /* intel_modes.c */ |
||
997 | int intel_connector_update_modes(struct drm_connector *connector, |
||
998 | struct edid *edid); |
||
999 | int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter); |
||
1000 | void intel_attach_force_audio_property(struct drm_connector *connector); |
||
1001 | void intel_attach_broadcast_rgb_property(struct drm_connector *connector); |
||
1002 | |||
1003 | |||
1004 | /* intel_overlay.c */ |
||
1005 | void intel_setup_overlay(struct drm_device *dev); |
||
1006 | void intel_cleanup_overlay(struct drm_device *dev); |
||
1007 | int intel_overlay_switch_off(struct intel_overlay *overlay); |
||
1008 | int intel_overlay_put_image(struct drm_device *dev, void *data, |
||
2342 | Serge | 1009 | struct drm_file *file_priv); |
4560 | Serge | 1010 | int intel_overlay_attrs(struct drm_device *dev, void *data, |
2342 | Serge | 1011 | struct drm_file *file_priv); |
1012 | |||
3031 | serge | 1013 | |
4560 | Serge | 1014 | /* intel_panel.c */ |
1015 | int intel_panel_init(struct intel_panel *panel, |
||
5060 | serge | 1016 | struct drm_display_mode *fixed_mode, |
1017 | struct drm_display_mode *downclock_mode); |
||
4560 | Serge | 1018 | void intel_panel_fini(struct intel_panel *panel); |
1019 | void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode, |
||
1020 | struct drm_display_mode *adjusted_mode); |
||
1021 | void intel_pch_panel_fitting(struct intel_crtc *crtc, |
||
1022 | struct intel_crtc_config *pipe_config, |
||
1023 | int fitting_mode); |
||
1024 | void intel_gmch_panel_fitting(struct intel_crtc *crtc, |
||
1025 | struct intel_crtc_config *pipe_config, |
||
1026 | int fitting_mode); |
||
5060 | serge | 1027 | void intel_panel_set_backlight_acpi(struct intel_connector *connector, |
1028 | u32 level, u32 max); |
||
4560 | Serge | 1029 | int intel_panel_setup_backlight(struct drm_connector *connector); |
1030 | void intel_panel_enable_backlight(struct intel_connector *connector); |
||
1031 | void intel_panel_disable_backlight(struct intel_connector *connector); |
||
1032 | void intel_panel_destroy_backlight(struct drm_connector *connector); |
||
1033 | void intel_panel_init_backlight_funcs(struct drm_device *dev); |
||
1034 | enum drm_connector_status intel_panel_detect(struct drm_device *dev); |
||
1035 | extern struct drm_display_mode *intel_find_panel_downclock( |
||
1036 | struct drm_device *dev, |
||
1037 | struct drm_display_mode *fixed_mode, |
||
1038 | struct drm_connector *connector); |
||
4104 | Serge | 1039 | |
4560 | Serge | 1040 | /* intel_pm.c */ |
1041 | void intel_init_clock_gating(struct drm_device *dev); |
||
1042 | void intel_suspend_hw(struct drm_device *dev); |
||
5060 | serge | 1043 | int ilk_wm_max_level(const struct drm_device *dev); |
4560 | Serge | 1044 | void intel_update_watermarks(struct drm_crtc *crtc); |
1045 | void intel_update_sprite_watermarks(struct drm_plane *plane, |
||
1046 | struct drm_crtc *crtc, |
||
5060 | serge | 1047 | uint32_t sprite_width, |
1048 | uint32_t sprite_height, |
||
1049 | int pixel_size, |
||
4560 | Serge | 1050 | bool enabled, bool scaled); |
1051 | void intel_init_pm(struct drm_device *dev); |
||
1052 | void intel_pm_setup(struct drm_device *dev); |
||
1053 | bool intel_fbc_enabled(struct drm_device *dev); |
||
1054 | void intel_update_fbc(struct drm_device *dev); |
||
1055 | void intel_gpu_ips_init(struct drm_i915_private *dev_priv); |
||
1056 | void intel_gpu_ips_teardown(void); |
||
5060 | serge | 1057 | int intel_power_domains_init(struct drm_i915_private *); |
1058 | void intel_power_domains_remove(struct drm_i915_private *); |
||
1059 | bool intel_display_power_enabled(struct drm_i915_private *dev_priv, |
||
4560 | Serge | 1060 | enum intel_display_power_domain domain); |
5060 | serge | 1061 | bool intel_display_power_enabled_unlocked(struct drm_i915_private *dev_priv, |
4560 | Serge | 1062 | enum intel_display_power_domain domain); |
5060 | serge | 1063 | void intel_display_power_get(struct drm_i915_private *dev_priv, |
4560 | Serge | 1064 | enum intel_display_power_domain domain); |
5060 | serge | 1065 | void intel_display_power_put(struct drm_i915_private *dev_priv, |
4104 | Serge | 1066 | enum intel_display_power_domain domain); |
5060 | serge | 1067 | void intel_power_domains_init_hw(struct drm_i915_private *dev_priv); |
1068 | void intel_init_gt_powersave(struct drm_device *dev); |
||
1069 | void intel_cleanup_gt_powersave(struct drm_device *dev); |
||
4560 | Serge | 1070 | void intel_enable_gt_powersave(struct drm_device *dev); |
1071 | void intel_disable_gt_powersave(struct drm_device *dev); |
||
5060 | serge | 1072 | void intel_suspend_gt_powersave(struct drm_device *dev); |
1073 | void intel_reset_gt_powersave(struct drm_device *dev); |
||
4560 | Serge | 1074 | void ironlake_teardown_rc6(struct drm_device *dev); |
4104 | Serge | 1075 | void gen6_update_ring_freq(struct drm_device *dev); |
4560 | Serge | 1076 | void gen6_rps_idle(struct drm_i915_private *dev_priv); |
1077 | void gen6_rps_boost(struct drm_i915_private *dev_priv); |
||
1078 | void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv); |
||
1079 | void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv); |
||
1080 | void intel_runtime_pm_get(struct drm_i915_private *dev_priv); |
||
5060 | serge | 1081 | void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv); |
4560 | Serge | 1082 | void intel_runtime_pm_put(struct drm_i915_private *dev_priv); |
1083 | void intel_init_runtime_pm(struct drm_i915_private *dev_priv); |
||
1084 | void intel_fini_runtime_pm(struct drm_i915_private *dev_priv); |
||
1085 | void ilk_wm_get_hw_state(struct drm_device *dev); |
||
3031 | serge | 1086 | |
1087 | |||
4560 | Serge | 1088 | /* intel_sdvo.c */ |
1089 | bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob); |
||
3746 | Serge | 1090 | |
4104 | Serge | 1091 | |
4560 | Serge | 1092 | /* intel_sprite.c */ |
1093 | int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane); |
||
1094 | void intel_flush_primary_plane(struct drm_i915_private *dev_priv, |
||
1095 | enum plane plane); |
||
1096 | void intel_plane_restore(struct drm_plane *plane); |
||
1097 | void intel_plane_disable(struct drm_plane *plane); |
||
1098 | int intel_sprite_set_colorkey(struct drm_device *dev, void *data, |
||
1099 | struct drm_file *file_priv); |
||
1100 | int intel_sprite_get_colorkey(struct drm_device *dev, void *data, |
||
1101 | struct drm_file *file_priv); |
||
1102 | |||
1103 | |||
1104 | /* intel_tv.c */ |
||
1105 | void intel_tv_init(struct drm_device *dev); |
||
1106 | |||
2326 | Serge | 1107 | #endif /* __INTEL_DRV_H__ */1)><1)>0)><0)> |