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2326 | Serge | 1 | /* |
2 | * Copyright (c) 2006 Dave Airlie |
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3 | * Copyright (c) 2007-2008 Intel Corporation |
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4 | * Jesse Barnes |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the "Software"), |
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8 | * to deal in the Software without restriction, including without limitation |
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9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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10 | * and/or sell copies of the Software, and to permit persons to whom the |
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11 | * Software is furnished to do so, subject to the following conditions: |
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12 | * |
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13 | * The above copyright notice and this permission notice (including the next |
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14 | * paragraph) shall be included in all copies or substantial portions of the |
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15 | * Software. |
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16 | * |
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17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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22 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
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23 | * IN THE SOFTWARE. |
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24 | */ |
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25 | #ifndef __INTEL_DRV_H__ |
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26 | #define __INTEL_DRV_H__ |
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27 | |||
5354 | serge | 28 | #include |
2326 | Serge | 29 | #include |
4104 | Serge | 30 | #include |
3031 | serge | 31 | #include |
2326 | Serge | 32 | #include "i915_drv.h" |
3031 | serge | 33 | #include |
34 | #include |
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35 | #include |
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5060 | serge | 36 | #include |
5354 | serge | 37 | #include |
6084 | serge | 38 | #include |
2326 | Serge | 39 | |
3746 | Serge | 40 | /** |
41 | * _wait_for - magic (register) wait macro |
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42 | * |
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43 | * Does the right thing for modeset paths when run under kdgb or similar atomic |
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44 | * contexts. Note that it's important that we check the condition again after |
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45 | * having timed out, since the timeout could be due to preemption or similar and |
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46 | * we've never had a chance to check the condition before the timeout. |
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47 | */ |
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2326 | Serge | 48 | #define _wait_for(COND, MS, W) ({ \ |
5060 | serge | 49 | unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \ |
2326 | Serge | 50 | int ret__ = 0; \ |
2342 | Serge | 51 | while (!(COND)) { \ |
5060 | serge | 52 | if (time_after(jiffies, timeout__)) { \ |
3746 | Serge | 53 | if (!(COND)) \ |
6084 | serge | 54 | ret__ = -ETIMEDOUT; \ |
2326 | Serge | 55 | break; \ |
56 | } \ |
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3031 | serge | 57 | if (W ) { \ |
58 | msleep(W); \ |
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59 | } else { \ |
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60 | cpu_relax(); \ |
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61 | } \ |
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2326 | Serge | 62 | } \ |
63 | ret__; \ |
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64 | }) |
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65 | |||
66 | #define wait_for(COND, MS) _wait_for(COND, MS, 1) |
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67 | #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0) |
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4104 | Serge | 68 | #define wait_for_atomic_us(COND, US) _wait_for((COND), \ |
69 | DIV_ROUND_UP((US), 1000), 0) |
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2326 | Serge | 70 | |
4560 | Serge | 71 | #define KHz(x) (1000 * (x)) |
72 | #define MHz(x) KHz(1000 * (x)) |
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2326 | Serge | 73 | |
74 | /* |
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75 | * Display related stuff |
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76 | */ |
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77 | |||
78 | /* store information about an Ixxx DVO */ |
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79 | /* The i830->i865 use multiple DVOs with multiple i2cs */ |
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80 | /* the i915, i945 have a single sDVO i2c bus - which is different */ |
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81 | #define MAX_OUTPUTS 6 |
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82 | /* maximum connectors per crtcs in the mode set */ |
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83 | |||
5060 | serge | 84 | /* Maximum cursor sizes */ |
85 | #define GEN2_CURSOR_WIDTH 64 |
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86 | #define GEN2_CURSOR_HEIGHT 64 |
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87 | #define MAX_CURSOR_WIDTH 256 |
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88 | #define MAX_CURSOR_HEIGHT 256 |
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89 | |||
2326 | Serge | 90 | #define INTEL_I2C_BUS_DVO 1 |
91 | #define INTEL_I2C_BUS_SDVO 2 |
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92 | |||
93 | /* these are outputs from the chip - integrated only |
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94 | external chips are via DVO or SDVO output */ |
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5354 | serge | 95 | enum intel_output_type { |
96 | INTEL_OUTPUT_UNUSED = 0, |
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97 | INTEL_OUTPUT_ANALOG = 1, |
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98 | INTEL_OUTPUT_DVO = 2, |
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99 | INTEL_OUTPUT_SDVO = 3, |
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100 | INTEL_OUTPUT_LVDS = 4, |
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101 | INTEL_OUTPUT_TVOUT = 5, |
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102 | INTEL_OUTPUT_HDMI = 6, |
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103 | INTEL_OUTPUT_DISPLAYPORT = 7, |
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104 | INTEL_OUTPUT_EDP = 8, |
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105 | INTEL_OUTPUT_DSI = 9, |
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106 | INTEL_OUTPUT_UNKNOWN = 10, |
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107 | INTEL_OUTPUT_DP_MST = 11, |
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108 | }; |
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2326 | Serge | 109 | |
110 | #define INTEL_DVO_CHIP_NONE 0 |
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111 | #define INTEL_DVO_CHIP_LVDS 1 |
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112 | #define INTEL_DVO_CHIP_TMDS 2 |
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113 | #define INTEL_DVO_CHIP_TVOUT 4 |
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114 | |||
5060 | serge | 115 | #define INTEL_DSI_VIDEO_MODE 0 |
116 | #define INTEL_DSI_COMMAND_MODE 1 |
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4560 | Serge | 117 | |
2326 | Serge | 118 | struct intel_framebuffer { |
119 | struct drm_framebuffer base; |
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6320 | serge | 120 | struct drm_i915_gem_object *obj; |
6283 | serge | 121 | void *private; |
2326 | Serge | 122 | }; |
123 | |||
124 | struct intel_fbdev { |
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125 | struct drm_fb_helper helper; |
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5060 | serge | 126 | struct intel_framebuffer *fb; |
2326 | Serge | 127 | struct list_head fbdev_list; |
128 | struct drm_display_mode *our_mode; |
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5060 | serge | 129 | int preferred_bpp; |
2326 | Serge | 130 | }; |
131 | |||
132 | struct intel_encoder { |
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133 | struct drm_encoder base; |
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3031 | serge | 134 | |
5354 | serge | 135 | enum intel_output_type type; |
5060 | serge | 136 | unsigned int cloneable; |
2326 | Serge | 137 | void (*hot_plug)(struct intel_encoder *); |
3746 | Serge | 138 | bool (*compute_config)(struct intel_encoder *, |
6084 | serge | 139 | struct intel_crtc_state *); |
3480 | Serge | 140 | void (*pre_pll_enable)(struct intel_encoder *); |
3031 | serge | 141 | void (*pre_enable)(struct intel_encoder *); |
142 | void (*enable)(struct intel_encoder *); |
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3746 | Serge | 143 | void (*mode_set)(struct intel_encoder *intel_encoder); |
3031 | serge | 144 | void (*disable)(struct intel_encoder *); |
145 | void (*post_disable)(struct intel_encoder *); |
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6084 | serge | 146 | void (*post_pll_disable)(struct intel_encoder *); |
3031 | serge | 147 | /* Read out the current hw state of this connector, returning true if |
148 | * the encoder is active. If the encoder is enabled it also set the pipe |
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149 | * it is connected to in the pipe parameter. */ |
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150 | bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe); |
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4104 | Serge | 151 | /* Reconstructs the equivalent mode flags for the current hardware |
152 | * state. This must be called _after_ display->get_pipe_config has |
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153 | * pre-filled the pipe config. Note that intel_encoder->base.crtc must |
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154 | * be set correctly before calling this function. */ |
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155 | void (*get_config)(struct intel_encoder *, |
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6084 | serge | 156 | struct intel_crtc_state *pipe_config); |
5060 | serge | 157 | /* |
158 | * Called during system suspend after all pending requests for the |
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159 | * encoder are flushed (for example for DP AUX transactions) and |
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160 | * device interrupts are disabled. |
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161 | */ |
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162 | void (*suspend)(struct intel_encoder *); |
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2326 | Serge | 163 | int crtc_mask; |
3746 | Serge | 164 | enum hpd_pin hpd_pin; |
2326 | Serge | 165 | }; |
166 | |||
3243 | Serge | 167 | struct intel_panel { |
168 | struct drm_display_mode *fixed_mode; |
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4560 | Serge | 169 | struct drm_display_mode *downclock_mode; |
3243 | Serge | 170 | int fitting_mode; |
4560 | Serge | 171 | |
172 | /* backlight */ |
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173 | struct { |
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174 | bool present; |
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175 | u32 level; |
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5060 | serge | 176 | u32 min; |
4560 | Serge | 177 | u32 max; |
178 | bool enabled; |
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179 | bool combination_mode; /* gen 2/4 only */ |
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180 | bool active_low_pwm; |
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6084 | serge | 181 | |
182 | /* PWM chip */ |
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183 | bool util_pin_active_low; /* bxt+ */ |
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184 | u8 controller; /* bxt+ only */ |
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185 | struct pwm_device *pwm; |
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186 | |||
4560 | Serge | 187 | struct backlight_device *device; |
6084 | serge | 188 | |
189 | /* Connector and platform specific backlight functions */ |
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190 | int (*setup)(struct intel_connector *connector, enum pipe pipe); |
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191 | uint32_t (*get)(struct intel_connector *connector); |
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192 | void (*set)(struct intel_connector *connector, uint32_t level); |
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193 | void (*disable)(struct intel_connector *connector); |
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194 | void (*enable)(struct intel_connector *connector); |
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195 | uint32_t (*hz_to_pwm)(struct intel_connector *connector, |
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196 | uint32_t hz); |
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197 | void (*power)(struct intel_connector *, bool enable); |
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4560 | Serge | 198 | } backlight; |
3243 | Serge | 199 | }; |
200 | |||
2326 | Serge | 201 | struct intel_connector { |
202 | struct drm_connector base; |
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3031 | serge | 203 | /* |
204 | * The fixed encoder this connector is connected to. |
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205 | */ |
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2326 | Serge | 206 | struct intel_encoder *encoder; |
3031 | serge | 207 | |
208 | /* Reads out the current hw, returning true if the connector is enabled |
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209 | * and active (i.e. dpms ON state). */ |
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210 | bool (*get_hw_state)(struct intel_connector *); |
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3243 | Serge | 211 | |
5060 | serge | 212 | /* |
213 | * Removes all interfaces through which the connector is accessible |
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214 | * - like sysfs, debugfs entries -, so that no new operations can be |
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215 | * started on the connector. Also makes sure all currently pending |
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216 | * operations finish before returing. |
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217 | */ |
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218 | void (*unregister)(struct intel_connector *); |
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219 | |||
3243 | Serge | 220 | /* Panel info for eDP and LVDS */ |
221 | struct intel_panel panel; |
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222 | |||
223 | /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */ |
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224 | struct edid *edid; |
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5354 | serge | 225 | struct edid *detect_edid; |
3746 | Serge | 226 | |
227 | /* since POLL and HPD connectors may use the same HPD line keep the native |
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228 | state of connector->polled in case hotplug storm detection changes it */ |
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229 | u8 polled; |
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5060 | serge | 230 | |
231 | void *port; /* store this opaque as its illegal to dereference it */ |
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232 | |||
233 | struct intel_dp *mst_port; |
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2326 | Serge | 234 | }; |
235 | |||
4104 | Serge | 236 | typedef struct dpll { |
237 | /* given values */ |
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238 | int n; |
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239 | int m1, m2; |
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240 | int p1, p2; |
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241 | /* derived values */ |
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242 | int dot; |
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243 | int vco; |
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244 | int m; |
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245 | int p; |
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246 | } intel_clock_t; |
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247 | |||
6084 | serge | 248 | struct intel_atomic_state { |
249 | struct drm_atomic_state base; |
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250 | |||
251 | unsigned int cdclk; |
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252 | bool dpll_set; |
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253 | struct intel_shared_dpll_config shared_dpll[I915_NUM_PLLS]; |
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254 | }; |
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255 | |||
5354 | serge | 256 | struct intel_plane_state { |
6084 | serge | 257 | struct drm_plane_state base; |
5354 | serge | 258 | struct drm_rect src; |
259 | struct drm_rect dst; |
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260 | struct drm_rect clip; |
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261 | bool visible; |
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6084 | serge | 262 | |
263 | /* |
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264 | * scaler_id |
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265 | * = -1 : not using a scaler |
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266 | * >= 0 : using a scalers |
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267 | * |
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268 | * plane requiring a scaler: |
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269 | * - During check_plane, its bit is set in |
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270 | * crtc_state->scaler_state.scaler_users by calling helper function |
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271 | * update_scaler_plane. |
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272 | * - scaler_id indicates the scaler it got assigned. |
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273 | * |
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274 | * plane doesn't require a scaler: |
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275 | * - this can happen when scaling is no more required or plane simply |
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276 | * got disabled. |
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277 | * - During check_plane, corresponding bit is reset in |
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278 | * crtc_state->scaler_state.scaler_users by calling helper function |
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279 | * update_scaler_plane. |
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280 | */ |
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281 | int scaler_id; |
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282 | |||
283 | struct drm_intel_sprite_colorkey ckey; |
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5354 | serge | 284 | }; |
285 | |||
6084 | serge | 286 | struct intel_initial_plane_config { |
287 | struct intel_framebuffer *fb; |
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288 | unsigned int tiling; |
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5060 | serge | 289 | int size; |
290 | u32 base; |
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291 | }; |
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292 | |||
6084 | serge | 293 | #define SKL_MIN_SRC_W 8 |
294 | #define SKL_MAX_SRC_W 4096 |
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295 | #define SKL_MIN_SRC_H 8 |
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296 | #define SKL_MAX_SRC_H 4096 |
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297 | #define SKL_MIN_DST_W 8 |
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298 | #define SKL_MAX_DST_W 4096 |
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299 | #define SKL_MIN_DST_H 8 |
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300 | #define SKL_MAX_DST_H 4096 |
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301 | |||
302 | struct intel_scaler { |
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303 | int in_use; |
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304 | uint32_t mode; |
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305 | }; |
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306 | |||
307 | struct intel_crtc_scaler_state { |
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308 | #define SKL_NUM_SCALERS 2 |
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309 | struct intel_scaler scalers[SKL_NUM_SCALERS]; |
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310 | |||
311 | /* |
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312 | * scaler_users: keeps track of users requesting scalers on this crtc. |
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313 | * |
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314 | * If a bit is set, a user is using a scaler. |
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315 | * Here user can be a plane or crtc as defined below: |
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316 | * bits 0-30 - plane (bit position is index from drm_plane_index) |
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317 | * bit 31 - crtc |
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318 | * |
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319 | * Instead of creating a new index to cover planes and crtc, using |
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320 | * existing drm_plane_index for planes which is well less than 31 |
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321 | * planes and bit 31 for crtc. This should be fine to cover all |
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322 | * our platforms. |
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323 | * |
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324 | * intel_atomic_setup_scalers will setup available scalers to users |
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325 | * requesting scalers. It will gracefully fail if request exceeds |
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326 | * avilability. |
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327 | */ |
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328 | #define SKL_CRTC_INDEX 31 |
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329 | unsigned scaler_users; |
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330 | |||
331 | /* scaler used by crtc for panel fitting purpose */ |
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332 | int scaler_id; |
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333 | }; |
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334 | |||
335 | /* drm_mode->private_flags */ |
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336 | #define I915_MODE_FLAG_INHERITED 1 |
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337 | |||
338 | struct intel_crtc_state { |
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339 | struct drm_crtc_state base; |
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340 | |||
4104 | Serge | 341 | /** |
342 | * quirks - bitfield with hw state readout quirks |
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343 | * |
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344 | * For various reasons the hw state readout code might not be able to |
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345 | * completely faithfully read out the current state. These cases are |
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346 | * tracked with quirk flags so that fastboot and state checker can act |
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347 | * accordingly. |
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348 | */ |
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6084 | serge | 349 | #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */ |
4104 | Serge | 350 | unsigned long quirks; |
351 | |||
6084 | serge | 352 | bool update_pipe; |
4560 | Serge | 353 | |
354 | /* Pipe source size (ie. panel fitter input size) |
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355 | * All planes will be positioned inside this space, |
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356 | * and get clipped at the edges. */ |
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357 | int pipe_src_w, pipe_src_h; |
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358 | |||
3746 | Serge | 359 | /* Whether to set up the PCH/FDI. Note that we never allow sharing |
360 | * between pch encoders and cpu encoders. */ |
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361 | bool has_pch_encoder; |
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362 | |||
5354 | serge | 363 | /* Are we sending infoframes on the attached port */ |
364 | bool has_infoframe; |
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365 | |||
3746 | Serge | 366 | /* CPU Transcoder for the pipe. Currently this can only differ from the |
367 | * pipe on Haswell (where we have a special eDP transcoder). */ |
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368 | enum transcoder cpu_transcoder; |
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369 | |||
370 | /* |
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371 | * Use reduced/limited/broadcast rbg range, compressing from the full |
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372 | * range fed into the crtcs. |
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373 | */ |
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374 | bool limited_color_range; |
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375 | |||
376 | /* DP has a bunch of special case unfortunately, so mark the pipe |
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377 | * accordingly. */ |
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378 | bool has_dp_encoder; |
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4104 | Serge | 379 | |
5060 | serge | 380 | /* Whether we should send NULL infoframes. Required for audio. */ |
381 | bool has_hdmi_sink; |
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382 | |||
383 | /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or |
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384 | * has_dp_encoder is set. */ |
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385 | bool has_audio; |
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386 | |||
4104 | Serge | 387 | /* |
388 | * Enable dithering, used when the selected pipe bpp doesn't match the |
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389 | * plane bpp. |
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390 | */ |
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3746 | Serge | 391 | bool dither; |
392 | |||
393 | /* Controls for the clock computation, to override various stages. */ |
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394 | bool clock_set; |
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395 | |||
4104 | Serge | 396 | /* SDVO TV has a bunch of special case. To make multifunction encoders |
397 | * work correctly, we need to track this at runtime.*/ |
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398 | bool sdvo_tv_clock; |
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399 | |||
400 | /* |
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401 | * crtc bandwidth limit, don't increase pipe bpp or clock if not really |
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402 | * required. This is set in the 2nd loop of calling encoder's |
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403 | * ->compute_config if the first pick doesn't work out. |
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404 | */ |
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405 | bool bw_constrained; |
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406 | |||
3746 | Serge | 407 | /* Settings for the intel dpll used on pretty much everything but |
408 | * haswell. */ |
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4104 | Serge | 409 | struct dpll dpll; |
3746 | Serge | 410 | |
4104 | Serge | 411 | /* Selected dpll when shared or DPLL_ID_PRIVATE. */ |
412 | enum intel_dpll_id shared_dpll; |
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413 | |||
5354 | serge | 414 | /* |
415 | * - PORT_CLK_SEL for DDI ports on HSW/BDW. |
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416 | * - enum skl_dpll on SKL |
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417 | */ |
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5060 | serge | 418 | uint32_t ddi_pll_sel; |
419 | |||
4104 | Serge | 420 | /* Actual register state of the dpll, for shared dpll cross-checking. */ |
421 | struct intel_dpll_hw_state dpll_hw_state; |
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422 | |||
3746 | Serge | 423 | int pipe_bpp; |
424 | struct intel_link_m_n dp_m_n; |
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4104 | Serge | 425 | |
5060 | serge | 426 | /* m2_n2 for eDP downclock */ |
427 | struct intel_link_m_n dp_m2_n2; |
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5354 | serge | 428 | bool has_drrs; |
5060 | serge | 429 | |
4104 | Serge | 430 | /* |
431 | * Frequence the dpll for the port should run at. Differs from the |
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4560 | Serge | 432 | * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also |
433 | * already multiplied by pixel_multiplier. |
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3746 | Serge | 434 | */ |
4104 | Serge | 435 | int port_clock; |
436 | |||
3746 | Serge | 437 | /* Used by SDVO (and if we ever fix it, HDMI). */ |
438 | unsigned pixel_multiplier; |
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4104 | Serge | 439 | |
6084 | serge | 440 | uint8_t lane_count; |
441 | |||
4104 | Serge | 442 | /* Panel fitter controls for gen2-gen4 + VLV */ |
443 | struct { |
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444 | u32 control; |
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445 | u32 pgm_ratios; |
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446 | u32 lvds_border_bits; |
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447 | } gmch_pfit; |
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448 | |||
449 | /* Panel fitter placement and size for Ironlake+ */ |
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450 | struct { |
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451 | u32 pos; |
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452 | u32 size; |
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453 | bool enabled; |
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5060 | serge | 454 | bool force_thru; |
4104 | Serge | 455 | } pch_pfit; |
456 | |||
457 | /* FDI configuration, only valid if has_pch_encoder is set. */ |
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458 | int fdi_lanes; |
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459 | struct intel_link_m_n fdi_m_n; |
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460 | |||
461 | bool ips_enabled; |
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4560 | Serge | 462 | |
463 | bool double_wide; |
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5060 | serge | 464 | |
465 | bool dp_encoder_is_mst; |
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466 | int pbn; |
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6084 | serge | 467 | |
468 | struct intel_crtc_scaler_state scaler_state; |
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469 | |||
470 | /* w/a for waiting 2 vblanks during crtc enable */ |
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471 | enum pipe hsw_workaround_pipe; |
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3746 | Serge | 472 | }; |
473 | |||
6084 | serge | 474 | struct vlv_wm_state { |
475 | struct vlv_pipe_wm wm[3]; |
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476 | struct vlv_sr_wm sr[3]; |
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477 | uint8_t num_active_planes; |
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478 | uint8_t num_levels; |
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479 | uint8_t level; |
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480 | bool cxsr; |
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481 | }; |
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482 | |||
4560 | Serge | 483 | struct intel_pipe_wm { |
484 | struct intel_wm_level wm[5]; |
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485 | uint32_t linetime; |
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486 | bool fbc_wm_enabled; |
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5060 | serge | 487 | bool pipe_enabled; |
488 | bool sprites_enabled; |
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489 | bool sprites_scaled; |
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4560 | Serge | 490 | }; |
491 | |||
5060 | serge | 492 | struct intel_mmio_flip { |
5354 | serge | 493 | struct work_struct work; |
6084 | serge | 494 | struct drm_i915_private *i915; |
495 | struct drm_i915_gem_request *req; |
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496 | struct intel_crtc *crtc; |
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5060 | serge | 497 | }; |
498 | |||
5354 | serge | 499 | struct skl_pipe_wm { |
500 | struct skl_wm_level wm[8]; |
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501 | struct skl_wm_level trans_wm; |
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502 | uint32_t linetime; |
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503 | }; |
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504 | |||
6084 | serge | 505 | /* |
506 | * Tracking of operations that need to be performed at the beginning/end of an |
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507 | * atomic commit, outside the atomic section where interrupts are disabled. |
||
508 | * These are generally operations that grab mutexes or might otherwise sleep |
||
509 | * and thus can't be run with interrupts disabled. |
||
510 | */ |
||
511 | struct intel_crtc_atomic_commit { |
||
512 | /* Sleepable operations to perform before commit */ |
||
513 | bool wait_for_flips; |
||
514 | bool disable_fbc; |
||
515 | bool disable_ips; |
||
516 | bool disable_cxsr; |
||
517 | bool pre_disable_primary; |
||
518 | bool update_wm_pre, update_wm_post; |
||
519 | unsigned disabled_planes; |
||
520 | |||
521 | /* Sleepable operations to perform after commit */ |
||
522 | unsigned fb_bits; |
||
523 | bool wait_vblank; |
||
524 | bool update_fbc; |
||
525 | bool post_enable_primary; |
||
526 | unsigned update_sprite_watermarks; |
||
527 | }; |
||
528 | |||
2326 | Serge | 529 | struct intel_crtc { |
530 | struct drm_crtc base; |
||
531 | enum pipe pipe; |
||
532 | enum plane plane; |
||
533 | u8 lut_r[256], lut_g[256], lut_b[256]; |
||
3031 | serge | 534 | /* |
535 | * Whether the crtc and the connected output pipeline is active. Implies |
||
536 | * that crtc->enabled is set, i.e. the current mode configuration has |
||
537 | * some outputs connected to this crtc. |
||
538 | */ |
||
539 | bool active; |
||
4560 | Serge | 540 | unsigned long enabled_power_domains; |
2326 | Serge | 541 | bool lowfreq_avail; |
542 | struct intel_overlay *overlay; |
||
543 | struct intel_unpin_work *unpin_work; |
||
544 | |||
3243 | Serge | 545 | atomic_t unpin_work_count; |
546 | |||
3031 | serge | 547 | /* Display surface base address adjustement for pageflips. Note that on |
548 | * gen4+ this only adjusts up to a tile, offsets within a tile are |
||
549 | * handled in the hw itself (with the TILEOFF register). */ |
||
550 | unsigned long dspaddr_offset; |
||
6084 | serge | 551 | int adjusted_x; |
552 | int adjusted_y; |
||
3031 | serge | 553 | |
2326 | Serge | 554 | uint32_t cursor_addr; |
5060 | serge | 555 | uint32_t cursor_cntl; |
5354 | serge | 556 | uint32_t cursor_size; |
5060 | serge | 557 | uint32_t cursor_base; |
2342 | Serge | 558 | |
6084 | serge | 559 | struct intel_crtc_state *config; |
3746 | Serge | 560 | |
3480 | Serge | 561 | /* reset counter value when the last flip was submitted */ |
562 | unsigned int reset_counter; |
||
4104 | Serge | 563 | |
564 | /* Access to these should be protected by dev_priv->irq_lock. */ |
||
565 | bool cpu_fifo_underrun_disabled; |
||
566 | bool pch_fifo_underrun_disabled; |
||
4560 | Serge | 567 | |
568 | /* per-pipe watermark state */ |
||
569 | struct { |
||
570 | /* watermarks currently being used */ |
||
571 | struct intel_pipe_wm active; |
||
5354 | serge | 572 | /* SKL wm values currently in use */ |
573 | struct skl_pipe_wm skl_active; |
||
6084 | serge | 574 | /* allow CxSR on this pipe */ |
575 | bool cxsr_allowed; |
||
4560 | Serge | 576 | } wm; |
5060 | serge | 577 | |
578 | int scanline_offset; |
||
6084 | serge | 579 | |
580 | struct { |
||
581 | unsigned start_vbl_count; |
||
582 | ktime_t start_vbl_time; |
||
583 | int min_vbl, max_vbl; |
||
584 | int scanline_start; |
||
585 | } debug; |
||
586 | |||
587 | struct intel_crtc_atomic_commit atomic; |
||
588 | |||
589 | /* scalers available on this crtc */ |
||
590 | int num_scalers; |
||
591 | |||
592 | struct vlv_wm_state wm_state; |
||
2326 | Serge | 593 | }; |
594 | |||
4104 | Serge | 595 | struct intel_plane_wm_parameters { |
596 | uint32_t horiz_pixels; |
||
5060 | serge | 597 | uint32_t vert_pixels; |
6084 | serge | 598 | /* |
599 | * For packed pixel formats: |
||
600 | * bytes_per_pixel - holds bytes per pixel |
||
601 | * For planar pixel formats: |
||
602 | * bytes_per_pixel - holds bytes per pixel for uv-plane |
||
603 | * y_bytes_per_pixel - holds bytes per pixel for y-plane |
||
604 | */ |
||
4104 | Serge | 605 | uint8_t bytes_per_pixel; |
6084 | serge | 606 | uint8_t y_bytes_per_pixel; |
4104 | Serge | 607 | bool enabled; |
608 | bool scaled; |
||
6084 | serge | 609 | u64 tiling; |
610 | unsigned int rotation; |
||
611 | uint16_t fifo_size; |
||
4104 | Serge | 612 | }; |
613 | |||
2342 | Serge | 614 | struct intel_plane { |
615 | struct drm_plane base; |
||
3746 | Serge | 616 | int plane; |
2342 | Serge | 617 | enum pipe pipe; |
3243 | Serge | 618 | bool can_scale; |
2342 | Serge | 619 | int max_downscale; |
6084 | serge | 620 | uint32_t frontbuffer_bit; |
4104 | Serge | 621 | |
622 | /* Since we need to change the watermarks before/after |
||
623 | * enabling/disabling the planes, we need to store the parameters here |
||
624 | * as the other pieces of the struct may not reflect the values we want |
||
625 | * for the watermark calculations. Currently only Haswell uses this. |
||
626 | */ |
||
627 | struct intel_plane_wm_parameters wm; |
||
628 | |||
6084 | serge | 629 | /* |
630 | * NOTE: Do not place new plane state fields here (e.g., when adding |
||
631 | * new plane properties). New runtime state should now be placed in |
||
632 | * the intel_plane_state structure and accessed via drm_plane->state. |
||
633 | */ |
||
634 | |||
2342 | Serge | 635 | void (*update_plane)(struct drm_plane *plane, |
4104 | Serge | 636 | struct drm_crtc *crtc, |
2342 | Serge | 637 | struct drm_framebuffer *fb, |
638 | int crtc_x, int crtc_y, |
||
639 | unsigned int crtc_w, unsigned int crtc_h, |
||
640 | uint32_t x, uint32_t y, |
||
641 | uint32_t src_w, uint32_t src_h); |
||
4104 | Serge | 642 | void (*disable_plane)(struct drm_plane *plane, |
643 | struct drm_crtc *crtc); |
||
6084 | serge | 644 | int (*check_plane)(struct drm_plane *plane, |
645 | struct intel_crtc_state *crtc_state, |
||
646 | struct intel_plane_state *state); |
||
647 | void (*commit_plane)(struct drm_plane *plane, |
||
648 | struct intel_plane_state *state); |
||
2342 | Serge | 649 | }; |
650 | |||
3031 | serge | 651 | struct intel_watermark_params { |
652 | unsigned long fifo_size; |
||
653 | unsigned long max_wm; |
||
654 | unsigned long default_wm; |
||
655 | unsigned long guard_size; |
||
656 | unsigned long cacheline_size; |
||
657 | }; |
||
658 | |||
659 | struct cxsr_latency { |
||
660 | int is_desktop; |
||
661 | int is_ddr3; |
||
662 | unsigned long fsb_freq; |
||
663 | unsigned long mem_freq; |
||
664 | unsigned long display_sr; |
||
665 | unsigned long display_hpll_disable; |
||
666 | unsigned long cursor_sr; |
||
667 | unsigned long cursor_hpll_disable; |
||
668 | }; |
||
669 | |||
6084 | serge | 670 | #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base) |
2326 | Serge | 671 | #define to_intel_crtc(x) container_of(x, struct intel_crtc, base) |
6084 | serge | 672 | #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base) |
2326 | Serge | 673 | #define to_intel_connector(x) container_of(x, struct intel_connector, base) |
674 | #define to_intel_encoder(x) container_of(x, struct intel_encoder, base) |
||
675 | #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base) |
||
2342 | Serge | 676 | #define to_intel_plane(x) container_of(x, struct intel_plane, base) |
6084 | serge | 677 | #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base) |
5060 | serge | 678 | #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL) |
2326 | Serge | 679 | |
3031 | serge | 680 | struct intel_hdmi { |
3746 | Serge | 681 | u32 hdmi_reg; |
3031 | serge | 682 | int ddc_bus; |
6084 | serge | 683 | bool limited_color_range; |
3480 | Serge | 684 | bool color_range_auto; |
3031 | serge | 685 | bool has_hdmi_sink; |
686 | bool has_audio; |
||
687 | enum hdmi_force_audio force_audio; |
||
3480 | Serge | 688 | bool rgb_quant_range_selectable; |
5060 | serge | 689 | enum hdmi_picture_aspect aspect_ratio; |
6084 | serge | 690 | struct intel_connector *attached_connector; |
3031 | serge | 691 | void (*write_infoframe)(struct drm_encoder *encoder, |
4104 | Serge | 692 | enum hdmi_infoframe_type type, |
4560 | Serge | 693 | const void *frame, ssize_t len); |
3031 | serge | 694 | void (*set_infoframes)(struct drm_encoder *encoder, |
5060 | serge | 695 | bool enable, |
6084 | serge | 696 | const struct drm_display_mode *adjusted_mode); |
5354 | serge | 697 | bool (*infoframe_enabled)(struct drm_encoder *encoder); |
3031 | serge | 698 | }; |
699 | |||
5060 | serge | 700 | struct intel_dp_mst_encoder; |
3031 | serge | 701 | #define DP_MAX_DOWNSTREAM_PORTS 0x10 |
702 | |||
6084 | serge | 703 | /* |
704 | * enum link_m_n_set: |
||
705 | * When platform provides two set of M_N registers for dp, we can |
||
706 | * program them and switch between them incase of DRRS. |
||
707 | * But When only one such register is provided, we have to program the |
||
708 | * required divider value on that registers itself based on the DRRS state. |
||
709 | * |
||
710 | * M1_N1 : Program dp_m_n on M1_N1 registers |
||
711 | * dp_m2_n2 on M2_N2 registers (If supported) |
||
712 | * |
||
713 | * M2_N2 : Program dp_m2_n2 on M1_N1 registers |
||
714 | * M2_N2 registers are not supported |
||
5060 | serge | 715 | */ |
6084 | serge | 716 | |
717 | enum link_m_n_set { |
||
718 | /* Sets the m1_n1 and m2_n2 */ |
||
719 | M1_N1 = 0, |
||
720 | M2_N2 |
||
5060 | serge | 721 | }; |
722 | |||
6084 | serge | 723 | struct sink_crc { |
724 | bool started; |
||
725 | u8 last_crc[6]; |
||
726 | int last_count; |
||
727 | }; |
||
728 | |||
3031 | serge | 729 | struct intel_dp { |
730 | uint32_t output_reg; |
||
3746 | Serge | 731 | uint32_t aux_ch_ctl_reg; |
3031 | serge | 732 | uint32_t DP; |
6084 | serge | 733 | int link_rate; |
734 | uint8_t lane_count; |
||
3031 | serge | 735 | bool has_audio; |
736 | enum hdmi_force_audio force_audio; |
||
6084 | serge | 737 | bool limited_color_range; |
3480 | Serge | 738 | bool color_range_auto; |
3031 | serge | 739 | uint8_t dpcd[DP_RECEIVER_CAP_SIZE]; |
4104 | Serge | 740 | uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE]; |
3031 | serge | 741 | uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS]; |
6084 | serge | 742 | /* sink rates as reported by DP_SUPPORTED_LINK_RATES */ |
743 | uint8_t num_sink_rates; |
||
744 | int sink_rates[DP_MAX_SUPPORTED_RATES]; |
||
745 | struct sink_crc sink_crc; |
||
5060 | serge | 746 | struct drm_dp_aux aux; |
3031 | serge | 747 | uint8_t train_set[4]; |
748 | int panel_power_up_delay; |
||
749 | int panel_power_down_delay; |
||
750 | int panel_power_cycle_delay; |
||
751 | int backlight_on_delay; |
||
752 | int backlight_off_delay; |
||
753 | struct delayed_work panel_vdd_work; |
||
754 | bool want_panel_vdd; |
||
5060 | serge | 755 | unsigned long last_power_cycle; |
756 | unsigned long last_power_on; |
||
757 | unsigned long last_backlight_off; |
||
758 | |||
5354 | serge | 759 | /* |
760 | * Pipe whose power sequencer is currently locked into |
||
761 | * this port. Only relevant on VLV/CHV. |
||
762 | */ |
||
763 | enum pipe pps_pipe; |
||
764 | struct edp_power_seq pps_delays; |
||
765 | |||
5060 | serge | 766 | bool can_mst; /* this port supports mst */ |
767 | bool is_mst; |
||
768 | int active_mst_links; |
||
769 | /* connector directly attached - won't be use for modeset in mst world */ |
||
3243 | Serge | 770 | struct intel_connector *attached_connector; |
5060 | serge | 771 | |
772 | /* mst connector list */ |
||
773 | struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES]; |
||
774 | struct drm_dp_mst_topology_mgr mst_mgr; |
||
775 | |||
776 | uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index); |
||
777 | /* |
||
778 | * This function returns the value we have to program the AUX_CTL |
||
779 | * register with to kick off an AUX transaction. |
||
780 | */ |
||
781 | uint32_t (*get_aux_send_ctl)(struct intel_dp *dp, |
||
782 | bool has_aux_irq, |
||
783 | int send_bytes, |
||
784 | uint32_t aux_clock_divider); |
||
785 | |||
6084 | serge | 786 | /* Displayport compliance testing */ |
787 | unsigned long compliance_test_type; |
||
788 | unsigned long compliance_test_data; |
||
789 | bool compliance_test_active; |
||
3031 | serge | 790 | }; |
791 | |||
3243 | Serge | 792 | struct intel_digital_port { |
793 | struct intel_encoder base; |
||
794 | enum port port; |
||
4104 | Serge | 795 | u32 saved_port_bits; |
3243 | Serge | 796 | struct intel_dp dp; |
797 | struct intel_hdmi hdmi; |
||
6084 | serge | 798 | enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool); |
799 | bool release_cl2_override; |
||
3243 | Serge | 800 | }; |
801 | |||
5060 | serge | 802 | struct intel_dp_mst_encoder { |
803 | struct intel_encoder base; |
||
804 | enum pipe pipe; |
||
805 | struct intel_digital_port *primary; |
||
806 | void *port; /* store this opaque as its illegal to dereference it */ |
||
807 | }; |
||
808 | |||
6084 | serge | 809 | static inline enum dpio_channel |
4104 | Serge | 810 | vlv_dport_to_channel(struct intel_digital_port *dport) |
811 | { |
||
812 | switch (dport->port) { |
||
813 | case PORT_B: |
||
5060 | serge | 814 | case PORT_D: |
4560 | Serge | 815 | return DPIO_CH0; |
4104 | Serge | 816 | case PORT_C: |
4560 | Serge | 817 | return DPIO_CH1; |
4104 | Serge | 818 | default: |
819 | BUG(); |
||
820 | } |
||
821 | } |
||
822 | |||
6084 | serge | 823 | static inline enum dpio_phy |
824 | vlv_dport_to_phy(struct intel_digital_port *dport) |
||
825 | { |
||
826 | switch (dport->port) { |
||
827 | case PORT_B: |
||
828 | case PORT_C: |
||
829 | return DPIO_PHY0; |
||
830 | case PORT_D: |
||
831 | return DPIO_PHY1; |
||
832 | default: |
||
833 | BUG(); |
||
834 | } |
||
835 | } |
||
836 | |||
837 | static inline enum dpio_channel |
||
5060 | serge | 838 | vlv_pipe_to_channel(enum pipe pipe) |
839 | { |
||
840 | switch (pipe) { |
||
841 | case PIPE_A: |
||
842 | case PIPE_C: |
||
843 | return DPIO_CH0; |
||
844 | case PIPE_B: |
||
845 | return DPIO_CH1; |
||
846 | default: |
||
847 | BUG(); |
||
848 | } |
||
849 | } |
||
850 | |||
2326 | Serge | 851 | static inline struct drm_crtc * |
852 | intel_get_crtc_for_pipe(struct drm_device *dev, int pipe) |
||
853 | { |
||
854 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
855 | return dev_priv->pipe_to_crtc_mapping[pipe]; |
||
856 | } |
||
857 | |||
858 | static inline struct drm_crtc * |
||
859 | intel_get_crtc_for_plane(struct drm_device *dev, int plane) |
||
860 | { |
||
861 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
862 | return dev_priv->plane_to_crtc_mapping[plane]; |
||
863 | } |
||
864 | |||
865 | struct intel_unpin_work { |
||
2360 | Serge | 866 | struct work_struct work; |
3243 | Serge | 867 | struct drm_crtc *crtc; |
6084 | serge | 868 | struct drm_framebuffer *old_fb; |
2326 | Serge | 869 | struct drm_i915_gem_object *pending_flip_obj; |
870 | struct drm_pending_vblank_event *event; |
||
3243 | Serge | 871 | atomic_t pending; |
872 | #define INTEL_FLIP_INACTIVE 0 |
||
873 | #define INTEL_FLIP_PENDING 1 |
||
874 | #define INTEL_FLIP_COMPLETE 2 |
||
5060 | serge | 875 | u32 flip_count; |
876 | u32 gtt_offset; |
||
6084 | serge | 877 | struct drm_i915_gem_request *flip_queued_req; |
878 | u32 flip_queued_vblank; |
||
879 | u32 flip_ready_vblank; |
||
2326 | Serge | 880 | bool enable_stall_check; |
881 | }; |
||
882 | |||
4560 | Serge | 883 | struct intel_load_detect_pipe { |
884 | struct drm_framebuffer *release_fb; |
||
885 | bool load_detect_temp; |
||
886 | int dpms_mode; |
||
887 | }; |
||
2326 | Serge | 888 | |
4560 | Serge | 889 | static inline struct intel_encoder * |
890 | intel_attached_encoder(struct drm_connector *connector) |
||
2326 | Serge | 891 | { |
892 | return to_intel_connector(connector)->encoder; |
||
893 | } |
||
894 | |||
3243 | Serge | 895 | static inline struct intel_digital_port * |
896 | enc_to_dig_port(struct drm_encoder *encoder) |
||
897 | { |
||
898 | return container_of(encoder, struct intel_digital_port, base.base); |
||
899 | } |
||
900 | |||
5060 | serge | 901 | static inline struct intel_dp_mst_encoder * |
902 | enc_to_mst(struct drm_encoder *encoder) |
||
903 | { |
||
904 | return container_of(encoder, struct intel_dp_mst_encoder, base.base); |
||
905 | } |
||
906 | |||
4104 | Serge | 907 | static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder) |
908 | { |
||
909 | return &enc_to_dig_port(encoder)->dp; |
||
910 | } |
||
911 | |||
3243 | Serge | 912 | static inline struct intel_digital_port * |
913 | dp_to_dig_port(struct intel_dp *intel_dp) |
||
914 | { |
||
915 | return container_of(intel_dp, struct intel_digital_port, dp); |
||
916 | } |
||
917 | |||
918 | static inline struct intel_digital_port * |
||
919 | hdmi_to_dig_port(struct intel_hdmi *intel_hdmi) |
||
920 | { |
||
921 | return container_of(intel_hdmi, struct intel_digital_port, hdmi); |
||
922 | } |
||
923 | |||
5354 | serge | 924 | /* |
925 | * Returns the number of planes for this pipe, ie the number of sprites + 1 |
||
926 | * (primary plane). This doesn't count the cursor plane then. |
||
927 | */ |
||
928 | static inline unsigned int intel_num_planes(struct intel_crtc *crtc) |
||
929 | { |
||
930 | return INTEL_INFO(crtc->base.dev)->num_sprites[crtc->pipe] + 1; |
||
931 | } |
||
4560 | Serge | 932 | |
5354 | serge | 933 | /* intel_fifo_underrun.c */ |
934 | bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv, |
||
4560 | Serge | 935 | enum pipe pipe, bool enable); |
5354 | serge | 936 | bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv, |
4560 | Serge | 937 | enum transcoder pch_transcoder, |
938 | bool enable); |
||
5354 | serge | 939 | void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv, |
940 | enum pipe pipe); |
||
941 | void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv, |
||
942 | enum transcoder pch_transcoder); |
||
943 | void i9xx_check_fifo_underruns(struct drm_i915_private *dev_priv); |
||
944 | |||
945 | /* i915_irq.c */ |
||
5060 | serge | 946 | void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask); |
947 | void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask); |
||
948 | void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask); |
||
949 | void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask); |
||
5354 | serge | 950 | void gen6_reset_rps_interrupts(struct drm_device *dev); |
951 | void gen6_enable_rps_interrupts(struct drm_device *dev); |
||
952 | void gen6_disable_rps_interrupts(struct drm_device *dev); |
||
6084 | serge | 953 | u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask); |
5354 | serge | 954 | void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv); |
955 | void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv); |
||
5060 | serge | 956 | static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv) |
957 | { |
||
958 | /* |
||
959 | * We only use drm_irq_uninstall() at unload and VT switch, so |
||
960 | * this is the only thing we need to check. |
||
961 | */ |
||
5354 | serge | 962 | return dev_priv->pm.irqs_enabled; |
5060 | serge | 963 | } |
4560 | Serge | 964 | |
5060 | serge | 965 | int intel_get_crtc_scanline(struct intel_crtc *crtc); |
6084 | serge | 966 | void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv, |
967 | unsigned int pipe_mask); |
||
4560 | Serge | 968 | |
969 | /* intel_crt.c */ |
||
970 | void intel_crt_init(struct drm_device *dev); |
||
971 | |||
972 | |||
973 | /* intel_ddi.c */ |
||
974 | void intel_prepare_ddi(struct drm_device *dev); |
||
975 | void hsw_fdi_link_train(struct drm_crtc *crtc); |
||
976 | void intel_ddi_init(struct drm_device *dev, enum port port); |
||
977 | enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder); |
||
978 | bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe); |
||
979 | void intel_ddi_pll_init(struct drm_device *dev); |
||
980 | void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc); |
||
981 | void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv, |
||
982 | enum transcoder cpu_transcoder); |
||
983 | void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc); |
||
984 | void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc); |
||
6084 | serge | 985 | bool intel_ddi_pll_select(struct intel_crtc *crtc, |
986 | struct intel_crtc_state *crtc_state); |
||
4560 | Serge | 987 | void intel_ddi_set_pipe_settings(struct drm_crtc *crtc); |
988 | void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder); |
||
989 | bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector); |
||
990 | void intel_ddi_fdi_disable(struct drm_crtc *crtc); |
||
991 | void intel_ddi_get_config(struct intel_encoder *encoder, |
||
6084 | serge | 992 | struct intel_crtc_state *pipe_config); |
993 | struct intel_encoder * |
||
994 | intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state); |
||
4560 | Serge | 995 | |
5060 | serge | 996 | void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder); |
997 | void intel_ddi_clock_get(struct intel_encoder *encoder, |
||
6084 | serge | 998 | struct intel_crtc_state *pipe_config); |
5060 | serge | 999 | void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state); |
6084 | serge | 1000 | uint32_t ddi_signal_levels(struct intel_dp *intel_dp); |
4560 | Serge | 1001 | |
5354 | serge | 1002 | /* intel_frontbuffer.c */ |
5060 | serge | 1003 | void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj, |
6084 | serge | 1004 | enum fb_op_origin origin); |
5060 | serge | 1005 | void intel_frontbuffer_flip_prepare(struct drm_device *dev, |
1006 | unsigned frontbuffer_bits); |
||
1007 | void intel_frontbuffer_flip_complete(struct drm_device *dev, |
||
1008 | unsigned frontbuffer_bits); |
||
1009 | void intel_frontbuffer_flip(struct drm_device *dev, |
||
6084 | serge | 1010 | unsigned frontbuffer_bits); |
1011 | unsigned int intel_fb_align_height(struct drm_device *dev, |
||
1012 | unsigned int height, |
||
1013 | uint32_t pixel_format, |
||
1014 | uint64_t fb_format_modifier); |
||
1015 | void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire, |
||
1016 | enum fb_op_origin origin); |
||
1017 | u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier, |
||
1018 | uint32_t pixel_format); |
||
5060 | serge | 1019 | |
5354 | serge | 1020 | /* intel_audio.c */ |
1021 | void intel_init_audio(struct drm_device *dev); |
||
1022 | void intel_audio_codec_enable(struct intel_encoder *encoder); |
||
1023 | void intel_audio_codec_disable(struct intel_encoder *encoder); |
||
6084 | serge | 1024 | void i915_audio_component_init(struct drm_i915_private *dev_priv); |
1025 | void i915_audio_component_cleanup(struct drm_i915_private *dev_priv); |
||
5354 | serge | 1026 | |
1027 | /* intel_display.c */ |
||
6084 | serge | 1028 | extern const struct drm_plane_funcs intel_plane_funcs; |
5354 | serge | 1029 | bool intel_has_pending_fb_unpin(struct drm_device *dev); |
1030 | int intel_pch_rawclk(struct drm_device *dev); |
||
6084 | serge | 1031 | int intel_hrawclk(struct drm_device *dev); |
5354 | serge | 1032 | void intel_mark_busy(struct drm_device *dev); |
4560 | Serge | 1033 | void intel_mark_idle(struct drm_device *dev); |
1034 | void intel_crtc_restore_mode(struct drm_crtc *crtc); |
||
6084 | serge | 1035 | int intel_display_suspend(struct drm_device *dev); |
4560 | Serge | 1036 | void intel_encoder_destroy(struct drm_encoder *encoder); |
6084 | serge | 1037 | int intel_connector_init(struct intel_connector *); |
1038 | struct intel_connector *intel_connector_alloc(void); |
||
4560 | Serge | 1039 | bool intel_connector_get_hw_state(struct intel_connector *connector); |
1040 | void intel_connector_attach_encoder(struct intel_connector *connector, |
||
6084 | serge | 1041 | struct intel_encoder *encoder); |
4560 | Serge | 1042 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector); |
1043 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, |
||
6084 | serge | 1044 | struct drm_crtc *crtc); |
4560 | Serge | 1045 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector); |
2326 | Serge | 1046 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
1047 | struct drm_file *file_priv); |
||
4560 | Serge | 1048 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
6084 | serge | 1049 | enum pipe pipe); |
5354 | serge | 1050 | bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type); |
1051 | static inline void |
||
1052 | intel_wait_for_vblank(struct drm_device *dev, int pipe) |
||
1053 | { |
||
1054 | drm_wait_one_vblank(dev, pipe); |
||
1055 | } |
||
4560 | Serge | 1056 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp); |
1057 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
||
6084 | serge | 1058 | struct intel_digital_port *dport, |
1059 | unsigned int expected_mask); |
||
4560 | Serge | 1060 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
6084 | serge | 1061 | struct drm_display_mode *mode, |
5060 | serge | 1062 | struct intel_load_detect_pipe *old, |
1063 | struct drm_modeset_acquire_ctx *ctx); |
||
4560 | Serge | 1064 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
6084 | serge | 1065 | struct intel_load_detect_pipe *old, |
1066 | struct drm_modeset_acquire_ctx *ctx); |
||
5354 | serge | 1067 | int intel_pin_and_fence_fb_obj(struct drm_plane *plane, |
1068 | struct drm_framebuffer *fb, |
||
6084 | serge | 1069 | const struct drm_plane_state *plane_state, |
1070 | struct intel_engine_cs *pipelined, |
||
1071 | struct drm_i915_gem_request **pipelined_request); |
||
5060 | serge | 1072 | struct drm_framebuffer * |
1073 | __intel_framebuffer_create(struct drm_device *dev, |
||
6084 | serge | 1074 | struct drm_mode_fb_cmd2 *mode_cmd, |
1075 | struct drm_i915_gem_object *obj); |
||
4560 | Serge | 1076 | void intel_prepare_page_flip(struct drm_device *dev, int plane); |
1077 | void intel_finish_page_flip(struct drm_device *dev, int pipe); |
||
1078 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane); |
||
5354 | serge | 1079 | void intel_check_page_flip(struct drm_device *dev, int pipe); |
6084 | serge | 1080 | int intel_prepare_plane_fb(struct drm_plane *plane, |
1081 | const struct drm_plane_state *new_state); |
||
1082 | void intel_cleanup_plane_fb(struct drm_plane *plane, |
||
1083 | const struct drm_plane_state *old_state); |
||
1084 | int intel_plane_atomic_get_property(struct drm_plane *plane, |
||
1085 | const struct drm_plane_state *state, |
||
1086 | struct drm_property *property, |
||
1087 | uint64_t *val); |
||
1088 | int intel_plane_atomic_set_property(struct drm_plane *plane, |
||
1089 | struct drm_plane_state *state, |
||
1090 | struct drm_property *property, |
||
1091 | uint64_t val); |
||
1092 | int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state, |
||
1093 | struct drm_plane_state *plane_state); |
||
5060 | serge | 1094 | |
6084 | serge | 1095 | unsigned int |
1096 | intel_tile_height(struct drm_device *dev, uint32_t pixel_format, |
||
1097 | uint64_t fb_format_modifier, unsigned int plane); |
||
1098 | |||
1099 | static inline bool |
||
1100 | intel_rotation_90_or_270(unsigned int rotation) |
||
1101 | { |
||
1102 | return rotation & (BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270)); |
||
1103 | } |
||
1104 | |||
1105 | void intel_create_rotation_property(struct drm_device *dev, |
||
1106 | struct intel_plane *plane); |
||
1107 | |||
5060 | serge | 1108 | /* shared dpll functions */ |
4560 | Serge | 1109 | struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc); |
4104 | Serge | 1110 | void assert_shared_dpll(struct drm_i915_private *dev_priv, |
1111 | struct intel_shared_dpll *pll, |
||
1112 | bool state); |
||
1113 | #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true) |
||
1114 | #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false) |
||
6084 | serge | 1115 | struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc, |
1116 | struct intel_crtc_state *state); |
||
5060 | serge | 1117 | |
5354 | serge | 1118 | void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe, |
1119 | const struct dpll *dpll); |
||
1120 | void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe); |
||
1121 | |||
5060 | serge | 1122 | /* modesetting asserts */ |
5354 | serge | 1123 | void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1124 | enum pipe pipe); |
||
4104 | Serge | 1125 | void assert_pll(struct drm_i915_private *dev_priv, |
1126 | enum pipe pipe, bool state); |
||
1127 | #define assert_pll_enabled(d, p) assert_pll(d, p, true) |
||
1128 | #define assert_pll_disabled(d, p) assert_pll(d, p, false) |
||
1129 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
||
1130 | enum pipe pipe, bool state); |
||
1131 | #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true) |
||
1132 | #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false) |
||
4560 | Serge | 1133 | void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state); |
2342 | Serge | 1134 | #define assert_pipe_enabled(d, p) assert_pipe(d, p, true) |
1135 | #define assert_pipe_disabled(d, p) assert_pipe(d, p, false) |
||
6084 | serge | 1136 | unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv, |
1137 | int *x, int *y, |
||
1138 | unsigned int tiling_mode, |
||
1139 | unsigned int bpp, |
||
1140 | unsigned int pitch); |
||
5354 | serge | 1141 | void intel_prepare_reset(struct drm_device *dev); |
1142 | void intel_finish_reset(struct drm_device *dev); |
||
5060 | serge | 1143 | void hsw_enable_pc8(struct drm_i915_private *dev_priv); |
1144 | void hsw_disable_pc8(struct drm_i915_private *dev_priv); |
||
6084 | serge | 1145 | void broxton_init_cdclk(struct drm_device *dev); |
1146 | void broxton_uninit_cdclk(struct drm_device *dev); |
||
1147 | void broxton_ddi_phy_init(struct drm_device *dev); |
||
1148 | void broxton_ddi_phy_uninit(struct drm_device *dev); |
||
1149 | void bxt_enable_dc9(struct drm_i915_private *dev_priv); |
||
1150 | void bxt_disable_dc9(struct drm_i915_private *dev_priv); |
||
1151 | void skl_init_cdclk(struct drm_i915_private *dev_priv); |
||
1152 | void skl_uninit_cdclk(struct drm_i915_private *dev_priv); |
||
4560 | Serge | 1153 | void intel_dp_get_m_n(struct intel_crtc *crtc, |
6084 | serge | 1154 | struct intel_crtc_state *pipe_config); |
1155 | void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n); |
||
4560 | Serge | 1156 | int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n); |
1157 | void |
||
6084 | serge | 1158 | ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config, |
4560 | Serge | 1159 | int dotclock); |
6084 | serge | 1160 | bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock, |
1161 | intel_clock_t *best_clock); |
||
1162 | int chv_calc_dpll_params(int refclk, intel_clock_t *pll_clock); |
||
1163 | |||
4560 | Serge | 1164 | bool intel_crtc_active(struct drm_crtc *crtc); |
1165 | void hsw_enable_ips(struct intel_crtc *crtc); |
||
1166 | void hsw_disable_ips(struct intel_crtc *crtc); |
||
5060 | serge | 1167 | enum intel_display_power_domain |
1168 | intel_display_port_power_domain(struct intel_encoder *intel_encoder); |
||
6084 | serge | 1169 | enum intel_display_power_domain |
1170 | intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder); |
||
5060 | serge | 1171 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
6084 | serge | 1172 | struct intel_crtc_state *pipe_config); |
5060 | serge | 1173 | void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc); |
5354 | serge | 1174 | void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file); |
3243 | Serge | 1175 | |
6084 | serge | 1176 | int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state); |
1177 | int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state); |
||
1178 | |||
6660 | serge | 1179 | u32 intel_plane_obj_offset(struct intel_plane *intel_plane, |
6084 | serge | 1180 | struct drm_i915_gem_object *obj, |
1181 | unsigned int plane); |
||
1182 | |||
1183 | u32 skl_plane_ctl_format(uint32_t pixel_format); |
||
1184 | u32 skl_plane_ctl_tiling(uint64_t fb_modifier); |
||
1185 | u32 skl_plane_ctl_rotation(unsigned int rotation); |
||
1186 | |||
1187 | /* intel_csr.c */ |
||
1188 | void intel_csr_ucode_init(struct drm_device *dev); |
||
1189 | enum csr_state intel_csr_load_status_get(struct drm_i915_private *dev_priv); |
||
1190 | void intel_csr_load_status_set(struct drm_i915_private *dev_priv, |
||
1191 | enum csr_state state); |
||
1192 | void intel_csr_load_program(struct drm_device *dev); |
||
1193 | void intel_csr_ucode_fini(struct drm_device *dev); |
||
1194 | void assert_csr_loaded(struct drm_i915_private *dev_priv); |
||
1195 | |||
4560 | Serge | 1196 | /* intel_dp.c */ |
6660 | serge | 1197 | bool intel_dp_init(struct drm_device *dev, int output_reg, enum port port); |
4560 | Serge | 1198 | bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port, |
1199 | struct intel_connector *intel_connector); |
||
6084 | serge | 1200 | void intel_dp_set_link_params(struct intel_dp *intel_dp, |
1201 | const struct intel_crtc_state *pipe_config); |
||
4560 | Serge | 1202 | void intel_dp_start_link_train(struct intel_dp *intel_dp); |
1203 | void intel_dp_stop_link_train(struct intel_dp *intel_dp); |
||
1204 | void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode); |
||
6660 | serge | 1205 | void intel_dp_encoder_reset(struct drm_encoder *encoder); |
1206 | void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder); |
||
4560 | Serge | 1207 | void intel_dp_encoder_destroy(struct drm_encoder *encoder); |
5060 | serge | 1208 | int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc); |
4560 | Serge | 1209 | bool intel_dp_compute_config(struct intel_encoder *encoder, |
6084 | serge | 1210 | struct intel_crtc_state *pipe_config); |
4560 | Serge | 1211 | bool intel_dp_is_edp(struct drm_device *dev, enum port port); |
6084 | serge | 1212 | enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, |
1213 | bool long_hpd); |
||
5060 | serge | 1214 | void intel_edp_backlight_on(struct intel_dp *intel_dp); |
1215 | void intel_edp_backlight_off(struct intel_dp *intel_dp); |
||
1216 | void intel_edp_panel_vdd_on(struct intel_dp *intel_dp); |
||
1217 | void intel_edp_panel_on(struct intel_dp *intel_dp); |
||
1218 | void intel_edp_panel_off(struct intel_dp *intel_dp); |
||
1219 | void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector); |
||
1220 | void intel_dp_mst_suspend(struct drm_device *dev); |
||
1221 | void intel_dp_mst_resume(struct drm_device *dev); |
||
6084 | serge | 1222 | int intel_dp_max_link_rate(struct intel_dp *intel_dp); |
1223 | int intel_dp_rate_select(struct intel_dp *intel_dp, int rate); |
||
5060 | serge | 1224 | void intel_dp_hot_plug(struct intel_encoder *intel_encoder); |
5354 | serge | 1225 | void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv); |
1226 | uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes); |
||
6084 | serge | 1227 | void intel_plane_destroy(struct drm_plane *plane); |
1228 | void intel_edp_drrs_enable(struct intel_dp *intel_dp); |
||
1229 | void intel_edp_drrs_disable(struct intel_dp *intel_dp); |
||
1230 | void intel_edp_drrs_invalidate(struct drm_device *dev, |
||
1231 | unsigned frontbuffer_bits); |
||
1232 | void intel_edp_drrs_flush(struct drm_device *dev, unsigned frontbuffer_bits); |
||
1233 | bool intel_digital_port_connected(struct drm_i915_private *dev_priv, |
||
1234 | struct intel_digital_port *port); |
||
1235 | void hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config); |
||
5354 | serge | 1236 | |
5060 | serge | 1237 | /* intel_dp_mst.c */ |
1238 | int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id); |
||
1239 | void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port); |
||
4560 | Serge | 1240 | /* intel_dsi.c */ |
5060 | serge | 1241 | void intel_dsi_init(struct drm_device *dev); |
4560 | Serge | 1242 | |
1243 | |||
1244 | /* intel_dvo.c */ |
||
1245 | void intel_dvo_init(struct drm_device *dev); |
||
1246 | |||
1247 | |||
1248 | /* legacy fbdev emulation in intel_fbdev.c */ |
||
6084 | serge | 1249 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
4560 | Serge | 1250 | extern int intel_fbdev_init(struct drm_device *dev); |
5354 | serge | 1251 | extern void intel_fbdev_initial_config(void *data, async_cookie_t cookie); |
4560 | Serge | 1252 | extern void intel_fbdev_fini(struct drm_device *dev); |
5354 | serge | 1253 | extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous); |
4560 | Serge | 1254 | extern void intel_fbdev_output_poll_changed(struct drm_device *dev); |
1255 | extern void intel_fbdev_restore_mode(struct drm_device *dev); |
||
1256 | #else |
||
1257 | static inline int intel_fbdev_init(struct drm_device *dev) |
||
1258 | { |
||
1259 | return 0; |
||
1260 | } |
||
1261 | |||
5354 | serge | 1262 | static inline void intel_fbdev_initial_config(void *data, async_cookie_t cookie) |
4560 | Serge | 1263 | { |
1264 | } |
||
1265 | |||
1266 | static inline void intel_fbdev_fini(struct drm_device *dev) |
||
1267 | { |
||
1268 | } |
||
1269 | |||
5354 | serge | 1270 | static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous) |
4560 | Serge | 1271 | { |
1272 | } |
||
1273 | |||
1274 | static inline void intel_fbdev_restore_mode(struct drm_device *dev) |
||
1275 | { |
||
1276 | } |
||
1277 | #endif |
||
1278 | |||
6084 | serge | 1279 | /* intel_fbc.c */ |
1280 | bool intel_fbc_enabled(struct drm_i915_private *dev_priv); |
||
1281 | void intel_fbc_update(struct drm_i915_private *dev_priv); |
||
1282 | void intel_fbc_init(struct drm_i915_private *dev_priv); |
||
1283 | void intel_fbc_disable(struct drm_i915_private *dev_priv); |
||
1284 | void intel_fbc_disable_crtc(struct intel_crtc *crtc); |
||
1285 | void intel_fbc_invalidate(struct drm_i915_private *dev_priv, |
||
1286 | unsigned int frontbuffer_bits, |
||
1287 | enum fb_op_origin origin); |
||
1288 | void intel_fbc_flush(struct drm_i915_private *dev_priv, |
||
1289 | unsigned int frontbuffer_bits, enum fb_op_origin origin); |
||
1290 | const char *intel_no_fbc_reason_str(enum no_fbc_reason reason); |
||
1291 | void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv); |
||
1292 | |||
4560 | Serge | 1293 | /* intel_hdmi.c */ |
1294 | void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port); |
||
1295 | void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, |
||
1296 | struct intel_connector *intel_connector); |
||
1297 | struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder); |
||
1298 | bool intel_hdmi_compute_config(struct intel_encoder *encoder, |
||
6084 | serge | 1299 | struct intel_crtc_state *pipe_config); |
4560 | Serge | 1300 | |
1301 | |||
1302 | /* intel_lvds.c */ |
||
1303 | void intel_lvds_init(struct drm_device *dev); |
||
1304 | bool intel_is_dual_link_lvds(struct drm_device *dev); |
||
1305 | |||
1306 | |||
1307 | /* intel_modes.c */ |
||
1308 | int intel_connector_update_modes(struct drm_connector *connector, |
||
1309 | struct edid *edid); |
||
1310 | int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter); |
||
1311 | void intel_attach_force_audio_property(struct drm_connector *connector); |
||
1312 | void intel_attach_broadcast_rgb_property(struct drm_connector *connector); |
||
6084 | serge | 1313 | void intel_attach_aspect_ratio_property(struct drm_connector *connector); |
4560 | Serge | 1314 | |
1315 | |||
1316 | /* intel_overlay.c */ |
||
1317 | void intel_setup_overlay(struct drm_device *dev); |
||
1318 | void intel_cleanup_overlay(struct drm_device *dev); |
||
1319 | int intel_overlay_switch_off(struct intel_overlay *overlay); |
||
1320 | int intel_overlay_put_image(struct drm_device *dev, void *data, |
||
6084 | serge | 1321 | struct drm_file *file_priv); |
4560 | Serge | 1322 | int intel_overlay_attrs(struct drm_device *dev, void *data, |
6084 | serge | 1323 | struct drm_file *file_priv); |
1324 | void intel_overlay_reset(struct drm_i915_private *dev_priv); |
||
2342 | Serge | 1325 | |
3031 | serge | 1326 | |
4560 | Serge | 1327 | /* intel_panel.c */ |
1328 | int intel_panel_init(struct intel_panel *panel, |
||
5060 | serge | 1329 | struct drm_display_mode *fixed_mode, |
1330 | struct drm_display_mode *downclock_mode); |
||
4560 | Serge | 1331 | void intel_panel_fini(struct intel_panel *panel); |
1332 | void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode, |
||
1333 | struct drm_display_mode *adjusted_mode); |
||
1334 | void intel_pch_panel_fitting(struct intel_crtc *crtc, |
||
6084 | serge | 1335 | struct intel_crtc_state *pipe_config, |
4560 | Serge | 1336 | int fitting_mode); |
1337 | void intel_gmch_panel_fitting(struct intel_crtc *crtc, |
||
6084 | serge | 1338 | struct intel_crtc_state *pipe_config, |
4560 | Serge | 1339 | int fitting_mode); |
5060 | serge | 1340 | void intel_panel_set_backlight_acpi(struct intel_connector *connector, |
1341 | u32 level, u32 max); |
||
5354 | serge | 1342 | int intel_panel_setup_backlight(struct drm_connector *connector, enum pipe pipe); |
4560 | Serge | 1343 | void intel_panel_enable_backlight(struct intel_connector *connector); |
1344 | void intel_panel_disable_backlight(struct intel_connector *connector); |
||
1345 | void intel_panel_destroy_backlight(struct drm_connector *connector); |
||
1346 | enum drm_connector_status intel_panel_detect(struct drm_device *dev); |
||
1347 | extern struct drm_display_mode *intel_find_panel_downclock( |
||
1348 | struct drm_device *dev, |
||
1349 | struct drm_display_mode *fixed_mode, |
||
1350 | struct drm_connector *connector); |
||
5354 | serge | 1351 | void intel_backlight_register(struct drm_device *dev); |
1352 | void intel_backlight_unregister(struct drm_device *dev); |
||
4104 | Serge | 1353 | |
5354 | serge | 1354 | |
1355 | /* intel_psr.c */ |
||
1356 | void intel_psr_enable(struct intel_dp *intel_dp); |
||
1357 | void intel_psr_disable(struct intel_dp *intel_dp); |
||
1358 | void intel_psr_invalidate(struct drm_device *dev, |
||
6084 | serge | 1359 | unsigned frontbuffer_bits); |
5354 | serge | 1360 | void intel_psr_flush(struct drm_device *dev, |
6084 | serge | 1361 | unsigned frontbuffer_bits, |
1362 | enum fb_op_origin origin); |
||
5354 | serge | 1363 | void intel_psr_init(struct drm_device *dev); |
6084 | serge | 1364 | void intel_psr_single_frame_update(struct drm_device *dev, |
1365 | unsigned frontbuffer_bits); |
||
5354 | serge | 1366 | |
1367 | /* intel_runtime_pm.c */ |
||
1368 | int intel_power_domains_init(struct drm_i915_private *); |
||
1369 | void intel_power_domains_fini(struct drm_i915_private *); |
||
1370 | void intel_power_domains_init_hw(struct drm_i915_private *dev_priv); |
||
1371 | void intel_runtime_pm_enable(struct drm_i915_private *dev_priv); |
||
1372 | |||
1373 | bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv, |
||
1374 | enum intel_display_power_domain domain); |
||
1375 | bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv, |
||
1376 | enum intel_display_power_domain domain); |
||
1377 | void intel_display_power_get(struct drm_i915_private *dev_priv, |
||
1378 | enum intel_display_power_domain domain); |
||
1379 | void intel_display_power_put(struct drm_i915_private *dev_priv, |
||
1380 | enum intel_display_power_domain domain); |
||
1381 | void intel_runtime_pm_get(struct drm_i915_private *dev_priv); |
||
1382 | void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv); |
||
1383 | void intel_runtime_pm_put(struct drm_i915_private *dev_priv); |
||
1384 | |||
1385 | void intel_display_set_init_power(struct drm_i915_private *dev, bool enable); |
||
1386 | |||
6084 | serge | 1387 | void chv_phy_powergate_lanes(struct intel_encoder *encoder, |
1388 | bool override, unsigned int mask); |
||
1389 | bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy, |
||
1390 | enum dpio_channel ch, bool override); |
||
1391 | |||
1392 | |||
4560 | Serge | 1393 | /* intel_pm.c */ |
1394 | void intel_init_clock_gating(struct drm_device *dev); |
||
1395 | void intel_suspend_hw(struct drm_device *dev); |
||
5060 | serge | 1396 | int ilk_wm_max_level(const struct drm_device *dev); |
4560 | Serge | 1397 | void intel_update_watermarks(struct drm_crtc *crtc); |
1398 | void intel_update_sprite_watermarks(struct drm_plane *plane, |
||
1399 | struct drm_crtc *crtc, |
||
5060 | serge | 1400 | uint32_t sprite_width, |
1401 | uint32_t sprite_height, |
||
1402 | int pixel_size, |
||
4560 | Serge | 1403 | bool enabled, bool scaled); |
1404 | void intel_init_pm(struct drm_device *dev); |
||
1405 | void intel_pm_setup(struct drm_device *dev); |
||
1406 | void intel_gpu_ips_init(struct drm_i915_private *dev_priv); |
||
1407 | void intel_gpu_ips_teardown(void); |
||
5060 | serge | 1408 | void intel_init_gt_powersave(struct drm_device *dev); |
1409 | void intel_cleanup_gt_powersave(struct drm_device *dev); |
||
4560 | Serge | 1410 | void intel_enable_gt_powersave(struct drm_device *dev); |
1411 | void intel_disable_gt_powersave(struct drm_device *dev); |
||
5060 | serge | 1412 | void intel_suspend_gt_powersave(struct drm_device *dev); |
1413 | void intel_reset_gt_powersave(struct drm_device *dev); |
||
4104 | Serge | 1414 | void gen6_update_ring_freq(struct drm_device *dev); |
6084 | serge | 1415 | void gen6_rps_busy(struct drm_i915_private *dev_priv); |
1416 | void gen6_rps_reset_ei(struct drm_i915_private *dev_priv); |
||
4560 | Serge | 1417 | void gen6_rps_idle(struct drm_i915_private *dev_priv); |
6084 | serge | 1418 | void gen6_rps_boost(struct drm_i915_private *dev_priv, |
1419 | struct intel_rps_client *rps, |
||
1420 | unsigned long submitted); |
||
1421 | void intel_queue_rps_boost_for_request(struct drm_device *dev, |
||
1422 | struct drm_i915_gem_request *req); |
||
1423 | void vlv_wm_get_hw_state(struct drm_device *dev); |
||
4560 | Serge | 1424 | void ilk_wm_get_hw_state(struct drm_device *dev); |
5354 | serge | 1425 | void skl_wm_get_hw_state(struct drm_device *dev); |
1426 | void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv, |
||
1427 | struct skl_ddb_allocation *ddb /* out */); |
||
6084 | serge | 1428 | uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config); |
3031 | serge | 1429 | |
4560 | Serge | 1430 | /* intel_sdvo.c */ |
1431 | bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob); |
||
3746 | Serge | 1432 | |
4104 | Serge | 1433 | |
4560 | Serge | 1434 | /* intel_sprite.c */ |
1435 | int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane); |
||
1436 | int intel_sprite_set_colorkey(struct drm_device *dev, void *data, |
||
1437 | struct drm_file *file_priv); |
||
6084 | serge | 1438 | void intel_pipe_update_start(struct intel_crtc *crtc); |
1439 | void intel_pipe_update_end(struct intel_crtc *crtc); |
||
4560 | Serge | 1440 | |
1441 | /* intel_tv.c */ |
||
1442 | void intel_tv_init(struct drm_device *dev); |
||
1443 | |||
6084 | serge | 1444 | /* intel_atomic.c */ |
1445 | int intel_connector_atomic_get_property(struct drm_connector *connector, |
||
1446 | const struct drm_connector_state *state, |
||
1447 | struct drm_property *property, |
||
1448 | uint64_t *val); |
||
1449 | struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc); |
||
1450 | void intel_crtc_destroy_state(struct drm_crtc *crtc, |
||
1451 | struct drm_crtc_state *state); |
||
1452 | struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev); |
||
1453 | void intel_atomic_state_clear(struct drm_atomic_state *); |
||
1454 | struct intel_shared_dpll_config * |
||
1455 | intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s); |
||
1456 | |||
1457 | static inline struct intel_crtc_state * |
||
1458 | intel_atomic_get_crtc_state(struct drm_atomic_state *state, |
||
1459 | struct intel_crtc *crtc) |
||
1460 | { |
||
1461 | struct drm_crtc_state *crtc_state; |
||
1462 | crtc_state = drm_atomic_get_crtc_state(state, &crtc->base); |
||
1463 | if (IS_ERR(crtc_state)) |
||
1464 | return ERR_CAST(crtc_state); |
||
1465 | |||
1466 | return to_intel_crtc_state(crtc_state); |
||
1467 | } |
||
1468 | int intel_atomic_setup_scalers(struct drm_device *dev, |
||
1469 | struct intel_crtc *intel_crtc, |
||
1470 | struct intel_crtc_state *crtc_state); |
||
1471 | |||
1472 | /* intel_atomic_plane.c */ |
||
1473 | struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane); |
||
1474 | struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane); |
||
1475 | void intel_plane_destroy_state(struct drm_plane *plane, |
||
1476 | struct drm_plane_state *state); |
||
1477 | extern const struct drm_plane_helper_funcs intel_plane_helper_funcs; |
||
1478 | |||
2326 | Serge | 1479 | #endif /* __INTEL_DRV_H__ */0)><0)> |