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Rev | Author | Line No. | Line |
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2326 | Serge | 1 | /* |
2 | * Copyright (c) 2006 Dave Airlie |
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3 | * Copyright (c) 2007-2008 Intel Corporation |
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4 | * Jesse Barnes |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the "Software"), |
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8 | * to deal in the Software without restriction, including without limitation |
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9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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10 | * and/or sell copies of the Software, and to permit persons to whom the |
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11 | * Software is furnished to do so, subject to the following conditions: |
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12 | * |
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13 | * The above copyright notice and this permission notice (including the next |
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14 | * paragraph) shall be included in all copies or substantial portions of the |
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15 | * Software. |
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16 | * |
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17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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22 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
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23 | * IN THE SOFTWARE. |
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24 | */ |
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25 | #ifndef __INTEL_DRV_H__ |
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26 | #define __INTEL_DRV_H__ |
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27 | |||
28 | #include |
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4104 | Serge | 29 | #include |
3031 | serge | 30 | #include |
2326 | Serge | 31 | #include "i915_drv.h" |
3031 | serge | 32 | #include |
33 | #include |
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34 | #include |
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35 | #include |
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2326 | Serge | 36 | |
3482 | Serge | 37 | #define KBUILD_MODNAME "i915.dll" |
38 | |||
3746 | Serge | 39 | |
3031 | serge | 40 | #define cpu_relax() asm volatile("rep; nop") |
41 | |||
3746 | Serge | 42 | /** |
43 | * _wait_for - magic (register) wait macro |
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44 | * |
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45 | * Does the right thing for modeset paths when run under kdgb or similar atomic |
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46 | * contexts. Note that it's important that we check the condition again after |
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47 | * having timed out, since the timeout could be due to preemption or similar and |
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48 | * we've never had a chance to check the condition before the timeout. |
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49 | */ |
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2326 | Serge | 50 | #define _wait_for(COND, MS, W) ({ \ |
3031 | serge | 51 | unsigned long timeout__ = GetTimerTicks() + msecs_to_jiffies(MS); \ |
2326 | Serge | 52 | int ret__ = 0; \ |
2342 | Serge | 53 | while (!(COND)) { \ |
3031 | serge | 54 | if (time_after(GetTimerTicks(), timeout__)) { \ |
3746 | Serge | 55 | if (!(COND)) \ |
2326 | Serge | 56 | ret__ = -ETIMEDOUT; \ |
57 | break; \ |
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58 | } \ |
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3031 | serge | 59 | if (W ) { \ |
60 | msleep(W); \ |
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61 | } else { \ |
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62 | cpu_relax(); \ |
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63 | } \ |
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2326 | Serge | 64 | } \ |
65 | ret__; \ |
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66 | }) |
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67 | |||
68 | #define wait_for(COND, MS) _wait_for(COND, MS, 1) |
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69 | #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0) |
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4104 | Serge | 70 | #define wait_for_atomic_us(COND, US) _wait_for((COND), \ |
71 | DIV_ROUND_UP((US), 1000), 0) |
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2326 | Serge | 72 | |
4560 | Serge | 73 | #define KHz(x) (1000 * (x)) |
74 | #define MHz(x) KHz(1000 * (x)) |
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2326 | Serge | 75 | |
76 | /* |
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77 | * Display related stuff |
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78 | */ |
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79 | |||
80 | /* store information about an Ixxx DVO */ |
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81 | /* The i830->i865 use multiple DVOs with multiple i2cs */ |
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82 | /* the i915, i945 have a single sDVO i2c bus - which is different */ |
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83 | #define MAX_OUTPUTS 6 |
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84 | /* maximum connectors per crtcs in the mode set */ |
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85 | |||
86 | #define INTEL_I2C_BUS_DVO 1 |
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87 | #define INTEL_I2C_BUS_SDVO 2 |
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88 | |||
89 | /* these are outputs from the chip - integrated only |
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90 | external chips are via DVO or SDVO output */ |
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91 | #define INTEL_OUTPUT_UNUSED 0 |
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92 | #define INTEL_OUTPUT_ANALOG 1 |
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93 | #define INTEL_OUTPUT_DVO 2 |
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94 | #define INTEL_OUTPUT_SDVO 3 |
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95 | #define INTEL_OUTPUT_LVDS 4 |
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96 | #define INTEL_OUTPUT_TVOUT 5 |
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97 | #define INTEL_OUTPUT_HDMI 6 |
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98 | #define INTEL_OUTPUT_DISPLAYPORT 7 |
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99 | #define INTEL_OUTPUT_EDP 8 |
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4560 | Serge | 100 | #define INTEL_OUTPUT_DSI 9 |
101 | #define INTEL_OUTPUT_UNKNOWN 10 |
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2326 | Serge | 102 | |
103 | #define INTEL_DVO_CHIP_NONE 0 |
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104 | #define INTEL_DVO_CHIP_LVDS 1 |
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105 | #define INTEL_DVO_CHIP_TMDS 2 |
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106 | #define INTEL_DVO_CHIP_TVOUT 4 |
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107 | |||
4560 | Serge | 108 | #define INTEL_DSI_COMMAND_MODE 0 |
109 | #define INTEL_DSI_VIDEO_MODE 1 |
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110 | |||
2326 | Serge | 111 | struct intel_framebuffer { |
112 | struct drm_framebuffer base; |
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113 | struct drm_i915_gem_object *obj; |
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114 | }; |
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115 | |||
116 | struct intel_fbdev { |
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117 | struct drm_fb_helper helper; |
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118 | struct intel_framebuffer ifb; |
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119 | struct list_head fbdev_list; |
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120 | struct drm_display_mode *our_mode; |
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121 | }; |
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122 | |||
123 | struct intel_encoder { |
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124 | struct drm_encoder base; |
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3031 | serge | 125 | /* |
126 | * The new crtc this encoder will be driven from. Only differs from |
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127 | * base->crtc while a modeset is in progress. |
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128 | */ |
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129 | struct intel_crtc *new_crtc; |
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130 | |||
2326 | Serge | 131 | int type; |
3031 | serge | 132 | /* |
133 | * Intel hw has only one MUX where encoders could be clone, hence a |
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134 | * simple flag is enough to compute the possible_clones mask. |
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135 | */ |
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136 | bool cloneable; |
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137 | bool connectors_active; |
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2326 | Serge | 138 | void (*hot_plug)(struct intel_encoder *); |
3746 | Serge | 139 | bool (*compute_config)(struct intel_encoder *, |
140 | struct intel_crtc_config *); |
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3480 | Serge | 141 | void (*pre_pll_enable)(struct intel_encoder *); |
3031 | serge | 142 | void (*pre_enable)(struct intel_encoder *); |
143 | void (*enable)(struct intel_encoder *); |
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3746 | Serge | 144 | void (*mode_set)(struct intel_encoder *intel_encoder); |
3031 | serge | 145 | void (*disable)(struct intel_encoder *); |
146 | void (*post_disable)(struct intel_encoder *); |
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147 | /* Read out the current hw state of this connector, returning true if |
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148 | * the encoder is active. If the encoder is enabled it also set the pipe |
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149 | * it is connected to in the pipe parameter. */ |
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150 | bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe); |
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4104 | Serge | 151 | /* Reconstructs the equivalent mode flags for the current hardware |
152 | * state. This must be called _after_ display->get_pipe_config has |
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153 | * pre-filled the pipe config. Note that intel_encoder->base.crtc must |
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154 | * be set correctly before calling this function. */ |
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155 | void (*get_config)(struct intel_encoder *, |
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156 | struct intel_crtc_config *pipe_config); |
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2326 | Serge | 157 | int crtc_mask; |
3746 | Serge | 158 | enum hpd_pin hpd_pin; |
2326 | Serge | 159 | }; |
160 | |||
3243 | Serge | 161 | struct intel_panel { |
162 | struct drm_display_mode *fixed_mode; |
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4560 | Serge | 163 | struct drm_display_mode *downclock_mode; |
3243 | Serge | 164 | int fitting_mode; |
4560 | Serge | 165 | |
166 | /* backlight */ |
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167 | struct { |
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168 | bool present; |
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169 | u32 level; |
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170 | u32 max; |
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171 | bool enabled; |
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172 | bool combination_mode; /* gen 2/4 only */ |
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173 | bool active_low_pwm; |
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174 | struct backlight_device *device; |
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175 | } backlight; |
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3243 | Serge | 176 | }; |
177 | |||
2326 | Serge | 178 | struct intel_connector { |
179 | struct drm_connector base; |
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3031 | serge | 180 | /* |
181 | * The fixed encoder this connector is connected to. |
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182 | */ |
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2326 | Serge | 183 | struct intel_encoder *encoder; |
3031 | serge | 184 | |
185 | /* |
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186 | * The new encoder this connector will be driven. Only differs from |
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187 | * encoder while a modeset is in progress. |
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188 | */ |
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189 | struct intel_encoder *new_encoder; |
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190 | |||
191 | /* Reads out the current hw, returning true if the connector is enabled |
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192 | * and active (i.e. dpms ON state). */ |
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193 | bool (*get_hw_state)(struct intel_connector *); |
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3243 | Serge | 194 | |
195 | /* Panel info for eDP and LVDS */ |
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196 | struct intel_panel panel; |
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197 | |||
198 | /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */ |
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199 | struct edid *edid; |
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3746 | Serge | 200 | |
201 | /* since POLL and HPD connectors may use the same HPD line keep the native |
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202 | state of connector->polled in case hotplug storm detection changes it */ |
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203 | u8 polled; |
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2326 | Serge | 204 | }; |
205 | |||
4104 | Serge | 206 | typedef struct dpll { |
207 | /* given values */ |
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208 | int n; |
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209 | int m1, m2; |
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210 | int p1, p2; |
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211 | /* derived values */ |
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212 | int dot; |
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213 | int vco; |
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214 | int m; |
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215 | int p; |
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216 | } intel_clock_t; |
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217 | |||
3746 | Serge | 218 | struct intel_crtc_config { |
4104 | Serge | 219 | /** |
220 | * quirks - bitfield with hw state readout quirks |
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221 | * |
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222 | * For various reasons the hw state readout code might not be able to |
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223 | * completely faithfully read out the current state. These cases are |
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224 | * tracked with quirk flags so that fastboot and state checker can act |
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225 | * accordingly. |
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226 | */ |
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227 | #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */ |
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228 | unsigned long quirks; |
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229 | |||
4560 | Serge | 230 | /* User requested mode, only valid as a starting point to |
231 | * compute adjusted_mode, except in the case of (S)DVO where |
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232 | * it's also for the output timings of the (S)DVO chip. |
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233 | * adjusted_mode will then correspond to the S(DVO) chip's |
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234 | * preferred input timings. */ |
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3746 | Serge | 235 | struct drm_display_mode requested_mode; |
4560 | Serge | 236 | /* Actual pipe timings ie. what we program into the pipe timing |
237 | * registers. adjusted_mode.crtc_clock is the pipe pixel clock. */ |
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3746 | Serge | 238 | struct drm_display_mode adjusted_mode; |
4560 | Serge | 239 | |
240 | /* Pipe source size (ie. panel fitter input size) |
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241 | * All planes will be positioned inside this space, |
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242 | * and get clipped at the edges. */ |
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243 | int pipe_src_w, pipe_src_h; |
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244 | |||
3746 | Serge | 245 | /* Whether to set up the PCH/FDI. Note that we never allow sharing |
246 | * between pch encoders and cpu encoders. */ |
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247 | bool has_pch_encoder; |
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248 | |||
249 | /* CPU Transcoder for the pipe. Currently this can only differ from the |
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250 | * pipe on Haswell (where we have a special eDP transcoder). */ |
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251 | enum transcoder cpu_transcoder; |
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252 | |||
253 | /* |
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254 | * Use reduced/limited/broadcast rbg range, compressing from the full |
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255 | * range fed into the crtcs. |
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256 | */ |
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257 | bool limited_color_range; |
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258 | |||
259 | /* DP has a bunch of special case unfortunately, so mark the pipe |
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260 | * accordingly. */ |
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261 | bool has_dp_encoder; |
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4104 | Serge | 262 | |
263 | /* |
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264 | * Enable dithering, used when the selected pipe bpp doesn't match the |
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265 | * plane bpp. |
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266 | */ |
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3746 | Serge | 267 | bool dither; |
268 | |||
269 | /* Controls for the clock computation, to override various stages. */ |
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270 | bool clock_set; |
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271 | |||
4104 | Serge | 272 | /* SDVO TV has a bunch of special case. To make multifunction encoders |
273 | * work correctly, we need to track this at runtime.*/ |
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274 | bool sdvo_tv_clock; |
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275 | |||
276 | /* |
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277 | * crtc bandwidth limit, don't increase pipe bpp or clock if not really |
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278 | * required. This is set in the 2nd loop of calling encoder's |
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279 | * ->compute_config if the first pick doesn't work out. |
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280 | */ |
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281 | bool bw_constrained; |
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282 | |||
3746 | Serge | 283 | /* Settings for the intel dpll used on pretty much everything but |
284 | * haswell. */ |
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4104 | Serge | 285 | struct dpll dpll; |
3746 | Serge | 286 | |
4104 | Serge | 287 | /* Selected dpll when shared or DPLL_ID_PRIVATE. */ |
288 | enum intel_dpll_id shared_dpll; |
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289 | |||
290 | /* Actual register state of the dpll, for shared dpll cross-checking. */ |
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291 | struct intel_dpll_hw_state dpll_hw_state; |
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292 | |||
3746 | Serge | 293 | int pipe_bpp; |
294 | struct intel_link_m_n dp_m_n; |
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4104 | Serge | 295 | |
296 | /* |
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297 | * Frequence the dpll for the port should run at. Differs from the |
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4560 | Serge | 298 | * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also |
299 | * already multiplied by pixel_multiplier. |
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3746 | Serge | 300 | */ |
4104 | Serge | 301 | int port_clock; |
302 | |||
3746 | Serge | 303 | /* Used by SDVO (and if we ever fix it, HDMI). */ |
304 | unsigned pixel_multiplier; |
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4104 | Serge | 305 | |
306 | /* Panel fitter controls for gen2-gen4 + VLV */ |
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307 | struct { |
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308 | u32 control; |
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309 | u32 pgm_ratios; |
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310 | u32 lvds_border_bits; |
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311 | } gmch_pfit; |
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312 | |||
313 | /* Panel fitter placement and size for Ironlake+ */ |
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314 | struct { |
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315 | u32 pos; |
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316 | u32 size; |
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317 | bool enabled; |
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318 | } pch_pfit; |
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319 | |||
320 | /* FDI configuration, only valid if has_pch_encoder is set. */ |
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321 | int fdi_lanes; |
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322 | struct intel_link_m_n fdi_m_n; |
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323 | |||
324 | bool ips_enabled; |
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4560 | Serge | 325 | |
326 | bool double_wide; |
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3746 | Serge | 327 | }; |
328 | |||
4560 | Serge | 329 | struct intel_pipe_wm { |
330 | struct intel_wm_level wm[5]; |
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331 | uint32_t linetime; |
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332 | bool fbc_wm_enabled; |
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333 | }; |
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334 | |||
2326 | Serge | 335 | struct intel_crtc { |
336 | struct drm_crtc base; |
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337 | enum pipe pipe; |
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338 | enum plane plane; |
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339 | u8 lut_r[256], lut_g[256], lut_b[256]; |
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3031 | serge | 340 | /* |
341 | * Whether the crtc and the connected output pipeline is active. Implies |
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342 | * that crtc->enabled is set, i.e. the current mode configuration has |
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343 | * some outputs connected to this crtc. |
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344 | */ |
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345 | bool active; |
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4560 | Serge | 346 | unsigned long enabled_power_domains; |
3480 | Serge | 347 | bool eld_vld; |
4560 | Serge | 348 | bool primary_enabled; /* is the primary plane (partially) visible? */ |
2326 | Serge | 349 | bool lowfreq_avail; |
350 | struct intel_overlay *overlay; |
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351 | struct intel_unpin_work *unpin_work; |
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352 | |||
3243 | Serge | 353 | atomic_t unpin_work_count; |
354 | |||
3031 | serge | 355 | /* Display surface base address adjustement for pageflips. Note that on |
356 | * gen4+ this only adjusts up to a tile, offsets within a tile are |
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357 | * handled in the hw itself (with the TILEOFF register). */ |
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358 | unsigned long dspaddr_offset; |
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359 | |||
2326 | Serge | 360 | struct drm_i915_gem_object *cursor_bo; |
361 | uint32_t cursor_addr; |
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362 | int16_t cursor_x, cursor_y; |
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363 | int16_t cursor_width, cursor_height; |
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364 | bool cursor_visible; |
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2342 | Serge | 365 | |
3746 | Serge | 366 | struct intel_crtc_config config; |
367 | |||
3243 | Serge | 368 | uint32_t ddi_pll_sel; |
3480 | Serge | 369 | |
370 | /* reset counter value when the last flip was submitted */ |
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371 | unsigned int reset_counter; |
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4104 | Serge | 372 | |
373 | /* Access to these should be protected by dev_priv->irq_lock. */ |
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374 | bool cpu_fifo_underrun_disabled; |
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375 | bool pch_fifo_underrun_disabled; |
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4560 | Serge | 376 | |
377 | /* per-pipe watermark state */ |
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378 | struct { |
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379 | /* watermarks currently being used */ |
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380 | struct intel_pipe_wm active; |
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381 | } wm; |
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2326 | Serge | 382 | }; |
383 | |||
4104 | Serge | 384 | struct intel_plane_wm_parameters { |
385 | uint32_t horiz_pixels; |
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386 | uint8_t bytes_per_pixel; |
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387 | bool enabled; |
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388 | bool scaled; |
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389 | }; |
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390 | |||
2342 | Serge | 391 | struct intel_plane { |
392 | struct drm_plane base; |
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3746 | Serge | 393 | int plane; |
2342 | Serge | 394 | enum pipe pipe; |
395 | struct drm_i915_gem_object *obj; |
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3243 | Serge | 396 | bool can_scale; |
2342 | Serge | 397 | int max_downscale; |
398 | u32 lut_r[1024], lut_g[1024], lut_b[1024]; |
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3746 | Serge | 399 | int crtc_x, crtc_y; |
400 | unsigned int crtc_w, crtc_h; |
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401 | uint32_t src_x, src_y; |
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402 | uint32_t src_w, src_h; |
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4104 | Serge | 403 | |
404 | /* Since we need to change the watermarks before/after |
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405 | * enabling/disabling the planes, we need to store the parameters here |
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406 | * as the other pieces of the struct may not reflect the values we want |
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407 | * for the watermark calculations. Currently only Haswell uses this. |
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408 | */ |
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409 | struct intel_plane_wm_parameters wm; |
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410 | |||
2342 | Serge | 411 | void (*update_plane)(struct drm_plane *plane, |
4104 | Serge | 412 | struct drm_crtc *crtc, |
2342 | Serge | 413 | struct drm_framebuffer *fb, |
414 | struct drm_i915_gem_object *obj, |
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415 | int crtc_x, int crtc_y, |
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416 | unsigned int crtc_w, unsigned int crtc_h, |
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417 | uint32_t x, uint32_t y, |
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418 | uint32_t src_w, uint32_t src_h); |
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4104 | Serge | 419 | void (*disable_plane)(struct drm_plane *plane, |
420 | struct drm_crtc *crtc); |
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2342 | Serge | 421 | int (*update_colorkey)(struct drm_plane *plane, |
422 | struct drm_intel_sprite_colorkey *key); |
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423 | void (*get_colorkey)(struct drm_plane *plane, |
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424 | struct drm_intel_sprite_colorkey *key); |
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425 | }; |
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426 | |||
3031 | serge | 427 | struct intel_watermark_params { |
428 | unsigned long fifo_size; |
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429 | unsigned long max_wm; |
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430 | unsigned long default_wm; |
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431 | unsigned long guard_size; |
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432 | unsigned long cacheline_size; |
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433 | }; |
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434 | |||
435 | struct cxsr_latency { |
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436 | int is_desktop; |
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437 | int is_ddr3; |
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438 | unsigned long fsb_freq; |
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439 | unsigned long mem_freq; |
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440 | unsigned long display_sr; |
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441 | unsigned long display_hpll_disable; |
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442 | unsigned long cursor_sr; |
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443 | unsigned long cursor_hpll_disable; |
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444 | }; |
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445 | |||
2326 | Serge | 446 | #define to_intel_crtc(x) container_of(x, struct intel_crtc, base) |
447 | #define to_intel_connector(x) container_of(x, struct intel_connector, base) |
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448 | #define to_intel_encoder(x) container_of(x, struct intel_encoder, base) |
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449 | #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base) |
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2342 | Serge | 450 | #define to_intel_plane(x) container_of(x, struct intel_plane, base) |
2326 | Serge | 451 | |
3031 | serge | 452 | struct intel_hdmi { |
3746 | Serge | 453 | u32 hdmi_reg; |
3031 | serge | 454 | int ddc_bus; |
455 | uint32_t color_range; |
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3480 | Serge | 456 | bool color_range_auto; |
3031 | serge | 457 | bool has_hdmi_sink; |
458 | bool has_audio; |
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459 | enum hdmi_force_audio force_audio; |
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3480 | Serge | 460 | bool rgb_quant_range_selectable; |
3031 | serge | 461 | void (*write_infoframe)(struct drm_encoder *encoder, |
4104 | Serge | 462 | enum hdmi_infoframe_type type, |
4560 | Serge | 463 | const void *frame, ssize_t len); |
3031 | serge | 464 | void (*set_infoframes)(struct drm_encoder *encoder, |
465 | struct drm_display_mode *adjusted_mode); |
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466 | }; |
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467 | |||
468 | #define DP_MAX_DOWNSTREAM_PORTS 0x10 |
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469 | |||
470 | struct intel_dp { |
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471 | uint32_t output_reg; |
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3746 | Serge | 472 | uint32_t aux_ch_ctl_reg; |
3031 | serge | 473 | uint32_t DP; |
474 | bool has_audio; |
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475 | enum hdmi_force_audio force_audio; |
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476 | uint32_t color_range; |
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3480 | Serge | 477 | bool color_range_auto; |
3031 | serge | 478 | uint8_t link_bw; |
479 | uint8_t lane_count; |
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480 | uint8_t dpcd[DP_RECEIVER_CAP_SIZE]; |
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4104 | Serge | 481 | uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE]; |
3031 | serge | 482 | uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS]; |
483 | struct i2c_adapter adapter; |
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484 | struct i2c_algo_dp_aux_data algo; |
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485 | uint8_t train_set[4]; |
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486 | int panel_power_up_delay; |
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487 | int panel_power_down_delay; |
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488 | int panel_power_cycle_delay; |
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489 | int backlight_on_delay; |
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490 | int backlight_off_delay; |
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491 | struct delayed_work panel_vdd_work; |
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492 | bool want_panel_vdd; |
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4104 | Serge | 493 | bool psr_setup_done; |
3243 | Serge | 494 | struct intel_connector *attached_connector; |
3031 | serge | 495 | }; |
496 | |||
3243 | Serge | 497 | struct intel_digital_port { |
498 | struct intel_encoder base; |
||
499 | enum port port; |
||
4104 | Serge | 500 | u32 saved_port_bits; |
3243 | Serge | 501 | struct intel_dp dp; |
502 | struct intel_hdmi hdmi; |
||
503 | }; |
||
504 | |||
4104 | Serge | 505 | static inline int |
506 | vlv_dport_to_channel(struct intel_digital_port *dport) |
||
507 | { |
||
508 | switch (dport->port) { |
||
509 | case PORT_B: |
||
4560 | Serge | 510 | return DPIO_CH0; |
4104 | Serge | 511 | case PORT_C: |
4560 | Serge | 512 | return DPIO_CH1; |
4104 | Serge | 513 | default: |
514 | BUG(); |
||
515 | } |
||
516 | } |
||
517 | |||
2326 | Serge | 518 | static inline struct drm_crtc * |
519 | intel_get_crtc_for_pipe(struct drm_device *dev, int pipe) |
||
520 | { |
||
521 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
522 | return dev_priv->pipe_to_crtc_mapping[pipe]; |
||
523 | } |
||
524 | |||
525 | static inline struct drm_crtc * |
||
526 | intel_get_crtc_for_plane(struct drm_device *dev, int plane) |
||
527 | { |
||
528 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
529 | return dev_priv->plane_to_crtc_mapping[plane]; |
||
530 | } |
||
531 | |||
532 | struct intel_unpin_work { |
||
2360 | Serge | 533 | struct work_struct work; |
3243 | Serge | 534 | struct drm_crtc *crtc; |
2326 | Serge | 535 | struct drm_i915_gem_object *old_fb_obj; |
536 | struct drm_i915_gem_object *pending_flip_obj; |
||
537 | struct drm_pending_vblank_event *event; |
||
3243 | Serge | 538 | atomic_t pending; |
539 | #define INTEL_FLIP_INACTIVE 0 |
||
540 | #define INTEL_FLIP_PENDING 1 |
||
541 | #define INTEL_FLIP_COMPLETE 2 |
||
2326 | Serge | 542 | bool enable_stall_check; |
543 | }; |
||
544 | |||
3031 | serge | 545 | struct intel_set_config { |
546 | struct drm_encoder **save_connector_encoders; |
||
547 | struct drm_crtc **save_encoder_crtcs; |
||
548 | |||
549 | bool fb_changed; |
||
550 | bool mode_changed; |
||
551 | }; |
||
552 | |||
4560 | Serge | 553 | struct intel_load_detect_pipe { |
554 | struct drm_framebuffer *release_fb; |
||
555 | bool load_detect_temp; |
||
556 | int dpms_mode; |
||
557 | }; |
||
2326 | Serge | 558 | |
4560 | Serge | 559 | static inline struct intel_encoder * |
560 | intel_attached_encoder(struct drm_connector *connector) |
||
2326 | Serge | 561 | { |
562 | return to_intel_connector(connector)->encoder; |
||
563 | } |
||
564 | |||
3243 | Serge | 565 | static inline struct intel_digital_port * |
566 | enc_to_dig_port(struct drm_encoder *encoder) |
||
567 | { |
||
568 | return container_of(encoder, struct intel_digital_port, base.base); |
||
569 | } |
||
570 | |||
4104 | Serge | 571 | static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder) |
572 | { |
||
573 | return &enc_to_dig_port(encoder)->dp; |
||
574 | } |
||
575 | |||
3243 | Serge | 576 | static inline struct intel_digital_port * |
577 | dp_to_dig_port(struct intel_dp *intel_dp) |
||
578 | { |
||
579 | return container_of(intel_dp, struct intel_digital_port, dp); |
||
580 | } |
||
581 | |||
582 | static inline struct intel_digital_port * |
||
583 | hdmi_to_dig_port(struct intel_hdmi *intel_hdmi) |
||
584 | { |
||
585 | return container_of(intel_hdmi, struct intel_digital_port, hdmi); |
||
586 | } |
||
587 | |||
4560 | Serge | 588 | |
589 | /* i915_irq.c */ |
||
590 | bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev, |
||
591 | enum pipe pipe, bool enable); |
||
592 | bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev, |
||
593 | enum transcoder pch_transcoder, |
||
594 | bool enable); |
||
595 | void ilk_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask); |
||
596 | void ilk_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask); |
||
597 | void snb_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask); |
||
598 | void snb_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask); |
||
599 | void hsw_pc8_disable_interrupts(struct drm_device *dev); |
||
600 | void hsw_pc8_restore_interrupts(struct drm_device *dev); |
||
601 | |||
602 | |||
603 | /* intel_crt.c */ |
||
604 | void intel_crt_init(struct drm_device *dev); |
||
605 | |||
606 | |||
607 | /* intel_ddi.c */ |
||
608 | void intel_prepare_ddi(struct drm_device *dev); |
||
609 | void hsw_fdi_link_train(struct drm_crtc *crtc); |
||
610 | void intel_ddi_init(struct drm_device *dev, enum port port); |
||
611 | enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder); |
||
612 | bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe); |
||
613 | int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv); |
||
614 | void intel_ddi_pll_init(struct drm_device *dev); |
||
615 | void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc); |
||
616 | void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv, |
||
617 | enum transcoder cpu_transcoder); |
||
618 | void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc); |
||
619 | void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc); |
||
620 | void intel_ddi_setup_hw_pll_state(struct drm_device *dev); |
||
621 | bool intel_ddi_pll_select(struct intel_crtc *crtc); |
||
622 | void intel_ddi_pll_enable(struct intel_crtc *crtc); |
||
623 | void intel_ddi_put_crtc_pll(struct drm_crtc *crtc); |
||
624 | void intel_ddi_set_pipe_settings(struct drm_crtc *crtc); |
||
625 | void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder); |
||
626 | bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector); |
||
627 | void intel_ddi_fdi_disable(struct drm_crtc *crtc); |
||
628 | void intel_ddi_get_config(struct intel_encoder *encoder, |
||
629 | struct intel_crtc_config *pipe_config); |
||
630 | |||
631 | |||
632 | /* intel_display.c */ |
||
633 | const char *intel_output_name(int output); |
||
634 | bool intel_has_pending_fb_unpin(struct drm_device *dev); |
||
635 | int intel_pch_rawclk(struct drm_device *dev); |
||
636 | void intel_mark_busy(struct drm_device *dev); |
||
637 | void intel_mark_fb_busy(struct drm_i915_gem_object *obj, |
||
638 | struct intel_ring_buffer *ring); |
||
639 | void intel_mark_idle(struct drm_device *dev); |
||
640 | void intel_crtc_restore_mode(struct drm_crtc *crtc); |
||
641 | void intel_crtc_update_dpms(struct drm_crtc *crtc); |
||
642 | void intel_encoder_destroy(struct drm_encoder *encoder); |
||
643 | void intel_connector_dpms(struct drm_connector *, int mode); |
||
644 | bool intel_connector_get_hw_state(struct intel_connector *connector); |
||
645 | void intel_modeset_check_state(struct drm_device *dev); |
||
3480 | Serge | 646 | bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, |
647 | struct intel_digital_port *port); |
||
4560 | Serge | 648 | void intel_connector_attach_encoder(struct intel_connector *connector, |
2326 | Serge | 649 | struct intel_encoder *encoder); |
4560 | Serge | 650 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector); |
651 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, |
||
2326 | Serge | 652 | struct drm_crtc *crtc); |
4560 | Serge | 653 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector); |
2326 | Serge | 654 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
655 | struct drm_file *file_priv); |
||
4560 | Serge | 656 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
3243 | Serge | 657 | enum pipe pipe); |
4560 | Serge | 658 | void intel_wait_for_vblank(struct drm_device *dev, int pipe); |
659 | void intel_wait_for_pipe_off(struct drm_device *dev, int pipe); |
||
660 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp); |
||
661 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
||
662 | struct intel_digital_port *dport); |
||
663 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
||
2326 | Serge | 664 | struct drm_display_mode *mode, |
665 | struct intel_load_detect_pipe *old); |
||
4560 | Serge | 666 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
2326 | Serge | 667 | struct intel_load_detect_pipe *old); |
4560 | Serge | 668 | int intel_pin_and_fence_fb_obj(struct drm_device *dev, |
2326 | Serge | 669 | struct drm_i915_gem_object *obj, |
670 | struct intel_ring_buffer *pipelined); |
||
4560 | Serge | 671 | void intel_unpin_fb_obj(struct drm_i915_gem_object *obj); |
672 | int intel_framebuffer_init(struct drm_device *dev, |
||
2326 | Serge | 673 | struct intel_framebuffer *ifb, |
2342 | Serge | 674 | struct drm_mode_fb_cmd2 *mode_cmd, |
2326 | Serge | 675 | struct drm_i915_gem_object *obj); |
4560 | Serge | 676 | void intel_framebuffer_fini(struct intel_framebuffer *fb); |
677 | void intel_prepare_page_flip(struct drm_device *dev, int plane); |
||
678 | void intel_finish_page_flip(struct drm_device *dev, int pipe); |
||
679 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane); |
||
680 | struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc); |
||
4104 | Serge | 681 | void assert_shared_dpll(struct drm_i915_private *dev_priv, |
682 | struct intel_shared_dpll *pll, |
||
683 | bool state); |
||
684 | #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true) |
||
685 | #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false) |
||
686 | void assert_pll(struct drm_i915_private *dev_priv, |
||
687 | enum pipe pipe, bool state); |
||
688 | #define assert_pll_enabled(d, p) assert_pll(d, p, true) |
||
689 | #define assert_pll_disabled(d, p) assert_pll(d, p, false) |
||
690 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
||
691 | enum pipe pipe, bool state); |
||
692 | #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true) |
||
693 | #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false) |
||
4560 | Serge | 694 | void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state); |
2342 | Serge | 695 | #define assert_pipe_enabled(d, p) assert_pipe(d, p, true) |
696 | #define assert_pipe_disabled(d, p) assert_pipe(d, p, false) |
||
4560 | Serge | 697 | void intel_write_eld(struct drm_encoder *encoder, |
2342 | Serge | 698 | struct drm_display_mode *mode); |
4560 | Serge | 699 | unsigned long intel_gen4_compute_page_offset(int *x, int *y, |
3480 | Serge | 700 | unsigned int tiling_mode, |
3243 | Serge | 701 | unsigned int bpp, |
702 | unsigned int pitch); |
||
4560 | Serge | 703 | void intel_display_handle_reset(struct drm_device *dev); |
704 | void hsw_enable_pc8_work(struct work_struct *__work); |
||
705 | void hsw_enable_package_c8(struct drm_i915_private *dev_priv); |
||
706 | void hsw_disable_package_c8(struct drm_i915_private *dev_priv); |
||
707 | void intel_dp_get_m_n(struct intel_crtc *crtc, |
||
708 | struct intel_crtc_config *pipe_config); |
||
709 | int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n); |
||
710 | void |
||
711 | ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config, |
||
712 | int dotclock); |
||
713 | bool intel_crtc_active(struct drm_crtc *crtc); |
||
714 | void hsw_enable_ips(struct intel_crtc *crtc); |
||
715 | void hsw_disable_ips(struct intel_crtc *crtc); |
||
716 | void intel_display_set_init_power(struct drm_device *dev, bool enable); |
||
717 | int valleyview_get_vco(struct drm_i915_private *dev_priv); |
||
3243 | Serge | 718 | |
4560 | Serge | 719 | /* intel_dp.c */ |
720 | void intel_dp_init(struct drm_device *dev, int output_reg, enum port port); |
||
721 | bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port, |
||
722 | struct intel_connector *intel_connector); |
||
723 | void intel_dp_start_link_train(struct intel_dp *intel_dp); |
||
724 | void intel_dp_complete_link_train(struct intel_dp *intel_dp); |
||
725 | void intel_dp_stop_link_train(struct intel_dp *intel_dp); |
||
726 | void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode); |
||
727 | void intel_dp_encoder_destroy(struct drm_encoder *encoder); |
||
728 | void intel_dp_check_link_status(struct intel_dp *intel_dp); |
||
729 | bool intel_dp_compute_config(struct intel_encoder *encoder, |
||
730 | struct intel_crtc_config *pipe_config); |
||
731 | bool intel_dp_is_edp(struct drm_device *dev, enum port port); |
||
732 | void ironlake_edp_backlight_on(struct intel_dp *intel_dp); |
||
733 | void ironlake_edp_backlight_off(struct intel_dp *intel_dp); |
||
734 | void ironlake_edp_panel_on(struct intel_dp *intel_dp); |
||
735 | void ironlake_edp_panel_off(struct intel_dp *intel_dp); |
||
736 | void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp); |
||
737 | void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync); |
||
738 | void intel_edp_psr_enable(struct intel_dp *intel_dp); |
||
739 | void intel_edp_psr_disable(struct intel_dp *intel_dp); |
||
740 | void intel_edp_psr_update(struct drm_device *dev); |
||
741 | |||
742 | |||
743 | /* intel_dsi.c */ |
||
744 | bool intel_dsi_init(struct drm_device *dev); |
||
745 | |||
746 | |||
747 | /* intel_dvo.c */ |
||
748 | void intel_dvo_init(struct drm_device *dev); |
||
749 | |||
750 | |||
751 | /* legacy fbdev emulation in intel_fbdev.c */ |
||
752 | #ifdef CONFIG_DRM_I915_FBDEV |
||
753 | extern int intel_fbdev_init(struct drm_device *dev); |
||
754 | extern void intel_fbdev_initial_config(struct drm_device *dev); |
||
755 | extern void intel_fbdev_fini(struct drm_device *dev); |
||
756 | extern void intel_fbdev_set_suspend(struct drm_device *dev, int state); |
||
757 | extern void intel_fbdev_output_poll_changed(struct drm_device *dev); |
||
758 | extern void intel_fbdev_restore_mode(struct drm_device *dev); |
||
759 | #else |
||
760 | static inline int intel_fbdev_init(struct drm_device *dev) |
||
761 | { |
||
762 | return 0; |
||
763 | } |
||
764 | |||
765 | static inline void intel_fbdev_initial_config(struct drm_device *dev) |
||
766 | { |
||
767 | } |
||
768 | |||
769 | static inline void intel_fbdev_fini(struct drm_device *dev) |
||
770 | { |
||
771 | } |
||
772 | |||
773 | static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state) |
||
774 | { |
||
775 | } |
||
776 | |||
777 | static inline void intel_fbdev_restore_mode(struct drm_device *dev) |
||
778 | { |
||
779 | } |
||
780 | #endif |
||
781 | |||
782 | /* intel_hdmi.c */ |
||
783 | void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port); |
||
784 | void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, |
||
785 | struct intel_connector *intel_connector); |
||
786 | struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder); |
||
787 | bool intel_hdmi_compute_config(struct intel_encoder *encoder, |
||
788 | struct intel_crtc_config *pipe_config); |
||
789 | |||
790 | |||
791 | /* intel_lvds.c */ |
||
792 | void intel_lvds_init(struct drm_device *dev); |
||
793 | bool intel_is_dual_link_lvds(struct drm_device *dev); |
||
794 | |||
795 | |||
796 | /* intel_modes.c */ |
||
797 | int intel_connector_update_modes(struct drm_connector *connector, |
||
798 | struct edid *edid); |
||
799 | int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter); |
||
800 | void intel_attach_force_audio_property(struct drm_connector *connector); |
||
801 | void intel_attach_broadcast_rgb_property(struct drm_connector *connector); |
||
802 | |||
803 | |||
804 | /* intel_overlay.c */ |
||
805 | void intel_setup_overlay(struct drm_device *dev); |
||
806 | void intel_cleanup_overlay(struct drm_device *dev); |
||
807 | int intel_overlay_switch_off(struct intel_overlay *overlay); |
||
808 | int intel_overlay_put_image(struct drm_device *dev, void *data, |
||
2342 | Serge | 809 | struct drm_file *file_priv); |
4560 | Serge | 810 | int intel_overlay_attrs(struct drm_device *dev, void *data, |
2342 | Serge | 811 | struct drm_file *file_priv); |
812 | |||
3031 | serge | 813 | |
4560 | Serge | 814 | /* intel_panel.c */ |
815 | int intel_panel_init(struct intel_panel *panel, |
||
816 | struct drm_display_mode *fixed_mode); |
||
817 | void intel_panel_fini(struct intel_panel *panel); |
||
818 | void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode, |
||
819 | struct drm_display_mode *adjusted_mode); |
||
820 | void intel_pch_panel_fitting(struct intel_crtc *crtc, |
||
821 | struct intel_crtc_config *pipe_config, |
||
822 | int fitting_mode); |
||
823 | void intel_gmch_panel_fitting(struct intel_crtc *crtc, |
||
824 | struct intel_crtc_config *pipe_config, |
||
825 | int fitting_mode); |
||
826 | void intel_panel_set_backlight(struct intel_connector *connector, u32 level, |
||
827 | u32 max); |
||
828 | int intel_panel_setup_backlight(struct drm_connector *connector); |
||
829 | void intel_panel_enable_backlight(struct intel_connector *connector); |
||
830 | void intel_panel_disable_backlight(struct intel_connector *connector); |
||
831 | void intel_panel_destroy_backlight(struct drm_connector *connector); |
||
832 | void intel_panel_init_backlight_funcs(struct drm_device *dev); |
||
833 | enum drm_connector_status intel_panel_detect(struct drm_device *dev); |
||
834 | extern struct drm_display_mode *intel_find_panel_downclock( |
||
835 | struct drm_device *dev, |
||
836 | struct drm_display_mode *fixed_mode, |
||
837 | struct drm_connector *connector); |
||
4104 | Serge | 838 | |
4560 | Serge | 839 | /* intel_pm.c */ |
840 | void intel_init_clock_gating(struct drm_device *dev); |
||
841 | void intel_suspend_hw(struct drm_device *dev); |
||
842 | void intel_update_watermarks(struct drm_crtc *crtc); |
||
843 | void intel_update_sprite_watermarks(struct drm_plane *plane, |
||
844 | struct drm_crtc *crtc, |
||
845 | uint32_t sprite_width, int pixel_size, |
||
846 | bool enabled, bool scaled); |
||
847 | void intel_init_pm(struct drm_device *dev); |
||
848 | void intel_pm_setup(struct drm_device *dev); |
||
849 | bool intel_fbc_enabled(struct drm_device *dev); |
||
850 | void intel_update_fbc(struct drm_device *dev); |
||
851 | void intel_gpu_ips_init(struct drm_i915_private *dev_priv); |
||
852 | void intel_gpu_ips_teardown(void); |
||
853 | int intel_power_domains_init(struct drm_device *dev); |
||
854 | void intel_power_domains_remove(struct drm_device *dev); |
||
855 | bool intel_display_power_enabled(struct drm_device *dev, |
||
856 | enum intel_display_power_domain domain); |
||
857 | bool intel_display_power_enabled_sw(struct drm_device *dev, |
||
858 | enum intel_display_power_domain domain); |
||
859 | void intel_display_power_get(struct drm_device *dev, |
||
860 | enum intel_display_power_domain domain); |
||
861 | void intel_display_power_put(struct drm_device *dev, |
||
4104 | Serge | 862 | enum intel_display_power_domain domain); |
4560 | Serge | 863 | void intel_power_domains_init_hw(struct drm_device *dev); |
864 | void intel_set_power_well(struct drm_device *dev, bool enable); |
||
865 | void intel_enable_gt_powersave(struct drm_device *dev); |
||
866 | void intel_disable_gt_powersave(struct drm_device *dev); |
||
867 | void ironlake_teardown_rc6(struct drm_device *dev); |
||
4104 | Serge | 868 | void gen6_update_ring_freq(struct drm_device *dev); |
4560 | Serge | 869 | void gen6_rps_idle(struct drm_i915_private *dev_priv); |
870 | void gen6_rps_boost(struct drm_i915_private *dev_priv); |
||
871 | void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv); |
||
872 | void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv); |
||
873 | void intel_runtime_pm_get(struct drm_i915_private *dev_priv); |
||
874 | void intel_runtime_pm_put(struct drm_i915_private *dev_priv); |
||
875 | void intel_init_runtime_pm(struct drm_i915_private *dev_priv); |
||
876 | void intel_fini_runtime_pm(struct drm_i915_private *dev_priv); |
||
877 | void ilk_wm_get_hw_state(struct drm_device *dev); |
||
3031 | serge | 878 | |
879 | |||
4560 | Serge | 880 | /* intel_sdvo.c */ |
881 | bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob); |
||
3746 | Serge | 882 | |
4104 | Serge | 883 | |
4560 | Serge | 884 | /* intel_sprite.c */ |
885 | int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane); |
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886 | void intel_flush_primary_plane(struct drm_i915_private *dev_priv, |
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887 | enum plane plane); |
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888 | void intel_plane_restore(struct drm_plane *plane); |
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889 | void intel_plane_disable(struct drm_plane *plane); |
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890 | int intel_sprite_set_colorkey(struct drm_device *dev, void *data, |
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891 | struct drm_file *file_priv); |
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892 | int intel_sprite_get_colorkey(struct drm_device *dev, void *data, |
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893 | struct drm_file *file_priv); |
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894 | |||
895 | |||
896 | /* intel_tv.c */ |
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897 | void intel_tv_init(struct drm_device *dev); |
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898 | |||
2326 | Serge | 899 | #endif /* __INTEL_DRV_H__ */0)><0)> |