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5060 | serge | 1 | /* |
2 | * Copyright © 2014 Intel Corporation |
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3 | * |
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4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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5 | * copy of this software and associated documentation files (the "Software"), |
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6 | * to deal in the Software without restriction, including without limitation |
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7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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8 | * and/or sell copies of the Software, and to permit persons to whom the |
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9 | * Software is furnished to do so, subject to the following conditions: |
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10 | * |
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11 | * The above copyright notice and this permission notice (including the next |
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12 | * paragraph) shall be included in all copies or substantial portions of the |
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13 | * Software. |
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14 | * |
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15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
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21 | * IN THE SOFTWARE. |
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22 | * |
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23 | * Please try to maintain the following order within this file unless it makes |
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24 | * sense to do otherwise. From top to bottom: |
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25 | * 1. typedefs |
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26 | * 2. #defines, and macros |
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27 | * 3. structure definitions |
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28 | * 4. function prototypes |
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29 | * |
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30 | * Within each section, please try to order by generation in ascending order, |
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31 | * from top to bottom (ie. gen6 on the top, gen8 on the bottom). |
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32 | */ |
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33 | |||
34 | #ifndef __I915_GEM_GTT_H__ |
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35 | #define __I915_GEM_GTT_H__ |
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36 | |||
5354 | serge | 37 | struct drm_i915_file_private; |
38 | |||
6084 | serge | 39 | typedef uint32_t gen6_pte_t; |
40 | typedef uint64_t gen8_pte_t; |
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41 | typedef uint64_t gen8_pde_t; |
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42 | typedef uint64_t gen8_ppgtt_pdpe_t; |
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43 | typedef uint64_t gen8_ppgtt_pml4e_t; |
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5060 | serge | 44 | |
45 | #define gtt_total_entries(gtt) ((gtt).base.total >> PAGE_SHIFT) |
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46 | |||
6084 | serge | 47 | |
5060 | serge | 48 | /* gen6-hsw has bit 11-4 for physical addr bit 39-32 */ |
49 | #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0)) |
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50 | #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) |
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51 | #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) |
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52 | #define GEN6_PTE_CACHE_LLC (2 << 1) |
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53 | #define GEN6_PTE_UNCACHED (1 << 1) |
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54 | #define GEN6_PTE_VALID (1 << 0) |
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55 | |||
6084 | serge | 56 | #define I915_PTES(pte_len) (PAGE_SIZE / (pte_len)) |
57 | #define I915_PTE_MASK(pte_len) (I915_PTES(pte_len) - 1) |
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58 | #define I915_PDES 512 |
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59 | #define I915_PDE_MASK (I915_PDES - 1) |
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60 | #define NUM_PTE(pde_shift) (1 << (pde_shift - PAGE_SHIFT)) |
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61 | |||
62 | #define GEN6_PTES I915_PTES(sizeof(gen6_pte_t)) |
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63 | #define GEN6_PD_SIZE (I915_PDES * PAGE_SIZE) |
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5060 | serge | 64 | #define GEN6_PD_ALIGN (PAGE_SIZE * 16) |
6084 | serge | 65 | #define GEN6_PDE_SHIFT 22 |
5060 | serge | 66 | #define GEN6_PDE_VALID (1 << 0) |
67 | |||
68 | #define GEN7_PTE_CACHE_L3_LLC (3 << 1) |
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69 | |||
70 | #define BYT_PTE_SNOOPED_BY_CPU_CACHES (1 << 2) |
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71 | #define BYT_PTE_WRITEABLE (1 << 1) |
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72 | |||
73 | /* Cacheability Control is a 4-bit value. The low three bits are stored in bits |
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74 | * 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE. |
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75 | */ |
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76 | #define HSW_CACHEABILITY_CONTROL(bits) ((((bits) & 0x7) << 1) | \ |
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77 | (((bits) & 0x8) << (11 - 3))) |
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78 | #define HSW_WB_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x2) |
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79 | #define HSW_WB_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x3) |
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80 | #define HSW_WB_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x8) |
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81 | #define HSW_WB_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0xb) |
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82 | #define HSW_WT_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x7) |
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83 | #define HSW_WT_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x6) |
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84 | #define HSW_PTE_UNCACHED (0) |
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85 | #define HSW_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0x7f0)) |
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86 | #define HSW_PTE_ADDR_ENCODE(addr) HSW_GTT_ADDR_ENCODE(addr) |
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87 | |||
88 | /* GEN8 legacy style address is defined as a 3 level page table: |
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89 | * 31:30 | 29:21 | 20:12 | 11:0 |
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90 | * PDPE | PDE | PTE | offset |
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91 | * The difference as compared to normal x86 3 level page table is the PDPEs are |
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92 | * programmed via register. |
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6084 | serge | 93 | * |
94 | * GEN8 48b legacy style address is defined as a 4 level page table: |
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95 | * 47:39 | 38:30 | 29:21 | 20:12 | 11:0 |
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96 | * PML4E | PDPE | PDE | PTE | offset |
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5060 | serge | 97 | */ |
6084 | serge | 98 | #define GEN8_PML4ES_PER_PML4 512 |
99 | #define GEN8_PML4E_SHIFT 39 |
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100 | #define GEN8_PML4E_MASK (GEN8_PML4ES_PER_PML4 - 1) |
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5060 | serge | 101 | #define GEN8_PDPE_SHIFT 30 |
6084 | serge | 102 | /* NB: GEN8_PDPE_MASK is untrue for 32b platforms, but it has no impact on 32b page |
103 | * tables */ |
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104 | #define GEN8_PDPE_MASK 0x1ff |
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5060 | serge | 105 | #define GEN8_PDE_SHIFT 21 |
106 | #define GEN8_PDE_MASK 0x1ff |
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107 | #define GEN8_PTE_SHIFT 12 |
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108 | #define GEN8_PTE_MASK 0x1ff |
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6084 | serge | 109 | #define GEN8_LEGACY_PDPES 4 |
110 | #define GEN8_PTES I915_PTES(sizeof(gen8_pte_t)) |
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5060 | serge | 111 | |
6084 | serge | 112 | #define I915_PDPES_PER_PDP(dev) (USES_FULL_48BIT_PPGTT(dev) ?\ |
113 | GEN8_PML4ES_PER_PML4 : GEN8_LEGACY_PDPES) |
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114 | |||
5060 | serge | 115 | #define PPAT_UNCACHED_INDEX (_PAGE_PWT | _PAGE_PCD) |
116 | #define PPAT_CACHED_PDE_INDEX 0 /* WB LLC */ |
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117 | #define PPAT_CACHED_INDEX _PAGE_PAT /* WB LLCeLLC */ |
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118 | #define PPAT_DISPLAY_ELLC_INDEX _PAGE_PCD /* WT eLLC */ |
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119 | |||
120 | #define CHV_PPAT_SNOOP (1<<6) |
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121 | #define GEN8_PPAT_AGE(x) (x<<4) |
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122 | #define GEN8_PPAT_LLCeLLC (3<<2) |
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123 | #define GEN8_PPAT_LLCELLC (2<<2) |
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124 | #define GEN8_PPAT_LLC (1<<2) |
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125 | #define GEN8_PPAT_WB (3<<0) |
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126 | #define GEN8_PPAT_WT (2<<0) |
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127 | #define GEN8_PPAT_WC (1<<0) |
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128 | #define GEN8_PPAT_UC (0<<0) |
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129 | #define GEN8_PPAT_ELLC_OVERRIDE (0<<2) |
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130 | #define GEN8_PPAT(i, x) ((uint64_t) (x) << ((i) * 8)) |
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131 | |||
6084 | serge | 132 | enum i915_ggtt_view_type { |
133 | I915_GGTT_VIEW_NORMAL = 0, |
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134 | I915_GGTT_VIEW_ROTATED, |
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135 | I915_GGTT_VIEW_PARTIAL, |
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136 | }; |
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137 | |||
138 | struct intel_rotation_info { |
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139 | unsigned int height; |
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140 | unsigned int pitch; |
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141 | unsigned int uv_offset; |
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142 | uint32_t pixel_format; |
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143 | uint64_t fb_modifier; |
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144 | unsigned int width_pages, height_pages; |
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145 | uint64_t size; |
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146 | unsigned int width_pages_uv, height_pages_uv; |
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147 | uint64_t size_uv; |
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148 | unsigned int uv_start_page; |
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149 | }; |
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150 | |||
151 | struct i915_ggtt_view { |
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152 | enum i915_ggtt_view_type type; |
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153 | |||
154 | union { |
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155 | struct { |
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156 | u64 offset; |
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157 | unsigned int size; |
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158 | } partial; |
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159 | } params; |
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160 | |||
161 | struct sg_table *pages; |
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162 | |||
163 | union { |
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164 | struct intel_rotation_info rotation_info; |
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165 | }; |
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166 | }; |
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167 | |||
168 | extern const struct i915_ggtt_view i915_ggtt_view_normal; |
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169 | extern const struct i915_ggtt_view i915_ggtt_view_rotated; |
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170 | |||
5060 | serge | 171 | enum i915_cache_level; |
6084 | serge | 172 | |
5060 | serge | 173 | /** |
174 | * A VMA represents a GEM BO that is bound into an address space. Therefore, a |
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175 | * VMA's presence cannot be guaranteed before binding, or after unbinding the |
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176 | * object into/from the address space. |
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177 | * |
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178 | * To make things as simple as possible (ie. no refcounting), a VMA's lifetime |
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179 | * will always be <= an objects lifetime. So object refcounting should cover us. |
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180 | */ |
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181 | struct i915_vma { |
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182 | struct drm_mm_node node; |
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183 | struct drm_i915_gem_object *obj; |
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184 | struct i915_address_space *vm; |
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185 | |||
5354 | serge | 186 | /** Flags and address space this VMA is bound to */ |
187 | #define GLOBAL_BIND (1<<0) |
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188 | #define LOCAL_BIND (1<<1) |
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189 | unsigned int bound : 4; |
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190 | |||
6084 | serge | 191 | /** |
192 | * Support different GGTT views into the same object. |
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193 | * This means there can be multiple VMA mappings per object and per VM. |
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194 | * i915_ggtt_view_type is used to distinguish between those entries. |
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195 | * The default one of zero (I915_GGTT_VIEW_NORMAL) is default and also |
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196 | * assumed in GEM functions which take no ggtt view parameter. |
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197 | */ |
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198 | struct i915_ggtt_view ggtt_view; |
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199 | |||
5060 | serge | 200 | /** This object's place on the active/inactive lists */ |
201 | struct list_head mm_list; |
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202 | |||
203 | struct list_head vma_link; /* Link in the object's VMA list */ |
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204 | |||
205 | /** This vma's place in the batchbuffer or on the eviction list */ |
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206 | struct list_head exec_list; |
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207 | |||
208 | /** |
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209 | * Used for performing relocations during execbuffer insertion. |
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210 | */ |
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211 | struct hlist_node exec_node; |
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212 | unsigned long exec_handle; |
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213 | struct drm_i915_gem_exec_object2 *exec_entry; |
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214 | |||
215 | /** |
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216 | * How many users have pinned this object in GTT space. The following |
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6084 | serge | 217 | * users can each hold at most one reference: pwrite/pread, execbuffer |
218 | * (objects are not allowed multiple times for the same batchbuffer), |
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219 | * and the framebuffer code. When switching/pageflipping, the |
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220 | * framebuffer code has at most two buffers pinned per crtc. |
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5060 | serge | 221 | * |
222 | * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3 |
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223 | * bits with absolutely no headroom. So use 4 bits. */ |
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224 | unsigned int pin_count:4; |
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225 | #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf |
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6084 | serge | 226 | }; |
5060 | serge | 227 | |
6084 | serge | 228 | struct i915_page_dma { |
229 | struct page *page; |
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230 | union { |
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231 | dma_addr_t daddr; |
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232 | |||
233 | /* For gen6/gen7 only. This is the offset in the GGTT |
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234 | * where the page directory entries for PPGTT begin |
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235 | */ |
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236 | uint32_t ggtt_offset; |
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237 | }; |
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5060 | serge | 238 | }; |
239 | |||
6084 | serge | 240 | #define px_base(px) (&(px)->base) |
241 | #define px_page(px) (px_base(px)->page) |
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242 | #define px_dma(px) (px_base(px)->daddr) |
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243 | |||
244 | struct i915_page_scratch { |
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245 | struct i915_page_dma base; |
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246 | }; |
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247 | |||
248 | struct i915_page_table { |
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249 | struct i915_page_dma base; |
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250 | |||
251 | unsigned long *used_ptes; |
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252 | }; |
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253 | |||
254 | struct i915_page_directory { |
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255 | struct i915_page_dma base; |
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256 | |||
257 | unsigned long *used_pdes; |
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258 | struct i915_page_table *page_table[I915_PDES]; /* PDEs */ |
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259 | }; |
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260 | |||
261 | struct i915_page_directory_pointer { |
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262 | struct i915_page_dma base; |
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263 | |||
264 | unsigned long *used_pdpes; |
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265 | struct i915_page_directory **page_directory; |
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266 | }; |
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267 | |||
268 | struct i915_pml4 { |
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269 | struct i915_page_dma base; |
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270 | |||
271 | DECLARE_BITMAP(used_pml4es, GEN8_PML4ES_PER_PML4); |
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272 | struct i915_page_directory_pointer *pdps[GEN8_PML4ES_PER_PML4]; |
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273 | }; |
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274 | |||
5060 | serge | 275 | struct i915_address_space { |
276 | struct drm_mm mm; |
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277 | struct drm_device *dev; |
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278 | struct list_head global_link; |
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6084 | serge | 279 | u64 start; /* Start offset always 0 for dri2 */ |
280 | u64 total; /* size addr space maps (ex. 2GB for ggtt) */ |
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5060 | serge | 281 | |
6084 | serge | 282 | struct i915_page_scratch *scratch_page; |
283 | struct i915_page_table *scratch_pt; |
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284 | struct i915_page_directory *scratch_pd; |
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285 | struct i915_page_directory_pointer *scratch_pdp; /* GEN8+ & 48b PPGTT */ |
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5060 | serge | 286 | |
287 | /** |
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288 | * List of objects currently involved in rendering. |
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289 | * |
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290 | * Includes buffers having the contents of their GPU caches |
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6084 | serge | 291 | * flushed, not necessarily primitives. last_read_req |
5060 | serge | 292 | * represents when the rendering involved will be completed. |
293 | * |
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294 | * A reference is held on the buffer while on this list. |
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295 | */ |
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296 | struct list_head active_list; |
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297 | |||
298 | /** |
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299 | * LRU list of objects which are not in the ringbuffer and |
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300 | * are ready to unbind, but are still in the GTT. |
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301 | * |
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6084 | serge | 302 | * last_read_req is NULL while an object is in this list. |
5060 | serge | 303 | * |
304 | * A reference is not held on the buffer while on this list, |
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305 | * as merely being GTT-bound shouldn't prevent its being |
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306 | * freed, and we'll pull it off the list in the free path. |
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307 | */ |
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308 | struct list_head inactive_list; |
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309 | |||
310 | /* FIXME: Need a more generic return type */ |
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6084 | serge | 311 | gen6_pte_t (*pte_encode)(dma_addr_t addr, |
312 | enum i915_cache_level level, |
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313 | bool valid, u32 flags); /* Create a valid PTE */ |
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314 | /* flags for pte_encode */ |
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315 | #define PTE_READ_ONLY (1<<0) |
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316 | int (*allocate_va_range)(struct i915_address_space *vm, |
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317 | uint64_t start, |
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318 | uint64_t length); |
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5060 | serge | 319 | void (*clear_range)(struct i915_address_space *vm, |
320 | uint64_t start, |
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321 | uint64_t length, |
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322 | bool use_scratch); |
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323 | void (*insert_entries)(struct i915_address_space *vm, |
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324 | struct sg_table *st, |
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325 | uint64_t start, |
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326 | enum i915_cache_level cache_level, u32 flags); |
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327 | void (*cleanup)(struct i915_address_space *vm); |
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6084 | serge | 328 | /** Unmap an object from an address space. This usually consists of |
329 | * setting the valid PTE entries to a reserved scratch page. */ |
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330 | void (*unbind_vma)(struct i915_vma *vma); |
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331 | /* Map an object into an address space with the given cache flags. */ |
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332 | int (*bind_vma)(struct i915_vma *vma, |
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333 | enum i915_cache_level cache_level, |
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334 | u32 flags); |
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5060 | serge | 335 | }; |
336 | |||
337 | /* The Graphics Translation Table is the way in which GEN hardware translates a |
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338 | * Graphics Virtual Address into a Physical Address. In addition to the normal |
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339 | * collateral associated with any va->pa translations GEN hardware also has a |
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340 | * portion of the GTT which can be mapped by the CPU and remain both coherent |
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341 | * and correct (in cases like swizzling). That region is referred to as GMADR in |
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342 | * the spec. |
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343 | */ |
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344 | struct i915_gtt { |
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345 | struct i915_address_space base; |
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6084 | serge | 346 | |
5060 | serge | 347 | size_t stolen_size; /* Total size of stolen memory */ |
6084 | serge | 348 | size_t stolen_usable_size; /* Total size minus BIOS reserved */ |
349 | u64 mappable_end; /* End offset that we can CPU map */ |
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5060 | serge | 350 | struct io_mapping *mappable; /* Mapping to our CPU mappable region */ |
351 | phys_addr_t mappable_base; /* PA of our GMADR */ |
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352 | |||
353 | /** "Graphics Stolen Memory" holds the global PTEs */ |
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354 | void __iomem *gsm; |
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355 | |||
356 | bool do_idle_maps; |
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357 | |||
358 | int mtrr; |
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359 | |||
360 | /* global gtt ops */ |
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6084 | serge | 361 | int (*gtt_probe)(struct drm_device *dev, u64 *gtt_total, |
5060 | serge | 362 | size_t *stolen, phys_addr_t *mappable_base, |
6084 | serge | 363 | u64 *mappable_end); |
5060 | serge | 364 | }; |
365 | |||
366 | struct i915_hw_ppgtt { |
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367 | struct i915_address_space base; |
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368 | struct kref ref; |
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369 | struct drm_mm_node node; |
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6084 | serge | 370 | unsigned long pd_dirty_rings; |
5060 | serge | 371 | union { |
6084 | serge | 372 | struct i915_pml4 pml4; /* GEN8+ & 48b PPGTT */ |
373 | struct i915_page_directory_pointer pdp; /* GEN8+ */ |
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374 | struct i915_page_directory pd; /* GEN6-7 */ |
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5060 | serge | 375 | }; |
376 | |||
5354 | serge | 377 | struct drm_i915_file_private *file_priv; |
5060 | serge | 378 | |
6084 | serge | 379 | gen6_pte_t __iomem *pd_addr; |
380 | |||
5060 | serge | 381 | int (*enable)(struct i915_hw_ppgtt *ppgtt); |
382 | int (*switch_mm)(struct i915_hw_ppgtt *ppgtt, |
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6084 | serge | 383 | struct drm_i915_gem_request *req); |
384 | void (*debug_dump)(struct i915_hw_ppgtt *ppgtt, struct seq_file *m); |
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5060 | serge | 385 | }; |
386 | |||
6084 | serge | 387 | /* For each pde iterates over every pde between from start until start + length. |
388 | * If start, and start+length are not perfectly divisible, the macro will round |
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389 | * down, and up as needed. The macro modifies pde, start, and length. Dev is |
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390 | * only used to differentiate shift values. Temp is temp. On gen6/7, start = 0, |
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391 | * and length = 2G effectively iterates over every PDE in the system. |
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392 | * |
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393 | * XXX: temp is not actually needed, but it saves doing the ALIGN operation. |
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394 | */ |
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395 | #define gen6_for_each_pde(pt, pd, start, length, temp, iter) \ |
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396 | for (iter = gen6_pde_index(start); \ |
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397 | length > 0 && iter < I915_PDES ? \ |
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398 | (pt = (pd)->page_table[iter]), 1 : 0; \ |
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399 | iter++, \ |
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400 | temp = ALIGN(start+1, 1 << GEN6_PDE_SHIFT) - start, \ |
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401 | temp = min_t(unsigned, temp, length), \ |
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402 | start += temp, length -= temp) |
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403 | |||
404 | #define gen6_for_all_pdes(pt, ppgtt, iter) \ |
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405 | for (iter = 0; \ |
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406 | pt = ppgtt->pd.page_table[iter], iter < I915_PDES; \ |
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407 | iter++) |
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408 | |||
409 | static inline uint32_t i915_pte_index(uint64_t address, uint32_t pde_shift) |
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410 | { |
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411 | const uint32_t mask = NUM_PTE(pde_shift) - 1; |
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412 | |||
413 | return (address >> PAGE_SHIFT) & mask; |
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414 | } |
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415 | |||
416 | /* Helper to counts the number of PTEs within the given length. This count |
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417 | * does not cross a page table boundary, so the max value would be |
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418 | * GEN6_PTES for GEN6, and GEN8_PTES for GEN8. |
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419 | */ |
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420 | static inline uint32_t i915_pte_count(uint64_t addr, size_t length, |
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421 | uint32_t pde_shift) |
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422 | { |
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423 | const uint64_t mask = ~((1 << pde_shift) - 1); |
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424 | uint64_t end; |
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425 | |||
426 | WARN_ON(length == 0); |
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427 | WARN_ON(offset_in_page(addr|length)); |
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428 | |||
429 | end = addr + length; |
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430 | |||
431 | if ((addr & mask) != (end & mask)) |
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432 | return NUM_PTE(pde_shift) - i915_pte_index(addr, pde_shift); |
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433 | |||
434 | return i915_pte_index(end, pde_shift) - i915_pte_index(addr, pde_shift); |
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435 | } |
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436 | |||
437 | static inline uint32_t i915_pde_index(uint64_t addr, uint32_t shift) |
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438 | { |
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439 | return (addr >> shift) & I915_PDE_MASK; |
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440 | } |
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441 | |||
442 | static inline uint32_t gen6_pte_index(uint32_t addr) |
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443 | { |
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444 | return i915_pte_index(addr, GEN6_PDE_SHIFT); |
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445 | } |
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446 | |||
447 | static inline size_t gen6_pte_count(uint32_t addr, uint32_t length) |
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448 | { |
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449 | return i915_pte_count(addr, length, GEN6_PDE_SHIFT); |
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450 | } |
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451 | |||
452 | static inline uint32_t gen6_pde_index(uint32_t addr) |
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453 | { |
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454 | return i915_pde_index(addr, GEN6_PDE_SHIFT); |
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455 | } |
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456 | |||
457 | /* Equivalent to the gen6 version, For each pde iterates over every pde |
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458 | * between from start until start + length. On gen8+ it simply iterates |
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459 | * over every page directory entry in a page directory. |
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460 | */ |
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461 | #define gen8_for_each_pde(pt, pd, start, length, temp, iter) \ |
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462 | for (iter = gen8_pde_index(start); \ |
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463 | length > 0 && iter < I915_PDES ? \ |
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464 | (pt = (pd)->page_table[iter]), 1 : 0; \ |
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465 | iter++, \ |
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466 | temp = ALIGN(start+1, 1 << GEN8_PDE_SHIFT) - start, \ |
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467 | temp = min(temp, length), \ |
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468 | start += temp, length -= temp) |
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469 | |||
470 | #define gen8_for_each_pdpe(pd, pdp, start, length, temp, iter) \ |
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471 | for (iter = gen8_pdpe_index(start); \ |
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472 | length > 0 && (iter < I915_PDPES_PER_PDP(dev)) ? \ |
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473 | (pd = (pdp)->page_directory[iter]), 1 : 0; \ |
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474 | iter++, \ |
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475 | temp = ALIGN(start+1, 1 << GEN8_PDPE_SHIFT) - start, \ |
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476 | temp = min(temp, length), \ |
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477 | start += temp, length -= temp) |
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478 | |||
479 | #define gen8_for_each_pml4e(pdp, pml4, start, length, temp, iter) \ |
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480 | for (iter = gen8_pml4e_index(start); \ |
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481 | length > 0 && iter < GEN8_PML4ES_PER_PML4 ? \ |
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482 | (pdp = (pml4)->pdps[iter]), 1 : 0; \ |
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483 | iter++, \ |
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484 | temp = ALIGN(start+1, 1ULL << GEN8_PML4E_SHIFT) - start, \ |
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485 | temp = min(temp, length), \ |
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486 | start += temp, length -= temp) |
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487 | |||
488 | static inline uint32_t gen8_pte_index(uint64_t address) |
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489 | { |
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490 | return i915_pte_index(address, GEN8_PDE_SHIFT); |
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491 | } |
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492 | |||
493 | static inline uint32_t gen8_pde_index(uint64_t address) |
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494 | { |
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495 | return i915_pde_index(address, GEN8_PDE_SHIFT); |
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496 | } |
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497 | |||
498 | static inline uint32_t gen8_pdpe_index(uint64_t address) |
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499 | { |
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500 | return (address >> GEN8_PDPE_SHIFT) & GEN8_PDPE_MASK; |
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501 | } |
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502 | |||
503 | static inline uint32_t gen8_pml4e_index(uint64_t address) |
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504 | { |
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505 | return (address >> GEN8_PML4E_SHIFT) & GEN8_PML4E_MASK; |
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506 | } |
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507 | |||
508 | static inline size_t gen8_pte_count(uint64_t address, uint64_t length) |
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509 | { |
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510 | return i915_pte_count(address, length, GEN8_PDE_SHIFT); |
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511 | } |
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512 | |||
513 | static inline dma_addr_t |
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514 | i915_page_dir_dma_addr(const struct i915_hw_ppgtt *ppgtt, const unsigned n) |
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515 | { |
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516 | return test_bit(n, ppgtt->pdp.used_pdpes) ? |
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517 | px_dma(ppgtt->pdp.page_directory[n]) : |
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518 | px_dma(ppgtt->base.scratch_pd); |
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519 | } |
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520 | |||
5060 | serge | 521 | int i915_gem_gtt_init(struct drm_device *dev); |
522 | void i915_gem_init_global_gtt(struct drm_device *dev); |
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5354 | serge | 523 | void i915_global_gtt_cleanup(struct drm_device *dev); |
5060 | serge | 524 | |
525 | |||
5354 | serge | 526 | int i915_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt); |
527 | int i915_ppgtt_init_hw(struct drm_device *dev); |
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6084 | serge | 528 | int i915_ppgtt_init_ring(struct drm_i915_gem_request *req); |
5354 | serge | 529 | void i915_ppgtt_release(struct kref *kref); |
530 | struct i915_hw_ppgtt *i915_ppgtt_create(struct drm_device *dev, |
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531 | struct drm_i915_file_private *fpriv); |
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532 | static inline void i915_ppgtt_get(struct i915_hw_ppgtt *ppgtt) |
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533 | { |
||
534 | if (ppgtt) |
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535 | kref_get(&ppgtt->ref); |
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536 | } |
||
537 | static inline void i915_ppgtt_put(struct i915_hw_ppgtt *ppgtt) |
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538 | { |
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539 | if (ppgtt) |
||
540 | kref_put(&ppgtt->ref, i915_ppgtt_release); |
||
541 | } |
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542 | |||
5060 | serge | 543 | void i915_check_and_clear_faults(struct drm_device *dev); |
544 | void i915_gem_suspend_gtt_mappings(struct drm_device *dev); |
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545 | void i915_gem_restore_gtt_mappings(struct drm_device *dev); |
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546 | |||
547 | int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj); |
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548 | void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj); |
||
549 | |||
6084 | serge | 550 | static inline bool |
551 | i915_ggtt_view_equal(const struct i915_ggtt_view *a, |
||
552 | const struct i915_ggtt_view *b) |
||
553 | { |
||
554 | if (WARN_ON(!a || !b)) |
||
555 | return false; |
||
556 | |||
557 | if (a->type != b->type) |
||
558 | return false; |
||
559 | if (a->type == I915_GGTT_VIEW_PARTIAL) |
||
560 | return !memcmp(&a->params, &b->params, sizeof(a->params)); |
||
561 | return true; |
||
562 | } |
||
563 | |||
564 | size_t |
||
565 | i915_ggtt_view_size(struct drm_i915_gem_object *obj, |
||
566 | const struct i915_ggtt_view *view); |
||
567 | |||
5060 | serge | 568 | #endif><>>><>>><>>><>>><>>0) |