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Rev | Author | Line No. | Line |
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2326 | Serge | 1 | /* |
2 | * Copyright © 2008 Intel Corporation |
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3 | * |
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4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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5 | * copy of this software and associated documentation files (the "Software"), |
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6 | * to deal in the Software without restriction, including without limitation |
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7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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8 | * and/or sell copies of the Software, and to permit persons to whom the |
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9 | * Software is furnished to do so, subject to the following conditions: |
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10 | * |
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11 | * The above copyright notice and this permission notice (including the next |
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12 | * paragraph) shall be included in all copies or substantial portions of the |
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13 | * Software. |
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14 | * |
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15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
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21 | * IN THE SOFTWARE. |
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22 | * |
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23 | * Authors: |
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24 | * Eric Anholt |
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25 | * |
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26 | */ |
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27 | |||
28 | #include "drmP.h" |
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29 | #include "drm.h" |
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2330 | Serge | 30 | #include "i915_drm.h" |
2326 | Serge | 31 | #include "i915_drv.h" |
32 | //#include "i915_trace.h" |
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33 | #include "intel_drv.h" |
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34 | //#include |
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2330 | Serge | 35 | #include |
2326 | Serge | 36 | //#include |
37 | #include |
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38 | |||
2332 | Serge | 39 | |
40 | #define MAX_ERRNO 4095 |
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41 | |||
42 | #define IS_ERR_VALUE(x) unlikely((x) >= (unsigned long)-MAX_ERRNO) |
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43 | |||
44 | static inline long IS_ERR(const void *ptr) |
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45 | { |
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46 | return IS_ERR_VALUE((unsigned long)ptr); |
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47 | } |
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48 | |||
49 | static inline void *ERR_PTR(long error) |
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50 | { |
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51 | return (void *) error; |
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52 | } |
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53 | |||
54 | static inline long PTR_ERR(const void *ptr) |
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55 | { |
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56 | return (long) ptr; |
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57 | } |
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58 | |||
59 | |||
60 | /** |
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61 | * Initialize an already allocated GEM object of the specified size with |
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62 | * shmfs backing store. |
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63 | */ |
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64 | int drm_gem_object_init(struct drm_device *dev, |
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65 | struct drm_gem_object *obj, size_t size) |
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66 | { |
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67 | BUG_ON((size & (PAGE_SIZE - 1)) != 0); |
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68 | |||
69 | obj->dev = dev; |
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70 | atomic_set(&obj->handle_count, 0); |
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71 | obj->size = size; |
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72 | |||
73 | return 0; |
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74 | } |
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75 | |||
76 | |||
77 | |||
78 | |||
2326 | Serge | 79 | #define I915_EXEC_CONSTANTS_MASK (3<<6) |
80 | #define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) /* default */ |
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81 | #define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6) |
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82 | #define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */ |
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83 | |||
2332 | Serge | 84 | static __must_check int i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj); |
85 | static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); |
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86 | static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj); |
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87 | static __must_check int i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, |
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88 | bool write); |
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89 | static __must_check int i915_gem_object_set_cpu_read_domain_range(struct drm_i915_gem_object *obj, |
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90 | uint64_t offset, |
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91 | uint64_t size); |
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92 | static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_i915_gem_object *obj); |
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93 | static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, |
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94 | unsigned alignment, |
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95 | bool map_and_fenceable); |
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96 | static void i915_gem_clear_fence_reg(struct drm_device *dev, |
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97 | struct drm_i915_fence_reg *reg); |
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98 | static int i915_gem_phys_pwrite(struct drm_device *dev, |
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99 | struct drm_i915_gem_object *obj, |
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100 | struct drm_i915_gem_pwrite *args, |
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101 | struct drm_file *file); |
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102 | static void i915_gem_free_object_tail(struct drm_i915_gem_object *obj); |
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2326 | Serge | 103 | |
2332 | Serge | 104 | static int i915_gem_inactive_shrink(struct shrinker *shrinker, |
105 | struct shrink_control *sc); |
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106 | |||
107 | /* some bookkeeping */ |
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108 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, |
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109 | size_t size) |
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110 | { |
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111 | dev_priv->mm.object_count++; |
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112 | dev_priv->mm.object_memory += size; |
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113 | } |
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114 | |||
115 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, |
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116 | size_t size) |
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117 | { |
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118 | dev_priv->mm.object_count--; |
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119 | dev_priv->mm.object_memory -= size; |
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120 | } |
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121 | |||
122 | #if 0 |
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123 | |||
124 | static int |
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125 | i915_gem_wait_for_error(struct drm_device *dev) |
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126 | { |
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127 | struct drm_i915_private *dev_priv = dev->dev_private; |
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128 | struct completion *x = &dev_priv->error_completion; |
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129 | unsigned long flags; |
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130 | int ret; |
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131 | |||
132 | if (!atomic_read(&dev_priv->mm.wedged)) |
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133 | return 0; |
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134 | |||
135 | ret = wait_for_completion_interruptible(x); |
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136 | if (ret) |
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137 | return ret; |
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138 | |||
139 | if (atomic_read(&dev_priv->mm.wedged)) { |
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140 | /* GPU is hung, bump the completion count to account for |
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141 | * the token we just consumed so that we never hit zero and |
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142 | * end up waiting upon a subsequent completion event that |
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143 | * will never happen. |
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144 | */ |
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145 | spin_lock_irqsave(&x->wait.lock, flags); |
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146 | x->done++; |
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147 | spin_unlock_irqrestore(&x->wait.lock, flags); |
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148 | } |
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149 | return 0; |
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150 | } |
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151 | |||
152 | int i915_mutex_lock_interruptible(struct drm_device *dev) |
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153 | { |
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154 | int ret; |
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155 | |||
156 | ret = i915_gem_wait_for_error(dev); |
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157 | if (ret) |
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158 | return ret; |
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159 | |||
160 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
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161 | if (ret) |
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162 | return ret; |
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163 | |||
164 | WARN_ON(i915_verify_lists(dev)); |
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165 | return 0; |
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166 | } |
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167 | |||
168 | static inline bool |
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169 | i915_gem_object_is_inactive(struct drm_i915_gem_object *obj) |
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170 | { |
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171 | return obj->gtt_space && !obj->active && obj->pin_count == 0; |
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172 | } |
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173 | |||
174 | #endif |
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175 | |||
176 | void i915_gem_do_init(struct drm_device *dev, |
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177 | unsigned long start, |
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178 | unsigned long mappable_end, |
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179 | unsigned long end) |
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180 | { |
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181 | drm_i915_private_t *dev_priv = dev->dev_private; |
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182 | |||
183 | drm_mm_init(&dev_priv->mm.gtt_space, start, end - start); |
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184 | |||
185 | dev_priv->mm.gtt_start = start; |
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186 | dev_priv->mm.gtt_mappable_end = mappable_end; |
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187 | dev_priv->mm.gtt_end = end; |
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188 | dev_priv->mm.gtt_total = end - start; |
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189 | dev_priv->mm.mappable_gtt_total = min(end, mappable_end) - start; |
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190 | |||
191 | /* Take over this portion of the GTT */ |
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192 | intel_gtt_clear_range(start / PAGE_SIZE, (end-start) / PAGE_SIZE); |
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193 | } |
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194 | |||
195 | #if 0 |
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196 | |||
197 | int |
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198 | i915_gem_init_ioctl(struct drm_device *dev, void *data, |
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199 | struct drm_file *file) |
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200 | { |
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201 | struct drm_i915_gem_init *args = data; |
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202 | |||
203 | if (args->gtt_start >= args->gtt_end || |
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204 | (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1)) |
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205 | return -EINVAL; |
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206 | |||
207 | mutex_lock(&dev->struct_mutex); |
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208 | i915_gem_do_init(dev, args->gtt_start, args->gtt_end, args->gtt_end); |
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209 | mutex_unlock(&dev->struct_mutex); |
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210 | |||
211 | return 0; |
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212 | } |
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213 | |||
214 | int |
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215 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
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216 | struct drm_file *file) |
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217 | { |
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218 | struct drm_i915_private *dev_priv = dev->dev_private; |
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219 | struct drm_i915_gem_get_aperture *args = data; |
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220 | struct drm_i915_gem_object *obj; |
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221 | size_t pinned; |
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222 | |||
223 | if (!(dev->driver->driver_features & DRIVER_GEM)) |
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224 | return -ENODEV; |
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225 | |||
226 | pinned = 0; |
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227 | mutex_lock(&dev->struct_mutex); |
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228 | list_for_each_entry(obj, &dev_priv->mm.pinned_list, mm_list) |
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229 | pinned += obj->gtt_space->size; |
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230 | mutex_unlock(&dev->struct_mutex); |
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231 | |||
232 | args->aper_size = dev_priv->mm.gtt_total; |
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233 | args->aper_available_size = args->aper_size -pinned; |
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234 | |||
235 | return 0; |
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236 | } |
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237 | |||
238 | static int |
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239 | i915_gem_create(struct drm_file *file, |
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240 | struct drm_device *dev, |
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241 | uint64_t size, |
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242 | uint32_t *handle_p) |
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243 | { |
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244 | struct drm_i915_gem_object *obj; |
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245 | int ret; |
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246 | u32 handle; |
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247 | |||
248 | size = roundup(size, PAGE_SIZE); |
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249 | |||
250 | /* Allocate the new object */ |
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251 | obj = i915_gem_alloc_object(dev, size); |
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252 | if (obj == NULL) |
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253 | return -ENOMEM; |
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254 | |||
255 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
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256 | if (ret) { |
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257 | drm_gem_object_release(&obj->base); |
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258 | i915_gem_info_remove_obj(dev->dev_private, obj->base.size); |
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259 | kfree(obj); |
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260 | return ret; |
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261 | } |
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262 | |||
263 | /* drop reference from allocate - handle holds it now */ |
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264 | drm_gem_object_unreference(&obj->base); |
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265 | // trace_i915_gem_object_create(obj); |
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266 | |||
267 | *handle_p = handle; |
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268 | return 0; |
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269 | } |
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270 | |||
271 | int |
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272 | i915_gem_dumb_create(struct drm_file *file, |
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273 | struct drm_device *dev, |
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274 | struct drm_mode_create_dumb *args) |
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275 | { |
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276 | /* have to work out size/pitch and return them */ |
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277 | args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64); |
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278 | args->size = args->pitch * args->height; |
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279 | return i915_gem_create(file, dev, |
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280 | args->size, &args->handle); |
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281 | } |
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282 | |||
283 | int i915_gem_dumb_destroy(struct drm_file *file, |
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284 | struct drm_device *dev, |
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285 | uint32_t handle) |
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286 | { |
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287 | return drm_gem_handle_delete(file, handle); |
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288 | } |
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289 | |||
2326 | Serge | 290 | /** |
2332 | Serge | 291 | * Creates a new mm object and returns a handle to it. |
292 | */ |
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293 | int |
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294 | i915_gem_create_ioctl(struct drm_device *dev, void *data, |
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295 | struct drm_file *file) |
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296 | { |
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297 | struct drm_i915_gem_create *args = data; |
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298 | return i915_gem_create(file, dev, |
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299 | args->size, &args->handle); |
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300 | } |
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301 | |||
302 | static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) |
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303 | { |
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304 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
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305 | |||
306 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && |
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307 | obj->tiling_mode != I915_TILING_NONE; |
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308 | } |
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309 | |||
310 | static inline void |
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311 | slow_shmem_copy(struct page *dst_page, |
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312 | int dst_offset, |
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313 | struct page *src_page, |
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314 | int src_offset, |
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315 | int length) |
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316 | { |
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317 | char *dst_vaddr, *src_vaddr; |
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318 | |||
319 | dst_vaddr = kmap(dst_page); |
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320 | src_vaddr = kmap(src_page); |
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321 | |||
322 | memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length); |
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323 | |||
324 | kunmap(src_page); |
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325 | kunmap(dst_page); |
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326 | } |
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327 | |||
328 | static inline void |
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329 | slow_shmem_bit17_copy(struct page *gpu_page, |
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330 | int gpu_offset, |
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331 | struct page *cpu_page, |
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332 | int cpu_offset, |
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333 | int length, |
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334 | int is_read) |
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335 | { |
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336 | char *gpu_vaddr, *cpu_vaddr; |
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337 | |||
338 | /* Use the unswizzled path if this page isn't affected. */ |
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339 | if ((page_to_phys(gpu_page) & (1 << 17)) == 0) { |
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340 | if (is_read) |
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341 | return slow_shmem_copy(cpu_page, cpu_offset, |
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342 | gpu_page, gpu_offset, length); |
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343 | else |
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344 | return slow_shmem_copy(gpu_page, gpu_offset, |
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345 | cpu_page, cpu_offset, length); |
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346 | } |
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347 | |||
348 | gpu_vaddr = kmap(gpu_page); |
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349 | cpu_vaddr = kmap(cpu_page); |
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350 | |||
351 | /* Copy the data, XORing A6 with A17 (1). The user already knows he's |
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352 | * XORing with the other bits (A9 for Y, A9 and A10 for X) |
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353 | */ |
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354 | while (length > 0) { |
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355 | int cacheline_end = ALIGN(gpu_offset + 1, 64); |
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356 | int this_length = min(cacheline_end - gpu_offset, length); |
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357 | int swizzled_gpu_offset = gpu_offset ^ 64; |
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358 | |||
359 | if (is_read) { |
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360 | memcpy(cpu_vaddr + cpu_offset, |
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361 | gpu_vaddr + swizzled_gpu_offset, |
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362 | this_length); |
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363 | } else { |
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364 | memcpy(gpu_vaddr + swizzled_gpu_offset, |
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365 | cpu_vaddr + cpu_offset, |
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366 | this_length); |
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367 | } |
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368 | cpu_offset += this_length; |
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369 | gpu_offset += this_length; |
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370 | length -= this_length; |
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371 | } |
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372 | |||
373 | kunmap(cpu_page); |
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374 | kunmap(gpu_page); |
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375 | } |
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376 | |||
377 | /** |
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378 | * This is the fast shmem pread path, which attempts to copy_from_user directly |
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379 | * from the backing pages of the object to the user's address space. On a |
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380 | * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow(). |
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381 | */ |
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382 | static int |
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383 | i915_gem_shmem_pread_fast(struct drm_device *dev, |
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384 | struct drm_i915_gem_object *obj, |
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385 | struct drm_i915_gem_pread *args, |
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386 | struct drm_file *file) |
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387 | { |
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388 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
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389 | ssize_t remain; |
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390 | loff_t offset; |
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391 | char __user *user_data; |
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392 | int page_offset, page_length; |
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393 | |||
394 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
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395 | remain = args->size; |
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396 | |||
397 | offset = args->offset; |
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398 | |||
399 | while (remain > 0) { |
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400 | struct page *page; |
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401 | char *vaddr; |
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402 | int ret; |
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403 | |||
404 | /* Operation in this page |
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405 | * |
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406 | * page_offset = offset within page |
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407 | * page_length = bytes to copy for this page |
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408 | */ |
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409 | page_offset = offset_in_page(offset); |
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410 | page_length = remain; |
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411 | if ((page_offset + remain) > PAGE_SIZE) |
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412 | page_length = PAGE_SIZE - page_offset; |
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413 | |||
414 | page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT); |
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415 | if (IS_ERR(page)) |
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416 | return PTR_ERR(page); |
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417 | |||
418 | vaddr = kmap_atomic(page); |
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419 | ret = __copy_to_user_inatomic(user_data, |
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420 | vaddr + page_offset, |
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421 | page_length); |
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422 | kunmap_atomic(vaddr); |
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423 | |||
424 | mark_page_accessed(page); |
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425 | page_cache_release(page); |
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426 | if (ret) |
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427 | return -EFAULT; |
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428 | |||
429 | remain -= page_length; |
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430 | user_data += page_length; |
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431 | offset += page_length; |
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432 | } |
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433 | |||
434 | return 0; |
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435 | } |
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436 | |||
437 | /** |
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438 | * This is the fallback shmem pread path, which allocates temporary storage |
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439 | * in kernel space to copy_to_user into outside of the struct_mutex, so we |
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440 | * can copy out of the object's backing pages while holding the struct mutex |
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441 | * and not take page faults. |
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442 | */ |
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443 | static int |
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444 | i915_gem_shmem_pread_slow(struct drm_device *dev, |
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445 | struct drm_i915_gem_object *obj, |
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446 | struct drm_i915_gem_pread *args, |
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447 | struct drm_file *file) |
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448 | { |
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449 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
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450 | struct mm_struct *mm = current->mm; |
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451 | struct page **user_pages; |
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452 | ssize_t remain; |
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453 | loff_t offset, pinned_pages, i; |
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454 | loff_t first_data_page, last_data_page, num_pages; |
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455 | int shmem_page_offset; |
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456 | int data_page_index, data_page_offset; |
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457 | int page_length; |
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458 | int ret; |
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459 | uint64_t data_ptr = args->data_ptr; |
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460 | int do_bit17_swizzling; |
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461 | |||
462 | remain = args->size; |
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463 | |||
464 | /* Pin the user pages containing the data. We can't fault while |
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465 | * holding the struct mutex, yet we want to hold it while |
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466 | * dereferencing the user data. |
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467 | */ |
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468 | first_data_page = data_ptr / PAGE_SIZE; |
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469 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; |
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470 | num_pages = last_data_page - first_data_page + 1; |
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471 | |||
472 | user_pages = drm_malloc_ab(num_pages, sizeof(struct page *)); |
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473 | if (user_pages == NULL) |
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474 | return -ENOMEM; |
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475 | |||
476 | mutex_unlock(&dev->struct_mutex); |
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477 | down_read(&mm->mmap_sem); |
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478 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, |
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479 | num_pages, 1, 0, user_pages, NULL); |
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480 | up_read(&mm->mmap_sem); |
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481 | mutex_lock(&dev->struct_mutex); |
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482 | if (pinned_pages < num_pages) { |
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483 | ret = -EFAULT; |
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484 | goto out; |
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485 | } |
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486 | |||
487 | ret = i915_gem_object_set_cpu_read_domain_range(obj, |
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488 | args->offset, |
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489 | args->size); |
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490 | if (ret) |
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491 | goto out; |
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492 | |||
493 | do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
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494 | |||
495 | offset = args->offset; |
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496 | |||
497 | while (remain > 0) { |
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498 | struct page *page; |
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499 | |||
500 | /* Operation in this page |
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501 | * |
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502 | * shmem_page_offset = offset within page in shmem file |
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503 | * data_page_index = page number in get_user_pages return |
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504 | * data_page_offset = offset with data_page_index page. |
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505 | * page_length = bytes to copy for this page |
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506 | */ |
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507 | shmem_page_offset = offset_in_page(offset); |
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508 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; |
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509 | data_page_offset = offset_in_page(data_ptr); |
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510 | |||
511 | page_length = remain; |
||
512 | if ((shmem_page_offset + page_length) > PAGE_SIZE) |
||
513 | page_length = PAGE_SIZE - shmem_page_offset; |
||
514 | if ((data_page_offset + page_length) > PAGE_SIZE) |
||
515 | page_length = PAGE_SIZE - data_page_offset; |
||
516 | |||
517 | page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT); |
||
518 | if (IS_ERR(page)) { |
||
519 | ret = PTR_ERR(page); |
||
520 | goto out; |
||
521 | } |
||
522 | |||
523 | if (do_bit17_swizzling) { |
||
524 | slow_shmem_bit17_copy(page, |
||
525 | shmem_page_offset, |
||
526 | user_pages[data_page_index], |
||
527 | data_page_offset, |
||
528 | page_length, |
||
529 | 1); |
||
530 | } else { |
||
531 | slow_shmem_copy(user_pages[data_page_index], |
||
532 | data_page_offset, |
||
533 | page, |
||
534 | shmem_page_offset, |
||
535 | page_length); |
||
536 | } |
||
537 | |||
538 | mark_page_accessed(page); |
||
539 | page_cache_release(page); |
||
540 | |||
541 | remain -= page_length; |
||
542 | data_ptr += page_length; |
||
543 | offset += page_length; |
||
544 | } |
||
545 | |||
546 | out: |
||
547 | for (i = 0; i < pinned_pages; i++) { |
||
548 | SetPageDirty(user_pages[i]); |
||
549 | mark_page_accessed(user_pages[i]); |
||
550 | page_cache_release(user_pages[i]); |
||
551 | } |
||
552 | drm_free_large(user_pages); |
||
553 | |||
554 | return ret; |
||
555 | } |
||
556 | #endif |
||
557 | |||
558 | |||
559 | |||
560 | |||
561 | |||
562 | |||
563 | |||
564 | |||
565 | |||
566 | |||
567 | |||
568 | |||
569 | |||
570 | |||
571 | |||
572 | |||
573 | |||
574 | |||
575 | |||
576 | |||
577 | |||
578 | |||
579 | |||
580 | |||
581 | |||
582 | |||
583 | |||
584 | |||
585 | |||
586 | |||
587 | |||
588 | |||
589 | |||
590 | |||
591 | |||
592 | |||
593 | |||
594 | |||
595 | |||
596 | |||
597 | |||
598 | |||
599 | |||
600 | |||
601 | |||
602 | |||
603 | |||
604 | |||
605 | |||
606 | |||
607 | |||
608 | |||
609 | |||
610 | |||
611 | |||
612 | |||
613 | |||
614 | |||
615 | |||
616 | |||
617 | |||
618 | |||
619 | |||
620 | |||
621 | |||
622 | |||
623 | |||
624 | |||
625 | |||
626 | |||
627 | |||
628 | |||
629 | |||
630 | static uint32_t |
||
631 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode) |
||
632 | { |
||
633 | uint32_t gtt_size; |
||
634 | |||
635 | if (INTEL_INFO(dev)->gen >= 4 || |
||
636 | tiling_mode == I915_TILING_NONE) |
||
637 | return size; |
||
638 | |||
639 | /* Previous chips need a power-of-two fence region when tiling */ |
||
640 | if (INTEL_INFO(dev)->gen == 3) |
||
641 | gtt_size = 1024*1024; |
||
642 | else |
||
643 | gtt_size = 512*1024; |
||
644 | |||
645 | while (gtt_size < size) |
||
646 | gtt_size <<= 1; |
||
647 | |||
648 | return gtt_size; |
||
649 | } |
||
650 | |||
651 | /** |
||
652 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object |
||
653 | * @obj: object to check |
||
654 | * |
||
655 | * Return the required GTT alignment for an object, taking into account |
||
656 | * potential fence register mapping. |
||
657 | */ |
||
658 | static uint32_t |
||
659 | i915_gem_get_gtt_alignment(struct drm_device *dev, |
||
660 | uint32_t size, |
||
661 | int tiling_mode) |
||
662 | { |
||
663 | /* |
||
664 | * Minimum alignment is 4k (GTT page size), but might be greater |
||
665 | * if a fence register is needed for the object. |
||
666 | */ |
||
667 | if (INTEL_INFO(dev)->gen >= 4 || |
||
668 | tiling_mode == I915_TILING_NONE) |
||
669 | return 4096; |
||
670 | |||
671 | /* |
||
672 | * Previous chips need to be aligned to the size of the smallest |
||
673 | * fence register that can contain the object. |
||
674 | */ |
||
675 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
||
676 | } |
||
677 | |||
678 | /** |
||
679 | * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an |
||
680 | * unfenced object |
||
681 | * @dev: the device |
||
682 | * @size: size of the object |
||
683 | * @tiling_mode: tiling mode of the object |
||
684 | * |
||
685 | * Return the required GTT alignment for an object, only taking into account |
||
686 | * unfenced tiled surface requirements. |
||
687 | */ |
||
688 | uint32_t |
||
689 | i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev, |
||
690 | uint32_t size, |
||
691 | int tiling_mode) |
||
692 | { |
||
693 | /* |
||
694 | * Minimum alignment is 4k (GTT page size) for sane hw. |
||
695 | */ |
||
696 | if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev) || |
||
697 | tiling_mode == I915_TILING_NONE) |
||
698 | return 4096; |
||
699 | |||
700 | /* Previous hardware however needs to be aligned to a power-of-two |
||
701 | * tile height. The simplest method for determining this is to reuse |
||
702 | * the power-of-tile object size. |
||
703 | */ |
||
704 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
||
705 | } |
||
706 | |||
707 | |||
708 | |||
709 | |||
710 | |||
711 | |||
712 | |||
713 | |||
714 | |||
715 | |||
716 | |||
717 | |||
718 | |||
719 | |||
720 | |||
721 | |||
722 | |||
723 | static int |
||
724 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj, |
||
725 | gfp_t gfpmask) |
||
726 | { |
||
727 | int page_count, i; |
||
728 | struct page *page; |
||
729 | |||
730 | /* Get the list of pages out of our struct file. They'll be pinned |
||
731 | * at this point until we release them. |
||
732 | */ |
||
733 | page_count = obj->base.size / PAGE_SIZE; |
||
734 | BUG_ON(obj->pages != NULL); |
||
735 | obj->pages = malloc(page_count * sizeof(struct page *)); |
||
736 | if (obj->pages == NULL) |
||
737 | return -ENOMEM; |
||
738 | |||
739 | |||
740 | for (i = 0; i < page_count; i++) { |
||
741 | page = (struct page*)AllocPage(); // oh-oh |
||
742 | if (IS_ERR(page)) |
||
743 | goto err_pages; |
||
744 | |||
745 | obj->pages[i] = page; |
||
746 | } |
||
747 | |||
748 | // if (obj->tiling_mode != I915_TILING_NONE) |
||
749 | // i915_gem_object_do_bit_17_swizzle(obj); |
||
750 | |||
751 | |||
2340 | Serge | 752 | |
2332 | Serge | 753 | return 0; |
754 | |||
755 | err_pages: |
||
756 | // while (i--) |
||
757 | // page_cache_release(obj->pages[i]); |
||
758 | |||
759 | free(obj->pages); |
||
760 | obj->pages = NULL; |
||
761 | return PTR_ERR(page); |
||
762 | } |
||
763 | |||
764 | static void |
||
765 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj) |
||
766 | { |
||
767 | int page_count = obj->base.size / PAGE_SIZE; |
||
768 | int i; |
||
769 | |||
770 | BUG_ON(obj->madv == __I915_MADV_PURGED); |
||
771 | |||
772 | // if (obj->tiling_mode != I915_TILING_NONE) |
||
773 | // i915_gem_object_save_bit_17_swizzle(obj); |
||
774 | |||
775 | if (obj->madv == I915_MADV_DONTNEED) |
||
776 | obj->dirty = 0; |
||
777 | /* It's a swap!!! |
||
778 | for (i = 0; i < page_count; i++) { |
||
779 | if (obj->dirty) |
||
780 | set_page_dirty(obj->pages[i]); |
||
781 | |||
782 | if (obj->madv == I915_MADV_WILLNEED) |
||
783 | mark_page_accessed(obj->pages[i]); |
||
784 | |||
785 | //page_cache_release(obj->pages[i]); |
||
786 | } |
||
787 | obj->dirty = 0; |
||
788 | */ |
||
789 | |||
790 | free(obj->pages); |
||
791 | obj->pages = NULL; |
||
792 | } |
||
793 | |||
794 | void |
||
795 | i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, |
||
796 | struct intel_ring_buffer *ring, |
||
797 | u32 seqno) |
||
798 | { |
||
799 | struct drm_device *dev = obj->base.dev; |
||
800 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
801 | |||
802 | BUG_ON(ring == NULL); |
||
803 | obj->ring = ring; |
||
804 | |||
805 | /* Add a reference if we're newly entering the active list. */ |
||
806 | if (!obj->active) { |
||
807 | // drm_gem_object_reference(&obj->base); |
||
808 | obj->active = 1; |
||
809 | } |
||
810 | |||
811 | /* Move from whatever list we were on to the tail of execution. */ |
||
812 | list_move_tail(&obj->mm_list, &dev_priv->mm.active_list); |
||
813 | list_move_tail(&obj->ring_list, &ring->active_list); |
||
814 | |||
815 | obj->last_rendering_seqno = seqno; |
||
816 | if (obj->fenced_gpu_access) { |
||
817 | struct drm_i915_fence_reg *reg; |
||
818 | |||
819 | BUG_ON(obj->fence_reg == I915_FENCE_REG_NONE); |
||
820 | |||
821 | obj->last_fenced_seqno = seqno; |
||
822 | obj->last_fenced_ring = ring; |
||
823 | |||
824 | reg = &dev_priv->fence_regs[obj->fence_reg]; |
||
825 | list_move_tail(®->lru_list, &dev_priv->mm.fence_list); |
||
826 | } |
||
827 | } |
||
828 | |||
829 | |||
830 | |||
831 | |||
832 | static void |
||
833 | i915_gem_process_flushing_list(struct intel_ring_buffer *ring, |
||
834 | uint32_t flush_domains) |
||
835 | { |
||
836 | struct drm_i915_gem_object *obj, *next; |
||
837 | |||
838 | list_for_each_entry_safe(obj, next, |
||
839 | &ring->gpu_write_list, |
||
840 | gpu_write_list) { |
||
841 | if (obj->base.write_domain & flush_domains) { |
||
842 | uint32_t old_write_domain = obj->base.write_domain; |
||
843 | |||
844 | obj->base.write_domain = 0; |
||
845 | list_del_init(&obj->gpu_write_list); |
||
846 | i915_gem_object_move_to_active(obj, ring, |
||
847 | i915_gem_next_request_seqno(ring)); |
||
848 | |||
849 | // trace_i915_gem_object_change_domain(obj, |
||
850 | // obj->base.read_domains, |
||
851 | // old_write_domain); |
||
852 | } |
||
853 | } |
||
854 | } |
||
855 | |||
856 | |||
857 | |||
858 | |||
859 | |||
860 | |||
861 | |||
862 | |||
863 | |||
864 | |||
865 | |||
866 | |||
867 | |||
868 | |||
869 | |||
870 | |||
871 | |||
872 | |||
873 | |||
874 | |||
875 | |||
876 | |||
877 | |||
878 | |||
879 | |||
880 | |||
881 | |||
882 | |||
883 | |||
884 | |||
885 | |||
886 | |||
887 | |||
888 | |||
889 | |||
890 | |||
891 | |||
892 | |||
893 | |||
894 | |||
895 | |||
896 | |||
897 | |||
898 | |||
899 | |||
900 | |||
901 | |||
902 | |||
903 | |||
904 | |||
905 | |||
906 | |||
907 | |||
908 | |||
909 | |||
910 | |||
911 | |||
912 | |||
913 | |||
914 | |||
915 | |||
916 | |||
917 | |||
918 | |||
919 | |||
920 | |||
921 | |||
922 | |||
923 | |||
924 | |||
925 | |||
926 | |||
927 | |||
928 | |||
929 | |||
930 | |||
931 | |||
932 | |||
933 | |||
934 | |||
935 | |||
936 | |||
937 | |||
938 | |||
939 | |||
940 | |||
941 | |||
942 | |||
943 | |||
944 | |||
945 | |||
946 | |||
947 | /** |
||
948 | * Ensures that all rendering to the object has completed and the object is |
||
949 | * safe to unbind from the GTT or access from the CPU. |
||
950 | */ |
||
951 | int |
||
952 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj) |
||
953 | { |
||
954 | int ret; |
||
955 | |||
956 | /* This function only exists to support waiting for existing rendering, |
||
957 | * not for emitting required flushes. |
||
958 | */ |
||
959 | BUG_ON((obj->base.write_domain & I915_GEM_GPU_DOMAINS) != 0); |
||
960 | |||
961 | /* If there is rendering queued on the buffer being evicted, wait for |
||
962 | * it. |
||
963 | */ |
||
964 | // if (obj->active) { |
||
965 | // ret = i915_wait_request(obj->ring, obj->last_rendering_seqno); |
||
966 | // if (ret) |
||
967 | // return ret; |
||
968 | // } |
||
969 | |||
970 | return 0; |
||
971 | } |
||
972 | |||
973 | |||
974 | int |
||
975 | i915_gem_flush_ring(struct intel_ring_buffer *ring, |
||
976 | uint32_t invalidate_domains, |
||
977 | uint32_t flush_domains) |
||
978 | { |
||
979 | int ret; |
||
980 | |||
981 | if (((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) == 0) |
||
982 | return 0; |
||
983 | |||
984 | // trace_i915_gem_ring_flush(ring, invalidate_domains, flush_domains); |
||
985 | |||
986 | ret = ring->flush(ring, invalidate_domains, flush_domains); |
||
987 | if (ret) |
||
988 | return ret; |
||
989 | |||
990 | if (flush_domains & I915_GEM_GPU_DOMAINS) |
||
991 | i915_gem_process_flushing_list(ring, flush_domains); |
||
992 | |||
993 | return 0; |
||
994 | } |
||
995 | |||
996 | |||
997 | |||
998 | |||
999 | |||
1000 | |||
1001 | |||
1002 | |||
1003 | |||
1004 | |||
1005 | |||
1006 | |||
1007 | |||
1008 | |||
1009 | |||
1010 | |||
1011 | |||
1012 | |||
1013 | |||
1014 | |||
1015 | /** |
||
2326 | Serge | 1016 | * i915_gem_clear_fence_reg - clear out fence register info |
1017 | * @obj: object to clear |
||
1018 | * |
||
1019 | * Zeroes out the fence register itself and clears out the associated |
||
1020 | * data structures in dev_priv and obj. |
||
1021 | */ |
||
1022 | static void |
||
1023 | i915_gem_clear_fence_reg(struct drm_device *dev, |
||
1024 | struct drm_i915_fence_reg *reg) |
||
1025 | { |
||
1026 | drm_i915_private_t *dev_priv = dev->dev_private; |
||
1027 | uint32_t fence_reg = reg - dev_priv->fence_regs; |
||
1028 | |||
1029 | switch (INTEL_INFO(dev)->gen) { |
||
1030 | case 7: |
||
1031 | case 6: |
||
1032 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + fence_reg*8, 0); |
||
1033 | break; |
||
1034 | case 5: |
||
1035 | case 4: |
||
1036 | I915_WRITE64(FENCE_REG_965_0 + fence_reg*8, 0); |
||
1037 | break; |
||
1038 | case 3: |
||
1039 | if (fence_reg >= 8) |
||
1040 | fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4; |
||
1041 | else |
||
1042 | case 2: |
||
1043 | fence_reg = FENCE_REG_830_0 + fence_reg * 4; |
||
1044 | |||
1045 | I915_WRITE(fence_reg, 0); |
||
1046 | break; |
||
1047 | } |
||
1048 | |||
1049 | list_del_init(®->lru_list); |
||
1050 | reg->obj = NULL; |
||
1051 | reg->setup_seqno = 0; |
||
1052 | } |
||
1053 | |||
2332 | Serge | 1054 | /** |
1055 | * Finds free space in the GTT aperture and binds the object there. |
||
1056 | */ |
||
1057 | static int |
||
1058 | i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, |
||
1059 | unsigned alignment, |
||
1060 | bool map_and_fenceable) |
||
1061 | { |
||
1062 | struct drm_device *dev = obj->base.dev; |
||
1063 | drm_i915_private_t *dev_priv = dev->dev_private; |
||
1064 | struct drm_mm_node *free_space; |
||
1065 | gfp_t gfpmask = 0; //__GFP_NORETRY | __GFP_NOWARN; |
||
1066 | u32 size, fence_size, fence_alignment, unfenced_alignment; |
||
1067 | bool mappable, fenceable; |
||
1068 | int ret; |
||
2326 | Serge | 1069 | |
2332 | Serge | 1070 | if (obj->madv != I915_MADV_WILLNEED) { |
1071 | DRM_ERROR("Attempting to bind a purgeable object\n"); |
||
1072 | return -EINVAL; |
||
1073 | } |
||
1074 | |||
1075 | fence_size = i915_gem_get_gtt_size(dev, |
||
1076 | obj->base.size, |
||
1077 | obj->tiling_mode); |
||
1078 | fence_alignment = i915_gem_get_gtt_alignment(dev, |
||
1079 | obj->base.size, |
||
1080 | obj->tiling_mode); |
||
1081 | unfenced_alignment = |
||
1082 | i915_gem_get_unfenced_gtt_alignment(dev, |
||
1083 | obj->base.size, |
||
1084 | obj->tiling_mode); |
||
1085 | |||
1086 | if (alignment == 0) |
||
1087 | alignment = map_and_fenceable ? fence_alignment : |
||
1088 | unfenced_alignment; |
||
1089 | if (map_and_fenceable && alignment & (fence_alignment - 1)) { |
||
1090 | DRM_ERROR("Invalid object alignment requested %u\n", alignment); |
||
1091 | return -EINVAL; |
||
1092 | } |
||
1093 | |||
1094 | size = map_and_fenceable ? fence_size : obj->base.size; |
||
1095 | |||
1096 | /* If the object is bigger than the entire aperture, reject it early |
||
1097 | * before evicting everything in a vain attempt to find space. |
||
1098 | */ |
||
1099 | if (obj->base.size > |
||
1100 | (map_and_fenceable ? dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) { |
||
1101 | DRM_ERROR("Attempting to bind an object larger than the aperture\n"); |
||
1102 | return -E2BIG; |
||
1103 | } |
||
1104 | |||
1105 | search_free: |
||
1106 | if (map_and_fenceable) |
||
1107 | free_space = |
||
1108 | drm_mm_search_free_in_range(&dev_priv->mm.gtt_space, |
||
1109 | size, alignment, 0, |
||
1110 | dev_priv->mm.gtt_mappable_end, |
||
1111 | 0); |
||
1112 | else |
||
1113 | free_space = drm_mm_search_free(&dev_priv->mm.gtt_space, |
||
1114 | size, alignment, 0); |
||
1115 | |||
1116 | if (free_space != NULL) { |
||
1117 | if (map_and_fenceable) |
||
1118 | obj->gtt_space = |
||
1119 | drm_mm_get_block_range_generic(free_space, |
||
1120 | size, alignment, 0, |
||
1121 | dev_priv->mm.gtt_mappable_end, |
||
1122 | 0); |
||
1123 | else |
||
1124 | obj->gtt_space = |
||
1125 | drm_mm_get_block(free_space, size, alignment); |
||
1126 | } |
||
1127 | if (obj->gtt_space == NULL) { |
||
1128 | /* If the gtt is empty and we're still having trouble |
||
1129 | * fitting our object in, we're out of memory. |
||
1130 | */ |
||
1131 | ret = 1; //i915_gem_evict_something(dev, size, alignment, |
||
1132 | // map_and_fenceable); |
||
1133 | if (ret) |
||
1134 | return ret; |
||
1135 | |||
1136 | goto search_free; |
||
1137 | } |
||
1138 | |||
1139 | ret = i915_gem_object_get_pages_gtt(obj, gfpmask); |
||
1140 | if (ret) { |
||
1141 | drm_mm_put_block(obj->gtt_space); |
||
1142 | obj->gtt_space = NULL; |
||
1143 | #if 0 |
||
1144 | if (ret == -ENOMEM) { |
||
1145 | /* first try to reclaim some memory by clearing the GTT */ |
||
1146 | ret = i915_gem_evict_everything(dev, false); |
||
1147 | if (ret) { |
||
1148 | /* now try to shrink everyone else */ |
||
1149 | if (gfpmask) { |
||
1150 | gfpmask = 0; |
||
1151 | goto search_free; |
||
1152 | } |
||
1153 | |||
1154 | return -ENOMEM; |
||
1155 | } |
||
1156 | |||
1157 | goto search_free; |
||
1158 | } |
||
1159 | #endif |
||
1160 | return ret; |
||
1161 | } |
||
1162 | |||
1163 | ret = i915_gem_gtt_bind_object(obj); |
||
1164 | if (ret) { |
||
1165 | // i915_gem_object_put_pages_gtt(obj); |
||
1166 | drm_mm_put_block(obj->gtt_space); |
||
1167 | obj->gtt_space = NULL; |
||
1168 | |||
1169 | // if (i915_gem_evict_everything(dev, false)) |
||
1170 | return ret; |
||
1171 | |||
1172 | // goto search_free; |
||
1173 | } |
||
1174 | |||
1175 | list_add_tail(&obj->gtt_list, &dev_priv->mm.gtt_list); |
||
1176 | list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list); |
||
1177 | |||
1178 | /* Assert that the object is not currently in any GPU domain. As it |
||
1179 | * wasn't in the GTT, there shouldn't be any way it could have been in |
||
1180 | * a GPU cache |
||
1181 | */ |
||
1182 | BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); |
||
1183 | BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); |
||
1184 | |||
1185 | obj->gtt_offset = obj->gtt_space->start; |
||
1186 | |||
1187 | fenceable = |
||
1188 | obj->gtt_space->size == fence_size && |
||
1189 | (obj->gtt_space->start & (fence_alignment -1)) == 0; |
||
1190 | |||
1191 | mappable = |
||
1192 | obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end; |
||
1193 | |||
1194 | obj->map_and_fenceable = mappable && fenceable; |
||
1195 | |||
1196 | // trace_i915_gem_object_bind(obj, map_and_fenceable); |
||
1197 | return 0; |
||
1198 | } |
||
1199 | |||
1200 | void |
||
1201 | i915_gem_clflush_object(struct drm_i915_gem_object *obj) |
||
1202 | { |
||
1203 | /* If we don't have a page list set up, then we're not pinned |
||
1204 | * to GPU, and we can ignore the cache flush because it'll happen |
||
1205 | * again at bind time. |
||
1206 | */ |
||
1207 | if (obj->pages == NULL) |
||
1208 | return; |
||
1209 | |||
1210 | /* If the GPU is snooping the contents of the CPU cache, |
||
1211 | * we do not need to manually clear the CPU cache lines. However, |
||
1212 | * the caches are only snooped when the render cache is |
||
1213 | * flushed/invalidated. As we always have to emit invalidations |
||
1214 | * and flushes when moving into and out of the RENDER domain, correct |
||
1215 | * snooping behaviour occurs naturally as the result of our domain |
||
1216 | * tracking. |
||
1217 | */ |
||
1218 | if (obj->cache_level != I915_CACHE_NONE) |
||
1219 | return; |
||
1220 | |||
1221 | // trace_i915_gem_object_clflush(obj); |
||
1222 | |||
1223 | // drm_clflush_pages(obj->pages, obj->base.size / PAGE_SIZE); |
||
1224 | mb(); |
||
1225 | __asm__ ("wbinvd"); // this is really ugly |
||
1226 | mb(); |
||
1227 | } |
||
1228 | |||
1229 | /** Flushes any GPU write domain for the object if it's dirty. */ |
||
1230 | static int |
||
1231 | i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj) |
||
1232 | { |
||
1233 | if ((obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0) |
||
1234 | return 0; |
||
1235 | |||
1236 | /* Queue the GPU write cache flushing we need. */ |
||
1237 | return i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain); |
||
1238 | } |
||
1239 | |||
1240 | |||
1241 | |||
1242 | |||
1243 | |||
1244 | |||
1245 | /** Flushes the CPU write domain for the object if it's dirty. */ |
||
2326 | Serge | 1246 | static void |
2332 | Serge | 1247 | i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj) |
1248 | { |
||
1249 | uint32_t old_write_domain; |
||
1250 | |||
1251 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) |
||
1252 | return; |
||
1253 | |||
1254 | i915_gem_clflush_object(obj); |
||
1255 | intel_gtt_chipset_flush(); |
||
1256 | old_write_domain = obj->base.write_domain; |
||
1257 | obj->base.write_domain = 0; |
||
1258 | |||
1259 | // trace_i915_gem_object_change_domain(obj, |
||
1260 | // obj->base.read_domains, |
||
1261 | // old_write_domain); |
||
1262 | } |
||
1263 | |||
1264 | /** |
||
1265 | * Moves a single object to the GTT read, and possibly write domain. |
||
1266 | * |
||
1267 | * This function returns when the move is complete, including waiting on |
||
1268 | * flushes to occur. |
||
1269 | */ |
||
1270 | int |
||
1271 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
||
1272 | { |
||
1273 | uint32_t old_write_domain, old_read_domains; |
||
1274 | int ret; |
||
1275 | |||
1276 | /* Not valid to be called on unbound objects. */ |
||
1277 | if (obj->gtt_space == NULL) |
||
1278 | return -EINVAL; |
||
1279 | |||
1280 | if (obj->base.write_domain == I915_GEM_DOMAIN_GTT) |
||
1281 | return 0; |
||
1282 | |||
1283 | ret = i915_gem_object_flush_gpu_write_domain(obj); |
||
1284 | if (ret) |
||
1285 | return ret; |
||
1286 | |||
1287 | if (obj->pending_gpu_write || write) { |
||
1288 | ret = i915_gem_object_wait_rendering(obj); |
||
1289 | if (ret) |
||
1290 | return ret; |
||
1291 | } |
||
1292 | |||
1293 | i915_gem_object_flush_cpu_write_domain(obj); |
||
1294 | |||
1295 | old_write_domain = obj->base.write_domain; |
||
1296 | old_read_domains = obj->base.read_domains; |
||
1297 | |||
1298 | /* It should now be out of any other write domains, and we can update |
||
1299 | * the domain values for our changes. |
||
1300 | */ |
||
1301 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
||
1302 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
||
1303 | if (write) { |
||
1304 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
||
1305 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; |
||
1306 | obj->dirty = 1; |
||
1307 | } |
||
1308 | |||
1309 | return 0; |
||
1310 | } |
||
1311 | |||
2335 | Serge | 1312 | #if 0 |
1313 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
||
1314 | enum i915_cache_level cache_level) |
||
1315 | { |
||
1316 | int ret; |
||
2332 | Serge | 1317 | |
2335 | Serge | 1318 | if (obj->cache_level == cache_level) |
1319 | return 0; |
||
2332 | Serge | 1320 | |
2335 | Serge | 1321 | if (obj->pin_count) { |
1322 | DRM_DEBUG("can not change the cache level of pinned objects\n"); |
||
1323 | return -EBUSY; |
||
1324 | } |
||
2332 | Serge | 1325 | |
2335 | Serge | 1326 | if (obj->gtt_space) { |
1327 | ret = i915_gem_object_finish_gpu(obj); |
||
1328 | if (ret) |
||
1329 | return ret; |
||
2332 | Serge | 1330 | |
2335 | Serge | 1331 | i915_gem_object_finish_gtt(obj); |
2332 | Serge | 1332 | |
2335 | Serge | 1333 | /* Before SandyBridge, you could not use tiling or fence |
1334 | * registers with snooped memory, so relinquish any fences |
||
1335 | * currently pointing to our region in the aperture. |
||
1336 | */ |
||
1337 | if (INTEL_INFO(obj->base.dev)->gen < 6) { |
||
1338 | ret = i915_gem_object_put_fence(obj); |
||
1339 | if (ret) |
||
1340 | return ret; |
||
1341 | } |
||
2332 | Serge | 1342 | |
2335 | Serge | 1343 | i915_gem_gtt_rebind_object(obj, cache_level); |
1344 | } |
||
2332 | Serge | 1345 | |
2335 | Serge | 1346 | if (cache_level == I915_CACHE_NONE) { |
1347 | u32 old_read_domains, old_write_domain; |
||
2332 | Serge | 1348 | |
2335 | Serge | 1349 | /* If we're coming from LLC cached, then we haven't |
1350 | * actually been tracking whether the data is in the |
||
1351 | * CPU cache or not, since we only allow one bit set |
||
1352 | * in obj->write_domain and have been skipping the clflushes. |
||
1353 | * Just set it to the CPU cache for now. |
||
1354 | */ |
||
1355 | WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU); |
||
1356 | WARN_ON(obj->base.read_domains & ~I915_GEM_DOMAIN_CPU); |
||
2332 | Serge | 1357 | |
2335 | Serge | 1358 | old_read_domains = obj->base.read_domains; |
1359 | old_write_domain = obj->base.write_domain; |
||
2332 | Serge | 1360 | |
2335 | Serge | 1361 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
1362 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
||
2332 | Serge | 1363 | |
2335 | Serge | 1364 | trace_i915_gem_object_change_domain(obj, |
1365 | old_read_domains, |
||
1366 | old_write_domain); |
||
1367 | } |
||
2332 | Serge | 1368 | |
2335 | Serge | 1369 | obj->cache_level = cache_level; |
1370 | return 0; |
||
1371 | } |
||
1372 | #endif |
||
2332 | Serge | 1373 | |
2335 | Serge | 1374 | /* |
1375 | * Prepare buffer for display plane (scanout, cursors, etc). |
||
1376 | * Can be called from an uninterruptible phase (modesetting) and allows |
||
1377 | * any flushes to be pipelined (for pageflips). |
||
1378 | * |
||
1379 | * For the display plane, we want to be in the GTT but out of any write |
||
1380 | * domains. So in many ways this looks like set_to_gtt_domain() apart from the |
||
1381 | * ability to pipeline the waits, pinning and any additional subtleties |
||
1382 | * that may differentiate the display plane from ordinary buffers. |
||
1383 | */ |
||
1384 | int |
||
1385 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
||
1386 | u32 alignment, |
||
1387 | struct intel_ring_buffer *pipelined) |
||
1388 | { |
||
1389 | u32 old_read_domains, old_write_domain; |
||
1390 | int ret; |
||
2332 | Serge | 1391 | |
2335 | Serge | 1392 | ret = i915_gem_object_flush_gpu_write_domain(obj); |
1393 | if (ret) |
||
1394 | return ret; |
||
2332 | Serge | 1395 | |
2335 | Serge | 1396 | if (pipelined != obj->ring) { |
1397 | ret = i915_gem_object_wait_rendering(obj); |
||
1398 | if (ret == -ERESTARTSYS) |
||
1399 | return ret; |
||
1400 | } |
||
2332 | Serge | 1401 | |
2335 | Serge | 1402 | /* The display engine is not coherent with the LLC cache on gen6. As |
1403 | * a result, we make sure that the pinning that is about to occur is |
||
1404 | * done with uncached PTEs. This is lowest common denominator for all |
||
1405 | * chipsets. |
||
1406 | * |
||
1407 | * However for gen6+, we could do better by using the GFDT bit instead |
||
1408 | * of uncaching, which would allow us to flush all the LLC-cached data |
||
1409 | * with that bit in the PTE to main memory with just one PIPE_CONTROL. |
||
1410 | */ |
||
1411 | // ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE); |
||
1412 | // if (ret) |
||
1413 | // return ret; |
||
2332 | Serge | 1414 | |
2335 | Serge | 1415 | /* As the user may map the buffer once pinned in the display plane |
1416 | * (e.g. libkms for the bootup splash), we have to ensure that we |
||
1417 | * always use map_and_fenceable for all scanout buffers. |
||
1418 | */ |
||
1419 | ret = i915_gem_object_pin(obj, alignment, true); |
||
1420 | if (ret) |
||
1421 | return ret; |
||
2332 | Serge | 1422 | |
2335 | Serge | 1423 | i915_gem_object_flush_cpu_write_domain(obj); |
2332 | Serge | 1424 | |
2335 | Serge | 1425 | old_write_domain = obj->base.write_domain; |
1426 | old_read_domains = obj->base.read_domains; |
||
2332 | Serge | 1427 | |
2335 | Serge | 1428 | /* It should now be out of any other write domains, and we can update |
1429 | * the domain values for our changes. |
||
1430 | */ |
||
1431 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
||
1432 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
||
2332 | Serge | 1433 | |
2335 | Serge | 1434 | // trace_i915_gem_object_change_domain(obj, |
1435 | // old_read_domains, |
||
1436 | // old_write_domain); |
||
2332 | Serge | 1437 | |
2335 | Serge | 1438 | return 0; |
1439 | } |
||
2332 | Serge | 1440 | |
1441 | |||
1442 | |||
1443 | |||
1444 | |||
1445 | |||
1446 | |||
1447 | |||
1448 | |||
1449 | |||
1450 | |||
1451 | |||
1452 | |||
1453 | |||
1454 | |||
1455 | |||
1456 | |||
1457 | |||
1458 | |||
1459 | |||
1460 | |||
1461 | |||
1462 | |||
1463 | |||
1464 | |||
1465 | |||
1466 | |||
1467 | |||
1468 | |||
1469 | |||
1470 | |||
1471 | |||
1472 | |||
1473 | |||
1474 | |||
1475 | |||
1476 | |||
1477 | |||
1478 | |||
1479 | |||
1480 | |||
1481 | |||
1482 | |||
1483 | |||
2335 | Serge | 1484 | |
1485 | |||
2332 | Serge | 1486 | int |
1487 | i915_gem_object_pin(struct drm_i915_gem_object *obj, |
||
1488 | uint32_t alignment, |
||
1489 | bool map_and_fenceable) |
||
1490 | { |
||
1491 | struct drm_device *dev = obj->base.dev; |
||
1492 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
1493 | int ret; |
||
1494 | |||
1495 | BUG_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT); |
||
1496 | // WARN_ON(i915_verify_lists(dev)); |
||
1497 | |||
1498 | #if 0 |
||
1499 | if (obj->gtt_space != NULL) { |
||
1500 | if ((alignment && obj->gtt_offset & (alignment - 1)) || |
||
1501 | (map_and_fenceable && !obj->map_and_fenceable)) { |
||
1502 | WARN(obj->pin_count, |
||
1503 | "bo is already pinned with incorrect alignment:" |
||
1504 | " offset=%x, req.alignment=%x, req.map_and_fenceable=%d," |
||
1505 | " obj->map_and_fenceable=%d\n", |
||
1506 | obj->gtt_offset, alignment, |
||
1507 | map_and_fenceable, |
||
1508 | obj->map_and_fenceable); |
||
1509 | ret = i915_gem_object_unbind(obj); |
||
1510 | if (ret) |
||
1511 | return ret; |
||
1512 | } |
||
1513 | } |
||
1514 | #endif |
||
1515 | |||
1516 | if (obj->gtt_space == NULL) { |
||
1517 | ret = i915_gem_object_bind_to_gtt(obj, alignment, |
||
1518 | map_and_fenceable); |
||
1519 | if (ret) |
||
1520 | return ret; |
||
1521 | } |
||
1522 | |||
1523 | if (obj->pin_count++ == 0) { |
||
1524 | if (!obj->active) |
||
1525 | list_move_tail(&obj->mm_list, |
||
1526 | &dev_priv->mm.pinned_list); |
||
1527 | } |
||
1528 | obj->pin_mappable |= map_and_fenceable; |
||
1529 | |||
1530 | // WARN_ON(i915_verify_lists(dev)); |
||
1531 | return 0; |
||
1532 | } |
||
1533 | |||
1534 | |||
1535 | |||
1536 | |||
1537 | |||
1538 | |||
1539 | |||
1540 | |||
1541 | |||
1542 | |||
1543 | |||
1544 | |||
1545 | |||
1546 | |||
1547 | |||
1548 | |||
1549 | |||
1550 | |||
1551 | |||
1552 | |||
1553 | |||
1554 | |||
1555 | |||
1556 | |||
1557 | |||
1558 | |||
1559 | |||
1560 | |||
1561 | |||
1562 | |||
1563 | |||
1564 | |||
1565 | |||
1566 | |||
1567 | |||
1568 | |||
1569 | |||
1570 | |||
1571 | |||
1572 | |||
1573 | |||
1574 | |||
1575 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
||
1576 | size_t size) |
||
1577 | { |
||
1578 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
1579 | struct drm_i915_gem_object *obj; |
||
2340 | Serge | 1580 | |
2332 | Serge | 1581 | obj = kzalloc(sizeof(*obj), GFP_KERNEL); |
1582 | if (obj == NULL) |
||
1583 | return NULL; |
||
1584 | |||
1585 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
||
1586 | kfree(obj); |
||
1587 | return NULL; |
||
1588 | } |
||
1589 | |||
1590 | |||
1591 | i915_gem_info_add_obj(dev_priv, size); |
||
1592 | |||
1593 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
||
1594 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
||
1595 | |||
1596 | if (IS_GEN6(dev)) { |
||
1597 | /* On Gen6, we can have the GPU use the LLC (the CPU |
||
1598 | * cache) for about a 10% performance improvement |
||
1599 | * compared to uncached. Graphics requests other than |
||
1600 | * display scanout are coherent with the CPU in |
||
1601 | * accessing this cache. This means in this mode we |
||
1602 | * don't need to clflush on the CPU side, and on the |
||
1603 | * GPU side we only need to flush internal caches to |
||
1604 | * get data visible to the CPU. |
||
1605 | * |
||
1606 | * However, we maintain the display planes as UC, and so |
||
1607 | * need to rebind when first used as such. |
||
1608 | */ |
||
1609 | obj->cache_level = I915_CACHE_LLC; |
||
1610 | } else |
||
1611 | obj->cache_level = I915_CACHE_NONE; |
||
1612 | |||
1613 | obj->base.driver_private = NULL; |
||
1614 | obj->fence_reg = I915_FENCE_REG_NONE; |
||
1615 | INIT_LIST_HEAD(&obj->mm_list); |
||
1616 | INIT_LIST_HEAD(&obj->gtt_list); |
||
1617 | INIT_LIST_HEAD(&obj->ring_list); |
||
1618 | INIT_LIST_HEAD(&obj->exec_list); |
||
1619 | INIT_LIST_HEAD(&obj->gpu_write_list); |
||
1620 | obj->madv = I915_MADV_WILLNEED; |
||
1621 | /* Avoid an unnecessary call to unbind on the first bind. */ |
||
1622 | obj->map_and_fenceable = true; |
||
2340 | Serge | 1623 | |
2332 | Serge | 1624 | return obj; |
1625 | } |
||
1626 | |||
1627 | |||
1628 | |||
1629 | |||
1630 | |||
1631 | |||
1632 | |||
1633 | |||
1634 | |||
1635 | |||
1636 | |||
1637 | |||
1638 | |||
1639 | |||
1640 | |||
1641 | |||
1642 | |||
1643 | |||
1644 | |||
1645 | |||
1646 | |||
1647 | |||
1648 | |||
1649 | |||
1650 | int |
||
1651 | i915_gem_init_ringbuffer(struct drm_device *dev) |
||
1652 | { |
||
1653 | drm_i915_private_t *dev_priv = dev->dev_private; |
||
1654 | int ret; |
||
1655 | ENTER(); |
||
1656 | ret = intel_init_render_ring_buffer(dev); |
||
1657 | if (ret) |
||
1658 | return ret; |
||
1659 | |||
1660 | if (HAS_BSD(dev)) { |
||
1661 | ret = intel_init_bsd_ring_buffer(dev); |
||
1662 | if (ret) |
||
1663 | goto cleanup_render_ring; |
||
1664 | } |
||
1665 | |||
1666 | if (HAS_BLT(dev)) { |
||
1667 | ret = intel_init_blt_ring_buffer(dev); |
||
1668 | if (ret) |
||
1669 | goto cleanup_bsd_ring; |
||
1670 | } |
||
1671 | |||
1672 | dev_priv->next_seqno = 1; |
||
1673 | LEAVE(); |
||
1674 | return 0; |
||
1675 | |||
1676 | cleanup_bsd_ring: |
||
1677 | intel_cleanup_ring_buffer(&dev_priv->ring[VCS]); |
||
1678 | cleanup_render_ring: |
||
1679 | intel_cleanup_ring_buffer(&dev_priv->ring[RCS]); |
||
1680 | return ret; |
||
1681 | } |
||
1682 | |||
1683 | #if 0 |
||
1684 | void |
||
1685 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) |
||
1686 | { |
||
1687 | drm_i915_private_t *dev_priv = dev->dev_private; |
||
1688 | int i; |
||
1689 | |||
1690 | for (i = 0; i < I915_NUM_RINGS; i++) |
||
1691 | intel_cleanup_ring_buffer(&dev_priv->ring[i]); |
||
1692 | } |
||
1693 | |||
1694 | int |
||
1695 | i915_gem_entervt_ioctl(struct drm_device *dev, void *data, |
||
1696 | struct drm_file *file_priv) |
||
1697 | { |
||
1698 | drm_i915_private_t *dev_priv = dev->dev_private; |
||
1699 | int ret, i; |
||
1700 | |||
1701 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
||
1702 | return 0; |
||
1703 | |||
1704 | if (atomic_read(&dev_priv->mm.wedged)) { |
||
1705 | DRM_ERROR("Reenabling wedged hardware, good luck\n"); |
||
1706 | atomic_set(&dev_priv->mm.wedged, 0); |
||
1707 | } |
||
1708 | |||
1709 | mutex_lock(&dev->struct_mutex); |
||
1710 | dev_priv->mm.suspended = 0; |
||
1711 | |||
1712 | ret = i915_gem_init_ringbuffer(dev); |
||
1713 | if (ret != 0) { |
||
1714 | mutex_unlock(&dev->struct_mutex); |
||
1715 | return ret; |
||
1716 | } |
||
1717 | |||
1718 | BUG_ON(!list_empty(&dev_priv->mm.active_list)); |
||
1719 | BUG_ON(!list_empty(&dev_priv->mm.flushing_list)); |
||
1720 | BUG_ON(!list_empty(&dev_priv->mm.inactive_list)); |
||
1721 | for (i = 0; i < I915_NUM_RINGS; i++) { |
||
1722 | BUG_ON(!list_empty(&dev_priv->ring[i].active_list)); |
||
1723 | BUG_ON(!list_empty(&dev_priv->ring[i].request_list)); |
||
1724 | } |
||
1725 | mutex_unlock(&dev->struct_mutex); |
||
1726 | |||
1727 | ret = drm_irq_install(dev); |
||
1728 | if (ret) |
||
1729 | goto cleanup_ringbuffer; |
||
1730 | |||
1731 | return 0; |
||
1732 | |||
1733 | cleanup_ringbuffer: |
||
1734 | mutex_lock(&dev->struct_mutex); |
||
1735 | i915_gem_cleanup_ringbuffer(dev); |
||
1736 | dev_priv->mm.suspended = 1; |
||
1737 | mutex_unlock(&dev->struct_mutex); |
||
1738 | |||
1739 | return ret; |
||
1740 | } |
||
1741 | |||
1742 | int |
||
1743 | i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, |
||
1744 | struct drm_file *file_priv) |
||
1745 | { |
||
1746 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
||
1747 | return 0; |
||
1748 | |||
1749 | drm_irq_uninstall(dev); |
||
1750 | return i915_gem_idle(dev); |
||
1751 | } |
||
1752 | |||
1753 | void |
||
1754 | i915_gem_lastclose(struct drm_device *dev) |
||
1755 | { |
||
1756 | int ret; |
||
1757 | |||
1758 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
||
1759 | return; |
||
1760 | |||
1761 | ret = i915_gem_idle(dev); |
||
1762 | if (ret) |
||
1763 | DRM_ERROR("failed to idle hardware: %d\n", ret); |
||
1764 | } |
||
1765 | #endif |
||
1766 | |||
1767 | static void |
||
2326 | Serge | 1768 | init_ring_lists(struct intel_ring_buffer *ring) |
1769 | { |
||
1770 | INIT_LIST_HEAD(&ring->active_list); |
||
1771 | INIT_LIST_HEAD(&ring->request_list); |
||
1772 | INIT_LIST_HEAD(&ring->gpu_write_list); |
||
1773 | } |
||
1774 | |||
1775 | void |
||
1776 | i915_gem_load(struct drm_device *dev) |
||
1777 | { |
||
1778 | int i; |
||
1779 | drm_i915_private_t *dev_priv = dev->dev_private; |
||
1780 | |||
1781 | INIT_LIST_HEAD(&dev_priv->mm.active_list); |
||
1782 | INIT_LIST_HEAD(&dev_priv->mm.flushing_list); |
||
1783 | INIT_LIST_HEAD(&dev_priv->mm.inactive_list); |
||
1784 | INIT_LIST_HEAD(&dev_priv->mm.pinned_list); |
||
1785 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
||
1786 | INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list); |
||
1787 | INIT_LIST_HEAD(&dev_priv->mm.gtt_list); |
||
1788 | for (i = 0; i < I915_NUM_RINGS; i++) |
||
1789 | init_ring_lists(&dev_priv->ring[i]); |
||
1790 | for (i = 0; i < 16; i++) |
||
1791 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); |
||
1792 | // INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
||
1793 | // i915_gem_retire_work_handler); |
||
1794 | // init_completion(&dev_priv->error_completion); |
||
1795 | |||
1796 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
||
1797 | if (IS_GEN3(dev)) { |
||
1798 | u32 tmp = I915_READ(MI_ARB_STATE); |
||
1799 | if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) { |
||
1800 | /* arb state is a masked write, so set bit + bit in mask */ |
||
1801 | tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT); |
||
1802 | I915_WRITE(MI_ARB_STATE, tmp); |
||
1803 | } |
||
1804 | } |
||
1805 | |||
1806 | dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL; |
||
1807 | |||
1808 | if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
||
1809 | dev_priv->num_fence_regs = 16; |
||
1810 | else |
||
1811 | dev_priv->num_fence_regs = 8; |
||
1812 | |||
1813 | /* Initialize fence registers to zero */ |
||
1814 | for (i = 0; i < dev_priv->num_fence_regs; i++) { |
||
1815 | i915_gem_clear_fence_reg(dev, &dev_priv->fence_regs[i]); |
||
1816 | } |
||
1817 | |||
1818 | i915_gem_detect_bit_6_swizzle(dev); |
||
1819 | // init_waitqueue_head(&dev_priv->pending_flip_queue); |
||
1820 | |||
1821 | dev_priv->mm.interruptible = true; |
||
1822 | |||
1823 | // dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink; |
||
1824 | // dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS; |
||
1825 | // register_shrinker(&dev_priv->mm.inactive_shrinker); |
||
1826 | }>><>>>>>>=>>>=><=>>>>><>6)><6)>6) |
||
1827 | |||
1828 | |||
1829 |