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Rev | Author | Line No. | Line |
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1029 | serge | 1 | |
2 | |||
3 | |||
4 | |||
5 | |||
6 | |||
7 | |||
8 | |||
9 | { |
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10 | CHIP_FAMILY_UNKNOW, |
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11 | CHIP_FAMILY_LEGACY, |
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12 | CHIP_FAMILY_RADEON, |
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13 | CHIP_FAMILY_RV100, |
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14 | CHIP_FAMILY_RS100, /* U1 (IGP320M) or A3 (IGP320)*/ |
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15 | CHIP_FAMILY_RV200, |
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16 | CHIP_FAMILY_RS200, /* U2 (IGP330M/340M/350M) or A4 (IGP330/340/345/350), RS250 (IGP 7000) */ |
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17 | CHIP_FAMILY_R200, |
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18 | CHIP_FAMILY_RV250, |
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19 | CHIP_FAMILY_RS300, /* RS300/RS350 */ |
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20 | CHIP_FAMILY_RV280, |
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21 | CHIP_FAMILY_R300, |
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22 | CHIP_FAMILY_R350, |
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23 | CHIP_FAMILY_RV350, |
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24 | CHIP_FAMILY_RV380, /* RV370/RV380/M22/M24 */ |
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25 | CHIP_FAMILY_R420, /* R420/R423/M18 */ |
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26 | CHIP_FAMILY_RV410, /* RV410, M26 */ |
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27 | CHIP_FAMILY_RS400, /* xpress 200, 200m (RS400) Intel */ |
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28 | CHIP_FAMILY_RS480, /* xpress 200, 200m (RS410/480/482/485) AMD */ |
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29 | CHIP_FAMILY_RV515, /* rv515 */ |
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30 | CHIP_FAMILY_R520, /* r520 */ |
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31 | CHIP_FAMILY_RV530, /* rv530 */ |
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32 | CHIP_FAMILY_R580, /* r580 */ |
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33 | CHIP_FAMILY_RV560, /* rv560 */ |
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34 | CHIP_FAMILY_RV570, /* rv570 */ |
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35 | CHIP_FAMILY_RS600, |
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36 | CHIP_FAMILY_RS690, |
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37 | CHIP_FAMILY_RS740, |
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38 | CHIP_FAMILY_R600, /* r600 */ |
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39 | CHIP_FAMILY_R630, |
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40 | CHIP_FAMILY_RV610, |
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41 | CHIP_FAMILY_RV630, |
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42 | CHIP_FAMILY_RV670, |
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43 | CHIP_FAMILY_RV620, |
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44 | CHIP_FAMILY_RV635, |
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45 | CHIP_FAMILY_RS780, |
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46 | CHIP_FAMILY_RV770, |
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47 | CHIP_FAMILY_LAST |
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48 | } RADEONChipFamily; |
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49 | |||
50 | |||
51 | (rhdPtr->ChipFamily == CHIP_FAMILY_RV200) || \ |
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52 | (rhdPtr->ChipFamily == CHIP_FAMILY_RS100) || \ |
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53 | (rhdPtr->ChipFamily == CHIP_FAMILY_RS200) || \ |
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54 | (rhdPtr->ChipFamily == CHIP_FAMILY_RV250) || \ |
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55 | (rhdPtr->ChipFamily == CHIP_FAMILY_RV280) || \ |
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56 | (rhdPtr->ChipFamily == CHIP_FAMILY_RS300)) |
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57 | |||
58 | |||
59 | |||
60 | (info->ChipFamily == CHIP_FAMILY_RV350) || \ |
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61 | (info->ChipFamily == CHIP_FAMILY_R350) || \ |
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62 | (info->ChipFamily == CHIP_FAMILY_RV380) || \ |
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63 | (info->ChipFamily == CHIP_FAMILY_R420) || \ |
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64 | (info->ChipFamily == CHIP_FAMILY_RV410) || \ |
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65 | (info->ChipFamily == CHIP_FAMILY_RS400) || \ |
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66 | (info->ChipFamily == CHIP_FAMILY_RS480)) |
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67 | |||
68 | |||
69 | |||
70 | |||
71 | |||
72 | |||
73 | (info->ChipFamily == CHIP_FAMILY_R520) || \ |
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74 | (info->ChipFamily == CHIP_FAMILY_RV530) || \ |
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75 | (info->ChipFamily == CHIP_FAMILY_R580) || \ |
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76 | (info->ChipFamily == CHIP_FAMILY_RV560) || \ |
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77 | (info->ChipFamily == CHIP_FAMILY_RV570)) |
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78 | |||
79 | |||
80 | (info->ChipFamily == CHIP_FAMILY_RV350) || \ |
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81 | (info->ChipFamily == CHIP_FAMILY_R350) || \ |
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82 | (info->ChipFamily == CHIP_FAMILY_RV380) || \ |
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83 | (info->ChipFamily == CHIP_FAMILY_R420) || \ |
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84 | (info->ChipFamily == CHIP_FAMILY_RV410) || \ |
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85 | (info->ChipFamily == CHIP_FAMILY_RS690) || \ |
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86 | (info->ChipFamily == CHIP_FAMILY_RS600) || \ |
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87 | (info->ChipFamily == CHIP_FAMILY_RS740) || \ |
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88 | (info->ChipFamily == CHIP_FAMILY_RS400) || \ |
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89 | (info->ChipFamily == CHIP_FAMILY_RS480)) |
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90 | |||
91 | |||
92 | |||
93 | CARD_PCI, |
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94 | CARD_AGP, |
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95 | CARD_PCIE |
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96 | } RADEONCardType; |
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97 | |||
98 | |||
99 | RADEON_FAMILY_MASK = 0x0000ffffUL, |
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100 | RADEON_FLAGS_MASK = 0xffff0000UL, |
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101 | RADEON_IS_MOBILITY = 0x00010000UL, |
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102 | RADEON_IS_IGP = 0x00020000UL, |
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103 | RADEON_SINGLE_CRTC = 0x00040000UL, |
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104 | RADEON_IS_AGP = 0x00080000UL, |
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105 | RADEON_HAS_HIERZ = 0x00100000UL, |
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106 | RADEON_IS_PCIE = 0x00200000UL, |
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107 | RADEON_NEW_MEMMAP = 0x00400000UL, |
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108 | RADEON_IS_PCI = 0x00800000UL, |
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109 | RADEON_IS_IGPGART = 0x01000000UL, |
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110 | }; |
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111 | |||
112 | |||
113 | |||
114 | * Errata workarounds |
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115 | */ |
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116 | typedef enum { |
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117 | CHIP_ERRATA_R300_CG = 0x00000001, |
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118 | CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, |
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119 | CHIP_ERRATA_PLL_DELAY = 0x00000004 |
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120 | } RADEONErrata; |
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121 | |||
122 | |||
123 | { |
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124 | u32_t pci_device_id; |
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125 | RADEONChipFamily chip_family; |
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126 | int mobility; |
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127 | int igp; |
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128 | int nocrtc2; |
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129 | int nointtvout; |
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130 | int singledac; |
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131 | } RADEONCardInfo; |
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132 | |||
133 | |||
134 | |||
135 | #define RHD_MMIO_BAR 2 |
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136 | |||
137 | |||
138 | #define RHD_MEM_FB 2 |
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139 | |||
140 | |||
141 | #define R300_DEFAULT_GART_SIZE 32 /* MB (for R300 and above) */ |
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142 | #define RADEON_DEFAULT_RING_SIZE 1 /* MB (must be page aligned) */ |
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143 | #define RADEON_DEFAULT_BUFFER_SIZE 2 /* MB (must be page aligned) */ |
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144 | #define RADEON_DEFAULT_GART_TEX_SIZE 1 /* MB (must be page aligned) */ |
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145 | |||
146 | |||
147 | |||
148 | |||
149 | |||
150 | |||
151 | |||
152 | |||
153 | #define RADEON_TIMEOUT 4000000 /* Fall out of wait loops after this count */ |
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154 | |||
155 | |||
156 | |||
157 | { |
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158 | addr_t MMIOBase; |
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159 | size_t MMIOMapSize; |
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160 | |||
161 | |||
162 | |||
163 | |||
164 | addr_t FbFreeSize; |
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165 | |||
166 | |||
167 | // unsigned int FbScanoutStart; |
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168 | // unsigned int FbScanoutSize; |
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169 | |||
170 | |||
171 | |||
172 | |||
173 | u32_t mc_fb_location; |
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174 | u32_t mc_agp_location; |
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175 | u32_t mc_agp_location_hi; |
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176 | |||
177 | |||
178 | |||
179 | |||
180 | u32_t BusCntl; |
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181 | unsigned long FbMapSize; /* Size of frame buffer, in bytes */ |
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182 | unsigned long FbSecureSize; /* Size of secured fb area at end of |
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183 | framebuffer */ |
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184 | |||
185 | |||
186 | RADEONErrata ChipErrata; |
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187 | |||
188 | |||
189 | |||
190 | |||
191 | Bool IsMobility; |
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192 | Bool HasCRTC2; |
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193 | |||
194 | |||
195 | u32_t devfn; |
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196 | |||
197 | |||
198 | u16_t PciDeviceID; |
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199 | |||
200 | |||
201 | u16_t subdevice_id; |
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202 | |||
203 | |||
204 | |||
205 | |||
206 | u32_t ioBase[6]; |
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207 | u32_t memtype[6]; |
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208 | u32_t memsize[6]; |
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209 | |||
210 | |||
211 | struct mem_block *gart_heap; |
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212 | |||
213 | |||
214 | u32_t displayHeight; |
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215 | |||
216 | |||
217 | u32_t *gart_table; |
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218 | addr_t gart_table_dma; |
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219 | addr_t gart_vm_start; |
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220 | size_t gart_size; |
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221 | |||
222 | |||
223 | u32_t ring_rp; |
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224 | u32_t ring_wp; |
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225 | u32_t ringSize; |
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226 | u32_t ring_avail; |
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227 | |||
228 | |||
229 | u32_t pciAperSize; |
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230 | u32_t CPusecTimeout; |
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231 | |||
232 | |||
233 | int __ymin; |
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234 | int __xmax; |
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235 | int __ymax; |
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236 | |||
237 | |||
238 | u32_t dst_pitch_offset; |
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239 | u32_t surface_cntl; |
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240 | |||
241 | |||
242 | |||
243 | |||
244 | |||
245 | volatile u32_t scratch1; |
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246 | volatile u32_t scratch2; |
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247 | volatile u32_t scratch3; |
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248 | volatile u32_t scratch4; |
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249 | volatile u32_t scratch5; |
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250 | volatile u32_t scratch6; |
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251 | volatile u32_t scratch7; |
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252 | |||
253 | |||
254 | Bool IsDDR; |
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255 | |||
256 | |||
257 | int has_tcl; |
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258 | |||
259 | |||
260 | |||
261 | |||
262 | |||
263 | |||
264 | #define RADEON_CP_PACKET1 0x40000000 |
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265 | #define RADEON_CP_PACKET2 0x80000000 |
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266 | #define RADEON_CP_PACKET3 0xC0000000 |
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267 | |||
268 | |||
269 | # define RADEON_CNTL_BITBLT 0x00009200 |
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270 | # define RADEON_CNTL_TRANBLT 0x00009C00 |
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271 | |||
272 | |||
273 | # define RADEON_CNTL_PAINT_MULTI 0x00009A00 |
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274 | |||
275 | |||
276 | |||
277 | |||
278 | #define FINISH_ACCEL() |
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279 | #define COMMIT_RING() |
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280 | #define OUT_ACCEL_REG(reg, val) OUTREG(reg, val) |
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281 | |||
282 | |||
283 | |||
284 | |||
285 | (RADEON_CP_PACKET0 | ((n - 1 ) << 16) | ((reg) >> 2)) |
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286 | |||
287 | |||
288 | (RADEON_CP_PACKET1 | (((reg1) >> 2) << 11) | ((reg0) >> 2)) |
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289 | |||
290 | |||
291 | (RADEON_CP_PACKET2) |
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292 | |||
293 | |||
294 | (RADEON_CP_PACKET3 | (pkt) | ((n) << 16)) |
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295 | |||
296 | |||
297 | |||
298 | int avail = rhd.ring_rp-rhd.ring_wp; \ |
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299 | if (avail <=0 ) avail+= 0x4000; \ |
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300 | if( (req)+128 > avail) \ |
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301 | { \ |
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302 | rhd.ring_rp = INREG(RADEON_CP_RB_RPTR); \ |
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303 | avail = rhd.ring_rp-rhd.ring_wp; \ |
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304 | if (avail <= 0) avail+= 0x4000; \ |
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305 | if( (req)+128 > avail){ \ |
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306 | unlock_device(); \ |
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307 | return 0; \ |
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308 | }; \ |
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309 | } \ |
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310 | ring = &rhd.ringBase[rhd.ring_wp]; \ |
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311 | }while(0) |
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312 | |||
313 | |||
314 | |||
315 | |||
316 | |||
317 | |||
318 | do { \ |
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319 | ring[0] = CP_PACKET0((reg), 1); \ |
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320 | ring[1] = (val); \ |
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321 | ring+= 2; \ |
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322 | } while (0) |
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323 | |||
324 | |||
325 | |||
326 | |||
327 | rhd.ring_wp = (ring - rhd.ringBase) & 0x3FFF; \ |
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328 | /* Flush writes to ring */ \ |
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329 | DRM_MEMORYBARRIER(); \ |
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330 | /*GET_RING_HEAD( dev_priv ); */ \ |
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331 | OUTREG( RADEON_CP_RB_WPTR, rhd.ring_wp); \ |
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332 | /* read from PCI bus to ensure correct posting */ \ |
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333 | /* INREG( RADEON_CP_RB_RPTR ); */ \ |
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334 | } while (0) |
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335 | |||
336 | |||
337 | #define FINISH_ACCEL() COMMIT_RING() |
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338 | |||
339 | |||
340 | |||
341 | |||
342 | |||
343 | |||
344 | int token; /* id of the token */ |
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345 | const char * name; /* token name */ |
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346 | } SymTabRec, *SymTabPtr; |
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347 | |||
348 | |||
349 | |||
350 | { |
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351 | __asm__ __volatile__ ( |
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352 | "call *__imp__WaitMutex" |
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353 | ::"b" (&rhd.lock)); |
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354 | }; |
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355 | |||
356 | |||
357 | { |
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358 | rhd.lock = 0; |
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359 | } |
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360 | |||
361 | |||
362 | OUTREG8(u16_t offset, u8_t value) |
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363 | { |
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364 | *(volatile u8_t *)((u8_t *)(rhd.MMIOBase + offset)) = value; |
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365 | } |
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366 | |||
367 | |||
368 | |||
369 | { |
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370 | return *(volatile u32_t *)((u8_t*)(rhd.MMIOBase + offset)); |
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371 | } |
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372 | |||
373 | |||
374 | |||
375 | { |
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376 | *(volatile u32_t *)((u8_t *)(rhd.MMIOBase + offset)) = value; |
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377 | } |
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378 | |||
379 | |||
380 | // *(volatile u32_t *)((u8_t *)(rhd.MMIOBase + (u32_t)(offset))) = (u32_t)value |
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381 | |||
382 | |||
383 | |||
384 | { |
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385 | return *(volatile u32_t *)((u8_t*)(rhdPtr->MMIOBase + offset)); |
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386 | } |
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387 | |||
388 | |||
389 | MASKREG(u16_t offset, u32_t value, u32_t mask) |
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390 | { |
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391 | u32_t tmp; |
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392 | |||
393 | |||
394 | tmp &= ~mask; |
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395 | tmp |= (value & mask); |
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396 | OUTREG(offset, tmp); |
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397 | }; |
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398 | |||
399 | |||
400 | |||
401 | |||
402 | |||
403 | |||
404 | |||
405 | |||
406 | _RHDRegWrite(RHDPtr rhdPtr, u16_t offset, u32_t value) |
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407 | { |
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408 | *(volatile u32_t *)((u8_t *)(rhdPtr->MMIOBase + offset)) = value; |
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409 | } |
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410 | |||
411 | |||
412 | _RHDRegMask(RHDPtr rhdPtr, u16_t offset, u32_t value, u32_t mask) |
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413 | { |
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414 | u32_t tmp; |
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415 | |||
416 | |||
417 | tmp &= ~mask; |
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418 | tmp |= (value & mask); |
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419 | _RHDRegWrite(rhdPtr, offset, tmp); |
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420 | }; |
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421 | |||
422 | |||
423 | #define RHDRegWrite(ptr, offset, value) _RHDRegWrite((ptr)->rhdPtr, (offset), (value)) |
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424 | #define RHDRegMask(ptr, offset, value, mask) _RHDRegMask((ptr)->rhdPtr, (offset), (value), (mask)) |
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425 | |||
426 | |||
427 | |||
428 | |||
429 | |||
430 | // #define DBG(x) |
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431 | |||
432 | |||
433 | typedef struct s_cursor |
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434 | { |
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435 | u32_t magic; // 'CURS' |
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436 | void (*destroy)(struct s_cursor*); // destructor |
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437 | u32_t fd; // next object in list |
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438 | u32_t bk; // prev object in list |
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439 | u32_t pid; // owner id |
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440 | |||
441 | |||
442 | u32_t hot_x; // hotspot coords |
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443 | u32_t hot_y; |
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444 | }cursor_t; |
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445 | #pragma pack (pop) |
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446 | |||
447 | |||
448 | #define LOAD_FROM_MEM 1 |
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449 | #define LOAD_INDIRECT 2 |
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450 | |||
451 | |||
452 | void __stdcall copy_cursor(void *img, void *src); |
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453 | void destroy_cursor(cursor_t *cursor); |
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454 | void __destroy_cursor(cursor_t *cursor); // wrap |
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455 | |||
456 | |||
457 | void __stdcall r500_SetCursor(cursor_t *cursor, int x, int y); |
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458 | void __stdcall r500_CursorRestore(int x, int y); |
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459 | |||
460 | |||
461 | |||
462 | u32_t x ; |
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463 | u32_t y ; |
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464 | } xPointFixed; |
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465 | |||
466 | |||
467 | |||
468 | |||
469 | |||
470 | |||
471 | |||
472 | |||
473 | #define IntToxFixed(i) ((xFixed) (i) << XFIXED_BITS) |
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474 | |||
475 | |||
476 | |||
477 | |||
478 | ((type) << 16) | \ |
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479 | ((a) << 12) | \ |
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480 | ((r) << 8) | \ |
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481 | ((g) << 4) | \ |
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482 | ((b))) |
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483 | |||
484 | |||
485 | #define PICT_FORMAT_RGB(f) (((f) ) & 0xfff) |
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486 | |||
487 | |||
488 | #define PICT_TYPE_A 1 |
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489 | #define PICT_TYPE_ARGB 2 |
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490 | #define PICT_TYPE_ABGR 3 |
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491 | #define PICT_TYPE_COLOR 4 |
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492 | #define PICT_TYPE_GRAY 5 |
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493 | |||
494 | |||
495 | PICT_a8r8g8b8 = PICT_FORMAT(32,PICT_TYPE_ARGB,8,8,8,8), |
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496 | PICT_x8r8g8b8 = PICT_FORMAT(32,PICT_TYPE_ARGB,0,8,8,8), |
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497 | PICT_a8b8g8r8 = PICT_FORMAT(32,PICT_TYPE_ABGR,8,8,8,8), |
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498 | PICT_x8b8g8r8 = PICT_FORMAT(32,PICT_TYPE_ABGR,0,8,8,8), |
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499 | |||
500 | |||
501 | PICT_r8g8b8 = PICT_FORMAT(24,PICT_TYPE_ARGB,0,8,8,8), |
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502 | PICT_b8g8r8 = PICT_FORMAT(24,PICT_TYPE_ABGR,0,8,8,8), |
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503 | |||
504 | |||
505 | PICT_r5g6b5 = PICT_FORMAT(16,PICT_TYPE_ARGB,0,5,6,5), |
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506 | PICT_b5g6r5 = PICT_FORMAT(16,PICT_TYPE_ABGR,0,5,6,5), |
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507 | |||
508 | |||
509 | PICT_x1r5g5b5 = PICT_FORMAT(16,PICT_TYPE_ARGB,0,5,5,5), |
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510 | PICT_a1b5g5r5 = PICT_FORMAT(16,PICT_TYPE_ABGR,1,5,5,5), |
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511 | PICT_x1b5g5r5 = PICT_FORMAT(16,PICT_TYPE_ABGR,0,5,5,5), |
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512 | PICT_a4r4g4b4 = PICT_FORMAT(16,PICT_TYPE_ARGB,4,4,4,4), |
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513 | PICT_x4r4g4b4 = PICT_FORMAT(16,PICT_TYPE_ARGB,0,4,4,4), |
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514 | PICT_a4b4g4r4 = PICT_FORMAT(16,PICT_TYPE_ABGR,4,4,4,4), |
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515 | PICT_x4b4g4r4 = PICT_FORMAT(16,PICT_TYPE_ABGR,0,4,4,4), |
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516 | |||
517 | |||
518 | PICT_a8 = PICT_FORMAT(8,PICT_TYPE_A,8,0,0,0), |
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519 | PICT_r3g3b2 = PICT_FORMAT(8,PICT_TYPE_ARGB,0,3,3,2), |
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520 | PICT_b2g3r3 = PICT_FORMAT(8,PICT_TYPE_ABGR,0,3,3,2), |
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521 | PICT_a2r2g2b2 = PICT_FORMAT(8,PICT_TYPE_ARGB,2,2,2,2), |
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522 | PICT_a2b2g2r2 = PICT_FORMAT(8,PICT_TYPE_ABGR,2,2,2,2), |
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523 | |||
524 | |||
525 | PICT_g8 = PICT_FORMAT(8,PICT_TYPE_GRAY,0,0,0,0), |
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526 | |||
527 | |||
528 | |||
529 | |||
530 | PICT_x4g4 = PICT_FORMAT(8,PICT_TYPE_GRAY,0,0,0,0), |
||
531 | |||
532 | |||
533 | PICT_a4 = PICT_FORMAT(4,PICT_TYPE_A,4,0,0,0), |
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534 | PICT_r1g2b1 = PICT_FORMAT(4,PICT_TYPE_ARGB,0,1,2,1), |
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535 | PICT_b1g2r1 = PICT_FORMAT(4,PICT_TYPE_ABGR,0,1,2,1), |
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536 | PICT_a1r1g1b1 = PICT_FORMAT(4,PICT_TYPE_ARGB,1,1,1,1), |
||
537 | PICT_a1b1g1r1 = PICT_FORMAT(4,PICT_TYPE_ABGR,1,1,1,1), |
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538 | |||
539 | |||
540 | PICT_g4 = PICT_FORMAT(4,PICT_TYPE_GRAY,0,0,0,0), |
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541 | |||
542 | |||
543 | PICT_a1 = PICT_FORMAT(1,PICT_TYPE_A,1,0,0,0), |
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544 | |||
545 | |||
546 | } PictFormatShort; |
||
547 | |||
548 | |||
549 | |||
550 | |||
551 | |||
552 | |||
553 | |||
554 | |||
555 | static void init_pipes(RHDPtr info); |
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556 | Bool init_cp(RHDPtr info); |
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