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Rev | Author | Line No. | Line |
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3254 | Serge | 1 | //#include "../bitmap.h" |
2 | |||
3 | #include |
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4 | #include |
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5 | |||
6 | #include "sna.h" |
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7 | |||
3263 | Serge | 8 | #include |
9 | |||
10 | static struct sna_fb sna_fb; |
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3278 | Serge | 11 | static struct kgem_bo *mask_bo; |
3263 | Serge | 12 | |
3291 | Serge | 13 | static int mask_width, mask_height; |
14 | |||
15 | static inline void delay(uint32_t time) |
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16 | { |
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17 | __asm__ __volatile__( |
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18 | "int $0x40" |
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19 | ::"a"(5), "b"(time) |
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20 | :"memory"); |
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21 | }; |
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22 | |||
3258 | Serge | 23 | typedef struct __attribute__((packed)) |
24 | { |
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25 | unsigned handle; |
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26 | unsigned io_code; |
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27 | void *input; |
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28 | int inp_size; |
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29 | void *output; |
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30 | int out_size; |
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31 | }ioctl_t; |
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3254 | Serge | 32 | |
3258 | Serge | 33 | |
34 | static int call_service(ioctl_t *io) |
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35 | { |
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36 | int retval; |
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37 | |||
38 | asm volatile("int $0x40" |
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39 | :"=a"(retval) |
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40 | :"a"(68),"b"(17),"c"(io) |
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41 | :"memory","cc"); |
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42 | |||
43 | return retval; |
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44 | }; |
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45 | |||
3266 | Serge | 46 | static inline void get_proc_info(char *info) |
47 | { |
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48 | __asm__ __volatile__( |
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49 | "int $0x40" |
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50 | : |
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51 | :"a"(9), "b"(info), "c"(-1)); |
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52 | } |
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53 | |||
3254 | Serge | 54 | const struct intel_device_info * |
55 | intel_detect_chipset(struct pci_device *pci); |
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56 | |||
57 | //struct kgem_bo *create_bo(bitmap_t *bitmap); |
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58 | |||
59 | static bool sna_solid_cache_init(struct sna *sna); |
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60 | |||
61 | struct sna *sna_device; |
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62 | |||
3258 | Serge | 63 | static void no_render_reset(struct sna *sna) |
64 | { |
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65 | (void)sna; |
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66 | } |
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67 | |||
3254 | Serge | 68 | void no_render_init(struct sna *sna) |
69 | { |
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70 | struct sna_render *render = &sna->render; |
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71 | |||
72 | memset (render,0, sizeof (*render)); |
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73 | |||
74 | render->prefer_gpu = PREFER_GPU_BLT; |
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75 | |||
76 | render->vertices = render->vertex_data; |
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77 | render->vertex_size = ARRAY_SIZE(render->vertex_data); |
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78 | |||
79 | // render->composite = no_render_composite; |
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80 | |||
81 | // render->copy_boxes = no_render_copy_boxes; |
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82 | // render->copy = no_render_copy; |
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83 | |||
84 | // render->fill_boxes = no_render_fill_boxes; |
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85 | // render->fill = no_render_fill; |
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86 | // render->fill_one = no_render_fill_one; |
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87 | // render->clear = no_render_clear; |
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88 | |||
3258 | Serge | 89 | render->reset = no_render_reset; |
3263 | Serge | 90 | // render->flush = no_render_flush; |
3254 | Serge | 91 | // render->fini = no_render_fini; |
92 | |||
93 | // sna->kgem.context_switch = no_render_context_switch; |
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94 | // sna->kgem.retire = no_render_retire; |
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95 | |||
3258 | Serge | 96 | if (sna->kgem.gen >= 60) |
3254 | Serge | 97 | sna->kgem.ring = KGEM_RENDER; |
98 | |||
99 | sna_vertex_init(sna); |
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100 | } |
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101 | |||
102 | void sna_vertex_init(struct sna *sna) |
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103 | { |
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104 | // pthread_mutex_init(&sna->render.lock, NULL); |
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105 | // pthread_cond_init(&sna->render.wait, NULL); |
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106 | sna->render.active = 0; |
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107 | } |
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108 | |||
3291 | Serge | 109 | int sna_accel_init(struct sna *sna) |
3254 | Serge | 110 | { |
111 | const char *backend; |
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112 | |||
113 | // list_init(&sna->deferred_free); |
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114 | // list_init(&sna->dirty_pixmaps); |
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115 | // list_init(&sna->active_pixmaps); |
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116 | // list_init(&sna->inactive_clock[0]); |
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117 | // list_init(&sna->inactive_clock[1]); |
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118 | |||
119 | // sna_accel_install_timers(sna); |
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120 | |||
121 | |||
122 | backend = "no"; |
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123 | no_render_init(sna); |
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124 | |||
125 | if (sna->info->gen >= 0100) { |
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3280 | Serge | 126 | } else if (sna->info->gen >= 070) { |
3254 | Serge | 127 | if (gen7_render_init(sna)) |
3280 | Serge | 128 | backend = "IvyBridge"; |
3254 | Serge | 129 | } else if (sna->info->gen >= 060) { |
130 | if (gen6_render_init(sna)) |
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131 | backend = "SandyBridge"; |
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3280 | Serge | 132 | } else if (sna->info->gen >= 050) { |
3254 | Serge | 133 | if (gen5_render_init(sna)) |
134 | backend = "Ironlake"; |
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3291 | Serge | 135 | } else if (sna->info->gen >= 040) { |
3254 | Serge | 136 | if (gen4_render_init(sna)) |
137 | backend = "Broadwater/Crestline"; |
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3291 | Serge | 138 | /* } else if (sna->info->gen >= 030) { |
3254 | Serge | 139 | if (gen3_render_init(sna)) |
3291 | Serge | 140 | backend = "gen3"; */ |
3254 | Serge | 141 | } |
142 | |||
143 | DBG(("%s(backend=%s, prefer_gpu=%x)\n", |
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144 | __FUNCTION__, backend, sna->render.prefer_gpu)); |
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145 | |||
146 | kgem_reset(&sna->kgem); |
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147 | |||
148 | // if (!sna_solid_cache_init(sna)) |
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149 | // return false; |
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150 | |||
151 | sna_device = sna; |
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152 | |||
153 | |||
3263 | Serge | 154 | return kgem_init_fb(&sna->kgem, &sna_fb); |
3254 | Serge | 155 | } |
156 | |||
157 | int sna_init(uint32_t service) |
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158 | { |
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159 | ioctl_t io; |
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160 | |||
161 | static struct pci_device device; |
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162 | struct sna *sna; |
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163 | |||
164 | DBG(("%s\n", __FUNCTION__)); |
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165 | |||
3291 | Serge | 166 | sna = malloc(sizeof(*sna)); |
3254 | Serge | 167 | if (sna == NULL) |
3291 | Serge | 168 | return 0; |
3254 | Serge | 169 | |
3291 | Serge | 170 | memset(sna, 0, sizeof(*sna)); |
171 | |||
3254 | Serge | 172 | io.handle = service; |
3256 | Serge | 173 | io.io_code = SRV_GET_PCI_INFO; |
3254 | Serge | 174 | io.input = &device; |
175 | io.inp_size = sizeof(device); |
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176 | io.output = NULL; |
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177 | io.out_size = 0; |
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178 | |||
179 | if (call_service(&io)!=0) |
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3291 | Serge | 180 | { |
181 | free(sna); |
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182 | return 0; |
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183 | }; |
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184 | |||
3254 | Serge | 185 | sna->PciInfo = &device; |
186 | |||
187 | sna->info = intel_detect_chipset(sna->PciInfo); |
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188 | |||
189 | kgem_init(&sna->kgem, service, sna->PciInfo, sna->info->gen); |
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3291 | Serge | 190 | |
191 | delay(10); |
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3254 | Serge | 192 | /* |
193 | if (!xf86ReturnOptValBool(sna->Options, |
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194 | OPTION_RELAXED_FENCING, |
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195 | sna->kgem.has_relaxed_fencing)) { |
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196 | xf86DrvMsg(scrn->scrnIndex, |
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197 | sna->kgem.has_relaxed_fencing ? X_CONFIG : X_PROBED, |
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198 | "Disabling use of relaxed fencing\n"); |
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199 | sna->kgem.has_relaxed_fencing = 0; |
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200 | } |
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201 | if (!xf86ReturnOptValBool(sna->Options, |
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202 | OPTION_VMAP, |
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203 | sna->kgem.has_vmap)) { |
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204 | xf86DrvMsg(scrn->scrnIndex, |
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205 | sna->kgem.has_vmap ? X_CONFIG : X_PROBED, |
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206 | "Disabling use of vmap\n"); |
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207 | sna->kgem.has_vmap = 0; |
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208 | } |
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209 | */ |
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210 | |||
211 | /* Disable tiling by default */ |
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212 | sna->tiling = SNA_TILING_DISABLE; |
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213 | |||
214 | /* Default fail-safe value of 75 Hz */ |
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215 | // sna->vblank_interval = 1000 * 1000 * 1000 / 75; |
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216 | |||
217 | sna->flags = 0; |
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218 | |||
3291 | Serge | 219 | sna_accel_init(sna); |
220 | |||
221 | delay(10); |
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222 | |||
223 | return sna->render.caps; |
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3254 | Serge | 224 | } |
225 | |||
3291 | Serge | 226 | void sna_fini() |
227 | { |
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228 | if( sna_device ) |
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229 | { |
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230 | sna_device->render.fini(sna_device); |
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231 | kgem_bo_destroy(&sna_device->kgem, mask_bo); |
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232 | kgem_close_batches(&sna_device->kgem); |
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233 | kgem_cleanup_cache(&sna_device->kgem); |
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234 | }; |
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235 | } |
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236 | |||
3254 | Serge | 237 | #if 0 |
238 | |||
239 | static bool sna_solid_cache_init(struct sna *sna) |
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240 | { |
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241 | struct sna_solid_cache *cache = &sna->render.solid_cache; |
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242 | |||
243 | DBG(("%s\n", __FUNCTION__)); |
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244 | |||
245 | cache->cache_bo = |
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246 | kgem_create_linear(&sna->kgem, sizeof(cache->color)); |
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247 | if (!cache->cache_bo) |
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248 | return FALSE; |
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249 | |||
250 | /* |
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251 | * Initialise [0] with white since it is very common and filling the |
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252 | * zeroth slot simplifies some of the checks. |
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253 | */ |
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254 | cache->color[0] = 0xffffffff; |
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255 | cache->bo[0] = kgem_create_proxy(cache->cache_bo, 0, sizeof(uint32_t)); |
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256 | cache->bo[0]->pitch = 4; |
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257 | cache->dirty = 1; |
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258 | cache->size = 1; |
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259 | cache->last = 0; |
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260 | |||
261 | return TRUE; |
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262 | } |
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263 | |||
264 | void |
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265 | sna_render_flush_solid(struct sna *sna) |
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266 | { |
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267 | struct sna_solid_cache *cache = &sna->render.solid_cache; |
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268 | |||
269 | DBG(("sna_render_flush_solid(size=%d)\n", cache->size)); |
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270 | assert(cache->dirty); |
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271 | assert(cache->size); |
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272 | |||
273 | kgem_bo_write(&sna->kgem, cache->cache_bo, |
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274 | cache->color, cache->size*sizeof(uint32_t)); |
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275 | cache->dirty = 0; |
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276 | cache->last = 0; |
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277 | } |
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278 | |||
279 | static void |
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280 | sna_render_finish_solid(struct sna *sna, bool force) |
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281 | { |
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282 | struct sna_solid_cache *cache = &sna->render.solid_cache; |
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283 | int i; |
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284 | |||
285 | DBG(("sna_render_finish_solid(force=%d, domain=%d, busy=%d, dirty=%d)\n", |
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286 | force, cache->cache_bo->domain, cache->cache_bo->rq != NULL, cache->dirty)); |
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287 | |||
288 | if (!force && cache->cache_bo->domain != DOMAIN_GPU) |
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289 | return; |
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290 | |||
291 | if (cache->dirty) |
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292 | sna_render_flush_solid(sna); |
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293 | |||
294 | for (i = 0; i < cache->size; i++) { |
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295 | if (cache->bo[i] == NULL) |
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296 | continue; |
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297 | |||
298 | kgem_bo_destroy(&sna->kgem, cache->bo[i]); |
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299 | cache->bo[i] = NULL; |
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300 | } |
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301 | kgem_bo_destroy(&sna->kgem, cache->cache_bo); |
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302 | |||
303 | DBG(("sna_render_finish_solid reset\n")); |
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304 | |||
305 | cache->cache_bo = kgem_create_linear(&sna->kgem, sizeof(cache->color)); |
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306 | cache->bo[0] = kgem_create_proxy(cache->cache_bo, 0, sizeof(uint32_t)); |
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307 | cache->bo[0]->pitch = 4; |
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308 | if (force) |
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309 | cache->size = 1; |
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310 | } |
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311 | |||
312 | |||
313 | struct kgem_bo * |
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314 | sna_render_get_solid(struct sna *sna, uint32_t color) |
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315 | { |
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316 | struct sna_solid_cache *cache = &sna->render.solid_cache; |
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317 | int i; |
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318 | |||
319 | DBG(("%s: %08x\n", __FUNCTION__, color)); |
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320 | |||
321 | // if ((color & 0xffffff) == 0) /* alpha only */ |
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322 | // return kgem_bo_reference(sna->render.alpha_cache.bo[color>>24]); |
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323 | |||
324 | if (color == 0xffffffff) { |
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325 | DBG(("%s(white)\n", __FUNCTION__)); |
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326 | return kgem_bo_reference(cache->bo[0]); |
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327 | } |
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328 | |||
329 | if (cache->color[cache->last] == color) { |
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330 | DBG(("sna_render_get_solid(%d) = %x (last)\n", |
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331 | cache->last, color)); |
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332 | return kgem_bo_reference(cache->bo[cache->last]); |
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333 | } |
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334 | |||
335 | for (i = 1; i < cache->size; i++) { |
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336 | if (cache->color[i] == color) { |
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337 | if (cache->bo[i] == NULL) { |
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338 | DBG(("sna_render_get_solid(%d) = %x (recreate)\n", |
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339 | i, color)); |
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340 | goto create; |
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341 | } else { |
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342 | DBG(("sna_render_get_solid(%d) = %x (old)\n", |
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343 | i, color)); |
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344 | goto done; |
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345 | } |
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346 | } |
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347 | } |
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348 | |||
349 | sna_render_finish_solid(sna, i == ARRAY_SIZE(cache->color)); |
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350 | |||
351 | i = cache->size++; |
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352 | cache->color[i] = color; |
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353 | cache->dirty = 1; |
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354 | DBG(("sna_render_get_solid(%d) = %x (new)\n", i, color)); |
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355 | |||
356 | create: |
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357 | cache->bo[i] = kgem_create_proxy(cache->cache_bo, |
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358 | i*sizeof(uint32_t), sizeof(uint32_t)); |
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359 | cache->bo[i]->pitch = 4; |
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360 | |||
361 | done: |
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362 | cache->last = i; |
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363 | return kgem_bo_reference(cache->bo[i]); |
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364 | } |
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365 | |||
366 | |||
367 | |||
3263 | Serge | 368 | int sna_blit_copy(bitmap_t *src_bitmap, int dst_x, int dst_y, |
369 | int w, int h, int src_x, int src_y) |
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3254 | Serge | 370 | |
371 | { |
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372 | struct sna_copy_op copy; |
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3263 | Serge | 373 | struct _Pixmap src, dst; |
374 | struct kgem_bo *src_bo; |
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3254 | Serge | 375 | |
3266 | Serge | 376 | char proc_info[1024]; |
377 | int winx, winy; |
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378 | |||
379 | get_proc_info(proc_info); |
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380 | |||
381 | winx = *(uint32_t*)(proc_info+34); |
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382 | winy = *(uint32_t*)(proc_info+38); |
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383 | |||
3263 | Serge | 384 | memset(&src, 0, sizeof(src)); |
385 | memset(&dst, 0, sizeof(dst)); |
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3254 | Serge | 386 | |
3263 | Serge | 387 | src.drawable.bitsPerPixel = 32; |
388 | src.drawable.width = src_bitmap->width; |
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389 | src.drawable.height = src_bitmap->height; |
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3254 | Serge | 390 | |
3263 | Serge | 391 | dst.drawable.bitsPerPixel = 32; |
392 | dst.drawable.width = sna_fb.width; |
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393 | dst.drawable.height = sna_fb.height; |
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3291 | Serge | 394 | |
3254 | Serge | 395 | memset(©, 0, sizeof(copy)); |
396 | |||
3263 | Serge | 397 | src_bo = (struct kgem_bo*)src_bitmap->handle; |
398 | |||
399 | if( sna_device->render.copy(sna_device, GXcopy, |
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400 | &src, src_bo, |
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401 | &dst, sna_fb.fb_bo, ©) ) |
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402 | { |
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3266 | Serge | 403 | copy.blt(sna_device, ©, src_x, src_y, w, h, winx+dst_x, winy+dst_y); |
3291 | Serge | 404 | copy.done(sna_device, ©); |
3263 | Serge | 405 | } |
3254 | Serge | 406 | |
3263 | Serge | 407 | kgem_submit(&sna_device->kgem); |
3291 | Serge | 408 | |
3263 | Serge | 409 | // __asm__ __volatile__("int3"); |
3291 | Serge | 410 | |
3254 | Serge | 411 | }; |
3280 | Serge | 412 | #endif |
3254 | Serge | 413 | |
3280 | Serge | 414 | |
3263 | Serge | 415 | int sna_create_bitmap(bitmap_t *bitmap) |
416 | { |
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417 | struct kgem_bo *bo; |
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3291 | Serge | 418 | |
3263 | Serge | 419 | bo = kgem_create_2d(&sna_device->kgem, bitmap->width, bitmap->height, |
420 | 32,I915_TILING_NONE, CREATE_CPU_MAP); |
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3291 | Serge | 421 | |
3263 | Serge | 422 | if(bo == NULL) |
423 | goto err_1; |
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424 | |||
425 | void *map = kgem_bo_map(&sna_device->kgem, bo); |
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426 | if(map == NULL) |
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427 | goto err_2; |
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428 | |||
429 | bitmap->handle = (uint32_t)bo; |
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430 | bitmap->pitch = bo->pitch; |
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431 | bitmap->data = map; |
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432 | |||
433 | return 0; |
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434 | |||
435 | err_2: |
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436 | kgem_bo_destroy(&sna_device->kgem, bo); |
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437 | |||
438 | err_1: |
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3291 | Serge | 439 | return -1; |
3266 | Serge | 440 | |
3263 | Serge | 441 | }; |
3266 | Serge | 442 | |
3291 | Serge | 443 | void sna_destroy_bitmap(bitmap_t *bitmap) |
444 | { |
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445 | struct kgem_bo *bo; |
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446 | |||
447 | bo = (struct kgem_bo *)bitmap->handle; |
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448 | |||
449 | kgem_bo_destroy(&sna_device->kgem, bo); |
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450 | |||
451 | }; |
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452 | |||
3266 | Serge | 453 | void sna_lock_bitmap(bitmap_t *bitmap) |
454 | { |
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455 | struct kgem_bo *bo; |
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456 | |||
457 | bo = (struct kgem_bo *)bitmap->handle; |
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458 | |||
459 | kgem_bo_sync__cpu(&sna_device->kgem, bo); |
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460 | |||
461 | }; |
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462 | |||
3278 | Serge | 463 | int sna_create_mask() |
464 | { |
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465 | struct kgem_bo *bo; |
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466 | int width, height; |
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467 | int i; |
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3266 | Serge | 468 | |
3291 | Serge | 469 | printf("%s width %d height %d\n", __FUNCTION__, sna_fb.width, sna_fb.height); |
3278 | Serge | 470 | |
3291 | Serge | 471 | bo = kgem_create_2d(&sna_device->kgem, sna_fb.width, sna_fb.height, |
3278 | Serge | 472 | 8,I915_TILING_NONE, CREATE_CPU_MAP); |
473 | |||
474 | if(bo == NULL) |
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475 | goto err_1; |
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476 | |||
477 | int *map = kgem_bo_map(&sna_device->kgem, bo); |
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478 | if(map == NULL) |
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479 | goto err_2; |
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480 | |||
481 | memset(map, 0, bo->pitch * height); |
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482 | |||
3291 | Serge | 483 | mask_bo = bo; |
484 | mask_width = width; |
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485 | mask_height = height; |
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486 | |||
3278 | Serge | 487 | return 0; |
488 | |||
489 | err_2: |
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490 | kgem_bo_destroy(&sna_device->kgem, bo); |
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491 | |||
492 | err_1: |
||
493 | return -1; |
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494 | |||
495 | }; |
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3254 | Serge | 496 | |
3278 | Serge | 497 | |
3291 | Serge | 498 | bool |
499 | gen6_composite(struct sna *sna, |
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500 | uint8_t op, |
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501 | PixmapPtr src, struct kgem_bo *src_bo, |
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502 | PixmapPtr mask,struct kgem_bo *mask_bo, |
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503 | PixmapPtr dst, struct kgem_bo *dst_bo, |
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504 | int32_t src_x, int32_t src_y, |
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505 | int32_t msk_x, int32_t msk_y, |
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506 | int32_t dst_x, int32_t dst_y, |
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507 | int32_t width, int32_t height, |
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508 | struct sna_composite_op *tmp); |
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3278 | Serge | 509 | |
510 | |||
511 | #define MAP(ptr) ((void*)((uintptr_t)(ptr) & ~3)) |
||
512 | |||
513 | int sna_blit_tex(bitmap_t *src_bitmap, int dst_x, int dst_y, |
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514 | int w, int h, int src_x, int src_y) |
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515 | |||
3254 | Serge | 516 | { |
517 | |||
3278 | Serge | 518 | // box.x1 = dst_x; |
519 | // box.y1 = dst_y; |
||
520 | // box.x2 = dst_x+w; |
||
521 | // box.y2 = dst_y+h; |
||
3254 | Serge | 522 | |
523 | |||
3278 | Serge | 524 | // cop.box(sna_device, &cop, &box); |
3254 | Serge | 525 | |
3278 | Serge | 526 | struct drm_i915_mask_update update; |
527 | |||
528 | struct sna_composite_op composite; |
||
529 | struct _Pixmap src, dst, mask; |
||
530 | struct kgem_bo *src_bo; |
||
3254 | Serge | 531 | |
3278 | Serge | 532 | char proc_info[1024]; |
533 | int winx, winy, winw, winh; |
||
3254 | Serge | 534 | |
3278 | Serge | 535 | get_proc_info(proc_info); |
3254 | Serge | 536 | |
3278 | Serge | 537 | winx = *(uint32_t*)(proc_info+34); |
538 | winy = *(uint32_t*)(proc_info+38); |
||
539 | winw = *(uint32_t*)(proc_info+42)+1; |
||
540 | winh = *(uint32_t*)(proc_info+46)+1; |
||
541 | |||
3291 | Serge | 542 | VG_CLEAR(update); |
543 | update.handle = mask_bo->handle; |
||
544 | // update.bo_size = __kgem_bo_size(mask_bo); |
||
545 | // update.bo_pitch = mask_bo->pitch; |
||
546 | update.bo_map = (__u32)MAP(mask_bo->map); |
||
547 | drmIoctl(sna_device->kgem.fd, SRV_MASK_UPDATE, &update); |
||
548 | mask_bo->pitch = update.bo_pitch; |
||
549 | |||
3278 | Serge | 550 | memset(&src, 0, sizeof(src)); |
551 | memset(&dst, 0, sizeof(dst)); |
||
552 | memset(&mask, 0, sizeof(dst)); |
||
553 | |||
554 | src.drawable.bitsPerPixel = 32; |
||
555 | src.drawable.width = src_bitmap->width; |
||
556 | src.drawable.height = src_bitmap->height; |
||
557 | |||
558 | dst.drawable.bitsPerPixel = 32; |
||
559 | dst.drawable.width = sna_fb.width; |
||
560 | dst.drawable.height = sna_fb.height; |
||
561 | |||
562 | mask.drawable.bitsPerPixel = 8; |
||
3291 | Serge | 563 | mask.drawable.width = update.width; |
564 | mask.drawable.height = update.height; |
||
3278 | Serge | 565 | |
566 | memset(&composite, 0, sizeof(composite)); |
||
567 | |||
568 | src_bo = (struct kgem_bo*)src_bitmap->handle; |
||
569 | |||
570 | |||
3291 | Serge | 571 | if( sna_device->render.blit_tex(sna_device, PictOpSrc, |
572 | &src, src_bo, |
||
573 | &mask, mask_bo, |
||
574 | &dst, sna_fb.fb_bo, |
||
575 | src_x, src_y, |
||
576 | dst_x, dst_y, |
||
577 | winx+dst_x, winy+dst_y, |
||
578 | w, h, |
||
3278 | Serge | 579 | &composite) ) |
580 | { |
||
3291 | Serge | 581 | struct sna_composite_rectangles r; |
3278 | Serge | 582 | |
583 | r.src.x = src_x; |
||
584 | r.src.y = src_y; |
||
585 | r.mask.x = dst_x; |
||
586 | r.mask.y = dst_y; |
||
3291 | Serge | 587 | r.dst.x = winx+dst_x; |
3278 | Serge | 588 | r.dst.y = winy+dst_y; |
3291 | Serge | 589 | r.width = w; |
590 | r.height = h; |
||
3278 | Serge | 591 | |
592 | composite.blt(sna_device, &composite, &r); |
||
593 | composite.done(sna_device, &composite); |
||
594 | }; |
||
595 | |||
596 | kgem_submit(&sna_device->kgem); |
||
597 | |||
3291 | Serge | 598 | return 0; |
3278 | Serge | 599 | } |
3254 | Serge | 600 | |
601 | |||
602 | |||
603 | |||
604 | |||
3278 | Serge | 605 | |
606 | |||
607 | |||
608 | |||
3254 | Serge | 609 | static const struct intel_device_info intel_generic_info = { |
610 | .gen = -1, |
||
611 | }; |
||
612 | |||
613 | static const struct intel_device_info intel_i915_info = { |
||
614 | .gen = 030, |
||
615 | }; |
||
616 | static const struct intel_device_info intel_i945_info = { |
||
617 | .gen = 031, |
||
618 | }; |
||
619 | |||
620 | static const struct intel_device_info intel_g33_info = { |
||
621 | .gen = 033, |
||
622 | }; |
||
623 | |||
624 | static const struct intel_device_info intel_i965_info = { |
||
625 | .gen = 040, |
||
626 | }; |
||
627 | |||
628 | static const struct intel_device_info intel_g4x_info = { |
||
629 | .gen = 045, |
||
630 | }; |
||
631 | |||
632 | static const struct intel_device_info intel_ironlake_info = { |
||
633 | .gen = 050, |
||
634 | }; |
||
635 | |||
636 | static const struct intel_device_info intel_sandybridge_info = { |
||
637 | .gen = 060, |
||
638 | }; |
||
639 | |||
640 | static const struct intel_device_info intel_ivybridge_info = { |
||
641 | .gen = 070, |
||
642 | }; |
||
643 | |||
644 | static const struct intel_device_info intel_valleyview_info = { |
||
645 | .gen = 071, |
||
646 | }; |
||
647 | |||
648 | static const struct intel_device_info intel_haswell_info = { |
||
649 | .gen = 075, |
||
650 | }; |
||
651 | |||
652 | #define INTEL_DEVICE_MATCH(d,i) \ |
||
653 | { 0x8086, (d), PCI_MATCH_ANY, PCI_MATCH_ANY, 0x3 << 16, 0xff << 16, (intptr_t)(i) } |
||
654 | |||
655 | |||
656 | static const struct pci_id_match intel_device_match[] = { |
||
657 | |||
658 | |||
659 | INTEL_DEVICE_MATCH (PCI_CHIP_I915_G, &intel_i915_info ), |
||
660 | INTEL_DEVICE_MATCH (PCI_CHIP_E7221_G, &intel_i915_info ), |
||
661 | INTEL_DEVICE_MATCH (PCI_CHIP_I915_GM, &intel_i915_info ), |
||
662 | INTEL_DEVICE_MATCH (PCI_CHIP_I945_G, &intel_i945_info ), |
||
663 | INTEL_DEVICE_MATCH (PCI_CHIP_I945_GM, &intel_i945_info ), |
||
664 | INTEL_DEVICE_MATCH (PCI_CHIP_I945_GME, &intel_i945_info ), |
||
665 | |||
666 | INTEL_DEVICE_MATCH (PCI_CHIP_PINEVIEW_M, &intel_g33_info ), |
||
667 | INTEL_DEVICE_MATCH (PCI_CHIP_PINEVIEW_G, &intel_g33_info ), |
||
668 | INTEL_DEVICE_MATCH (PCI_CHIP_G33_G, &intel_g33_info ), |
||
669 | INTEL_DEVICE_MATCH (PCI_CHIP_Q33_G, &intel_g33_info ), |
||
670 | /* Another marketing win: Q35 is another g33 device not a gen4 part |
||
671 | * like its G35 brethren. |
||
672 | */ |
||
673 | INTEL_DEVICE_MATCH (PCI_CHIP_Q35_G, &intel_g33_info ), |
||
674 | |||
675 | INTEL_DEVICE_MATCH (PCI_CHIP_I965_G, &intel_i965_info ), |
||
676 | INTEL_DEVICE_MATCH (PCI_CHIP_G35_G, &intel_i965_info ), |
||
677 | INTEL_DEVICE_MATCH (PCI_CHIP_I965_Q, &intel_i965_info ), |
||
678 | INTEL_DEVICE_MATCH (PCI_CHIP_I946_GZ, &intel_i965_info ), |
||
679 | INTEL_DEVICE_MATCH (PCI_CHIP_I965_GM, &intel_i965_info ), |
||
680 | INTEL_DEVICE_MATCH (PCI_CHIP_I965_GME, &intel_i965_info ), |
||
681 | |||
682 | INTEL_DEVICE_MATCH (PCI_CHIP_GM45_GM, &intel_g4x_info ), |
||
683 | INTEL_DEVICE_MATCH (PCI_CHIP_G45_E_G, &intel_g4x_info ), |
||
684 | INTEL_DEVICE_MATCH (PCI_CHIP_G45_G, &intel_g4x_info ), |
||
685 | INTEL_DEVICE_MATCH (PCI_CHIP_Q45_G, &intel_g4x_info ), |
||
686 | INTEL_DEVICE_MATCH (PCI_CHIP_G41_G, &intel_g4x_info ), |
||
687 | INTEL_DEVICE_MATCH (PCI_CHIP_B43_G, &intel_g4x_info ), |
||
688 | INTEL_DEVICE_MATCH (PCI_CHIP_B43_G1, &intel_g4x_info ), |
||
689 | |||
690 | INTEL_DEVICE_MATCH (PCI_CHIP_IRONLAKE_D_G, &intel_ironlake_info ), |
||
691 | INTEL_DEVICE_MATCH (PCI_CHIP_IRONLAKE_M_G, &intel_ironlake_info ), |
||
692 | |||
693 | INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_GT1, &intel_sandybridge_info ), |
||
694 | INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_GT2, &intel_sandybridge_info ), |
||
695 | INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_GT2_PLUS, &intel_sandybridge_info ), |
||
696 | INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_M_GT1, &intel_sandybridge_info ), |
||
697 | INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_M_GT2, &intel_sandybridge_info ), |
||
698 | INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS, &intel_sandybridge_info ), |
||
699 | INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_S_GT, &intel_sandybridge_info ), |
||
700 | |||
701 | INTEL_DEVICE_MATCH (PCI_CHIP_IVYBRIDGE_M_GT1, &intel_ivybridge_info ), |
||
702 | INTEL_DEVICE_MATCH (PCI_CHIP_IVYBRIDGE_M_GT2, &intel_ivybridge_info ), |
||
703 | INTEL_DEVICE_MATCH (PCI_CHIP_IVYBRIDGE_D_GT1, &intel_ivybridge_info ), |
||
704 | INTEL_DEVICE_MATCH (PCI_CHIP_IVYBRIDGE_D_GT2, &intel_ivybridge_info ), |
||
705 | INTEL_DEVICE_MATCH (PCI_CHIP_IVYBRIDGE_S_GT1, &intel_ivybridge_info ), |
||
706 | INTEL_DEVICE_MATCH (PCI_CHIP_IVYBRIDGE_S_GT2, &intel_ivybridge_info ), |
||
707 | |||
708 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_D_GT1, &intel_haswell_info ), |
||
709 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_D_GT2, &intel_haswell_info ), |
||
710 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_D_GT2_PLUS, &intel_haswell_info ), |
||
711 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_M_GT1, &intel_haswell_info ), |
||
712 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_M_GT2, &intel_haswell_info ), |
||
713 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_M_GT2_PLUS, &intel_haswell_info ), |
||
714 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_S_GT1, &intel_haswell_info ), |
||
715 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_S_GT2, &intel_haswell_info ), |
||
716 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_S_GT2_PLUS, &intel_haswell_info ), |
||
717 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_D_GT1, &intel_haswell_info ), |
||
718 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_D_GT2, &intel_haswell_info ), |
||
719 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_D_GT2_PLUS, &intel_haswell_info ), |
||
720 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_M_GT1, &intel_haswell_info ), |
||
721 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_M_GT2, &intel_haswell_info ), |
||
722 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_M_GT2_PLUS, &intel_haswell_info ), |
||
723 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_S_GT1, &intel_haswell_info ), |
||
724 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_S_GT2, &intel_haswell_info ), |
||
725 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_S_GT2_PLUS, &intel_haswell_info ), |
||
726 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_D_GT1, &intel_haswell_info ), |
||
727 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_D_GT2, &intel_haswell_info ), |
||
728 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_D_GT2_PLUS, &intel_haswell_info ), |
||
729 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_M_GT1, &intel_haswell_info ), |
||
730 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_M_GT2, &intel_haswell_info ), |
||
731 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_M_GT2_PLUS, &intel_haswell_info ), |
||
732 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_S_GT1, &intel_haswell_info ), |
||
733 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_S_GT2, &intel_haswell_info ), |
||
734 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_S_GT2_PLUS, &intel_haswell_info ), |
||
735 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_D_GT1, &intel_haswell_info ), |
||
736 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_D_GT2, &intel_haswell_info ), |
||
737 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_D_GT2_PLUS, &intel_haswell_info ), |
||
738 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_M_GT1, &intel_haswell_info ), |
||
739 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_M_GT2, &intel_haswell_info ), |
||
740 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_M_GT2_PLUS, &intel_haswell_info ), |
||
741 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_S_GT1, &intel_haswell_info ), |
||
742 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_S_GT2, &intel_haswell_info ), |
||
743 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_S_GT2_PLUS, &intel_haswell_info ), |
||
744 | |||
745 | INTEL_DEVICE_MATCH (PCI_CHIP_VALLEYVIEW_PO, &intel_valleyview_info ), |
||
746 | INTEL_DEVICE_MATCH (PCI_CHIP_VALLEYVIEW_1, &intel_valleyview_info ), |
||
747 | INTEL_DEVICE_MATCH (PCI_CHIP_VALLEYVIEW_2, &intel_valleyview_info ), |
||
748 | INTEL_DEVICE_MATCH (PCI_CHIP_VALLEYVIEW_3, &intel_valleyview_info ), |
||
749 | |||
750 | INTEL_DEVICE_MATCH (PCI_MATCH_ANY, &intel_generic_info ), |
||
751 | |||
752 | { 0, 0, 0 }, |
||
753 | }; |
||
754 | |||
755 | const struct pci_id_match *PciDevMatch(uint16_t dev,const struct pci_id_match *list) |
||
756 | { |
||
757 | while(list->device_id) |
||
758 | { |
||
759 | if(dev==list->device_id) |
||
760 | return list; |
||
761 | list++; |
||
762 | } |
||
763 | return NULL; |
||
764 | } |
||
765 | |||
766 | const struct intel_device_info * |
||
767 | intel_detect_chipset(struct pci_device *pci) |
||
768 | { |
||
769 | const struct pci_id_match *ent = NULL; |
||
770 | const char *name = NULL; |
||
771 | int i; |
||
772 | |||
773 | ent = PciDevMatch(pci->device_id, intel_device_match); |
||
774 | |||
775 | if(ent != NULL) |
||
776 | return (const struct intel_device_info*)ent->match_data; |
||
777 | else |
||
778 | return &intel_generic_info; |
||
779 | |||
780 | #if 0 |
||
781 | for (i = 0; intel_chipsets[i].name != NULL; i++) { |
||
782 | if (DEVICE_ID(pci) == intel_chipsets[i].token) { |
||
783 | name = intel_chipsets[i].name; |
||
784 | break; |
||
785 | } |
||
786 | } |
||
787 | if (name == NULL) { |
||
788 | xf86DrvMsg(scrn->scrnIndex, X_WARNING, "unknown chipset\n"); |
||
789 | name = "unknown"; |
||
790 | } else { |
||
791 | xf86DrvMsg(scrn->scrnIndex, from, |
||
792 | "Integrated Graphics Chipset: Intel(R) %s\n", |
||
793 | name); |
||
794 | } |
||
795 | |||
796 | scrn->chipset = name; |
||
797 | #endif |
||
798 | |||
799 | } |
||
800 | |||
801 | |||
3258 | Serge | 802 | int drmIoctl(int fd, unsigned long request, void *arg) |
803 | { |
||
804 | ioctl_t io; |
||
3254 | Serge | 805 | |
3258 | Serge | 806 | io.handle = fd; |
807 | io.io_code = request; |
||
808 | io.input = arg; |
||
809 | io.inp_size = 64; |
||
810 | io.output = NULL; |
||
811 | io.out_size = 0; |
||
3254 | Serge | 812 | |
3258 | Serge | 813 | return call_service(&io); |
814 | }><>><>>> |
||
815 |