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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 4304 | Serge | 1 | /************************************************************************** |
| 2 | * |
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| 3 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
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| 4 | * All Rights Reserved. |
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| 5 | * |
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| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 7 | * copy of this software and associated documentation files (the |
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| 8 | * "Software"), to deal in the Software without restriction, including |
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| 9 | * without limitation the rights to use, copy, modify, merge, publish, |
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| 10 | * distribute, sub license, and/or sell copies of the Software, and to |
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| 11 | * permit persons to whom the Software is furnished to do so, subject to |
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| 12 | * the following conditions: |
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| 13 | * |
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| 14 | * The above copyright notice and this permission notice (including the |
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| 15 | * next paragraph) shall be included in all copies or substantial portions |
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| 16 | * of the Software. |
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| 17 | * |
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| 18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
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| 19 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
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| 20 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
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| 21 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR |
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| 22 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
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| 23 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
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| 24 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
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| 25 | * |
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| 26 | **************************************************************************/ |
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| 27 | |||
| 28 | #ifndef GEN5_RENDER_H |
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| 29 | #define GEN5_RENDER_H |
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| 30 | |||
| 31 | #define GEN5_3D(Pipeline,Opcode,Subopcode) ((3 << 29) | \ |
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| 32 | ((Pipeline) << 27) | \ |
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| 33 | ((Opcode) << 24) | \ |
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| 34 | ((Subopcode) << 16)) |
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| 35 | |||
| 36 | #define GEN5_URB_FENCE GEN5_3D(0, 0, 0) |
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| 37 | #define GEN5_CS_URB_STATE GEN5_3D(0, 0, 1) |
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| 38 | #define GEN5_CONSTANT_BUFFER GEN5_3D(0, 0, 2) |
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| 39 | #define GEN5_STATE_PREFETCH GEN5_3D(0, 0, 3) |
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| 40 | |||
| 41 | #define GEN5_STATE_BASE_ADDRESS GEN5_3D(0, 1, 1) |
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| 42 | #define GEN5_STATE_SIP GEN5_3D(0, 1, 2) |
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| 43 | |||
| 44 | #define GEN5_PIPELINE_SELECT GEN5_3D(1, 1, 4) |
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| 45 | |||
| 46 | #define GEN5_MEDIA_STATE_POINTERS GEN5_3D(2, 0, 0) |
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| 47 | #define GEN5_MEDIA_OBJECT GEN5_3D(2, 1, 0) |
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| 48 | |||
| 49 | #define GEN5_3DSTATE_PIPELINED_POINTERS GEN5_3D(3, 0, 0) |
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| 50 | #define GEN5_3DSTATE_BINDING_TABLE_POINTERS GEN5_3D(3, 0, 1) |
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| 51 | # define GEN6_3DSTATE_BINDING_TABLE_MODIFY_PS (1 << 12)/* for GEN6 */ |
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| 52 | # define GEN6_3DSTATE_BINDING_TABLE_MODIFY_GS (1 << 9) /* for GEN6 */ |
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| 53 | # define GEN6_3DSTATE_BINDING_TABLE_MODIFY_VS (1 << 8) /* for GEN6 */ |
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| 54 | |||
| 55 | #define GEN5_3DSTATE_VERTEX_BUFFERS GEN5_3D(3, 0, 8) |
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| 56 | #define GEN5_3DSTATE_VERTEX_ELEMENTS GEN5_3D(3, 0, 9) |
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| 57 | #define GEN5_3DSTATE_INDEX_BUFFER GEN5_3D(3, 0, 0xa) |
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| 58 | #define GEN5_3DSTATE_VF_STATISTICS GEN5_3D(3, 0, 0xb) |
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| 59 | |||
| 60 | #define GEN5_3DSTATE_DRAWING_RECTANGLE GEN5_3D(3, 1, 0) |
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| 61 | #define GEN5_3DSTATE_CONSTANT_COLOR GEN5_3D(3, 1, 1) |
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| 62 | #define GEN5_3DSTATE_SAMPLER_PALETTE_LOAD GEN5_3D(3, 1, 2) |
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| 63 | #define GEN5_3DSTATE_CHROMA_KEY GEN5_3D(3, 1, 4) |
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| 64 | #define GEN5_3DSTATE_DEPTH_BUFFER GEN5_3D(3, 1, 5) |
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| 65 | # define GEN5_3DSTATE_DEPTH_BUFFER_TYPE_SHIFT 29 |
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| 66 | # define GEN5_3DSTATE_DEPTH_BUFFER_FORMAT_SHIFT 18 |
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| 67 | |||
| 68 | #define GEN5_3DSTATE_POLY_STIPPLE_OFFSET GEN5_3D(3, 1, 6) |
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| 69 | #define GEN5_3DSTATE_POLY_STIPPLE_PATTERN GEN5_3D(3, 1, 7) |
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| 70 | #define GEN5_3DSTATE_LINE_STIPPLE GEN5_3D(3, 1, 8) |
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| 71 | #define GEN5_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP GEN5_3D(3, 1, 9) |
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| 72 | /* These two are BLC and CTG only, not BW or CL */ |
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| 73 | #define GEN5_3DSTATE_AA_LINE_PARAMS GEN5_3D(3, 1, 0xa) |
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| 74 | #define GEN5_3DSTATE_GS_SVB_INDEX GEN5_3D(3, 1, 0xb) |
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| 75 | |||
| 76 | #define GEN5_PIPE_CONTROL GEN5_3D(3, 2, 0) |
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| 77 | |||
| 78 | #define GEN5_3DPRIMITIVE GEN5_3D(3, 3, 0) |
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| 79 | |||
| 80 | #define GEN5_3DSTATE_CLEAR_PARAMS GEN5_3D(3, 1, 0x10) |
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| 81 | /* DW1 */ |
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| 82 | # define GEN5_3DSTATE_DEPTH_CLEAR_VALID (1 << 15) |
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| 83 | |||
| 84 | /* for GEN6+ */ |
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| 85 | #define GEN6_3DSTATE_SAMPLER_STATE_POINTERS GEN5_3D(3, 0, 0x02) |
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| 86 | # define GEN6_3DSTATE_SAMPLER_STATE_MODIFY_PS (1 << 12) |
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| 87 | # define GEN6_3DSTATE_SAMPLER_STATE_MODIFY_GS (1 << 9) |
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| 88 | # define GEN6_3DSTATE_SAMPLER_STATE_MODIFY_VS (1 << 8) |
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| 89 | |||
| 90 | #define GEN6_3DSTATE_URB GEN5_3D(3, 0, 0x05) |
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| 91 | /* DW1 */ |
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| 92 | # define GEN6_3DSTATE_URB_VS_SIZE_SHIFT 16 |
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| 93 | # define GEN6_3DSTATE_URB_VS_ENTRIES_SHIFT 0 |
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| 94 | /* DW2 */ |
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| 95 | # define GEN6_3DSTATE_URB_GS_ENTRIES_SHIFT 8 |
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| 96 | # define GEN6_3DSTATE_URB_GS_SIZE_SHIFT 0 |
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| 97 | |||
| 98 | #define GEN6_3DSTATE_VIEWPORT_STATE_POINTERS GEN5_3D(3, 0, 0x0d) |
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| 99 | # define GEN6_3DSTATE_VIEWPORT_STATE_MODIFY_CC (1 << 12) |
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| 100 | # define GEN6_3DSTATE_VIEWPORT_STATE_MODIFY_SF (1 << 11) |
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| 101 | # define GEN6_3DSTATE_VIEWPORT_STATE_MODIFY_CLIP (1 << 10) |
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| 102 | |||
| 103 | #define GEN6_3DSTATE_CC_STATE_POINTERS GEN5_3D(3, 0, 0x0e) |
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| 104 | |||
| 105 | #define GEN6_3DSTATE_VS GEN5_3D(3, 0, 0x10) |
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| 106 | |||
| 107 | #define GEN6_3DSTATE_GS GEN5_3D(3, 0, 0x11) |
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| 108 | /* DW4 */ |
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| 109 | # define GEN6_3DSTATE_GS_DISPATCH_START_GRF_SHIFT 0 |
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| 110 | |||
| 111 | #define GEN6_3DSTATE_CLIP GEN5_3D(3, 0, 0x12) |
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| 112 | |||
| 113 | #define GEN6_3DSTATE_SF GEN5_3D(3, 0, 0x13) |
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| 114 | /* DW1 */ |
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| 115 | # define GEN6_3DSTATE_SF_NUM_OUTPUTS_SHIFT 22 |
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| 116 | # define GEN6_3DSTATE_SF_URB_ENTRY_READ_LENGTH_SHIFT 11 |
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| 117 | # define GEN6_3DSTATE_SF_URB_ENTRY_READ_OFFSET_SHIFT 4 |
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| 118 | /* DW2 */ |
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| 119 | /* DW3 */ |
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| 120 | # define GEN6_3DSTATE_SF_CULL_BOTH (0 << 29) |
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| 121 | # define GEN6_3DSTATE_SF_CULL_NONE (1 << 29) |
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| 122 | # define GEN6_3DSTATE_SF_CULL_FRONT (2 << 29) |
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| 123 | # define GEN6_3DSTATE_SF_CULL_BACK (3 << 29) |
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| 124 | /* DW4 */ |
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| 125 | # define GEN6_3DSTATE_SF_TRI_PROVOKE_SHIFT 29 |
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| 126 | # define GEN6_3DSTATE_SF_LINE_PROVOKE_SHIFT 27 |
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| 127 | # define GEN6_3DSTATE_SF_TRIFAN_PROVOKE_SHIFT 25 |
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| 128 | |||
| 129 | |||
| 130 | #define GEN6_3DSTATE_WM GEN5_3D(3, 0, 0x14) |
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| 131 | /* DW2 */ |
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| 132 | # define GEN6_3DSTATE_WM_SAMPLER_COUNT_SHITF 27 |
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| 133 | # define GEN6_3DSTATE_WM_BINDING_TABLE_ENTRY_COUNT_SHIFT 18 |
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| 134 | /* DW4 */ |
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| 135 | # define GEN6_3DSTATE_WM_DISPATCH_START_GRF_0_SHIFT 16 |
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| 136 | /* DW5 */ |
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| 137 | # define GEN6_3DSTATE_WM_MAX_THREADS_SHIFT 25 |
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| 138 | # define GEN6_3DSTATE_WM_DISPATCH_ENABLE (1 << 19) |
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| 139 | # define GEN6_3DSTATE_WM_16_DISPATCH_ENABLE (1 << 1) |
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| 140 | # define GEN6_3DSTATE_WM_8_DISPATCH_ENABLE (1 << 0) |
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| 141 | /* DW6 */ |
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| 142 | # define GEN6_3DSTATE_WM_NUM_SF_OUTPUTS_SHIFT 20 |
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| 143 | # define GEN6_3DSTATE_WM_NONPERSPECTIVE_SAMPLE_BARYCENTRIC (1 << 15) |
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| 144 | # define GEN6_3DSTATE_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC (1 << 14) |
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| 145 | # define GEN6_3DSTATE_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC (1 << 13) |
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| 146 | # define GEN6_3DSTATE_WM_PERSPECTIVE_SAMPLE_BARYCENTRIC (1 << 12) |
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| 147 | # define GEN6_3DSTATE_WM_PERSPECTIVE_CENTROID_BARYCENTRIC (1 << 11) |
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| 148 | # define GEN6_3DSTATE_WM_PERSPECTIVE_PIXEL_BARYCENTRIC (1 << 10) |
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| 149 | |||
| 150 | |||
| 151 | #define GEN6_3DSTATE_CONSTANT_VS GEN5_3D(3, 0, 0x15) |
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| 152 | #define GEN6_3DSTATE_CONSTANT_GS GEN5_3D(3, 0, 0x16) |
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| 153 | #define GEN6_3DSTATE_CONSTANT_PS GEN5_3D(3, 0, 0x17) |
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| 154 | |||
| 155 | #define GEN6_3DSTATE_SAMPLE_MASK GEN5_3D(3, 0, 0x18) |
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| 156 | |||
| 157 | #define GEN6_3DSTATE_MULTISAMPLE GEN5_3D(3, 1, 0x0d) |
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| 158 | /* DW1 */ |
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| 159 | # define GEN6_3DSTATE_MULTISAMPLE_PIXEL_LOCATION_CENTER (0 << 4) |
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| 160 | # define GEN6_3DSTATE_MULTISAMPLE_PIXEL_LOCATION_UPPER_LEFT (1 << 4) |
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| 161 | # define GEN6_3DSTATE_MULTISAMPLE_NUMSAMPLES_1 (0 << 1) |
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| 162 | # define GEN6_3DSTATE_MULTISAMPLE_NUMSAMPLES_4 (2 << 1) |
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| 163 | # define GEN6_3DSTATE_MULTISAMPLE_NUMSAMPLES_8 (3 << 1) |
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| 164 | |||
| 165 | #define PIPELINE_SELECT_3D 0 |
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| 166 | #define PIPELINE_SELECT_MEDIA 1 |
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| 167 | |||
| 168 | #define UF0_CS_REALLOC (1 << 13) |
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| 169 | #define UF0_VFE_REALLOC (1 << 12) |
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| 170 | #define UF0_SF_REALLOC (1 << 11) |
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| 171 | #define UF0_CLIP_REALLOC (1 << 10) |
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| 172 | #define UF0_GS_REALLOC (1 << 9) |
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| 173 | #define UF0_VS_REALLOC (1 << 8) |
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| 174 | #define UF1_CLIP_FENCE_SHIFT 20 |
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| 175 | #define UF1_GS_FENCE_SHIFT 10 |
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| 176 | #define UF1_VS_FENCE_SHIFT 0 |
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| 177 | #define UF2_CS_FENCE_SHIFT 20 |
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| 178 | #define UF2_VFE_FENCE_SHIFT 10 |
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| 179 | #define UF2_SF_FENCE_SHIFT 0 |
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| 180 | |||
| 181 | /* for GEN5_STATE_BASE_ADDRESS */ |
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| 182 | #define BASE_ADDRESS_MODIFY (1 << 0) |
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| 183 | |||
| 184 | /* for GEN5_3DSTATE_PIPELINED_POINTERS */ |
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| 185 | #define GEN5_GS_DISABLE 0 |
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| 186 | #define GEN5_GS_ENABLE 1 |
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| 187 | #define GEN5_CLIP_DISABLE 0 |
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| 188 | #define GEN5_CLIP_ENABLE 1 |
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| 189 | |||
| 190 | /* for GEN5_PIPE_CONTROL */ |
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| 191 | #define GEN5_PIPE_CONTROL_NOWRITE (0 << 14) |
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| 192 | #define GEN5_PIPE_CONTROL_WRITE_QWORD (1 << 14) |
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| 193 | #define GEN5_PIPE_CONTROL_WRITE_DEPTH (2 << 14) |
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| 194 | #define GEN5_PIPE_CONTROL_WRITE_TIME (3 << 14) |
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| 195 | #define GEN5_PIPE_CONTROL_DEPTH_STALL (1 << 13) |
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| 196 | #define GEN5_PIPE_CONTROL_WC_FLUSH (1 << 12) |
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| 197 | #define GEN5_PIPE_CONTROL_IS_FLUSH (1 << 11) |
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| 198 | #define GEN5_PIPE_CONTROL_TC_FLUSH (1 << 10) |
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| 199 | #define GEN5_PIPE_CONTROL_NOTIFY_ENABLE (1 << 8) |
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| 200 | #define GEN5_PIPE_CONTROL_GLOBAL_GTT (1 << 2) |
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| 201 | #define GEN5_PIPE_CONTROL_LOCAL_PGTT (0 << 2) |
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| 202 | #define GEN5_PIPE_CONTROL_DEPTH_CACHE_FLUSH (1 << 0) |
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| 203 | |||
| 204 | /* VERTEX_BUFFER_STATE Structure */ |
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| 205 | #define VB0_BUFFER_INDEX_SHIFT 27 |
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| 206 | #define GEN6_VB0_BUFFER_INDEX_SHIFT 26 |
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| 207 | #define VB0_VERTEXDATA (0 << 26) |
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| 208 | #define VB0_INSTANCEDATA (1 << 26) |
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| 209 | #define GEN6_VB0_VERTEXDATA (0 << 20) |
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| 210 | #define GEN6_VB0_INSTANCEDATA (1 << 20) |
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| 211 | #define VB0_BUFFER_PITCH_SHIFT 0 |
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| 212 | |||
| 213 | /* VERTEX_ELEMENT_STATE Structure */ |
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| 214 | #define VE0_VERTEX_BUFFER_INDEX_SHIFT 27 |
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| 215 | #define GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT 26 /* for GEN6 */ |
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| 216 | #define VE0_VALID (1 << 26) |
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| 217 | #define GEN6_VE0_VALID (1 << 25) /* for GEN6 */ |
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| 218 | #define VE0_FORMAT_SHIFT 16 |
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| 219 | #define VE0_OFFSET_SHIFT 0 |
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| 220 | #define VE1_VFCOMPONENT_0_SHIFT 28 |
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| 221 | #define VE1_VFCOMPONENT_1_SHIFT 24 |
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| 222 | #define VE1_VFCOMPONENT_2_SHIFT 20 |
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| 223 | #define VE1_VFCOMPONENT_3_SHIFT 16 |
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| 224 | #define VE1_DESTINATION_ELEMENT_OFFSET_SHIFT 0 |
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| 225 | |||
| 226 | /* 3DPRIMITIVE bits */ |
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| 227 | #define GEN5_3DPRIMITIVE_VERTEX_SEQUENTIAL (0 << 15) |
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| 228 | #define GEN5_3DPRIMITIVE_VERTEX_RANDOM (1 << 15) |
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| 229 | /* Primitive types are in gen5_defines.h */ |
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| 230 | #define GEN5_3DPRIMITIVE_TOPOLOGY_SHIFT 10 |
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| 231 | |||
| 232 | #define GEN5_SVG_CTL 0x7400 |
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| 233 | |||
| 234 | #define GEN5_SVG_CTL_GS_BA (0 << 8) |
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| 235 | #define GEN5_SVG_CTL_SS_BA (1 << 8) |
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| 236 | #define GEN5_SVG_CTL_IO_BA (2 << 8) |
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| 237 | #define GEN5_SVG_CTL_GS_AUB (3 << 8) |
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| 238 | #define GEN5_SVG_CTL_IO_AUB (4 << 8) |
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| 239 | #define GEN5_SVG_CTL_SIP (5 << 8) |
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| 240 | |||
| 241 | #define GEN5_SVG_RDATA 0x7404 |
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| 242 | #define GEN5_SVG_WORK_CTL 0x7408 |
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| 243 | |||
| 244 | #define GEN5_VF_CTL 0x7500 |
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| 245 | |||
| 246 | #define GEN5_VF_CTL_SNAPSHOT_COMPLETE (1 << 31) |
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| 247 | #define GEN5_VF_CTL_SNAPSHOT_MUX_SELECT_THREADID (0 << 8) |
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| 248 | #define GEN5_VF_CTL_SNAPSHOT_MUX_SELECT_VF_DEBUG (1 << 8) |
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| 249 | #define GEN5_VF_CTL_SNAPSHOT_TYPE_VERTEX_SEQUENCE (0 << 4) |
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| 250 | #define GEN5_VF_CTL_SNAPSHOT_TYPE_VERTEX_INDEX (1 << 4) |
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| 251 | #define GEN5_VF_CTL_SKIP_INITIAL_PRIMITIVES (1 << 3) |
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| 252 | #define GEN5_VF_CTL_MAX_PRIMITIVES_LIMIT_ENABLE (1 << 2) |
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| 253 | #define GEN5_VF_CTL_VERTEX_RANGE_LIMIT_ENABLE (1 << 1) |
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| 254 | #define GEN5_VF_CTL_SNAPSHOT_ENABLE (1 << 0) |
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| 255 | |||
| 256 | #define GEN5_VF_STRG_VAL 0x7504 |
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| 257 | #define GEN5_VF_STR_VL_OVR 0x7508 |
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| 258 | #define GEN5_VF_VC_OVR 0x750c |
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| 259 | #define GEN5_VF_STR_PSKIP 0x7510 |
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| 260 | #define GEN5_VF_MAX_PRIM 0x7514 |
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| 261 | #define GEN5_VF_RDATA 0x7518 |
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| 262 | |||
| 263 | #define GEN5_VS_CTL 0x7600 |
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| 264 | #define GEN5_VS_CTL_SNAPSHOT_COMPLETE (1 << 31) |
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| 265 | #define GEN5_VS_CTL_SNAPSHOT_MUX_VERTEX_0 (0 << 8) |
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| 266 | #define GEN5_VS_CTL_SNAPSHOT_MUX_VERTEX_1 (1 << 8) |
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| 267 | #define GEN5_VS_CTL_SNAPSHOT_MUX_VALID_COUNT (2 << 8) |
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| 268 | #define GEN5_VS_CTL_SNAPSHOT_MUX_VS_KERNEL_POINTER (3 << 8) |
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| 269 | #define GEN5_VS_CTL_SNAPSHOT_ALL_THREADS (1 << 2) |
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| 270 | #define GEN5_VS_CTL_THREAD_SNAPSHOT_ENABLE (1 << 1) |
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| 271 | #define GEN5_VS_CTL_SNAPSHOT_ENABLE (1 << 0) |
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| 272 | |||
| 273 | #define GEN5_VS_STRG_VAL 0x7604 |
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| 274 | #define GEN5_VS_RDATA 0x7608 |
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| 275 | |||
| 276 | #define GEN5_SF_CTL 0x7b00 |
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| 277 | #define GEN5_SF_CTL_SNAPSHOT_COMPLETE (1 << 31) |
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| 278 | #define GEN5_SF_CTL_SNAPSHOT_MUX_VERTEX_0_FF_ID (0 << 8) |
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| 279 | #define GEN5_SF_CTL_SNAPSHOT_MUX_VERTEX_0_REL_COUNT (1 << 8) |
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| 280 | #define GEN5_SF_CTL_SNAPSHOT_MUX_VERTEX_1_FF_ID (2 << 8) |
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| 281 | #define GEN5_SF_CTL_SNAPSHOT_MUX_VERTEX_1_REL_COUNT (3 << 8) |
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| 282 | #define GEN5_SF_CTL_SNAPSHOT_MUX_VERTEX_2_FF_ID (4 << 8) |
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| 283 | #define GEN5_SF_CTL_SNAPSHOT_MUX_VERTEX_2_REL_COUNT (5 << 8) |
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| 284 | #define GEN5_SF_CTL_SNAPSHOT_MUX_VERTEX_COUNT (6 << 8) |
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| 285 | #define GEN5_SF_CTL_SNAPSHOT_MUX_SF_KERNEL_POINTER (7 << 8) |
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| 286 | #define GEN5_SF_CTL_MIN_MAX_PRIMITIVE_RANGE_ENABLE (1 << 4) |
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| 287 | #define GEN5_SF_CTL_DEBUG_CLIP_RECTANGLE_ENABLE (1 << 3) |
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| 288 | #define GEN5_SF_CTL_SNAPSHOT_ALL_THREADS (1 << 2) |
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| 289 | #define GEN5_SF_CTL_THREAD_SNAPSHOT_ENABLE (1 << 1) |
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| 290 | #define GEN5_SF_CTL_SNAPSHOT_ENABLE (1 << 0) |
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| 291 | |||
| 292 | #define GEN5_SF_STRG_VAL 0x7b04 |
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| 293 | #define GEN5_SF_RDATA 0x7b18 |
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| 294 | |||
| 295 | #define GEN5_WIZ_CTL 0x7c00 |
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| 296 | #define GEN5_WIZ_CTL_SNAPSHOT_COMPLETE (1 << 31) |
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| 297 | #define GEN5_WIZ_CTL_SUBSPAN_INSTANCE_SHIFT 16 |
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| 298 | #define GEN5_WIZ_CTL_SNAPSHOT_MUX_WIZ_KERNEL_POINTER (0 << 8) |
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| 299 | #define GEN5_WIZ_CTL_SNAPSHOT_MUX_SUBSPAN_INSTANCE (1 << 8) |
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| 300 | #define GEN5_WIZ_CTL_SNAPSHOT_MUX_PRIMITIVE_SEQUENCE (2 << 8) |
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| 301 | #define GEN5_WIZ_CTL_SINGLE_SUBSPAN_DISPATCH (1 << 6) |
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| 302 | #define GEN5_WIZ_CTL_IGNORE_COLOR_SCOREBOARD_STALLS (1 << 5) |
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| 303 | #define GEN5_WIZ_CTL_ENABLE_SUBSPAN_INSTANCE_COMPARE (1 << 4) |
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| 304 | #define GEN5_WIZ_CTL_USE_UPSTREAM_SNAPSHOT_FLAG (1 << 3) |
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| 305 | #define GEN5_WIZ_CTL_SNAPSHOT_ALL_THREADS (1 << 2) |
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| 306 | #define GEN5_WIZ_CTL_THREAD_SNAPSHOT_ENABLE (1 << 1) |
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| 307 | #define GEN5_WIZ_CTL_SNAPSHOT_ENABLE (1 << 0) |
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| 308 | |||
| 309 | #define GEN5_WIZ_STRG_VAL 0x7c04 |
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| 310 | #define GEN5_WIZ_RDATA 0x7c18 |
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| 311 | |||
| 312 | #define GEN5_TS_CTL 0x7e00 |
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| 313 | #define GEN5_TS_CTL_SNAPSHOT_COMPLETE (1 << 31) |
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| 314 | #define GEN5_TS_CTL_SNAPSHOT_MESSAGE_ERROR (0 << 8) |
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| 315 | #define GEN5_TS_CTL_SNAPSHOT_INTERFACE_DESCRIPTOR (3 << 8) |
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| 316 | #define GEN5_TS_CTL_SNAPSHOT_ALL_CHILD_THREADS (1 << 2) |
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| 317 | #define GEN5_TS_CTL_SNAPSHOT_ALL_ROOT_THREADS (1 << 1) |
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| 318 | #define GEN5_TS_CTL_SNAPSHOT_ENABLE (1 << 0) |
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| 319 | |||
| 320 | #define GEN5_TS_STRG_VAL 0x7e04 |
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| 321 | #define GEN5_TS_RDATA 0x7e08 |
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| 322 | |||
| 323 | #define GEN5_TD_CTL 0x8000 |
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| 324 | #define GEN5_TD_CTL_MUX_SHIFT 8 |
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| 325 | #define GEN5_TD_CTL_EXTERNAL_HALT_R0_DEBUG_MATCH (1 << 7) |
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| 326 | #define GEN5_TD_CTL_FORCE_EXTERNAL_HALT (1 << 6) |
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| 327 | #define GEN5_TD_CTL_EXCEPTION_MASK_OVERRIDE (1 << 5) |
||
| 328 | #define GEN5_TD_CTL_FORCE_THREAD_BREAKPOINT_ENABLE (1 << 4) |
||
| 329 | #define GEN5_TD_CTL_BREAKPOINT_ENABLE (1 << 2) |
||
| 330 | #define GEN5_TD_CTL2 0x8004 |
||
| 331 | #define GEN5_TD_CTL2_ILLEGAL_OPCODE_EXCEPTION_OVERRIDE (1 << 28) |
||
| 332 | #define GEN5_TD_CTL2_MASKSTACK_EXCEPTION_OVERRIDE (1 << 26) |
||
| 333 | #define GEN5_TD_CTL2_SOFTWARE_EXCEPTION_OVERRIDE (1 << 25) |
||
| 334 | #define GEN5_TD_CTL2_ACTIVE_THREAD_LIMIT_SHIFT 16 |
||
| 335 | #define GEN5_TD_CTL2_ACTIVE_THREAD_LIMIT_ENABLE (1 << 8) |
||
| 336 | #define GEN5_TD_CTL2_THREAD_SPAWNER_EXECUTION_MASK_ENABLE (1 << 7) |
||
| 337 | #define GEN5_TD_CTL2_WIZ_EXECUTION_MASK_ENABLE (1 << 6) |
||
| 338 | #define GEN5_TD_CTL2_SF_EXECUTION_MASK_ENABLE (1 << 5) |
||
| 339 | #define GEN5_TD_CTL2_CLIPPER_EXECUTION_MASK_ENABLE (1 << 4) |
||
| 340 | #define GEN5_TD_CTL2_GS_EXECUTION_MASK_ENABLE (1 << 3) |
||
| 341 | #define GEN5_TD_CTL2_VS_EXECUTION_MASK_ENABLE (1 << 0) |
||
| 342 | #define GEN5_TD_VF_VS_EMSK 0x8008 |
||
| 343 | #define GEN5_TD_GS_EMSK 0x800c |
||
| 344 | #define GEN5_TD_CLIP_EMSK 0x8010 |
||
| 345 | #define GEN5_TD_SF_EMSK 0x8014 |
||
| 346 | #define GEN5_TD_WIZ_EMSK 0x8018 |
||
| 347 | #define GEN5_TD_0_6_EHTRG_VAL 0x801c |
||
| 348 | #define GEN5_TD_0_7_EHTRG_VAL 0x8020 |
||
| 349 | #define GEN5_TD_0_6_EHTRG_MSK 0x8024 |
||
| 350 | #define GEN5_TD_0_7_EHTRG_MSK 0x8028 |
||
| 351 | #define GEN5_TD_RDATA 0x802c |
||
| 352 | #define GEN5_TD_TS_EMSK 0x8030 |
||
| 353 | |||
| 354 | #define GEN5_EU_CTL 0x8800 |
||
| 355 | #define GEN5_EU_CTL_SELECT_SHIFT 16 |
||
| 356 | #define GEN5_EU_CTL_DATA_MUX_SHIFT 8 |
||
| 357 | #define GEN5_EU_ATT_0 0x8810 |
||
| 358 | #define GEN5_EU_ATT_1 0x8814 |
||
| 359 | #define GEN5_EU_ATT_DATA_0 0x8820 |
||
| 360 | #define GEN5_EU_ATT_DATA_1 0x8824 |
||
| 361 | #define GEN5_EU_ATT_CLR_0 0x8830 |
||
| 362 | #define GEN5_EU_ATT_CLR_1 0x8834 |
||
| 363 | #define GEN5_EU_RDATA 0x8840 |
||
| 364 | |||
| 365 | /* 3D state: |
||
| 366 | */ |
||
| 367 | #define _3DOP_3DSTATE_PIPELINED 0x0 |
||
| 368 | #define _3DOP_3DSTATE_NONPIPELINED 0x1 |
||
| 369 | #define _3DOP_3DCONTROL 0x2 |
||
| 370 | #define _3DOP_3DPRIMITIVE 0x3 |
||
| 371 | |||
| 372 | #define _3DSTATE_PIPELINED_POINTERS 0x00 |
||
| 373 | #define _3DSTATE_BINDING_TABLE_POINTERS 0x01 |
||
| 374 | #define _3DSTATE_VERTEX_BUFFERS 0x08 |
||
| 375 | #define _3DSTATE_VERTEX_ELEMENTS 0x09 |
||
| 376 | #define _3DSTATE_INDEX_BUFFER 0x0A |
||
| 377 | #define _3DSTATE_VF_STATISTICS 0x0B |
||
| 378 | #define _3DSTATE_DRAWING_RECTANGLE 0x00 |
||
| 379 | #define _3DSTATE_CONSTANT_COLOR 0x01 |
||
| 380 | #define _3DSTATE_SAMPLER_PALETTE_LOAD 0x02 |
||
| 381 | #define _3DSTATE_CHROMA_KEY 0x04 |
||
| 382 | #define _3DSTATE_DEPTH_BUFFER 0x05 |
||
| 383 | #define _3DSTATE_POLY_STIPPLE_OFFSET 0x06 |
||
| 384 | #define _3DSTATE_POLY_STIPPLE_PATTERN 0x07 |
||
| 385 | #define _3DSTATE_LINE_STIPPLE 0x08 |
||
| 386 | #define _3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP 0x09 |
||
| 387 | #define _3DCONTROL 0x00 |
||
| 388 | #define _3DPRIMITIVE 0x00 |
||
| 389 | |||
| 390 | #define _3DPRIM_POINTLIST 0x01 |
||
| 391 | #define _3DPRIM_LINELIST 0x02 |
||
| 392 | #define _3DPRIM_LINESTRIP 0x03 |
||
| 393 | #define _3DPRIM_TRILIST 0x04 |
||
| 394 | #define _3DPRIM_TRISTRIP 0x05 |
||
| 395 | #define _3DPRIM_TRIFAN 0x06 |
||
| 396 | #define _3DPRIM_QUADLIST 0x07 |
||
| 397 | #define _3DPRIM_QUADSTRIP 0x08 |
||
| 398 | #define _3DPRIM_LINELIST_ADJ 0x09 |
||
| 399 | #define _3DPRIM_LINESTRIP_ADJ 0x0A |
||
| 400 | #define _3DPRIM_TRILIST_ADJ 0x0B |
||
| 401 | #define _3DPRIM_TRISTRIP_ADJ 0x0C |
||
| 402 | #define _3DPRIM_TRISTRIP_REVERSE 0x0D |
||
| 403 | #define _3DPRIM_POLYGON 0x0E |
||
| 404 | #define _3DPRIM_RECTLIST 0x0F |
||
| 405 | #define _3DPRIM_LINELOOP 0x10 |
||
| 406 | #define _3DPRIM_POINTLIST_BF 0x11 |
||
| 407 | #define _3DPRIM_LINESTRIP_CONT 0x12 |
||
| 408 | #define _3DPRIM_LINESTRIP_BF 0x13 |
||
| 409 | #define _3DPRIM_LINESTRIP_CONT_BF 0x14 |
||
| 410 | #define _3DPRIM_TRIFAN_NOSTIPPLE 0x15 |
||
| 411 | |||
| 412 | #define _3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL 0 |
||
| 413 | #define _3DPRIM_VERTEXBUFFER_ACCESS_RANDOM 1 |
||
| 414 | |||
| 415 | #define GEN5_ANISORATIO_2 0 |
||
| 416 | #define GEN5_ANISORATIO_4 1 |
||
| 417 | #define GEN5_ANISORATIO_6 2 |
||
| 418 | #define GEN5_ANISORATIO_8 3 |
||
| 419 | #define GEN5_ANISORATIO_10 4 |
||
| 420 | #define GEN5_ANISORATIO_12 5 |
||
| 421 | #define GEN5_ANISORATIO_14 6 |
||
| 422 | #define GEN5_ANISORATIO_16 7 |
||
| 423 | |||
| 424 | #define GEN5_BLENDFACTOR_ONE 0x1 |
||
| 425 | #define GEN5_BLENDFACTOR_SRC_COLOR 0x2 |
||
| 426 | #define GEN5_BLENDFACTOR_SRC_ALPHA 0x3 |
||
| 427 | #define GEN5_BLENDFACTOR_DST_ALPHA 0x4 |
||
| 428 | #define GEN5_BLENDFACTOR_DST_COLOR 0x5 |
||
| 429 | #define GEN5_BLENDFACTOR_SRC_ALPHA_SATURATE 0x6 |
||
| 430 | #define GEN5_BLENDFACTOR_CONST_COLOR 0x7 |
||
| 431 | #define GEN5_BLENDFACTOR_CONST_ALPHA 0x8 |
||
| 432 | #define GEN5_BLENDFACTOR_SRC1_COLOR 0x9 |
||
| 433 | #define GEN5_BLENDFACTOR_SRC1_ALPHA 0x0A |
||
| 434 | #define GEN5_BLENDFACTOR_ZERO 0x11 |
||
| 435 | #define GEN5_BLENDFACTOR_INV_SRC_COLOR 0x12 |
||
| 436 | #define GEN5_BLENDFACTOR_INV_SRC_ALPHA 0x13 |
||
| 437 | #define GEN5_BLENDFACTOR_INV_DST_ALPHA 0x14 |
||
| 438 | #define GEN5_BLENDFACTOR_INV_DST_COLOR 0x15 |
||
| 439 | #define GEN5_BLENDFACTOR_INV_CONST_COLOR 0x17 |
||
| 440 | #define GEN5_BLENDFACTOR_INV_CONST_ALPHA 0x18 |
||
| 441 | #define GEN5_BLENDFACTOR_INV_SRC1_COLOR 0x19 |
||
| 442 | #define GEN5_BLENDFACTOR_INV_SRC1_ALPHA 0x1A |
||
| 443 | |||
| 444 | #define GEN5_BLENDFUNCTION_ADD 0 |
||
| 445 | #define GEN5_BLENDFUNCTION_SUBTRACT 1 |
||
| 446 | #define GEN5_BLENDFUNCTION_REVERSE_SUBTRACT 2 |
||
| 447 | #define GEN5_BLENDFUNCTION_MIN 3 |
||
| 448 | #define GEN5_BLENDFUNCTION_MAX 4 |
||
| 449 | |||
| 450 | #define GEN5_ALPHATEST_FORMAT_UNORM8 0 |
||
| 451 | #define GEN5_ALPHATEST_FORMAT_FLOAT32 1 |
||
| 452 | |||
| 453 | #define GEN5_CHROMAKEY_KILL_ON_ANY_MATCH 0 |
||
| 454 | #define GEN5_CHROMAKEY_REPLACE_BLACK 1 |
||
| 455 | |||
| 456 | #define GEN5_CLIP_API_OGL 0 |
||
| 457 | #define GEN5_CLIP_API_DX 1 |
||
| 458 | |||
| 459 | #define GEN5_CLIPMODE_NORMAL 0 |
||
| 460 | #define GEN5_CLIPMODE_CLIP_ALL 1 |
||
| 461 | #define GEN5_CLIPMODE_CLIP_NON_REJECTED 2 |
||
| 462 | #define GEN5_CLIPMODE_REJECT_ALL 3 |
||
| 463 | #define GEN5_CLIPMODE_ACCEPT_ALL 4 |
||
| 464 | |||
| 465 | #define GEN5_CLIP_NDCSPACE 0 |
||
| 466 | #define GEN5_CLIP_SCREENSPACE 1 |
||
| 467 | |||
| 468 | #define GEN5_COMPAREFUNCTION_ALWAYS 0 |
||
| 469 | #define GEN5_COMPAREFUNCTION_NEVER 1 |
||
| 470 | #define GEN5_COMPAREFUNCTION_LESS 2 |
||
| 471 | #define GEN5_COMPAREFUNCTION_EQUAL 3 |
||
| 472 | #define GEN5_COMPAREFUNCTION_LEQUAL 4 |
||
| 473 | #define GEN5_COMPAREFUNCTION_GREATER 5 |
||
| 474 | #define GEN5_COMPAREFUNCTION_NOTEQUAL 6 |
||
| 475 | #define GEN5_COMPAREFUNCTION_GEQUAL 7 |
||
| 476 | |||
| 477 | #define GEN5_COVERAGE_PIXELS_HALF 0 |
||
| 478 | #define GEN5_COVERAGE_PIXELS_1 1 |
||
| 479 | #define GEN5_COVERAGE_PIXELS_2 2 |
||
| 480 | #define GEN5_COVERAGE_PIXELS_4 3 |
||
| 481 | |||
| 482 | #define GEN5_CULLMODE_BOTH 0 |
||
| 483 | #define GEN5_CULLMODE_NONE 1 |
||
| 484 | #define GEN5_CULLMODE_FRONT 2 |
||
| 485 | #define GEN5_CULLMODE_BACK 3 |
||
| 486 | |||
| 487 | #define GEN5_DEFAULTCOLOR_R8G8B8A8_UNORM 0 |
||
| 488 | #define GEN5_DEFAULTCOLOR_R32G32B32A32_FLOAT 1 |
||
| 489 | |||
| 490 | #define GEN5_DEPTHFORMAT_D32_FLOAT_S8X24_UINT 0 |
||
| 491 | #define GEN5_DEPTHFORMAT_D32_FLOAT 1 |
||
| 492 | #define GEN5_DEPTHFORMAT_D24_UNORM_S8_UINT 2 |
||
| 493 | #define GEN5_DEPTHFORMAT_D16_UNORM 5 |
||
| 494 | |||
| 495 | #define GEN5_FLOATING_POINT_IEEE_754 0 |
||
| 496 | #define GEN5_FLOATING_POINT_NON_IEEE_754 1 |
||
| 497 | |||
| 498 | #define GEN5_FRONTWINDING_CW 0 |
||
| 499 | #define GEN5_FRONTWINDING_CCW 1 |
||
| 500 | |||
| 501 | #define GEN5_INDEX_BYTE 0 |
||
| 502 | #define GEN5_INDEX_WORD 1 |
||
| 503 | #define GEN5_INDEX_DWORD 2 |
||
| 504 | |||
| 505 | #define GEN5_LOGICOPFUNCTION_CLEAR 0 |
||
| 506 | #define GEN5_LOGICOPFUNCTION_NOR 1 |
||
| 507 | #define GEN5_LOGICOPFUNCTION_AND_INVERTED 2 |
||
| 508 | #define GEN5_LOGICOPFUNCTION_COPY_INVERTED 3 |
||
| 509 | #define GEN5_LOGICOPFUNCTION_AND_REVERSE 4 |
||
| 510 | #define GEN5_LOGICOPFUNCTION_INVERT 5 |
||
| 511 | #define GEN5_LOGICOPFUNCTION_XOR 6 |
||
| 512 | #define GEN5_LOGICOPFUNCTION_NAND 7 |
||
| 513 | #define GEN5_LOGICOPFUNCTION_AND 8 |
||
| 514 | #define GEN5_LOGICOPFUNCTION_EQUIV 9 |
||
| 515 | #define GEN5_LOGICOPFUNCTION_NOOP 10 |
||
| 516 | #define GEN5_LOGICOPFUNCTION_OR_INVERTED 11 |
||
| 517 | #define GEN5_LOGICOPFUNCTION_COPY 12 |
||
| 518 | #define GEN5_LOGICOPFUNCTION_OR_REVERSE 13 |
||
| 519 | #define GEN5_LOGICOPFUNCTION_OR 14 |
||
| 520 | #define GEN5_LOGICOPFUNCTION_SET 15 |
||
| 521 | |||
| 522 | #define GEN5_MAPFILTER_NEAREST 0x0 |
||
| 523 | #define GEN5_MAPFILTER_LINEAR 0x1 |
||
| 524 | #define GEN5_MAPFILTER_ANISOTROPIC 0x2 |
||
| 525 | |||
| 526 | #define GEN5_MIPFILTER_NONE 0 |
||
| 527 | #define GEN5_MIPFILTER_NEAREST 1 |
||
| 528 | #define GEN5_MIPFILTER_LINEAR 3 |
||
| 529 | |||
| 530 | #define GEN5_POLYGON_FRONT_FACING 0 |
||
| 531 | #define GEN5_POLYGON_BACK_FACING 1 |
||
| 532 | |||
| 533 | #define GEN5_PREFILTER_ALWAYS 0x0 |
||
| 534 | #define GEN5_PREFILTER_NEVER 0x1 |
||
| 535 | #define GEN5_PREFILTER_LESS 0x2 |
||
| 536 | #define GEN5_PREFILTER_EQUAL 0x3 |
||
| 537 | #define GEN5_PREFILTER_LEQUAL 0x4 |
||
| 538 | #define GEN5_PREFILTER_GREATER 0x5 |
||
| 539 | #define GEN5_PREFILTER_NOTEQUAL 0x6 |
||
| 540 | #define GEN5_PREFILTER_GEQUAL 0x7 |
||
| 541 | |||
| 542 | #define GEN5_PROVOKING_VERTEX_0 0 |
||
| 543 | #define GEN5_PROVOKING_VERTEX_1 1 |
||
| 544 | #define GEN5_PROVOKING_VERTEX_2 2 |
||
| 545 | |||
| 546 | #define GEN5_RASTRULE_UPPER_LEFT 0 |
||
| 547 | #define GEN5_RASTRULE_UPPER_RIGHT 1 |
||
| 548 | |||
| 549 | #define GEN5_RENDERTARGET_CLAMPRANGE_UNORM 0 |
||
| 550 | #define GEN5_RENDERTARGET_CLAMPRANGE_SNORM 1 |
||
| 551 | #define GEN5_RENDERTARGET_CLAMPRANGE_FORMAT 2 |
||
| 552 | |||
| 553 | #define GEN5_STENCILOP_KEEP 0 |
||
| 554 | #define GEN5_STENCILOP_ZERO 1 |
||
| 555 | #define GEN5_STENCILOP_REPLACE 2 |
||
| 556 | #define GEN5_STENCILOP_INCRSAT 3 |
||
| 557 | #define GEN5_STENCILOP_DECRSAT 4 |
||
| 558 | #define GEN5_STENCILOP_INCR 5 |
||
| 559 | #define GEN5_STENCILOP_DECR 6 |
||
| 560 | #define GEN5_STENCILOP_INVERT 7 |
||
| 561 | |||
| 562 | #define GEN5_SURFACE_MIPMAPLAYOUT_BELOW 0 |
||
| 563 | #define GEN5_SURFACE_MIPMAPLAYOUT_RIGHT 1 |
||
| 564 | |||
| 565 | #define GEN5_SURFACEFORMAT_R32G32B32A32_FLOAT 0x000 |
||
| 566 | #define GEN5_SURFACEFORMAT_R32G32B32A32_SINT 0x001 |
||
| 567 | #define GEN5_SURFACEFORMAT_R32G32B32A32_UINT 0x002 |
||
| 568 | #define GEN5_SURFACEFORMAT_R32G32B32A32_UNORM 0x003 |
||
| 569 | #define GEN5_SURFACEFORMAT_R32G32B32A32_SNORM 0x004 |
||
| 570 | #define GEN5_SURFACEFORMAT_R64G64_FLOAT 0x005 |
||
| 571 | #define GEN5_SURFACEFORMAT_R32G32B32X32_FLOAT 0x006 |
||
| 572 | #define GEN5_SURFACEFORMAT_R32G32B32A32_SSCALED 0x007 |
||
| 573 | #define GEN5_SURFACEFORMAT_R32G32B32A32_USCALED 0x008 |
||
| 574 | #define GEN5_SURFACEFORMAT_R32G32B32_FLOAT 0x040 |
||
| 575 | #define GEN5_SURFACEFORMAT_R32G32B32_SINT 0x041 |
||
| 576 | #define GEN5_SURFACEFORMAT_R32G32B32_UINT 0x042 |
||
| 577 | #define GEN5_SURFACEFORMAT_R32G32B32_UNORM 0x043 |
||
| 578 | #define GEN5_SURFACEFORMAT_R32G32B32_SNORM 0x044 |
||
| 579 | #define GEN5_SURFACEFORMAT_R32G32B32_SSCALED 0x045 |
||
| 580 | #define GEN5_SURFACEFORMAT_R32G32B32_USCALED 0x046 |
||
| 581 | #define GEN5_SURFACEFORMAT_R16G16B16A16_UNORM 0x080 |
||
| 582 | #define GEN5_SURFACEFORMAT_R16G16B16A16_SNORM 0x081 |
||
| 583 | #define GEN5_SURFACEFORMAT_R16G16B16A16_SINT 0x082 |
||
| 584 | #define GEN5_SURFACEFORMAT_R16G16B16A16_UINT 0x083 |
||
| 585 | #define GEN5_SURFACEFORMAT_R16G16B16A16_FLOAT 0x084 |
||
| 586 | #define GEN5_SURFACEFORMAT_R32G32_FLOAT 0x085 |
||
| 587 | #define GEN5_SURFACEFORMAT_R32G32_SINT 0x086 |
||
| 588 | #define GEN5_SURFACEFORMAT_R32G32_UINT 0x087 |
||
| 589 | #define GEN5_SURFACEFORMAT_R32_FLOAT_X8X24_TYPELESS 0x088 |
||
| 590 | #define GEN5_SURFACEFORMAT_X32_TYPELESS_G8X24_UINT 0x089 |
||
| 591 | #define GEN5_SURFACEFORMAT_L32A32_FLOAT 0x08A |
||
| 592 | #define GEN5_SURFACEFORMAT_R32G32_UNORM 0x08B |
||
| 593 | #define GEN5_SURFACEFORMAT_R32G32_SNORM 0x08C |
||
| 594 | #define GEN5_SURFACEFORMAT_R64_FLOAT 0x08D |
||
| 595 | #define GEN5_SURFACEFORMAT_R16G16B16X16_UNORM 0x08E |
||
| 596 | #define GEN5_SURFACEFORMAT_R16G16B16X16_FLOAT 0x08F |
||
| 597 | #define GEN5_SURFACEFORMAT_A32X32_FLOAT 0x090 |
||
| 598 | #define GEN5_SURFACEFORMAT_L32X32_FLOAT 0x091 |
||
| 599 | #define GEN5_SURFACEFORMAT_I32X32_FLOAT 0x092 |
||
| 600 | #define GEN5_SURFACEFORMAT_R16G16B16A16_SSCALED 0x093 |
||
| 601 | #define GEN5_SURFACEFORMAT_R16G16B16A16_USCALED 0x094 |
||
| 602 | #define GEN5_SURFACEFORMAT_R32G32_SSCALED 0x095 |
||
| 603 | #define GEN5_SURFACEFORMAT_R32G32_USCALED 0x096 |
||
| 604 | #define GEN5_SURFACEFORMAT_B8G8R8A8_UNORM 0x0C0 |
||
| 605 | #define GEN5_SURFACEFORMAT_B8G8R8A8_UNORM_SRGB 0x0C1 |
||
| 606 | #define GEN5_SURFACEFORMAT_R10G10B10A2_UNORM 0x0C2 |
||
| 607 | #define GEN5_SURFACEFORMAT_R10G10B10A2_UNORM_SRGB 0x0C3 |
||
| 608 | #define GEN5_SURFACEFORMAT_R10G10B10A2_UINT 0x0C4 |
||
| 609 | #define GEN5_SURFACEFORMAT_R10G10B10_SNORM_A2_UNORM 0x0C5 |
||
| 610 | #define GEN5_SURFACEFORMAT_R8G8B8A8_UNORM 0x0C7 |
||
| 611 | #define GEN5_SURFACEFORMAT_R8G8B8A8_UNORM_SRGB 0x0C8 |
||
| 612 | #define GEN5_SURFACEFORMAT_R8G8B8A8_SNORM 0x0C9 |
||
| 613 | #define GEN5_SURFACEFORMAT_R8G8B8A8_SINT 0x0CA |
||
| 614 | #define GEN5_SURFACEFORMAT_R8G8B8A8_UINT 0x0CB |
||
| 615 | #define GEN5_SURFACEFORMAT_R16G16_UNORM 0x0CC |
||
| 616 | #define GEN5_SURFACEFORMAT_R16G16_SNORM 0x0CD |
||
| 617 | #define GEN5_SURFACEFORMAT_R16G16_SINT 0x0CE |
||
| 618 | #define GEN5_SURFACEFORMAT_R16G16_UINT 0x0CF |
||
| 619 | #define GEN5_SURFACEFORMAT_R16G16_FLOAT 0x0D0 |
||
| 620 | #define GEN5_SURFACEFORMAT_B10G10R10A2_UNORM 0x0D1 |
||
| 621 | #define GEN5_SURFACEFORMAT_B10G10R10A2_UNORM_SRGB 0x0D2 |
||
| 622 | #define GEN5_SURFACEFORMAT_R11G11B10_FLOAT 0x0D3 |
||
| 623 | #define GEN5_SURFACEFORMAT_R32_SINT 0x0D6 |
||
| 624 | #define GEN5_SURFACEFORMAT_R32_UINT 0x0D7 |
||
| 625 | #define GEN5_SURFACEFORMAT_R32_FLOAT 0x0D8 |
||
| 626 | #define GEN5_SURFACEFORMAT_R24_UNORM_X8_TYPELESS 0x0D9 |
||
| 627 | #define GEN5_SURFACEFORMAT_X24_TYPELESS_G8_UINT 0x0DA |
||
| 628 | #define GEN5_SURFACEFORMAT_L16A16_UNORM 0x0DF |
||
| 629 | #define GEN5_SURFACEFORMAT_I24X8_UNORM 0x0E0 |
||
| 630 | #define GEN5_SURFACEFORMAT_L24X8_UNORM 0x0E1 |
||
| 631 | #define GEN5_SURFACEFORMAT_A24X8_UNORM 0x0E2 |
||
| 632 | #define GEN5_SURFACEFORMAT_I32_FLOAT 0x0E3 |
||
| 633 | #define GEN5_SURFACEFORMAT_L32_FLOAT 0x0E4 |
||
| 634 | #define GEN5_SURFACEFORMAT_A32_FLOAT 0x0E5 |
||
| 635 | #define GEN5_SURFACEFORMAT_B8G8R8X8_UNORM 0x0E9 |
||
| 636 | #define GEN5_SURFACEFORMAT_B8G8R8X8_UNORM_SRGB 0x0EA |
||
| 637 | #define GEN5_SURFACEFORMAT_R8G8B8X8_UNORM 0x0EB |
||
| 638 | #define GEN5_SURFACEFORMAT_R8G8B8X8_UNORM_SRGB 0x0EC |
||
| 639 | #define GEN5_SURFACEFORMAT_R9G9B9E5_SHAREDEXP 0x0ED |
||
| 640 | #define GEN5_SURFACEFORMAT_B10G10R10X2_UNORM 0x0EE |
||
| 641 | #define GEN5_SURFACEFORMAT_L16A16_FLOAT 0x0F0 |
||
| 642 | #define GEN5_SURFACEFORMAT_R32_UNORM 0x0F1 |
||
| 643 | #define GEN5_SURFACEFORMAT_R32_SNORM 0x0F2 |
||
| 644 | #define GEN5_SURFACEFORMAT_R10G10B10X2_USCALED 0x0F3 |
||
| 645 | #define GEN5_SURFACEFORMAT_R8G8B8A8_SSCALED 0x0F4 |
||
| 646 | #define GEN5_SURFACEFORMAT_R8G8B8A8_USCALED 0x0F5 |
||
| 647 | #define GEN5_SURFACEFORMAT_R16G16_SSCALED 0x0F6 |
||
| 648 | #define GEN5_SURFACEFORMAT_R16G16_USCALED 0x0F7 |
||
| 649 | #define GEN5_SURFACEFORMAT_R32_SSCALED 0x0F8 |
||
| 650 | #define GEN5_SURFACEFORMAT_R32_USCALED 0x0F9 |
||
| 651 | #define GEN5_SURFACEFORMAT_B5G6R5_UNORM 0x100 |
||
| 652 | #define GEN5_SURFACEFORMAT_B5G6R5_UNORM_SRGB 0x101 |
||
| 653 | #define GEN5_SURFACEFORMAT_B5G5R5A1_UNORM 0x102 |
||
| 654 | #define GEN5_SURFACEFORMAT_B5G5R5A1_UNORM_SRGB 0x103 |
||
| 655 | #define GEN5_SURFACEFORMAT_B4G4R4A4_UNORM 0x104 |
||
| 656 | #define GEN5_SURFACEFORMAT_B4G4R4A4_UNORM_SRGB 0x105 |
||
| 657 | #define GEN5_SURFACEFORMAT_R8G8_UNORM 0x106 |
||
| 658 | #define GEN5_SURFACEFORMAT_R8G8_SNORM 0x107 |
||
| 659 | #define GEN5_SURFACEFORMAT_R8G8_SINT 0x108 |
||
| 660 | #define GEN5_SURFACEFORMAT_R8G8_UINT 0x109 |
||
| 661 | #define GEN5_SURFACEFORMAT_R16_UNORM 0x10A |
||
| 662 | #define GEN5_SURFACEFORMAT_R16_SNORM 0x10B |
||
| 663 | #define GEN5_SURFACEFORMAT_R16_SINT 0x10C |
||
| 664 | #define GEN5_SURFACEFORMAT_R16_UINT 0x10D |
||
| 665 | #define GEN5_SURFACEFORMAT_R16_FLOAT 0x10E |
||
| 666 | #define GEN5_SURFACEFORMAT_I16_UNORM 0x111 |
||
| 667 | #define GEN5_SURFACEFORMAT_L16_UNORM 0x112 |
||
| 668 | #define GEN5_SURFACEFORMAT_A16_UNORM 0x113 |
||
| 669 | #define GEN5_SURFACEFORMAT_L8A8_UNORM 0x114 |
||
| 670 | #define GEN5_SURFACEFORMAT_I16_FLOAT 0x115 |
||
| 671 | #define GEN5_SURFACEFORMAT_L16_FLOAT 0x116 |
||
| 672 | #define GEN5_SURFACEFORMAT_A16_FLOAT 0x117 |
||
| 673 | #define GEN5_SURFACEFORMAT_R5G5_SNORM_B6_UNORM 0x119 |
||
| 674 | #define GEN5_SURFACEFORMAT_B5G5R5X1_UNORM 0x11A |
||
| 675 | #define GEN5_SURFACEFORMAT_B5G5R5X1_UNORM_SRGB 0x11B |
||
| 676 | #define GEN5_SURFACEFORMAT_R8G8_SSCALED 0x11C |
||
| 677 | #define GEN5_SURFACEFORMAT_R8G8_USCALED 0x11D |
||
| 678 | #define GEN5_SURFACEFORMAT_R16_SSCALED 0x11E |
||
| 679 | #define GEN5_SURFACEFORMAT_R16_USCALED 0x11F |
||
| 680 | #define GEN5_SURFACEFORMAT_R8_UNORM 0x140 |
||
| 681 | #define GEN5_SURFACEFORMAT_R8_SNORM 0x141 |
||
| 682 | #define GEN5_SURFACEFORMAT_R8_SINT 0x142 |
||
| 683 | #define GEN5_SURFACEFORMAT_R8_UINT 0x143 |
||
| 684 | #define GEN5_SURFACEFORMAT_A8_UNORM 0x144 |
||
| 685 | #define GEN5_SURFACEFORMAT_I8_UNORM 0x145 |
||
| 686 | #define GEN5_SURFACEFORMAT_L8_UNORM 0x146 |
||
| 687 | #define GEN5_SURFACEFORMAT_P4A4_UNORM 0x147 |
||
| 688 | #define GEN5_SURFACEFORMAT_A4P4_UNORM 0x148 |
||
| 689 | #define GEN5_SURFACEFORMAT_R8_SSCALED 0x149 |
||
| 690 | #define GEN5_SURFACEFORMAT_R8_USCALED 0x14A |
||
| 691 | #define GEN5_SURFACEFORMAT_R1_UINT 0x181 |
||
| 692 | #define GEN5_SURFACEFORMAT_YCRCB_NORMAL 0x182 |
||
| 693 | #define GEN5_SURFACEFORMAT_YCRCB_SWAPUVY 0x183 |
||
| 694 | #define GEN5_SURFACEFORMAT_BC1_UNORM 0x186 |
||
| 695 | #define GEN5_SURFACEFORMAT_BC2_UNORM 0x187 |
||
| 696 | #define GEN5_SURFACEFORMAT_BC3_UNORM 0x188 |
||
| 697 | #define GEN5_SURFACEFORMAT_BC4_UNORM 0x189 |
||
| 698 | #define GEN5_SURFACEFORMAT_BC5_UNORM 0x18A |
||
| 699 | #define GEN5_SURFACEFORMAT_BC1_UNORM_SRGB 0x18B |
||
| 700 | #define GEN5_SURFACEFORMAT_BC2_UNORM_SRGB 0x18C |
||
| 701 | #define GEN5_SURFACEFORMAT_BC3_UNORM_SRGB 0x18D |
||
| 702 | #define GEN5_SURFACEFORMAT_MONO8 0x18E |
||
| 703 | #define GEN5_SURFACEFORMAT_YCRCB_SWAPUV 0x18F |
||
| 704 | #define GEN5_SURFACEFORMAT_YCRCB_SWAPY 0x190 |
||
| 705 | #define GEN5_SURFACEFORMAT_DXT1_RGB 0x191 |
||
| 706 | #define GEN5_SURFACEFORMAT_FXT1 0x192 |
||
| 707 | #define GEN5_SURFACEFORMAT_R8G8B8_UNORM 0x193 |
||
| 708 | #define GEN5_SURFACEFORMAT_R8G8B8_SNORM 0x194 |
||
| 709 | #define GEN5_SURFACEFORMAT_R8G8B8_SSCALED 0x195 |
||
| 710 | #define GEN5_SURFACEFORMAT_R8G8B8_USCALED 0x196 |
||
| 711 | #define GEN5_SURFACEFORMAT_R64G64B64A64_FLOAT 0x197 |
||
| 712 | #define GEN5_SURFACEFORMAT_R64G64B64_FLOAT 0x198 |
||
| 713 | #define GEN5_SURFACEFORMAT_BC4_SNORM 0x199 |
||
| 714 | #define GEN5_SURFACEFORMAT_BC5_SNORM 0x19A |
||
| 715 | #define GEN5_SURFACEFORMAT_R16G16B16_UNORM 0x19C |
||
| 716 | #define GEN5_SURFACEFORMAT_R16G16B16_SNORM 0x19D |
||
| 717 | #define GEN5_SURFACEFORMAT_R16G16B16_SSCALED 0x19E |
||
| 718 | #define GEN5_SURFACEFORMAT_R16G16B16_USCALED 0x19F |
||
| 719 | |||
| 720 | #define GEN5_SURFACERETURNFORMAT_FLOAT32 0 |
||
| 721 | #define GEN5_SURFACERETURNFORMAT_S1 1 |
||
| 722 | |||
| 723 | #define GEN5_SURFACE_1D 0 |
||
| 724 | #define GEN5_SURFACE_2D 1 |
||
| 725 | #define GEN5_SURFACE_3D 2 |
||
| 726 | #define GEN5_SURFACE_CUBE 3 |
||
| 727 | #define GEN5_SURFACE_BUFFER 4 |
||
| 728 | #define GEN5_SURFACE_NULL 7 |
||
| 729 | |||
| 730 | #define GEN5_BORDER_COLOR_MODE_DEFAULT 0 |
||
| 731 | #define GEN5_BORDER_COLOR_MODE_LEGACY 1 |
||
| 732 | |||
| 733 | #define GEN5_TEXCOORDMODE_WRAP 0 |
||
| 734 | #define GEN5_TEXCOORDMODE_MIRROR 1 |
||
| 735 | #define GEN5_TEXCOORDMODE_CLAMP 2 |
||
| 736 | #define GEN5_TEXCOORDMODE_CUBE 3 |
||
| 737 | #define GEN5_TEXCOORDMODE_CLAMP_BORDER 4 |
||
| 738 | #define GEN5_TEXCOORDMODE_MIRROR_ONCE 5 |
||
| 739 | |||
| 740 | #define GEN5_THREAD_PRIORITY_NORMAL 0 |
||
| 741 | #define GEN5_THREAD_PRIORITY_HIGH 1 |
||
| 742 | |||
| 743 | #define GEN5_TILEWALK_XMAJOR 0 |
||
| 744 | #define GEN5_TILEWALK_YMAJOR 1 |
||
| 745 | |||
| 746 | #define GEN5_VERTEX_SUBPIXEL_PRECISION_8BITS 0 |
||
| 747 | #define GEN5_VERTEX_SUBPIXEL_PRECISION_4BITS 1 |
||
| 748 | |||
| 749 | #define GEN5_VERTEXBUFFER_ACCESS_VERTEXDATA 0 |
||
| 750 | #define GEN5_VERTEXBUFFER_ACCESS_INSTANCEDATA 1 |
||
| 751 | |||
| 752 | #define VFCOMPONENT_NOSTORE 0 |
||
| 753 | #define VFCOMPONENT_STORE_SRC 1 |
||
| 754 | #define VFCOMPONENT_STORE_0 2 |
||
| 755 | #define VFCOMPONENT_STORE_1_FLT 3 |
||
| 756 | #define VFCOMPONENT_STORE_1_INT 4 |
||
| 757 | #define VFCOMPONENT_STORE_VID 5 |
||
| 758 | #define VFCOMPONENT_STORE_IID 6 |
||
| 759 | #define VFCOMPONENT_STORE_PID 7 |
||
| 760 | |||
| 761 | |||
| 762 | /* Execution Unit (EU) defines |
||
| 763 | */ |
||
| 764 | |||
| 765 | #define GEN5_ALIGN_1 0 |
||
| 766 | #define GEN5_ALIGN_16 1 |
||
| 767 | |||
| 768 | #define GEN5_ADDRESS_DIRECT 0 |
||
| 769 | #define GEN5_ADDRESS_REGISTER_INDIRECT_REGISTER 1 |
||
| 770 | |||
| 771 | #define GEN5_CHANNEL_X 0 |
||
| 772 | #define GEN5_CHANNEL_Y 1 |
||
| 773 | #define GEN5_CHANNEL_Z 2 |
||
| 774 | #define GEN5_CHANNEL_W 3 |
||
| 775 | |||
| 776 | #define GEN5_COMPRESSION_NONE 0 |
||
| 777 | #define GEN5_COMPRESSION_2NDHALF 1 |
||
| 778 | #define GEN5_COMPRESSION_COMPRESSED 2 |
||
| 779 | |||
| 780 | #define GEN5_CONDITIONAL_NONE 0 |
||
| 781 | #define GEN5_CONDITIONAL_Z 1 |
||
| 782 | #define GEN5_CONDITIONAL_NZ 2 |
||
| 783 | #define GEN5_CONDITIONAL_EQ 1 /* Z */ |
||
| 784 | #define GEN5_CONDITIONAL_NEQ 2 /* NZ */ |
||
| 785 | #define GEN5_CONDITIONAL_G 3 |
||
| 786 | #define GEN5_CONDITIONAL_GE 4 |
||
| 787 | #define GEN5_CONDITIONAL_L 5 |
||
| 788 | #define GEN5_CONDITIONAL_LE 6 |
||
| 789 | #define GEN5_CONDITIONAL_C 7 |
||
| 790 | #define GEN5_CONDITIONAL_O 8 |
||
| 791 | |||
| 792 | #define GEN5_DEBUG_NONE 0 |
||
| 793 | #define GEN5_DEBUG_BREAKPOINT 1 |
||
| 794 | |||
| 795 | #define GEN5_DEPENDENCY_NORMAL 0 |
||
| 796 | #define GEN5_DEPENDENCY_NOTCLEARED 1 |
||
| 797 | #define GEN5_DEPENDENCY_NOTCHECKED 2 |
||
| 798 | #define GEN5_DEPENDENCY_DISABLE 3 |
||
| 799 | |||
| 800 | #define GEN5_EXECUTE_1 0 |
||
| 801 | #define GEN5_EXECUTE_2 1 |
||
| 802 | #define GEN5_EXECUTE_4 2 |
||
| 803 | #define GEN5_EXECUTE_8 3 |
||
| 804 | #define GEN5_EXECUTE_16 4 |
||
| 805 | #define GEN5_EXECUTE_32 5 |
||
| 806 | |||
| 807 | #define GEN5_HORIZONTAL_STRIDE_0 0 |
||
| 808 | #define GEN5_HORIZONTAL_STRIDE_1 1 |
||
| 809 | #define GEN5_HORIZONTAL_STRIDE_2 2 |
||
| 810 | #define GEN5_HORIZONTAL_STRIDE_4 3 |
||
| 811 | |||
| 812 | #define GEN5_INSTRUCTION_NORMAL 0 |
||
| 813 | #define GEN5_INSTRUCTION_SATURATE 1 |
||
| 814 | |||
| 815 | #define GEN5_MASK_ENABLE 0 |
||
| 816 | #define GEN5_MASK_DISABLE 1 |
||
| 817 | |||
| 818 | #define GEN5_OPCODE_MOV 1 |
||
| 819 | #define GEN5_OPCODE_SEL 2 |
||
| 820 | #define GEN5_OPCODE_NOT 4 |
||
| 821 | #define GEN5_OPCODE_AND 5 |
||
| 822 | #define GEN5_OPCODE_OR 6 |
||
| 823 | #define GEN5_OPCODE_XOR 7 |
||
| 824 | #define GEN5_OPCODE_SHR 8 |
||
| 825 | #define GEN5_OPCODE_SHL 9 |
||
| 826 | #define GEN5_OPCODE_RSR 10 |
||
| 827 | #define GEN5_OPCODE_RSL 11 |
||
| 828 | #define GEN5_OPCODE_ASR 12 |
||
| 829 | #define GEN5_OPCODE_CMP 16 |
||
| 830 | #define GEN5_OPCODE_JMPI 32 |
||
| 831 | #define GEN5_OPCODE_IF 34 |
||
| 832 | #define GEN5_OPCODE_IFF 35 |
||
| 833 | #define GEN5_OPCODE_ELSE 36 |
||
| 834 | #define GEN5_OPCODE_ENDIF 37 |
||
| 835 | #define GEN5_OPCODE_DO 38 |
||
| 836 | #define GEN5_OPCODE_WHILE 39 |
||
| 837 | #define GEN5_OPCODE_BREAK 40 |
||
| 838 | #define GEN5_OPCODE_CONTINUE 41 |
||
| 839 | #define GEN5_OPCODE_HALT 42 |
||
| 840 | #define GEN5_OPCODE_MSAVE 44 |
||
| 841 | #define GEN5_OPCODE_MRESTORE 45 |
||
| 842 | #define GEN5_OPCODE_PUSH 46 |
||
| 843 | #define GEN5_OPCODE_POP 47 |
||
| 844 | #define GEN5_OPCODE_WAIT 48 |
||
| 845 | #define GEN5_OPCODE_SEND 49 |
||
| 846 | #define GEN5_OPCODE_ADD 64 |
||
| 847 | #define GEN5_OPCODE_MUL 65 |
||
| 848 | #define GEN5_OPCODE_AVG 66 |
||
| 849 | #define GEN5_OPCODE_FRC 67 |
||
| 850 | #define GEN5_OPCODE_RNDU 68 |
||
| 851 | #define GEN5_OPCODE_RNDD 69 |
||
| 852 | #define GEN5_OPCODE_RNDE 70 |
||
| 853 | #define GEN5_OPCODE_RNDZ 71 |
||
| 854 | #define GEN5_OPCODE_MAC 72 |
||
| 855 | #define GEN5_OPCODE_MACH 73 |
||
| 856 | #define GEN5_OPCODE_LZD 74 |
||
| 857 | #define GEN5_OPCODE_SAD2 80 |
||
| 858 | #define GEN5_OPCODE_SADA2 81 |
||
| 859 | #define GEN5_OPCODE_DP4 84 |
||
| 860 | #define GEN5_OPCODE_DPH 85 |
||
| 861 | #define GEN5_OPCODE_DP3 86 |
||
| 862 | #define GEN5_OPCODE_DP2 87 |
||
| 863 | #define GEN5_OPCODE_DPA2 88 |
||
| 864 | #define GEN5_OPCODE_LINE 89 |
||
| 865 | #define GEN5_OPCODE_NOP 126 |
||
| 866 | |||
| 867 | #define GEN5_PREDICATE_NONE 0 |
||
| 868 | #define GEN5_PREDICATE_NORMAL 1 |
||
| 869 | #define GEN5_PREDICATE_ALIGN1_ANYV 2 |
||
| 870 | #define GEN5_PREDICATE_ALIGN1_ALLV 3 |
||
| 871 | #define GEN5_PREDICATE_ALIGN1_ANY2H 4 |
||
| 872 | #define GEN5_PREDICATE_ALIGN1_ALL2H 5 |
||
| 873 | #define GEN5_PREDICATE_ALIGN1_ANY4H 6 |
||
| 874 | #define GEN5_PREDICATE_ALIGN1_ALL4H 7 |
||
| 875 | #define GEN5_PREDICATE_ALIGN1_ANY8H 8 |
||
| 876 | #define GEN5_PREDICATE_ALIGN1_ALL8H 9 |
||
| 877 | #define GEN5_PREDICATE_ALIGN1_ANY16H 10 |
||
| 878 | #define GEN5_PREDICATE_ALIGN1_ALL16H 11 |
||
| 879 | #define GEN5_PREDICATE_ALIGN16_REPLICATE_X 2 |
||
| 880 | #define GEN5_PREDICATE_ALIGN16_REPLICATE_Y 3 |
||
| 881 | #define GEN5_PREDICATE_ALIGN16_REPLICATE_Z 4 |
||
| 882 | #define GEN5_PREDICATE_ALIGN16_REPLICATE_W 5 |
||
| 883 | #define GEN5_PREDICATE_ALIGN16_ANY4H 6 |
||
| 884 | #define GEN5_PREDICATE_ALIGN16_ALL4H 7 |
||
| 885 | |||
| 886 | #define GEN5_ARCHITECTURE_REGISTER_FILE 0 |
||
| 887 | #define GEN5_GENERAL_REGISTER_FILE 1 |
||
| 888 | #define GEN5_MESSAGE_REGISTER_FILE 2 |
||
| 889 | #define GEN5_IMMEDIATE_VALUE 3 |
||
| 890 | |||
| 891 | #define GEN5_REGISTER_TYPE_UD 0 |
||
| 892 | #define GEN5_REGISTER_TYPE_D 1 |
||
| 893 | #define GEN5_REGISTER_TYPE_UW 2 |
||
| 894 | #define GEN5_REGISTER_TYPE_W 3 |
||
| 895 | #define GEN5_REGISTER_TYPE_UB 4 |
||
| 896 | #define GEN5_REGISTER_TYPE_B 5 |
||
| 897 | #define GEN5_REGISTER_TYPE_VF 5 /* packed float vector, immediates only? */ |
||
| 898 | #define GEN5_REGISTER_TYPE_HF 6 |
||
| 899 | #define GEN5_REGISTER_TYPE_V 6 /* packed int vector, immediates only, uword dest only */ |
||
| 900 | #define GEN5_REGISTER_TYPE_F 7 |
||
| 901 | |||
| 902 | #define GEN5_ARF_NULL 0x00 |
||
| 903 | #define GEN5_ARF_ADDRESS 0x10 |
||
| 904 | #define GEN5_ARF_ACCUMULATOR 0x20 |
||
| 905 | #define GEN5_ARF_FLAG 0x30 |
||
| 906 | #define GEN5_ARF_MASK 0x40 |
||
| 907 | #define GEN5_ARF_MASK_STACK 0x50 |
||
| 908 | #define GEN5_ARF_MASK_STACK_DEPTH 0x60 |
||
| 909 | #define GEN5_ARF_STATE 0x70 |
||
| 910 | #define GEN5_ARF_CONTROL 0x80 |
||
| 911 | #define GEN5_ARF_NOTIFICATION_COUNT 0x90 |
||
| 912 | #define GEN5_ARF_IP 0xA0 |
||
| 913 | |||
| 914 | #define GEN5_AMASK 0 |
||
| 915 | #define GEN5_IMASK 1 |
||
| 916 | #define GEN5_LMASK 2 |
||
| 917 | #define GEN5_CMASK 3 |
||
| 918 | |||
| 919 | |||
| 920 | |||
| 921 | #define GEN5_THREAD_NORMAL 0 |
||
| 922 | #define GEN5_THREAD_ATOMIC 1 |
||
| 923 | #define GEN5_THREAD_SWITCH 2 |
||
| 924 | |||
| 925 | #define GEN5_VERTICAL_STRIDE_0 0 |
||
| 926 | #define GEN5_VERTICAL_STRIDE_1 1 |
||
| 927 | #define GEN5_VERTICAL_STRIDE_2 2 |
||
| 928 | #define GEN5_VERTICAL_STRIDE_4 3 |
||
| 929 | #define GEN5_VERTICAL_STRIDE_8 4 |
||
| 930 | #define GEN5_VERTICAL_STRIDE_16 5 |
||
| 931 | #define GEN5_VERTICAL_STRIDE_32 6 |
||
| 932 | #define GEN5_VERTICAL_STRIDE_64 7 |
||
| 933 | #define GEN5_VERTICAL_STRIDE_128 8 |
||
| 934 | #define GEN5_VERTICAL_STRIDE_256 9 |
||
| 935 | #define GEN5_VERTICAL_STRIDE_ONE_DIMENSIONAL 0xF |
||
| 936 | |||
| 937 | #define GEN5_WIDTH_1 0 |
||
| 938 | #define GEN5_WIDTH_2 1 |
||
| 939 | #define GEN5_WIDTH_4 2 |
||
| 940 | #define GEN5_WIDTH_8 3 |
||
| 941 | #define GEN5_WIDTH_16 4 |
||
| 942 | |||
| 943 | #define GEN5_STATELESS_BUFFER_BOUNDARY_1K 0 |
||
| 944 | #define GEN5_STATELESS_BUFFER_BOUNDARY_2K 1 |
||
| 945 | #define GEN5_STATELESS_BUFFER_BOUNDARY_4K 2 |
||
| 946 | #define GEN5_STATELESS_BUFFER_BOUNDARY_8K 3 |
||
| 947 | #define GEN5_STATELESS_BUFFER_BOUNDARY_16K 4 |
||
| 948 | #define GEN5_STATELESS_BUFFER_BOUNDARY_32K 5 |
||
| 949 | #define GEN5_STATELESS_BUFFER_BOUNDARY_64K 6 |
||
| 950 | #define GEN5_STATELESS_BUFFER_BOUNDARY_128K 7 |
||
| 951 | #define GEN5_STATELESS_BUFFER_BOUNDARY_256K 8 |
||
| 952 | #define GEN5_STATELESS_BUFFER_BOUNDARY_512K 9 |
||
| 953 | #define GEN5_STATELESS_BUFFER_BOUNDARY_1M 10 |
||
| 954 | #define GEN5_STATELESS_BUFFER_BOUNDARY_2M 11 |
||
| 955 | |||
| 956 | #define GEN5_POLYGON_FACING_FRONT 0 |
||
| 957 | #define GEN5_POLYGON_FACING_BACK 1 |
||
| 958 | |||
| 959 | #define GEN5_MESSAGE_TARGET_NULL 0 |
||
| 960 | #define GEN5_MESSAGE_TARGET_MATH 1 |
||
| 961 | #define GEN5_MESSAGE_TARGET_SAMPLER 2 |
||
| 962 | #define GEN5_MESSAGE_TARGET_GATEWAY 3 |
||
| 963 | #define GEN5_MESSAGE_TARGET_DATAPORT_READ 4 |
||
| 964 | #define GEN5_MESSAGE_TARGET_DATAPORT_WRITE 5 |
||
| 965 | #define GEN5_MESSAGE_TARGET_URB 6 |
||
| 966 | #define GEN5_MESSAGE_TARGET_THREAD_SPAWNER 7 |
||
| 967 | |||
| 968 | #define GEN5_SAMPLER_RETURN_FORMAT_FLOAT32 0 |
||
| 969 | #define GEN5_SAMPLER_RETURN_FORMAT_UINT32 2 |
||
| 970 | #define GEN5_SAMPLER_RETURN_FORMAT_SINT32 3 |
||
| 971 | |||
| 972 | #define GEN5_SAMPLER_MESSAGE_SIMD8_SAMPLE 0 |
||
| 973 | #define GEN5_SAMPLER_MESSAGE_SIMD16_SAMPLE 0 |
||
| 974 | #define GEN5_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS 0 |
||
| 975 | #define GEN5_SAMPLER_MESSAGE_SIMD8_KILLPIX 1 |
||
| 976 | #define GEN5_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD 1 |
||
| 977 | #define GEN5_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD 1 |
||
| 978 | #define GEN5_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS 2 |
||
| 979 | #define GEN5_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS 2 |
||
| 980 | #define GEN5_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_COMPARE 0 |
||
| 981 | #define GEN5_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE 2 |
||
| 982 | #define GEN5_SAMPLER_MESSAGE_SIMD4X2_RESINFO 2 |
||
| 983 | #define GEN5_SAMPLER_MESSAGE_SIMD8_RESINFO 2 |
||
| 984 | #define GEN5_SAMPLER_MESSAGE_SIMD16_RESINFO 2 |
||
| 985 | #define GEN5_SAMPLER_MESSAGE_SIMD4X2_LD 3 |
||
| 986 | #define GEN5_SAMPLER_MESSAGE_SIMD8_LD 3 |
||
| 987 | #define GEN5_SAMPLER_MESSAGE_SIMD16_LD 3 |
||
| 988 | |||
| 989 | #define GEN5_DATAPORT_OWORD_BLOCK_1_OWORDLOW 0 |
||
| 990 | #define GEN5_DATAPORT_OWORD_BLOCK_1_OWORDHIGH 1 |
||
| 991 | #define GEN5_DATAPORT_OWORD_BLOCK_2_OWORDS 2 |
||
| 992 | #define GEN5_DATAPORT_OWORD_BLOCK_4_OWORDS 3 |
||
| 993 | #define GEN5_DATAPORT_OWORD_BLOCK_8_OWORDS 4 |
||
| 994 | |||
| 995 | #define GEN5_DATAPORT_OWORD_DUAL_BLOCK_1OWORD 0 |
||
| 996 | #define GEN5_DATAPORT_OWORD_DUAL_BLOCK_4OWORDS 2 |
||
| 997 | |||
| 998 | #define GEN5_DATAPORT_DWORD_SCATTERED_BLOCK_8DWORDS 2 |
||
| 999 | #define GEN5_DATAPORT_DWORD_SCATTERED_BLOCK_16DWORDS 3 |
||
| 1000 | |||
| 1001 | #define GEN5_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ 0 |
||
| 1002 | #define GEN5_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ 1 |
||
| 1003 | #define GEN5_DATAPORT_READ_MESSAGE_DWORD_BLOCK_READ 2 |
||
| 1004 | #define GEN5_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ 3 |
||
| 1005 | |||
| 1006 | #define GEN5_DATAPORT_READ_TARGET_DATA_CACHE 0 |
||
| 1007 | #define GEN5_DATAPORT_READ_TARGET_RENDER_CACHE 1 |
||
| 1008 | #define GEN5_DATAPORT_READ_TARGET_SAMPLER_CACHE 2 |
||
| 1009 | |||
| 1010 | #define GEN5_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE 0 |
||
| 1011 | #define GEN5_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED 1 |
||
| 1012 | #define GEN5_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01 2 |
||
| 1013 | #define GEN5_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN23 3 |
||
| 1014 | #define GEN5_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01 4 |
||
| 1015 | |||
| 1016 | #define GEN5_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE 0 |
||
| 1017 | #define GEN5_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE 1 |
||
| 1018 | #define GEN5_DATAPORT_WRITE_MESSAGE_DWORD_BLOCK_WRITE 2 |
||
| 1019 | #define GEN5_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE 3 |
||
| 1020 | #define GEN5_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE 4 |
||
| 1021 | #define GEN5_DATAPORT_WRITE_MESSAGE_STREAMED_VERTEX_BUFFER_WRITE 5 |
||
| 1022 | #define GEN5_DATAPORT_WRITE_MESSAGE_FLUSH_RENDER_CACHE 7 |
||
| 1023 | |||
| 1024 | #define GEN5_MATH_FUNCTION_INV 1 |
||
| 1025 | #define GEN5_MATH_FUNCTION_LOG 2 |
||
| 1026 | #define GEN5_MATH_FUNCTION_EXP 3 |
||
| 1027 | #define GEN5_MATH_FUNCTION_SQRT 4 |
||
| 1028 | #define GEN5_MATH_FUNCTION_RSQ 5 |
||
| 1029 | #define GEN5_MATH_FUNCTION_SIN 6 /* was 7 */ |
||
| 1030 | #define GEN5_MATH_FUNCTION_COS 7 /* was 8 */ |
||
| 1031 | #define GEN5_MATH_FUNCTION_SINCOS 8 /* was 6 */ |
||
| 1032 | #define GEN5_MATH_FUNCTION_TAN 9 |
||
| 1033 | #define GEN5_MATH_FUNCTION_POW 10 |
||
| 1034 | #define GEN5_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER 11 |
||
| 1035 | #define GEN5_MATH_FUNCTION_INT_DIV_QUOTIENT 12 |
||
| 1036 | #define GEN5_MATH_FUNCTION_INT_DIV_REMAINDER 13 |
||
| 1037 | |||
| 1038 | #define GEN5_MATH_INTEGER_UNSIGNED 0 |
||
| 1039 | #define GEN5_MATH_INTEGER_SIGNED 1 |
||
| 1040 | |||
| 1041 | #define GEN5_MATH_PRECISION_FULL 0 |
||
| 1042 | #define GEN5_MATH_PRECISION_PARTIAL 1 |
||
| 1043 | |||
| 1044 | #define GEN5_MATH_SATURATE_NONE 0 |
||
| 1045 | #define GEN5_MATH_SATURATE_SATURATE 1 |
||
| 1046 | |||
| 1047 | #define GEN5_MATH_DATA_VECTOR 0 |
||
| 1048 | #define GEN5_MATH_DATA_SCALAR 1 |
||
| 1049 | |||
| 1050 | #define GEN5_URB_OPCODE_WRITE 0 |
||
| 1051 | |||
| 1052 | #define GEN5_URB_SWIZZLE_NONE 0 |
||
| 1053 | #define GEN5_URB_SWIZZLE_INTERLEAVE 1 |
||
| 1054 | #define GEN5_URB_SWIZZLE_TRANSPOSE 2 |
||
| 1055 | |||
| 1056 | #define GEN5_SCRATCH_SPACE_SIZE_1K 0 |
||
| 1057 | #define GEN5_SCRATCH_SPACE_SIZE_2K 1 |
||
| 1058 | #define GEN5_SCRATCH_SPACE_SIZE_4K 2 |
||
| 1059 | #define GEN5_SCRATCH_SPACE_SIZE_8K 3 |
||
| 1060 | #define GEN5_SCRATCH_SPACE_SIZE_16K 4 |
||
| 1061 | #define GEN5_SCRATCH_SPACE_SIZE_32K 5 |
||
| 1062 | #define GEN5_SCRATCH_SPACE_SIZE_64K 6 |
||
| 1063 | #define GEN5_SCRATCH_SPACE_SIZE_128K 7 |
||
| 1064 | #define GEN5_SCRATCH_SPACE_SIZE_256K 8 |
||
| 1065 | #define GEN5_SCRATCH_SPACE_SIZE_512K 9 |
||
| 1066 | #define GEN5_SCRATCH_SPACE_SIZE_1M 10 |
||
| 1067 | #define GEN5_SCRATCH_SPACE_SIZE_2M 11 |
||
| 1068 | |||
| 1069 | |||
| 1070 | |||
| 1071 | |||
| 1072 | #define CMD_URB_FENCE 0x6000 |
||
| 1073 | #define CMD_CONST_BUFFER_STATE 0x6001 |
||
| 1074 | #define CMD_CONST_BUFFER 0x6002 |
||
| 1075 | |||
| 1076 | #define CMD_STATE_BASE_ADDRESS 0x6101 |
||
| 1077 | #define CMD_STATE_INSN_POINTER 0x6102 |
||
| 1078 | #define CMD_PIPELINE_SELECT 0x6104 |
||
| 1079 | |||
| 1080 | #define CMD_PIPELINED_STATE_POINTERS 0x7800 |
||
| 1081 | #define CMD_BINDING_TABLE_PTRS 0x7801 |
||
| 1082 | #define CMD_VERTEX_BUFFER 0x7808 |
||
| 1083 | #define CMD_VERTEX_ELEMENT 0x7809 |
||
| 1084 | #define CMD_INDEX_BUFFER 0x780a |
||
| 1085 | #define CMD_VF_STATISTICS 0x780b |
||
| 1086 | |||
| 1087 | #define CMD_DRAW_RECT 0x7900 |
||
| 1088 | #define CMD_BLEND_CONSTANT_COLOR 0x7901 |
||
| 1089 | #define CMD_CHROMA_KEY 0x7904 |
||
| 1090 | #define CMD_DEPTH_BUFFER 0x7905 |
||
| 1091 | #define CMD_POLY_STIPPLE_OFFSET 0x7906 |
||
| 1092 | #define CMD_POLY_STIPPLE_PATTERN 0x7907 |
||
| 1093 | #define CMD_LINE_STIPPLE_PATTERN 0x7908 |
||
| 1094 | #define CMD_GLOBAL_DEPTH_OFFSET_CLAMP 0x7908 |
||
| 1095 | |||
| 1096 | #define CMD_PIPE_CONTROL 0x7a00 |
||
| 1097 | |||
| 1098 | #define CMD_3D_PRIM 0x7b00 |
||
| 1099 | |||
| 1100 | #define CMD_MI_FLUSH 0x0200 |
||
| 1101 | |||
| 1102 | |||
| 1103 | /* Various values from the R0 vertex header: |
||
| 1104 | */ |
||
| 1105 | #define R02_PRIM_END 0x1 |
||
| 1106 | #define R02_PRIM_START 0x2 |
||
| 1107 | |||
| 1108 | /* media pipeline */ |
||
| 1109 | |||
| 1110 | #define GEN5_VFE_MODE_GENERIC 0x0 |
||
| 1111 | #define GEN5_VFE_MODE_VLD_MPEG2 0x1 |
||
| 1112 | #define GEN5_VFE_MODE_IS 0x2 |
||
| 1113 | #define GEN5_VFE_MODE_AVC_MC 0x4 |
||
| 1114 | #define GEN5_VFE_MODE_AVC_IT 0x7 |
||
| 1115 | #define GEN5_VFE_MODE_VC1_IT 0xB |
||
| 1116 | |||
| 1117 | #define GEN5_VFE_DEBUG_COUNTER_FREE 0 |
||
| 1118 | #define GEN5_VFE_DEBUG_COUNTER_FROZEN 1 |
||
| 1119 | #define GEN5_VFE_DEBUG_COUNTER_ONCE 2 |
||
| 1120 | #define GEN5_VFE_DEBUG_COUNTER_ALWAYS 3 |
||
| 1121 | |||
| 1122 | /* VLD_STATE */ |
||
| 1123 | #define GEN5_MPEG_TOP_FIELD 1 |
||
| 1124 | #define GEN5_MPEG_BOTTOM_FIELD 2 |
||
| 1125 | #define GEN5_MPEG_FRAME 3 |
||
| 1126 | #define GEN5_MPEG_QSCALE_LINEAR 0 |
||
| 1127 | #define GEN5_MPEG_QSCALE_NONLINEAR 1 |
||
| 1128 | #define GEN5_MPEG_ZIGZAG_SCAN 0 |
||
| 1129 | #define GEN5_MPEG_ALTER_VERTICAL_SCAN 1 |
||
| 1130 | #define GEN5_MPEG_I_PICTURE 1 |
||
| 1131 | #define GEN5_MPEG_P_PICTURE 2 |
||
| 1132 | #define GEN5_MPEG_B_PICTURE 3 |
||
| 1133 | |||
| 1134 | /* Command packets: |
||
| 1135 | */ |
||
| 1136 | struct header |
||
| 1137 | { |
||
| 1138 | unsigned int length:16; |
||
| 1139 | unsigned int opcode:16; |
||
| 1140 | }; |
||
| 1141 | |||
| 1142 | |||
| 1143 | union header_union |
||
| 1144 | { |
||
| 1145 | struct header bits; |
||
| 1146 | unsigned int dword; |
||
| 1147 | }; |
||
| 1148 | |||
| 1149 | struct gen5_3d_control |
||
| 1150 | { |
||
| 1151 | struct |
||
| 1152 | { |
||
| 1153 | unsigned int length:8; |
||
| 1154 | unsigned int notify_enable:1; |
||
| 1155 | unsigned int pad:3; |
||
| 1156 | unsigned int wc_flush_enable:1; |
||
| 1157 | unsigned int depth_stall_enable:1; |
||
| 1158 | unsigned int operation:2; |
||
| 1159 | unsigned int opcode:16; |
||
| 1160 | } header; |
||
| 1161 | |||
| 1162 | struct |
||
| 1163 | { |
||
| 1164 | unsigned int pad:2; |
||
| 1165 | unsigned int dest_addr_type:1; |
||
| 1166 | unsigned int dest_addr:29; |
||
| 1167 | } dest; |
||
| 1168 | |||
| 1169 | unsigned int dword2; |
||
| 1170 | unsigned int dword3; |
||
| 1171 | }; |
||
| 1172 | |||
| 1173 | |||
| 1174 | struct gen5_3d_primitive |
||
| 1175 | { |
||
| 1176 | struct |
||
| 1177 | { |
||
| 1178 | unsigned int length:8; |
||
| 1179 | unsigned int pad:2; |
||
| 1180 | unsigned int topology:5; |
||
| 1181 | unsigned int indexed:1; |
||
| 1182 | unsigned int opcode:16; |
||
| 1183 | } header; |
||
| 1184 | |||
| 1185 | unsigned int verts_per_instance; |
||
| 1186 | unsigned int start_vert_location; |
||
| 1187 | unsigned int instance_count; |
||
| 1188 | unsigned int start_instance_location; |
||
| 1189 | unsigned int base_vert_location; |
||
| 1190 | }; |
||
| 1191 | |||
| 1192 | /* These seem to be passed around as function args, so it works out |
||
| 1193 | * better to keep them as #defines: |
||
| 1194 | */ |
||
| 1195 | #define GEN5_FLUSH_READ_CACHE 0x1 |
||
| 1196 | #define GEN5_FLUSH_STATE_CACHE 0x2 |
||
| 1197 | #define GEN5_INHIBIT_FLUSH_RENDER_CACHE 0x4 |
||
| 1198 | #define GEN5_FLUSH_SNAPSHOT_COUNTERS 0x8 |
||
| 1199 | |||
| 1200 | struct gen5_mi_flush |
||
| 1201 | { |
||
| 1202 | unsigned int flags:4; |
||
| 1203 | unsigned int pad:12; |
||
| 1204 | unsigned int opcode:16; |
||
| 1205 | }; |
||
| 1206 | |||
| 1207 | struct gen5_vf_statistics |
||
| 1208 | { |
||
| 1209 | unsigned int statistics_enable:1; |
||
| 1210 | unsigned int pad:15; |
||
| 1211 | unsigned int opcode:16; |
||
| 1212 | }; |
||
| 1213 | |||
| 1214 | |||
| 1215 | |||
| 1216 | struct gen5_binding_table_pointers |
||
| 1217 | { |
||
| 1218 | struct header header; |
||
| 1219 | unsigned int vs; |
||
| 1220 | unsigned int gs; |
||
| 1221 | unsigned int clp; |
||
| 1222 | unsigned int sf; |
||
| 1223 | unsigned int wm; |
||
| 1224 | }; |
||
| 1225 | |||
| 1226 | |||
| 1227 | struct gen5_blend_constant_color |
||
| 1228 | { |
||
| 1229 | struct header header; |
||
| 1230 | float blend_constant_color[4]; |
||
| 1231 | }; |
||
| 1232 | |||
| 1233 | |||
| 1234 | struct gen5_depthbuffer |
||
| 1235 | { |
||
| 1236 | union header_union header; |
||
| 1237 | |||
| 1238 | union { |
||
| 1239 | struct { |
||
| 1240 | unsigned int pitch:18; |
||
| 1241 | unsigned int format:3; |
||
| 1242 | unsigned int pad:4; |
||
| 1243 | unsigned int depth_offset_disable:1; |
||
| 1244 | unsigned int tile_walk:1; |
||
| 1245 | unsigned int tiled_surface:1; |
||
| 1246 | unsigned int pad2:1; |
||
| 1247 | unsigned int surface_type:3; |
||
| 1248 | } bits; |
||
| 1249 | unsigned int dword; |
||
| 1250 | } dword1; |
||
| 1251 | |||
| 1252 | unsigned int dword2_base_addr; |
||
| 1253 | |||
| 1254 | union { |
||
| 1255 | struct { |
||
| 1256 | unsigned int pad:1; |
||
| 1257 | unsigned int mipmap_layout:1; |
||
| 1258 | unsigned int lod:4; |
||
| 1259 | unsigned int width:13; |
||
| 1260 | unsigned int height:13; |
||
| 1261 | } bits; |
||
| 1262 | unsigned int dword; |
||
| 1263 | } dword3; |
||
| 1264 | |||
| 1265 | union { |
||
| 1266 | struct { |
||
| 1267 | unsigned int pad:12; |
||
| 1268 | unsigned int min_array_element:9; |
||
| 1269 | unsigned int depth:11; |
||
| 1270 | } bits; |
||
| 1271 | unsigned int dword; |
||
| 1272 | } dword4; |
||
| 1273 | }; |
||
| 1274 | |||
| 1275 | struct gen5_drawrect |
||
| 1276 | { |
||
| 1277 | struct header header; |
||
| 1278 | unsigned int xmin:16; |
||
| 1279 | unsigned int ymin:16; |
||
| 1280 | unsigned int xmax:16; |
||
| 1281 | unsigned int ymax:16; |
||
| 1282 | unsigned int xorg:16; |
||
| 1283 | unsigned int yorg:16; |
||
| 1284 | }; |
||
| 1285 | |||
| 1286 | |||
| 1287 | |||
| 1288 | |||
| 1289 | struct gen5_global_depth_offset_clamp |
||
| 1290 | { |
||
| 1291 | struct header header; |
||
| 1292 | float depth_offset_clamp; |
||
| 1293 | }; |
||
| 1294 | |||
| 1295 | struct gen5_indexbuffer |
||
| 1296 | { |
||
| 1297 | union { |
||
| 1298 | struct |
||
| 1299 | { |
||
| 1300 | unsigned int length:8; |
||
| 1301 | unsigned int index_format:2; |
||
| 1302 | unsigned int cut_index_enable:1; |
||
| 1303 | unsigned int pad:5; |
||
| 1304 | unsigned int opcode:16; |
||
| 1305 | } bits; |
||
| 1306 | unsigned int dword; |
||
| 1307 | |||
| 1308 | } header; |
||
| 1309 | |||
| 1310 | unsigned int buffer_start; |
||
| 1311 | unsigned int buffer_end; |
||
| 1312 | }; |
||
| 1313 | |||
| 1314 | |||
| 1315 | struct gen5_line_stipple |
||
| 1316 | { |
||
| 1317 | struct header header; |
||
| 1318 | |||
| 1319 | struct |
||
| 1320 | { |
||
| 1321 | unsigned int pattern:16; |
||
| 1322 | unsigned int pad:16; |
||
| 1323 | } bits0; |
||
| 1324 | |||
| 1325 | struct |
||
| 1326 | { |
||
| 1327 | unsigned int repeat_count:9; |
||
| 1328 | unsigned int pad:7; |
||
| 1329 | unsigned int inverse_repeat_count:16; |
||
| 1330 | } bits1; |
||
| 1331 | }; |
||
| 1332 | |||
| 1333 | |||
| 1334 | struct gen5_pipelined_state_pointers |
||
| 1335 | { |
||
| 1336 | struct header header; |
||
| 1337 | |||
| 1338 | struct { |
||
| 1339 | unsigned int pad:5; |
||
| 1340 | unsigned int offset:27; |
||
| 1341 | } vs; |
||
| 1342 | |||
| 1343 | struct |
||
| 1344 | { |
||
| 1345 | unsigned int enable:1; |
||
| 1346 | unsigned int pad:4; |
||
| 1347 | unsigned int offset:27; |
||
| 1348 | } gs; |
||
| 1349 | |||
| 1350 | struct |
||
| 1351 | { |
||
| 1352 | unsigned int enable:1; |
||
| 1353 | unsigned int pad:4; |
||
| 1354 | unsigned int offset:27; |
||
| 1355 | } clp; |
||
| 1356 | |||
| 1357 | struct |
||
| 1358 | { |
||
| 1359 | unsigned int pad:5; |
||
| 1360 | unsigned int offset:27; |
||
| 1361 | } sf; |
||
| 1362 | |||
| 1363 | struct |
||
| 1364 | { |
||
| 1365 | unsigned int pad:5; |
||
| 1366 | unsigned int offset:27; |
||
| 1367 | } wm; |
||
| 1368 | |||
| 1369 | struct |
||
| 1370 | { |
||
| 1371 | unsigned int pad:5; |
||
| 1372 | unsigned int offset:27; /* KW: check me! */ |
||
| 1373 | } cc; |
||
| 1374 | }; |
||
| 1375 | |||
| 1376 | |||
| 1377 | struct gen5_polygon_stipple_offset |
||
| 1378 | { |
||
| 1379 | struct header header; |
||
| 1380 | |||
| 1381 | struct { |
||
| 1382 | unsigned int y_offset:5; |
||
| 1383 | unsigned int pad:3; |
||
| 1384 | unsigned int x_offset:5; |
||
| 1385 | unsigned int pad0:19; |
||
| 1386 | } bits0; |
||
| 1387 | }; |
||
| 1388 | |||
| 1389 | |||
| 1390 | |||
| 1391 | struct gen5_polygon_stipple |
||
| 1392 | { |
||
| 1393 | struct header header; |
||
| 1394 | unsigned int stipple[32]; |
||
| 1395 | }; |
||
| 1396 | |||
| 1397 | |||
| 1398 | |||
| 1399 | struct gen5_pipeline_select |
||
| 1400 | { |
||
| 1401 | struct |
||
| 1402 | { |
||
| 1403 | unsigned int pipeline_select:1; |
||
| 1404 | unsigned int pad:15; |
||
| 1405 | unsigned int opcode:16; |
||
| 1406 | } header; |
||
| 1407 | }; |
||
| 1408 | |||
| 1409 | |||
| 1410 | struct gen5_pipe_control |
||
| 1411 | { |
||
| 1412 | struct |
||
| 1413 | { |
||
| 1414 | unsigned int length:8; |
||
| 1415 | unsigned int notify_enable:1; |
||
| 1416 | unsigned int pad:2; |
||
| 1417 | unsigned int instruction_state_cache_flush_enable:1; |
||
| 1418 | unsigned int write_cache_flush_enable:1; |
||
| 1419 | unsigned int depth_stall_enable:1; |
||
| 1420 | unsigned int post_sync_operation:2; |
||
| 1421 | |||
| 1422 | unsigned int opcode:16; |
||
| 1423 | } header; |
||
| 1424 | |||
| 1425 | struct |
||
| 1426 | { |
||
| 1427 | unsigned int pad:2; |
||
| 1428 | unsigned int dest_addr_type:1; |
||
| 1429 | unsigned int dest_addr:29; |
||
| 1430 | } bits1; |
||
| 1431 | |||
| 1432 | unsigned int data0; |
||
| 1433 | unsigned int data1; |
||
| 1434 | }; |
||
| 1435 | |||
| 1436 | |||
| 1437 | struct gen5_urb_fence |
||
| 1438 | { |
||
| 1439 | struct |
||
| 1440 | { |
||
| 1441 | unsigned int length:8; |
||
| 1442 | unsigned int vs_realloc:1; |
||
| 1443 | unsigned int gs_realloc:1; |
||
| 1444 | unsigned int clp_realloc:1; |
||
| 1445 | unsigned int sf_realloc:1; |
||
| 1446 | unsigned int vfe_realloc:1; |
||
| 1447 | unsigned int cs_realloc:1; |
||
| 1448 | unsigned int pad:2; |
||
| 1449 | unsigned int opcode:16; |
||
| 1450 | } header; |
||
| 1451 | |||
| 1452 | struct |
||
| 1453 | { |
||
| 1454 | unsigned int vs_fence:10; |
||
| 1455 | unsigned int gs_fence:10; |
||
| 1456 | unsigned int clp_fence:10; |
||
| 1457 | unsigned int pad:2; |
||
| 1458 | } bits0; |
||
| 1459 | |||
| 1460 | struct |
||
| 1461 | { |
||
| 1462 | unsigned int sf_fence:10; |
||
| 1463 | unsigned int vf_fence:10; |
||
| 1464 | unsigned int cs_fence:10; |
||
| 1465 | unsigned int pad:2; |
||
| 1466 | } bits1; |
||
| 1467 | }; |
||
| 1468 | |||
| 1469 | struct gen5_constant_buffer_state /* previously gen5_command_streamer */ |
||
| 1470 | { |
||
| 1471 | struct header header; |
||
| 1472 | |||
| 1473 | struct |
||
| 1474 | { |
||
| 1475 | unsigned int nr_urb_entries:3; |
||
| 1476 | unsigned int pad:1; |
||
| 1477 | unsigned int urb_entry_size:5; |
||
| 1478 | unsigned int pad0:23; |
||
| 1479 | } bits0; |
||
| 1480 | }; |
||
| 1481 | |||
| 1482 | struct gen5_constant_buffer |
||
| 1483 | { |
||
| 1484 | struct |
||
| 1485 | { |
||
| 1486 | unsigned int length:8; |
||
| 1487 | unsigned int valid:1; |
||
| 1488 | unsigned int pad:7; |
||
| 1489 | unsigned int opcode:16; |
||
| 1490 | } header; |
||
| 1491 | |||
| 1492 | struct |
||
| 1493 | { |
||
| 1494 | unsigned int buffer_length:6; |
||
| 1495 | unsigned int buffer_address:26; |
||
| 1496 | } bits0; |
||
| 1497 | }; |
||
| 1498 | |||
| 1499 | struct gen5_state_base_address |
||
| 1500 | { |
||
| 1501 | struct header header; |
||
| 1502 | |||
| 1503 | struct |
||
| 1504 | { |
||
| 1505 | unsigned int modify_enable:1; |
||
| 1506 | unsigned int pad:4; |
||
| 1507 | unsigned int general_state_address:27; |
||
| 1508 | } bits0; |
||
| 1509 | |||
| 1510 | struct |
||
| 1511 | { |
||
| 1512 | unsigned int modify_enable:1; |
||
| 1513 | unsigned int pad:4; |
||
| 1514 | unsigned int surface_state_address:27; |
||
| 1515 | } bits1; |
||
| 1516 | |||
| 1517 | struct |
||
| 1518 | { |
||
| 1519 | unsigned int modify_enable:1; |
||
| 1520 | unsigned int pad:4; |
||
| 1521 | unsigned int indirect_object_state_address:27; |
||
| 1522 | } bits2; |
||
| 1523 | |||
| 1524 | struct |
||
| 1525 | { |
||
| 1526 | unsigned int modify_enable:1; |
||
| 1527 | unsigned int pad:11; |
||
| 1528 | unsigned int general_state_upper_bound:20; |
||
| 1529 | } bits3; |
||
| 1530 | |||
| 1531 | struct |
||
| 1532 | { |
||
| 1533 | unsigned int modify_enable:1; |
||
| 1534 | unsigned int pad:11; |
||
| 1535 | unsigned int indirect_object_state_upper_bound:20; |
||
| 1536 | } bits4; |
||
| 1537 | }; |
||
| 1538 | |||
| 1539 | struct gen5_state_prefetch |
||
| 1540 | { |
||
| 1541 | struct header header; |
||
| 1542 | |||
| 1543 | struct |
||
| 1544 | { |
||
| 1545 | unsigned int prefetch_count:3; |
||
| 1546 | unsigned int pad:3; |
||
| 1547 | unsigned int prefetch_pointer:26; |
||
| 1548 | } bits0; |
||
| 1549 | }; |
||
| 1550 | |||
| 1551 | struct gen5_system_instruction_pointer |
||
| 1552 | { |
||
| 1553 | struct header header; |
||
| 1554 | |||
| 1555 | struct |
||
| 1556 | { |
||
| 1557 | unsigned int pad:4; |
||
| 1558 | unsigned int system_instruction_pointer:28; |
||
| 1559 | } bits0; |
||
| 1560 | }; |
||
| 1561 | |||
| 1562 | |||
| 1563 | |||
| 1564 | |||
| 1565 | /* State structs for the various fixed function units: |
||
| 1566 | */ |
||
| 1567 | |||
| 1568 | |||
| 1569 | struct thread0 |
||
| 1570 | { |
||
| 1571 | unsigned int pad0:1; |
||
| 1572 | unsigned int grf_reg_count:3; |
||
| 1573 | unsigned int pad1:2; |
||
| 1574 | unsigned int kernel_start_pointer:26; |
||
| 1575 | }; |
||
| 1576 | |||
| 1577 | struct thread1 |
||
| 1578 | { |
||
| 1579 | unsigned int ext_halt_exception_enable:1; |
||
| 1580 | unsigned int sw_exception_enable:1; |
||
| 1581 | unsigned int mask_stack_exception_enable:1; |
||
| 1582 | unsigned int timeout_exception_enable:1; |
||
| 1583 | unsigned int illegal_op_exception_enable:1; |
||
| 1584 | unsigned int pad0:3; |
||
| 1585 | unsigned int depth_coef_urb_read_offset:6; /* WM only */ |
||
| 1586 | unsigned int pad1:2; |
||
| 1587 | unsigned int floating_point_mode:1; |
||
| 1588 | unsigned int thread_priority:1; |
||
| 1589 | unsigned int binding_table_entry_count:8; |
||
| 1590 | unsigned int pad3:5; |
||
| 1591 | unsigned int single_program_flow:1; |
||
| 1592 | }; |
||
| 1593 | |||
| 1594 | struct thread2 |
||
| 1595 | { |
||
| 1596 | unsigned int per_thread_scratch_space:4; |
||
| 1597 | unsigned int pad0:6; |
||
| 1598 | unsigned int scratch_space_base_pointer:22; |
||
| 1599 | }; |
||
| 1600 | |||
| 1601 | |||
| 1602 | struct thread3 |
||
| 1603 | { |
||
| 1604 | unsigned int dispatch_grf_start_reg:4; |
||
| 1605 | unsigned int urb_entry_read_offset:6; |
||
| 1606 | unsigned int pad0:1; |
||
| 1607 | unsigned int urb_entry_read_length:6; |
||
| 1608 | unsigned int pad1:1; |
||
| 1609 | unsigned int const_urb_entry_read_offset:6; |
||
| 1610 | unsigned int pad2:1; |
||
| 1611 | unsigned int const_urb_entry_read_length:6; |
||
| 1612 | unsigned int pad3:1; |
||
| 1613 | }; |
||
| 1614 | |||
| 1615 | |||
| 1616 | |||
| 1617 | struct gen5_clip_unit_state |
||
| 1618 | { |
||
| 1619 | struct thread0 thread0; |
||
| 1620 | struct thread1 thread1; |
||
| 1621 | struct thread2 thread2; |
||
| 1622 | struct thread3 thread3; |
||
| 1623 | |||
| 1624 | struct |
||
| 1625 | { |
||
| 1626 | unsigned int pad0:9; |
||
| 1627 | unsigned int gs_output_stats:1; /* not always */ |
||
| 1628 | unsigned int stats_enable:1; |
||
| 1629 | unsigned int nr_urb_entries:7; |
||
| 1630 | unsigned int pad1:1; |
||
| 1631 | unsigned int urb_entry_allocation_size:5; |
||
| 1632 | unsigned int pad2:1; |
||
| 1633 | unsigned int max_threads:6; /* may be less */ |
||
| 1634 | unsigned int pad3:1; |
||
| 1635 | } thread4; |
||
| 1636 | |||
| 1637 | struct |
||
| 1638 | { |
||
| 1639 | unsigned int pad0:13; |
||
| 1640 | unsigned int clip_mode:3; |
||
| 1641 | unsigned int userclip_enable_flags:8; |
||
| 1642 | unsigned int userclip_must_clip:1; |
||
| 1643 | unsigned int pad1:1; |
||
| 1644 | unsigned int guard_band_enable:1; |
||
| 1645 | unsigned int viewport_z_clip_enable:1; |
||
| 1646 | unsigned int viewport_xy_clip_enable:1; |
||
| 1647 | unsigned int vertex_position_space:1; |
||
| 1648 | unsigned int api_mode:1; |
||
| 1649 | unsigned int pad2:1; |
||
| 1650 | } clip5; |
||
| 1651 | |||
| 1652 | struct |
||
| 1653 | { |
||
| 1654 | unsigned int pad0:5; |
||
| 1655 | unsigned int clipper_viewport_state_ptr:27; |
||
| 1656 | } clip6; |
||
| 1657 | |||
| 1658 | |||
| 1659 | float viewport_xmin; |
||
| 1660 | float viewport_xmax; |
||
| 1661 | float viewport_ymin; |
||
| 1662 | float viewport_ymax; |
||
| 1663 | }; |
||
| 1664 | |||
| 1665 | |||
| 1666 | |||
| 1667 | struct gen5_cc_unit_state |
||
| 1668 | { |
||
| 1669 | struct |
||
| 1670 | { |
||
| 1671 | unsigned int pad0:3; |
||
| 1672 | unsigned int bf_stencil_pass_depth_pass_op:3; |
||
| 1673 | unsigned int bf_stencil_pass_depth_fail_op:3; |
||
| 1674 | unsigned int bf_stencil_fail_op:3; |
||
| 1675 | unsigned int bf_stencil_func:3; |
||
| 1676 | unsigned int bf_stencil_enable:1; |
||
| 1677 | unsigned int pad1:2; |
||
| 1678 | unsigned int stencil_write_enable:1; |
||
| 1679 | unsigned int stencil_pass_depth_pass_op:3; |
||
| 1680 | unsigned int stencil_pass_depth_fail_op:3; |
||
| 1681 | unsigned int stencil_fail_op:3; |
||
| 1682 | unsigned int stencil_func:3; |
||
| 1683 | unsigned int stencil_enable:1; |
||
| 1684 | } cc0; |
||
| 1685 | |||
| 1686 | |||
| 1687 | struct |
||
| 1688 | { |
||
| 1689 | unsigned int bf_stencil_ref:8; |
||
| 1690 | unsigned int stencil_write_mask:8; |
||
| 1691 | unsigned int stencil_test_mask:8; |
||
| 1692 | unsigned int stencil_ref:8; |
||
| 1693 | } cc1; |
||
| 1694 | |||
| 1695 | |||
| 1696 | struct |
||
| 1697 | { |
||
| 1698 | unsigned int logicop_enable:1; |
||
| 1699 | unsigned int pad0:10; |
||
| 1700 | unsigned int depth_write_enable:1; |
||
| 1701 | unsigned int depth_test_function:3; |
||
| 1702 | unsigned int depth_test:1; |
||
| 1703 | unsigned int bf_stencil_write_mask:8; |
||
| 1704 | unsigned int bf_stencil_test_mask:8; |
||
| 1705 | } cc2; |
||
| 1706 | |||
| 1707 | |||
| 1708 | struct |
||
| 1709 | { |
||
| 1710 | unsigned int pad0:8; |
||
| 1711 | unsigned int alpha_test_func:3; |
||
| 1712 | unsigned int alpha_test:1; |
||
| 1713 | unsigned int blend_enable:1; |
||
| 1714 | unsigned int ia_blend_enable:1; |
||
| 1715 | unsigned int pad1:1; |
||
| 1716 | unsigned int alpha_test_format:1; |
||
| 1717 | unsigned int pad2:16; |
||
| 1718 | } cc3; |
||
| 1719 | |||
| 1720 | struct |
||
| 1721 | { |
||
| 1722 | unsigned int pad0:5; |
||
| 1723 | unsigned int cc_viewport_state_offset:27; |
||
| 1724 | } cc4; |
||
| 1725 | |||
| 1726 | struct |
||
| 1727 | { |
||
| 1728 | unsigned int pad0:2; |
||
| 1729 | unsigned int ia_dest_blend_factor:5; |
||
| 1730 | unsigned int ia_src_blend_factor:5; |
||
| 1731 | unsigned int ia_blend_function:3; |
||
| 1732 | unsigned int statistics_enable:1; |
||
| 1733 | unsigned int logicop_func:4; |
||
| 1734 | unsigned int pad1:11; |
||
| 1735 | unsigned int dither_enable:1; |
||
| 1736 | } cc5; |
||
| 1737 | |||
| 1738 | struct |
||
| 1739 | { |
||
| 1740 | unsigned int clamp_post_alpha_blend:1; |
||
| 1741 | unsigned int clamp_pre_alpha_blend:1; |
||
| 1742 | unsigned int clamp_range:2; |
||
| 1743 | unsigned int pad0:11; |
||
| 1744 | unsigned int y_dither_offset:2; |
||
| 1745 | unsigned int x_dither_offset:2; |
||
| 1746 | unsigned int dest_blend_factor:5; |
||
| 1747 | unsigned int src_blend_factor:5; |
||
| 1748 | unsigned int blend_function:3; |
||
| 1749 | } cc6; |
||
| 1750 | |||
| 1751 | struct { |
||
| 1752 | union { |
||
| 1753 | float f; |
||
| 1754 | unsigned char ub[4]; |
||
| 1755 | } alpha_ref; |
||
| 1756 | } cc7; |
||
| 1757 | }; |
||
| 1758 | |||
| 1759 | |||
| 1760 | |||
| 1761 | struct gen5_sf_unit_state |
||
| 1762 | { |
||
| 1763 | struct thread0 thread0; |
||
| 1764 | struct { |
||
| 1765 | unsigned int pad0:7; |
||
| 1766 | unsigned int sw_exception_enable:1; |
||
| 1767 | unsigned int pad1:3; |
||
| 1768 | unsigned int mask_stack_exception_enable:1; |
||
| 1769 | unsigned int pad2:1; |
||
| 1770 | unsigned int illegal_op_exception_enable:1; |
||
| 1771 | unsigned int pad3:2; |
||
| 1772 | unsigned int floating_point_mode:1; |
||
| 1773 | unsigned int thread_priority:1; |
||
| 1774 | unsigned int binding_table_entry_count:8; |
||
| 1775 | unsigned int pad4:5; |
||
| 1776 | unsigned int single_program_flow:1; |
||
| 1777 | } sf1; |
||
| 1778 | |||
| 1779 | struct thread2 thread2; |
||
| 1780 | struct thread3 thread3; |
||
| 1781 | |||
| 1782 | struct |
||
| 1783 | { |
||
| 1784 | unsigned int pad0:10; |
||
| 1785 | unsigned int stats_enable:1; |
||
| 1786 | unsigned int nr_urb_entries:7; |
||
| 1787 | unsigned int pad1:1; |
||
| 1788 | unsigned int urb_entry_allocation_size:5; |
||
| 1789 | unsigned int pad2:1; |
||
| 1790 | unsigned int max_threads:6; |
||
| 1791 | unsigned int pad3:1; |
||
| 1792 | } thread4; |
||
| 1793 | |||
| 1794 | struct |
||
| 1795 | { |
||
| 1796 | unsigned int front_winding:1; |
||
| 1797 | unsigned int viewport_transform:1; |
||
| 1798 | unsigned int pad0:3; |
||
| 1799 | unsigned int sf_viewport_state_offset:27; |
||
| 1800 | } sf5; |
||
| 1801 | |||
| 1802 | struct |
||
| 1803 | { |
||
| 1804 | unsigned int pad0:9; |
||
| 1805 | unsigned int dest_org_vbias:4; |
||
| 1806 | unsigned int dest_org_hbias:4; |
||
| 1807 | unsigned int scissor:1; |
||
| 1808 | unsigned int disable_2x2_trifilter:1; |
||
| 1809 | unsigned int disable_zero_pix_trifilter:1; |
||
| 1810 | unsigned int point_rast_rule:2; |
||
| 1811 | unsigned int line_endcap_aa_region_width:2; |
||
| 1812 | unsigned int line_width:4; |
||
| 1813 | unsigned int fast_scissor_disable:1; |
||
| 1814 | unsigned int cull_mode:2; |
||
| 1815 | unsigned int aa_enable:1; |
||
| 1816 | } sf6; |
||
| 1817 | |||
| 1818 | struct |
||
| 1819 | { |
||
| 1820 | unsigned int point_size:11; |
||
| 1821 | unsigned int use_point_size_state:1; |
||
| 1822 | unsigned int subpixel_precision:1; |
||
| 1823 | unsigned int sprite_point:1; |
||
| 1824 | unsigned int pad0:11; |
||
| 1825 | unsigned int trifan_pv:2; |
||
| 1826 | unsigned int linestrip_pv:2; |
||
| 1827 | unsigned int tristrip_pv:2; |
||
| 1828 | unsigned int line_last_pixel_enable:1; |
||
| 1829 | } sf7; |
||
| 1830 | |||
| 1831 | }; |
||
| 1832 | |||
| 1833 | |||
| 1834 | struct gen5_gs_unit_state |
||
| 1835 | { |
||
| 1836 | struct thread0 thread0; |
||
| 1837 | struct thread1 thread1; |
||
| 1838 | struct thread2 thread2; |
||
| 1839 | struct thread3 thread3; |
||
| 1840 | |||
| 1841 | struct |
||
| 1842 | { |
||
| 1843 | unsigned int pad0:10; |
||
| 1844 | unsigned int stats_enable:1; |
||
| 1845 | unsigned int nr_urb_entries:7; |
||
| 1846 | unsigned int pad1:1; |
||
| 1847 | unsigned int urb_entry_allocation_size:5; |
||
| 1848 | unsigned int pad2:1; |
||
| 1849 | unsigned int max_threads:1; |
||
| 1850 | unsigned int pad3:6; |
||
| 1851 | } thread4; |
||
| 1852 | |||
| 1853 | struct |
||
| 1854 | { |
||
| 1855 | unsigned int sampler_count:3; |
||
| 1856 | unsigned int pad0:2; |
||
| 1857 | unsigned int sampler_state_pointer:27; |
||
| 1858 | } gs5; |
||
| 1859 | |||
| 1860 | |||
| 1861 | struct |
||
| 1862 | { |
||
| 1863 | unsigned int max_vp_index:4; |
||
| 1864 | unsigned int pad0:26; |
||
| 1865 | unsigned int reorder_enable:1; |
||
| 1866 | unsigned int pad1:1; |
||
| 1867 | } gs6; |
||
| 1868 | }; |
||
| 1869 | |||
| 1870 | |||
| 1871 | struct gen5_vs_unit_state |
||
| 1872 | { |
||
| 1873 | struct thread0 thread0; |
||
| 1874 | struct thread1 thread1; |
||
| 1875 | struct thread2 thread2; |
||
| 1876 | struct thread3 thread3; |
||
| 1877 | |||
| 1878 | struct |
||
| 1879 | { |
||
| 1880 | unsigned int pad0:10; |
||
| 1881 | unsigned int stats_enable:1; |
||
| 1882 | unsigned int nr_urb_entries:7; |
||
| 1883 | unsigned int pad1:1; |
||
| 1884 | unsigned int urb_entry_allocation_size:5; |
||
| 1885 | unsigned int pad2:1; |
||
| 1886 | unsigned int max_threads:4; |
||
| 1887 | unsigned int pad3:3; |
||
| 1888 | } thread4; |
||
| 1889 | |||
| 1890 | struct |
||
| 1891 | { |
||
| 1892 | unsigned int sampler_count:3; |
||
| 1893 | unsigned int pad0:2; |
||
| 1894 | unsigned int sampler_state_pointer:27; |
||
| 1895 | } vs5; |
||
| 1896 | |||
| 1897 | struct |
||
| 1898 | { |
||
| 1899 | unsigned int vs_enable:1; |
||
| 1900 | unsigned int vert_cache_disable:1; |
||
| 1901 | unsigned int pad0:30; |
||
| 1902 | } vs6; |
||
| 1903 | }; |
||
| 1904 | |||
| 1905 | |||
| 1906 | struct gen5_wm_unit_state |
||
| 1907 | { |
||
| 1908 | struct thread0 thread0; |
||
| 1909 | struct thread1 thread1; |
||
| 1910 | struct thread2 thread2; |
||
| 1911 | struct thread3 thread3; |
||
| 1912 | |||
| 1913 | struct { |
||
| 1914 | unsigned int stats_enable:1; |
||
| 1915 | unsigned int pad0:1; |
||
| 1916 | unsigned int sampler_count:3; |
||
| 1917 | unsigned int sampler_state_pointer:27; |
||
| 1918 | } wm4; |
||
| 1919 | |||
| 1920 | struct |
||
| 1921 | { |
||
| 1922 | unsigned int enable_8_pix:1; |
||
| 1923 | unsigned int enable_16_pix:1; |
||
| 1924 | unsigned int enable_32_pix:1; |
||
| 1925 | unsigned int pad0:7; |
||
| 1926 | unsigned int legacy_global_depth_bias:1; |
||
| 1927 | unsigned int line_stipple:1; |
||
| 1928 | unsigned int depth_offset:1; |
||
| 1929 | unsigned int polygon_stipple:1; |
||
| 1930 | unsigned int line_aa_region_width:2; |
||
| 1931 | unsigned int line_endcap_aa_region_width:2; |
||
| 1932 | unsigned int early_depth_test:1; |
||
| 1933 | unsigned int thread_dispatch_enable:1; |
||
| 1934 | unsigned int program_uses_depth:1; |
||
| 1935 | unsigned int program_computes_depth:1; |
||
| 1936 | unsigned int program_uses_killpixel:1; |
||
| 1937 | unsigned int legacy_line_rast: 1; |
||
| 1938 | unsigned int transposed_urb_read:1; |
||
| 1939 | unsigned int max_threads:7; |
||
| 1940 | } wm5; |
||
| 1941 | |||
| 1942 | float global_depth_offset_constant; |
||
| 1943 | float global_depth_offset_scale; |
||
| 1944 | |||
| 1945 | struct { |
||
| 1946 | unsigned int pad0:1; |
||
| 1947 | unsigned int grf_reg_count_1:3; |
||
| 1948 | unsigned int pad1:2; |
||
| 1949 | unsigned int kernel_start_pointer_1:26; |
||
| 1950 | } wm8; |
||
| 1951 | |||
| 1952 | struct { |
||
| 1953 | unsigned int pad0:1; |
||
| 1954 | unsigned int grf_reg_count_2:3; |
||
| 1955 | unsigned int pad1:2; |
||
| 1956 | unsigned int kernel_start_pointer_2:26; |
||
| 1957 | } wm9; |
||
| 1958 | |||
| 1959 | struct { |
||
| 1960 | unsigned int pad0:1; |
||
| 1961 | unsigned int grf_reg_count_3:3; |
||
| 1962 | unsigned int pad1:2; |
||
| 1963 | unsigned int kernel_start_pointer_3:26; |
||
| 1964 | } wm10; |
||
| 1965 | }; |
||
| 1966 | |||
| 1967 | struct gen5_wm_unit_state_padded { |
||
| 1968 | struct gen5_wm_unit_state state; |
||
| 1969 | char pad[64 - sizeof(struct gen5_wm_unit_state)]; |
||
| 1970 | }; |
||
| 1971 | |||
| 1972 | /* The hardware supports two different modes for border color. The |
||
| 1973 | * default (OpenGL) mode uses floating-point color channels, while the |
||
| 1974 | * legacy mode uses 4 bytes. |
||
| 1975 | * |
||
| 1976 | * More significantly, the legacy mode respects the components of the |
||
| 1977 | * border color for channels not present in the source, (whereas the |
||
| 1978 | * default mode will ignore the border color's alpha channel and use |
||
| 1979 | * alpha==1 for an RGB source, for example). |
||
| 1980 | * |
||
| 1981 | * The legacy mode matches the semantics specified by the Render |
||
| 1982 | * extension. |
||
| 1983 | */ |
||
| 1984 | struct gen5_sampler_default_border_color { |
||
| 1985 | float color[4]; |
||
| 1986 | }; |
||
| 1987 | |||
| 1988 | struct gen5_sampler_legacy_border_color { |
||
| 1989 | uint8_t color[4]; |
||
| 1990 | }; |
||
| 1991 | |||
| 1992 | struct gen5_sampler_state { |
||
| 1993 | struct { |
||
| 1994 | unsigned int shadow_function:3; |
||
| 1995 | unsigned int lod_bias:11; |
||
| 1996 | unsigned int min_filter:3; |
||
| 1997 | unsigned int mag_filter:3; |
||
| 1998 | unsigned int mip_filter:2; |
||
| 1999 | unsigned int base_level:5; |
||
| 2000 | unsigned int pad:1; |
||
| 2001 | unsigned int lod_preclamp:1; |
||
| 2002 | unsigned int border_color_mode:1; |
||
| 2003 | unsigned int pad0:1; |
||
| 2004 | unsigned int disable:1; |
||
| 2005 | } ss0; |
||
| 2006 | |||
| 2007 | struct { |
||
| 2008 | unsigned int r_wrap_mode:3; |
||
| 2009 | unsigned int t_wrap_mode:3; |
||
| 2010 | unsigned int s_wrap_mode:3; |
||
| 2011 | unsigned int pad:3; |
||
| 2012 | unsigned int max_lod:10; |
||
| 2013 | unsigned int min_lod:10; |
||
| 2014 | } ss1; |
||
| 2015 | |||
| 2016 | struct { |
||
| 2017 | unsigned int pad:5; |
||
| 2018 | unsigned int border_color_pointer:27; |
||
| 2019 | } ss2; |
||
| 2020 | |||
| 2021 | struct { |
||
| 2022 | uint32_t pad:13; |
||
| 2023 | uint32_t address_round:6; |
||
| 2024 | uint32_t max_aniso:3; |
||
| 2025 | uint32_t chroma_key_mode:1; |
||
| 2026 | uint32_t chroma_key_index:2; |
||
| 2027 | uint32_t chroma_key_enable:1; |
||
| 2028 | uint32_t mbz:6; |
||
| 2029 | } ss3; |
||
| 2030 | }; |
||
| 2031 | |||
| 2032 | |||
| 2033 | struct gen5_clipper_viewport |
||
| 2034 | { |
||
| 2035 | float xmin; |
||
| 2036 | float xmax; |
||
| 2037 | float ymin; |
||
| 2038 | float ymax; |
||
| 2039 | }; |
||
| 2040 | |||
| 2041 | struct gen5_cc_viewport |
||
| 2042 | { |
||
| 2043 | float min_depth; |
||
| 2044 | float max_depth; |
||
| 2045 | }; |
||
| 2046 | |||
| 2047 | struct gen5_sf_viewport |
||
| 2048 | { |
||
| 2049 | struct { |
||
| 2050 | float m00; |
||
| 2051 | float m11; |
||
| 2052 | float m22; |
||
| 2053 | float m30; |
||
| 2054 | float m31; |
||
| 2055 | float m32; |
||
| 2056 | } viewport; |
||
| 2057 | |||
| 2058 | struct { |
||
| 2059 | short xmin; |
||
| 2060 | short ymin; |
||
| 2061 | short xmax; |
||
| 2062 | short ymax; |
||
| 2063 | } scissor; |
||
| 2064 | }; |
||
| 2065 | |||
| 2066 | /* Documented in the subsystem/shared-functions/sampler chapter... |
||
| 2067 | */ |
||
| 2068 | struct gen5_surface_state |
||
| 2069 | { |
||
| 2070 | struct { |
||
| 2071 | unsigned int cube_pos_z:1; |
||
| 2072 | unsigned int cube_neg_z:1; |
||
| 2073 | unsigned int cube_pos_y:1; |
||
| 2074 | unsigned int cube_neg_y:1; |
||
| 2075 | unsigned int cube_pos_x:1; |
||
| 2076 | unsigned int cube_neg_x:1; |
||
| 2077 | unsigned int pad:3; |
||
| 2078 | unsigned int render_cache_read_mode:1; |
||
| 2079 | unsigned int mipmap_layout_mode:1; |
||
| 2080 | unsigned int vert_line_stride_ofs:1; |
||
| 2081 | unsigned int vert_line_stride:1; |
||
| 2082 | unsigned int color_blend:1; |
||
| 2083 | unsigned int writedisable_blue:1; |
||
| 2084 | unsigned int writedisable_green:1; |
||
| 2085 | unsigned int writedisable_red:1; |
||
| 2086 | unsigned int writedisable_alpha:1; |
||
| 2087 | unsigned int surface_format:9; |
||
| 2088 | unsigned int data_return_format:1; |
||
| 2089 | unsigned int pad0:1; |
||
| 2090 | unsigned int surface_type:3; |
||
| 2091 | } ss0; |
||
| 2092 | |||
| 2093 | struct { |
||
| 2094 | unsigned int base_addr; |
||
| 2095 | } ss1; |
||
| 2096 | |||
| 2097 | struct { |
||
| 2098 | unsigned int render_target_rotation:2; |
||
| 2099 | unsigned int mip_count:4; |
||
| 2100 | unsigned int width:13; |
||
| 2101 | unsigned int height:13; |
||
| 2102 | } ss2; |
||
| 2103 | |||
| 2104 | struct { |
||
| 2105 | unsigned int tile_walk:1; |
||
| 2106 | unsigned int tiled_surface:1; |
||
| 2107 | unsigned int pad:1; |
||
| 2108 | unsigned int pitch:18; |
||
| 2109 | unsigned int depth:11; |
||
| 2110 | } ss3; |
||
| 2111 | |||
| 2112 | struct { |
||
| 2113 | unsigned int pad:19; |
||
| 2114 | unsigned int min_array_elt:9; |
||
| 2115 | unsigned int min_lod:4; |
||
| 2116 | } ss4; |
||
| 2117 | |||
| 2118 | struct { |
||
| 2119 | unsigned int pad:20; |
||
| 2120 | unsigned int y_offset:4; |
||
| 2121 | unsigned int pad2:1; |
||
| 2122 | unsigned int x_offset:7; |
||
| 2123 | } ss5; |
||
| 2124 | }; |
||
| 2125 | |||
| 2126 | /* Surface state DW0 */ |
||
| 2127 | #define GEN5_SURFACE_RC_READ_WRITE (1 << 8) |
||
| 2128 | #define GEN5_SURFACE_MIPLAYOUT_SHIFT 10 |
||
| 2129 | #define GEN5_SURFACE_MIPMAPLAYOUT_BELOW 0 |
||
| 2130 | #define GEN5_SURFACE_MIPMAPLAYOUT_RIGHT 1 |
||
| 2131 | #define GEN5_SURFACE_CUBEFACE_ENABLES 0x3f |
||
| 2132 | #define GEN5_SURFACE_BLEND_ENABLED (1 << 13) |
||
| 2133 | #define GEN5_SURFACE_WRITEDISABLE_B_SHIFT 14 |
||
| 2134 | #define GEN5_SURFACE_WRITEDISABLE_G_SHIFT 15 |
||
| 2135 | #define GEN5_SURFACE_WRITEDISABLE_R_SHIFT 16 |
||
| 2136 | #define GEN5_SURFACE_WRITEDISABLE_A_SHIFT 17 |
||
| 2137 | #define GEN5_SURFACE_FORMAT_SHIFT 18 |
||
| 2138 | #define GEN5_SURFACE_FORMAT_MASK INTEL_MASK(26, 18) |
||
| 2139 | |||
| 2140 | #define GEN5_SURFACE_TYPE_SHIFT 29 |
||
| 2141 | #define GEN5_SURFACE_TYPE_MASK GEN5_MASK(31, 29) |
||
| 2142 | #define GEN5_SURFACE_1D 0 |
||
| 2143 | #define GEN5_SURFACE_2D 1 |
||
| 2144 | #define GEN5_SURFACE_3D 2 |
||
| 2145 | #define GEN5_SURFACE_CUBE 3 |
||
| 2146 | #define GEN5_SURFACE_BUFFER 4 |
||
| 2147 | #define GEN5_SURFACE_NULL 7 |
||
| 2148 | |||
| 2149 | /* Surface state DW2 */ |
||
| 2150 | #define GEN5_SURFACE_HEIGHT_SHIFT 19 |
||
| 2151 | #define GEN5_SURFACE_HEIGHT_MASK GEN5_MASK(31, 19) |
||
| 2152 | #define GEN5_SURFACE_WIDTH_SHIFT 6 |
||
| 2153 | #define GEN5_SURFACE_WIDTH_MASK GEN5_MASK(18, 6) |
||
| 2154 | #define GEN5_SURFACE_LOD_SHIFT 2 |
||
| 2155 | #define GEN5_SURFACE_LOD_MASK GEN5_MASK(5, 2) |
||
| 2156 | |||
| 2157 | /* Surface state DW3 */ |
||
| 2158 | #define GEN5_SURFACE_DEPTH_SHIFT 21 |
||
| 2159 | #define GEN5_SURFACE_DEPTH_MASK GEN5_MASK(31, 21) |
||
| 2160 | #define GEN5_SURFACE_PITCH_SHIFT 3 |
||
| 2161 | #define GEN5_SURFACE_PITCH_MASK GEN5_MASK(19, 3) |
||
| 2162 | #define GEN5_SURFACE_TILED (1 << 1) |
||
| 2163 | #define GEN5_SURFACE_TILED_Y (1 << 0) |
||
| 2164 | |||
| 2165 | /* Surface state DW4 */ |
||
| 2166 | #define GEN5_SURFACE_MIN_LOD_SHIFT 28 |
||
| 2167 | #define GEN5_SURFACE_MIN_LOD_MASK GEN5_MASK(31, 28) |
||
| 2168 | |||
| 2169 | /* Surface state DW5 */ |
||
| 2170 | #define GEN5_SURFACE_X_OFFSET_SHIFT 25 |
||
| 2171 | #define GEN5_SURFACE_X_OFFSET_MASK GEN5_MASK(31, 25) |
||
| 2172 | #define GEN5_SURFACE_Y_OFFSET_SHIFT 20 |
||
| 2173 | #define GEN5_SURFACE_Y_OFFSET_MASK GEN5_MASK(23, 20) |
||
| 2174 | |||
| 2175 | struct gen5_vertex_buffer_state |
||
| 2176 | { |
||
| 2177 | struct { |
||
| 2178 | unsigned int pitch:11; |
||
| 2179 | unsigned int pad:15; |
||
| 2180 | unsigned int access_type:1; |
||
| 2181 | unsigned int vb_index:5; |
||
| 2182 | } vb0; |
||
| 2183 | |||
| 2184 | unsigned int start_addr; |
||
| 2185 | unsigned int max_index; |
||
| 2186 | #if 1 |
||
| 2187 | unsigned int instance_data_step_rate; /* not included for sequential/random vertices? */ |
||
| 2188 | #endif |
||
| 2189 | }; |
||
| 2190 | |||
| 2191 | #define GEN5_VBP_MAX 17 |
||
| 2192 | |||
| 2193 | struct gen5_vb_array_state { |
||
| 2194 | struct header header; |
||
| 2195 | struct gen5_vertex_buffer_state vb[GEN5_VBP_MAX]; |
||
| 2196 | }; |
||
| 2197 | |||
| 2198 | |||
| 2199 | struct gen5_vertex_element_state |
||
| 2200 | { |
||
| 2201 | struct |
||
| 2202 | { |
||
| 2203 | unsigned int src_offset:11; |
||
| 2204 | unsigned int pad:5; |
||
| 2205 | unsigned int src_format:9; |
||
| 2206 | unsigned int pad0:1; |
||
| 2207 | unsigned int valid:1; |
||
| 2208 | unsigned int vertex_buffer_index:5; |
||
| 2209 | } ve0; |
||
| 2210 | |||
| 2211 | struct |
||
| 2212 | { |
||
| 2213 | unsigned int dst_offset:8; |
||
| 2214 | unsigned int pad:8; |
||
| 2215 | unsigned int vfcomponent3:4; |
||
| 2216 | unsigned int vfcomponent2:4; |
||
| 2217 | unsigned int vfcomponent1:4; |
||
| 2218 | unsigned int vfcomponent0:4; |
||
| 2219 | } ve1; |
||
| 2220 | }; |
||
| 2221 | |||
| 2222 | #define GEN5_VEP_MAX 18 |
||
| 2223 | |||
| 2224 | struct gen5_vertex_element_packet { |
||
| 2225 | struct header header; |
||
| 2226 | struct gen5_vertex_element_state ve[GEN5_VEP_MAX]; /* note: less than _TNL_ATTRIB_MAX */ |
||
| 2227 | }; |
||
| 2228 | |||
| 2229 | |||
| 2230 | struct gen5_urb_immediate { |
||
| 2231 | unsigned int opcode:4; |
||
| 2232 | unsigned int offset:6; |
||
| 2233 | unsigned int swizzle_control:2; |
||
| 2234 | unsigned int pad:1; |
||
| 2235 | unsigned int allocate:1; |
||
| 2236 | unsigned int used:1; |
||
| 2237 | unsigned int complete:1; |
||
| 2238 | unsigned int response_length:4; |
||
| 2239 | unsigned int msg_length:4; |
||
| 2240 | unsigned int msg_target:4; |
||
| 2241 | unsigned int pad1:3; |
||
| 2242 | unsigned int end_of_thread:1; |
||
| 2243 | }; |
||
| 2244 | |||
| 2245 | /* Instruction format for the execution units: |
||
| 2246 | */ |
||
| 2247 | |||
| 2248 | struct gen5_instruction |
||
| 2249 | { |
||
| 2250 | struct |
||
| 2251 | { |
||
| 2252 | unsigned int opcode:7; |
||
| 2253 | unsigned int pad:1; |
||
| 2254 | unsigned int access_mode:1; |
||
| 2255 | unsigned int mask_control:1; |
||
| 2256 | unsigned int dependency_control:2; |
||
| 2257 | unsigned int compression_control:2; |
||
| 2258 | unsigned int thread_control:2; |
||
| 2259 | unsigned int predicate_control:4; |
||
| 2260 | unsigned int predicate_inverse:1; |
||
| 2261 | unsigned int execution_size:3; |
||
| 2262 | unsigned int destreg__conditonalmod:4; /* destreg - send, conditionalmod - others */ |
||
| 2263 | unsigned int pad0:2; |
||
| 2264 | unsigned int debug_control:1; |
||
| 2265 | unsigned int saturate:1; |
||
| 2266 | } header; |
||
| 2267 | |||
| 2268 | union { |
||
| 2269 | struct |
||
| 2270 | { |
||
| 2271 | unsigned int dest_reg_file:2; |
||
| 2272 | unsigned int dest_reg_type:3; |
||
| 2273 | unsigned int src0_reg_file:2; |
||
| 2274 | unsigned int src0_reg_type:3; |
||
| 2275 | unsigned int src1_reg_file:2; |
||
| 2276 | unsigned int src1_reg_type:3; |
||
| 2277 | unsigned int pad:1; |
||
| 2278 | unsigned int dest_subreg_nr:5; |
||
| 2279 | unsigned int dest_reg_nr:8; |
||
| 2280 | unsigned int dest_horiz_stride:2; |
||
| 2281 | unsigned int dest_address_mode:1; |
||
| 2282 | } da1; |
||
| 2283 | |||
| 2284 | struct |
||
| 2285 | { |
||
| 2286 | unsigned int dest_reg_file:2; |
||
| 2287 | unsigned int dest_reg_type:3; |
||
| 2288 | unsigned int src0_reg_file:2; |
||
| 2289 | unsigned int src0_reg_type:3; |
||
| 2290 | unsigned int pad:6; |
||
| 2291 | int dest_indirect_offset:10; /* offset against the deref'd address reg */ |
||
| 2292 | unsigned int dest_subreg_nr:3; /* subnr for the address reg a0.x */ |
||
| 2293 | unsigned int dest_horiz_stride:2; |
||
| 2294 | unsigned int dest_address_mode:1; |
||
| 2295 | } ia1; |
||
| 2296 | |||
| 2297 | struct |
||
| 2298 | { |
||
| 2299 | unsigned int dest_reg_file:2; |
||
| 2300 | unsigned int dest_reg_type:3; |
||
| 2301 | unsigned int src0_reg_file:2; |
||
| 2302 | unsigned int src0_reg_type:3; |
||
| 2303 | unsigned int src1_reg_file:2; |
||
| 2304 | unsigned int src1_reg_type:3; |
||
| 2305 | unsigned int pad0:1; |
||
| 2306 | unsigned int dest_writemask:4; |
||
| 2307 | unsigned int dest_subreg_nr:1; |
||
| 2308 | unsigned int dest_reg_nr:8; |
||
| 2309 | unsigned int pad1:2; |
||
| 2310 | unsigned int dest_address_mode:1; |
||
| 2311 | } da16; |
||
| 2312 | |||
| 2313 | struct |
||
| 2314 | { |
||
| 2315 | unsigned int dest_reg_file:2; |
||
| 2316 | unsigned int dest_reg_type:3; |
||
| 2317 | unsigned int src0_reg_file:2; |
||
| 2318 | unsigned int src0_reg_type:3; |
||
| 2319 | unsigned int pad0:6; |
||
| 2320 | unsigned int dest_writemask:4; |
||
| 2321 | int dest_indirect_offset:6; |
||
| 2322 | unsigned int dest_subreg_nr:3; |
||
| 2323 | unsigned int pad1:2; |
||
| 2324 | unsigned int dest_address_mode:1; |
||
| 2325 | } ia16; |
||
| 2326 | } bits1; |
||
| 2327 | |||
| 2328 | |||
| 2329 | union { |
||
| 2330 | struct |
||
| 2331 | { |
||
| 2332 | unsigned int src0_subreg_nr:5; |
||
| 2333 | unsigned int src0_reg_nr:8; |
||
| 2334 | unsigned int src0_abs:1; |
||
| 2335 | unsigned int src0_negate:1; |
||
| 2336 | unsigned int src0_address_mode:1; |
||
| 2337 | unsigned int src0_horiz_stride:2; |
||
| 2338 | unsigned int src0_width:3; |
||
| 2339 | unsigned int src0_vert_stride:4; |
||
| 2340 | unsigned int flag_reg_nr:1; |
||
| 2341 | unsigned int pad:6; |
||
| 2342 | } da1; |
||
| 2343 | |||
| 2344 | struct |
||
| 2345 | { |
||
| 2346 | int src0_indirect_offset:10; |
||
| 2347 | unsigned int src0_subreg_nr:3; |
||
| 2348 | unsigned int src0_abs:1; |
||
| 2349 | unsigned int src0_negate:1; |
||
| 2350 | unsigned int src0_address_mode:1; |
||
| 2351 | unsigned int src0_horiz_stride:2; |
||
| 2352 | unsigned int src0_width:3; |
||
| 2353 | unsigned int src0_vert_stride:4; |
||
| 2354 | unsigned int flag_reg_nr:1; |
||
| 2355 | unsigned int pad:6; |
||
| 2356 | } ia1; |
||
| 2357 | |||
| 2358 | struct |
||
| 2359 | { |
||
| 2360 | unsigned int src0_swz_x:2; |
||
| 2361 | unsigned int src0_swz_y:2; |
||
| 2362 | unsigned int src0_subreg_nr:1; |
||
| 2363 | unsigned int src0_reg_nr:8; |
||
| 2364 | unsigned int src0_abs:1; |
||
| 2365 | unsigned int src0_negate:1; |
||
| 2366 | unsigned int src0_address_mode:1; |
||
| 2367 | unsigned int src0_swz_z:2; |
||
| 2368 | unsigned int src0_swz_w:2; |
||
| 2369 | unsigned int pad0:1; |
||
| 2370 | unsigned int src0_vert_stride:4; |
||
| 2371 | unsigned int flag_reg_nr:1; |
||
| 2372 | unsigned int pad1:6; |
||
| 2373 | } da16; |
||
| 2374 | |||
| 2375 | struct |
||
| 2376 | { |
||
| 2377 | unsigned int src0_swz_x:2; |
||
| 2378 | unsigned int src0_swz_y:2; |
||
| 2379 | int src0_indirect_offset:6; |
||
| 2380 | unsigned int src0_subreg_nr:3; |
||
| 2381 | unsigned int src0_abs:1; |
||
| 2382 | unsigned int src0_negate:1; |
||
| 2383 | unsigned int src0_address_mode:1; |
||
| 2384 | unsigned int src0_swz_z:2; |
||
| 2385 | unsigned int src0_swz_w:2; |
||
| 2386 | unsigned int pad0:1; |
||
| 2387 | unsigned int src0_vert_stride:4; |
||
| 2388 | unsigned int flag_reg_nr:1; |
||
| 2389 | unsigned int pad1:6; |
||
| 2390 | } ia16; |
||
| 2391 | |||
| 2392 | } bits2; |
||
| 2393 | |||
| 2394 | union |
||
| 2395 | { |
||
| 2396 | struct |
||
| 2397 | { |
||
| 2398 | unsigned int src1_subreg_nr:5; |
||
| 2399 | unsigned int src1_reg_nr:8; |
||
| 2400 | unsigned int src1_abs:1; |
||
| 2401 | unsigned int src1_negate:1; |
||
| 2402 | unsigned int pad:1; |
||
| 2403 | unsigned int src1_horiz_stride:2; |
||
| 2404 | unsigned int src1_width:3; |
||
| 2405 | unsigned int src1_vert_stride:4; |
||
| 2406 | unsigned int pad0:7; |
||
| 2407 | } da1; |
||
| 2408 | |||
| 2409 | struct |
||
| 2410 | { |
||
| 2411 | unsigned int src1_swz_x:2; |
||
| 2412 | unsigned int src1_swz_y:2; |
||
| 2413 | unsigned int src1_subreg_nr:1; |
||
| 2414 | unsigned int src1_reg_nr:8; |
||
| 2415 | unsigned int src1_abs:1; |
||
| 2416 | unsigned int src1_negate:1; |
||
| 2417 | unsigned int pad0:1; |
||
| 2418 | unsigned int src1_swz_z:2; |
||
| 2419 | unsigned int src1_swz_w:2; |
||
| 2420 | unsigned int pad1:1; |
||
| 2421 | unsigned int src1_vert_stride:4; |
||
| 2422 | unsigned int pad2:7; |
||
| 2423 | } da16; |
||
| 2424 | |||
| 2425 | struct |
||
| 2426 | { |
||
| 2427 | int src1_indirect_offset:10; |
||
| 2428 | unsigned int src1_subreg_nr:3; |
||
| 2429 | unsigned int src1_abs:1; |
||
| 2430 | unsigned int src1_negate:1; |
||
| 2431 | unsigned int pad0:1; |
||
| 2432 | unsigned int src1_horiz_stride:2; |
||
| 2433 | unsigned int src1_width:3; |
||
| 2434 | unsigned int src1_vert_stride:4; |
||
| 2435 | unsigned int flag_reg_nr:1; |
||
| 2436 | unsigned int pad1:6; |
||
| 2437 | } ia1; |
||
| 2438 | |||
| 2439 | struct |
||
| 2440 | { |
||
| 2441 | unsigned int src1_swz_x:2; |
||
| 2442 | unsigned int src1_swz_y:2; |
||
| 2443 | int src1_indirect_offset:6; |
||
| 2444 | unsigned int src1_subreg_nr:3; |
||
| 2445 | unsigned int src1_abs:1; |
||
| 2446 | unsigned int src1_negate:1; |
||
| 2447 | unsigned int pad0:1; |
||
| 2448 | unsigned int src1_swz_z:2; |
||
| 2449 | unsigned int src1_swz_w:2; |
||
| 2450 | unsigned int pad1:1; |
||
| 2451 | unsigned int src1_vert_stride:4; |
||
| 2452 | unsigned int flag_reg_nr:1; |
||
| 2453 | unsigned int pad2:6; |
||
| 2454 | } ia16; |
||
| 2455 | |||
| 2456 | |||
| 2457 | struct |
||
| 2458 | { |
||
| 2459 | int jump_count:16; /* note: signed */ |
||
| 2460 | unsigned int pop_count:4; |
||
| 2461 | unsigned int pad0:12; |
||
| 2462 | } if_else; |
||
| 2463 | |||
| 2464 | struct { |
||
| 2465 | unsigned int function:4; |
||
| 2466 | unsigned int int_type:1; |
||
| 2467 | unsigned int precision:1; |
||
| 2468 | unsigned int saturate:1; |
||
| 2469 | unsigned int data_type:1; |
||
| 2470 | unsigned int pad0:8; |
||
| 2471 | unsigned int response_length:4; |
||
| 2472 | unsigned int msg_length:4; |
||
| 2473 | unsigned int msg_target:4; |
||
| 2474 | unsigned int pad1:3; |
||
| 2475 | unsigned int end_of_thread:1; |
||
| 2476 | } math; |
||
| 2477 | |||
| 2478 | struct { |
||
| 2479 | unsigned int binding_table_index:8; |
||
| 2480 | unsigned int sampler:4; |
||
| 2481 | unsigned int return_format:2; |
||
| 2482 | unsigned int msg_type:2; |
||
| 2483 | unsigned int response_length:4; |
||
| 2484 | unsigned int msg_length:4; |
||
| 2485 | unsigned int msg_target:4; |
||
| 2486 | unsigned int pad1:3; |
||
| 2487 | unsigned int end_of_thread:1; |
||
| 2488 | } sampler; |
||
| 2489 | |||
| 2490 | struct gen5_urb_immediate urb; |
||
| 2491 | |||
| 2492 | struct { |
||
| 2493 | unsigned int binding_table_index:8; |
||
| 2494 | unsigned int msg_control:4; |
||
| 2495 | unsigned int msg_type:2; |
||
| 2496 | unsigned int target_cache:2; |
||
| 2497 | unsigned int response_length:4; |
||
| 2498 | unsigned int msg_length:4; |
||
| 2499 | unsigned int msg_target:4; |
||
| 2500 | unsigned int pad1:3; |
||
| 2501 | unsigned int end_of_thread:1; |
||
| 2502 | } dp_read; |
||
| 2503 | |||
| 2504 | struct { |
||
| 2505 | unsigned int binding_table_index:8; |
||
| 2506 | unsigned int msg_control:3; |
||
| 2507 | unsigned int pixel_scoreboard_clear:1; |
||
| 2508 | unsigned int msg_type:3; |
||
| 2509 | unsigned int send_commit_msg:1; |
||
| 2510 | unsigned int response_length:4; |
||
| 2511 | unsigned int msg_length:4; |
||
| 2512 | unsigned int msg_target:4; |
||
| 2513 | unsigned int pad1:3; |
||
| 2514 | unsigned int end_of_thread:1; |
||
| 2515 | } dp_write; |
||
| 2516 | |||
| 2517 | struct { |
||
| 2518 | unsigned int pad:16; |
||
| 2519 | unsigned int response_length:4; |
||
| 2520 | unsigned int msg_length:4; |
||
| 2521 | unsigned int msg_target:4; |
||
| 2522 | unsigned int pad1:3; |
||
| 2523 | unsigned int end_of_thread:1; |
||
| 2524 | } generic; |
||
| 2525 | |||
| 2526 | unsigned int ud; |
||
| 2527 | } bits3; |
||
| 2528 | }; |
||
| 2529 | |||
| 2530 | /* media pipeline */ |
||
| 2531 | |||
| 2532 | struct gen5_vfe_state { |
||
| 2533 | struct { |
||
| 2534 | unsigned int per_thread_scratch_space:4; |
||
| 2535 | unsigned int pad3:3; |
||
| 2536 | unsigned int extend_vfe_state_present:1; |
||
| 2537 | unsigned int pad2:2; |
||
| 2538 | unsigned int scratch_base:22; |
||
| 2539 | } vfe0; |
||
| 2540 | |||
| 2541 | struct { |
||
| 2542 | unsigned int debug_counter_control:2; |
||
| 2543 | unsigned int children_present:1; |
||
| 2544 | unsigned int vfe_mode:4; |
||
| 2545 | unsigned int pad2:2; |
||
| 2546 | unsigned int num_urb_entries:7; |
||
| 2547 | unsigned int urb_entry_alloc_size:9; |
||
| 2548 | unsigned int max_threads:7; |
||
| 2549 | } vfe1; |
||
| 2550 | |||
| 2551 | struct { |
||
| 2552 | unsigned int pad4:4; |
||
| 2553 | unsigned int interface_descriptor_base:28; |
||
| 2554 | } vfe2; |
||
| 2555 | }; |
||
| 2556 | |||
| 2557 | struct gen5_vld_state { |
||
| 2558 | struct { |
||
| 2559 | unsigned int pad6:6; |
||
| 2560 | unsigned int scan_order:1; |
||
| 2561 | unsigned int intra_vlc_format:1; |
||
| 2562 | unsigned int quantizer_scale_type:1; |
||
| 2563 | unsigned int concealment_motion_vector:1; |
||
| 2564 | unsigned int frame_predict_frame_dct:1; |
||
| 2565 | unsigned int top_field_first:1; |
||
| 2566 | unsigned int picture_structure:2; |
||
| 2567 | unsigned int intra_dc_precision:2; |
||
| 2568 | unsigned int f_code_0_0:4; |
||
| 2569 | unsigned int f_code_0_1:4; |
||
| 2570 | unsigned int f_code_1_0:4; |
||
| 2571 | unsigned int f_code_1_1:4; |
||
| 2572 | } vld0; |
||
| 2573 | |||
| 2574 | struct { |
||
| 2575 | unsigned int pad2:9; |
||
| 2576 | unsigned int picture_coding_type:2; |
||
| 2577 | unsigned int pad:21; |
||
| 2578 | } vld1; |
||
| 2579 | |||
| 2580 | struct { |
||
| 2581 | unsigned int index_0:4; |
||
| 2582 | unsigned int index_1:4; |
||
| 2583 | unsigned int index_2:4; |
||
| 2584 | unsigned int index_3:4; |
||
| 2585 | unsigned int index_4:4; |
||
| 2586 | unsigned int index_5:4; |
||
| 2587 | unsigned int index_6:4; |
||
| 2588 | unsigned int index_7:4; |
||
| 2589 | } desc_remap_table0; |
||
| 2590 | |||
| 2591 | struct { |
||
| 2592 | unsigned int index_8:4; |
||
| 2593 | unsigned int index_9:4; |
||
| 2594 | unsigned int index_10:4; |
||
| 2595 | unsigned int index_11:4; |
||
| 2596 | unsigned int index_12:4; |
||
| 2597 | unsigned int index_13:4; |
||
| 2598 | unsigned int index_14:4; |
||
| 2599 | unsigned int index_15:4; |
||
| 2600 | } desc_remap_table1; |
||
| 2601 | }; |
||
| 2602 | |||
| 2603 | struct gen5_interface_descriptor { |
||
| 2604 | struct { |
||
| 2605 | unsigned int grf_reg_blocks:4; |
||
| 2606 | unsigned int pad:2; |
||
| 2607 | unsigned int kernel_start_pointer:26; |
||
| 2608 | } desc0; |
||
| 2609 | |||
| 2610 | struct { |
||
| 2611 | unsigned int pad:7; |
||
| 2612 | unsigned int software_exception:1; |
||
| 2613 | unsigned int pad2:3; |
||
| 2614 | unsigned int maskstack_exception:1; |
||
| 2615 | unsigned int pad3:1; |
||
| 2616 | unsigned int illegal_opcode_exception:1; |
||
| 2617 | unsigned int pad4:2; |
||
| 2618 | unsigned int floating_point_mode:1; |
||
| 2619 | unsigned int thread_priority:1; |
||
| 2620 | unsigned int single_program_flow:1; |
||
| 2621 | unsigned int pad5:1; |
||
| 2622 | unsigned int const_urb_entry_read_offset:6; |
||
| 2623 | unsigned int const_urb_entry_read_len:6; |
||
| 2624 | } desc1; |
||
| 2625 | |||
| 2626 | struct { |
||
| 2627 | unsigned int pad:2; |
||
| 2628 | unsigned int sampler_count:3; |
||
| 2629 | unsigned int sampler_state_pointer:27; |
||
| 2630 | } desc2; |
||
| 2631 | |||
| 2632 | struct { |
||
| 2633 | unsigned int binding_table_entry_count:5; |
||
| 2634 | unsigned int binding_table_pointer:27; |
||
| 2635 | } desc3; |
||
| 2636 | }; |
||
| 2637 | |||
| 2638 | struct gen6_blend_state |
||
| 2639 | { |
||
| 2640 | struct { |
||
| 2641 | unsigned int dest_blend_factor:5; |
||
| 2642 | unsigned int source_blend_factor:5; |
||
| 2643 | unsigned int pad3:1; |
||
| 2644 | unsigned int blend_func:3; |
||
| 2645 | unsigned int pad2:1; |
||
| 2646 | unsigned int ia_dest_blend_factor:5; |
||
| 2647 | unsigned int ia_source_blend_factor:5; |
||
| 2648 | unsigned int pad1:1; |
||
| 2649 | unsigned int ia_blend_func:3; |
||
| 2650 | unsigned int pad0:1; |
||
| 2651 | unsigned int ia_blend_enable:1; |
||
| 2652 | unsigned int blend_enable:1; |
||
| 2653 | } blend0; |
||
| 2654 | |||
| 2655 | struct { |
||
| 2656 | unsigned int post_blend_clamp_enable:1; |
||
| 2657 | unsigned int pre_blend_clamp_enable:1; |
||
| 2658 | unsigned int clamp_range:2; |
||
| 2659 | unsigned int pad0:4; |
||
| 2660 | unsigned int x_dither_offset:2; |
||
| 2661 | unsigned int y_dither_offset:2; |
||
| 2662 | unsigned int dither_enable:1; |
||
| 2663 | unsigned int alpha_test_func:3; |
||
| 2664 | unsigned int alpha_test_enable:1; |
||
| 2665 | unsigned int pad1:1; |
||
| 2666 | unsigned int logic_op_func:4; |
||
| 2667 | unsigned int logic_op_enable:1; |
||
| 2668 | unsigned int pad2:1; |
||
| 2669 | unsigned int write_disable_b:1; |
||
| 2670 | unsigned int write_disable_g:1; |
||
| 2671 | unsigned int write_disable_r:1; |
||
| 2672 | unsigned int write_disable_a:1; |
||
| 2673 | unsigned int pad3:1; |
||
| 2674 | unsigned int alpha_to_coverage_dither:1; |
||
| 2675 | unsigned int alpha_to_one:1; |
||
| 2676 | unsigned int alpha_to_coverage:1; |
||
| 2677 | } blend1; |
||
| 2678 | }; |
||
| 2679 | |||
| 2680 | struct gen6_color_calc_state |
||
| 2681 | { |
||
| 2682 | struct { |
||
| 2683 | unsigned int alpha_test_format:1; |
||
| 2684 | unsigned int pad0:14; |
||
| 2685 | unsigned int round_disable:1; |
||
| 2686 | unsigned int bf_stencil_ref:8; |
||
| 2687 | unsigned int stencil_ref:8; |
||
| 2688 | } cc0; |
||
| 2689 | |||
| 2690 | union { |
||
| 2691 | float alpha_ref_f; |
||
| 2692 | struct { |
||
| 2693 | unsigned int ui:8; |
||
| 2694 | unsigned int pad0:24; |
||
| 2695 | } alpha_ref_fi; |
||
| 2696 | } cc1; |
||
| 2697 | |||
| 2698 | float constant_r; |
||
| 2699 | float constant_g; |
||
| 2700 | float constant_b; |
||
| 2701 | float constant_a; |
||
| 2702 | }; |
||
| 2703 | |||
| 2704 | struct gen6_depth_stencil_state |
||
| 2705 | { |
||
| 2706 | struct { |
||
| 2707 | unsigned int pad0:3; |
||
| 2708 | unsigned int bf_stencil_pass_depth_pass_op:3; |
||
| 2709 | unsigned int bf_stencil_pass_depth_fail_op:3; |
||
| 2710 | unsigned int bf_stencil_fail_op:3; |
||
| 2711 | unsigned int bf_stencil_func:3; |
||
| 2712 | unsigned int bf_stencil_enable:1; |
||
| 2713 | unsigned int pad1:2; |
||
| 2714 | unsigned int stencil_write_enable:1; |
||
| 2715 | unsigned int stencil_pass_depth_pass_op:3; |
||
| 2716 | unsigned int stencil_pass_depth_fail_op:3; |
||
| 2717 | unsigned int stencil_fail_op:3; |
||
| 2718 | unsigned int stencil_func:3; |
||
| 2719 | unsigned int stencil_enable:1; |
||
| 2720 | } ds0; |
||
| 2721 | |||
| 2722 | struct { |
||
| 2723 | unsigned int bf_stencil_write_mask:8; |
||
| 2724 | unsigned int bf_stencil_test_mask:8; |
||
| 2725 | unsigned int stencil_write_mask:8; |
||
| 2726 | unsigned int stencil_test_mask:8; |
||
| 2727 | } ds1; |
||
| 2728 | |||
| 2729 | struct { |
||
| 2730 | unsigned int pad0:26; |
||
| 2731 | unsigned int depth_write_enable:1; |
||
| 2732 | unsigned int depth_test_func:3; |
||
| 2733 | unsigned int pad1:1; |
||
| 2734 | unsigned int depth_test_enable:1; |
||
| 2735 | } ds2; |
||
| 2736 | }; |
||
| 2737 | |||
| 2738 | typedef enum { |
||
| 2739 | SAMPLER_FILTER_NEAREST = 0, |
||
| 2740 | SAMPLER_FILTER_BILINEAR, |
||
| 2741 | FILTER_COUNT |
||
| 2742 | } sampler_filter_t; |
||
| 2743 | |||
| 2744 | typedef enum { |
||
| 2745 | SAMPLER_EXTEND_NONE = 0, |
||
| 2746 | SAMPLER_EXTEND_REPEAT, |
||
| 2747 | SAMPLER_EXTEND_PAD, |
||
| 2748 | SAMPLER_EXTEND_REFLECT, |
||
| 2749 | EXTEND_COUNT |
||
| 2750 | } sampler_extend_t; |
||
| 2751 | |||
| 2752 | typedef enum { |
||
| 2753 | WM_KERNEL = 0, |
||
| 2754 | WM_KERNEL_P, |
||
| 2755 | |||
| 2756 | WM_KERNEL_MASK, |
||
| 2757 | WM_KERNEL_MASK_P, |
||
| 2758 | |||
| 2759 | WM_KERNEL_MASKCA, |
||
| 2760 | WM_KERNEL_MASKCA_P, |
||
| 2761 | |||
| 2762 | WM_KERNEL_MASKSA, |
||
| 2763 | WM_KERNEL_MASKSA_P, |
||
| 2764 | |||
| 2765 | WM_KERNEL_OPACITY, |
||
| 2766 | WM_KERNEL_OPACITY_P, |
||
| 2767 | |||
| 2768 | WM_KERNEL_VIDEO_PLANAR, |
||
| 2769 | WM_KERNEL_VIDEO_PACKED, |
||
| 2770 | KERNEL_COUNT |
||
| 2771 | } wm_kernel_t; |
||
| 2772 | #endif |