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3545 | hidnplayr | 1 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
2 | ;; ;; |
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3 | ;; Copyright (C) KolibriOS team 2004-2012. All rights reserved. ;; |
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4 | ;; Distributed under terms of the GNU General Public License ;; |
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5 | ;; ;; |
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6 | ;; GNU GENERAL PUBLIC LICENSE ;; |
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7 | ;; Version 2, June 1991 ;; |
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8 | ;; ;; |
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9 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
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10 | |||
11 | |||
12 | ; PCI Bus defines |
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13 | |||
14 | PCI_HEADER_TYPE = 0x0e ; 8 bit |
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15 | PCI_BASE_ADDRESS_0 = 0x10 ; 32 bit |
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16 | PCI_BASE_ADDRESS_1 = 0x14 ; 32 bits |
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17 | PCI_BASE_ADDRESS_2 = 0x18 ; 32 bits |
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18 | PCI_BASE_ADDRESS_3 = 0x1c ; 32 bits |
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19 | PCI_BASE_ADDRESS_4 = 0x20 ; 32 bits |
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20 | PCI_BASE_ADDRESS_5 = 0x24 ; 32 bits |
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21 | PCI_BASE_ADDRESS_SPACE_IO = 0x01 |
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22 | PCI_BASE_ADDRESS_IO_MASK = 0xFFFFFFFC |
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23 | PCI_BASE_ADDRESS_MEM_MASK = 0xFFFFFFF0 |
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24 | |||
25 | ; PCI programming |
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26 | |||
27 | PCI_VENDOR_ID = 0x00 ; 16 bit |
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28 | PCI_DEVICE_ID = 0x02 ; 16 bits |
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29 | PCI_REG_COMMAND = 0x4 ; command register |
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30 | PCI_REG_STATUS = 0x6 ; status register |
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31 | PCI_REVISION_ID = 0x08 ; 8 bits |
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32 | PCI_REG_LATENCY = 0xd ; latency timer register |
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33 | PCI_REG_CAP_PTR = 0x34 ; capabilities pointer |
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34 | PCI_REG_IRQ = 0x3c |
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35 | PCI_REG_CAPABILITY_ID = 0x0 ; capapility ID in pm register block |
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36 | PCI_REG_PM_STATUS = 0x4 ; power management status register |
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37 | PCI_REG_PM_CTRL = 0x4 ; power management control register |
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38 | PCI_BIT_PIO = 1 ; bit0: io space control |
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39 | PCI_BIT_MMIO = 2 ; bit1: memory space control |
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40 | PCI_BIT_MASTER = 4 ; bit2: device acts as a PCI master |
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41 | |||
42 | |||
43 | macro PCI_find_io { |
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44 | |||
45 | local .check, .inc, .got |
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46 | |||
47 | xor eax, eax |
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48 | mov esi, PCI_BASE_ADDRESS_0 |
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49 | .check: |
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50 | stdcall PciRead32, [device.pci_bus], [device.pci_dev], esi |
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51 | |||
52 | test eax, PCI_BASE_ADDRESS_IO_MASK |
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53 | jz .inc |
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54 | |||
55 | test eax, PCI_BASE_ADDRESS_SPACE_IO |
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56 | jz .inc |
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57 | |||
58 | and eax, PCI_BASE_ADDRESS_IO_MASK |
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59 | jmp .got |
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60 | |||
61 | .inc: |
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62 | add esi, 4 |
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63 | cmp esi, PCI_BASE_ADDRESS_5 |
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64 | jbe .check |
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65 | xor eax, eax |
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66 | |||
67 | .got: |
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68 | mov [device.io_addr], eax |
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69 | |||
70 | } |
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71 | |||
72 | |||
73 | macro PCI_find_mmio32 { |
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74 | |||
75 | local .check, .inc, .got |
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76 | |||
77 | mov esi, PCI_BASE_ADDRESS_0 |
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78 | .check: |
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79 | stdcall PciRead32, [device.pci_bus], [device.pci_dev], esi |
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80 | |||
81 | test eax, PCI_BASE_ADDRESS_SPACE_IO ; mmio address? |
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82 | jnz .inc |
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83 | |||
84 | test eax, 100b ; 64 bit? |
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85 | jnz .inc |
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86 | and eax, not 1111b |
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87 | jmp .got |
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88 | |||
89 | .inc: |
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90 | add esi, 4 |
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91 | cmp esi, PCI_BASE_ADDRESS_5 |
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92 | jbe .check |
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93 | xor eax, eax |
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94 | |||
95 | .got: |
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96 | mov [device.mmio_addr], eax |
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97 | } |
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98 | |||
99 | macro PCI_find_irq { |
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100 | |||
101 | stdcall PciRead8, [device.pci_bus], [device.pci_dev], PCI_REG_IRQ |
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102 | mov [device.irq_line], al |
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103 | |||
104 | } |
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105 | |||
106 | macro PCI_find_rev { |
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107 | |||
108 | stdcall PciRead8, [device.pci_bus], [device.pci_dev], PCI_REVISION_ID |
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109 | mov [device.revision], al |
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110 | |||
111 | } |
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112 | |||
113 | macro PCI_make_bus_master bus, dev { |
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114 | |||
115 | stdcall PciRead32, [device.pci_bus], [device.pci_dev], PCI_REG_COMMAND |
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116 | or al, PCI_BIT_MASTER |
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117 | stdcall PciWrite32, [device.pci_bus], [device.pci_dev], PCI_REG_COMMAND, eax |
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118 | |||
119 | } |
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120 | |||
121 | macro PCI_adjust_latency min { |
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122 | |||
123 | local .not |
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124 | |||
125 | stdcall PciRead8, [device.pci_bus], [device.pci_dev], PCI_REG_LATENCY |
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126 | cmp al, min |
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127 | ja .not |
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128 | mov al, min |
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129 | stdcall PciWrite8, [device.pci_bus], [device.pci_dev], PCI_REG_LATENCY, eax |
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130 | .not: |
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131 | |||
132 | } |